HPLL-8001 [ETC]
PLL Frequency Synthesizer (92K in pdf) ; PLL频率合成器（以PDF 92K ）\n
| 型号： | HPLL-8001 |
| 厂家： | 
ETC |
| 描述： | PLL Frequency Synthesizer (92K in pdf)
|
| 文件： | 总12页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PLL Frequency Synthesizer
Technical Data
HPLL-8001
Features
Plastic SOP-14
Description
• Low Operating Current
Consumption ( 4 mA, typ.)
The HPLL-8001 is a phase-locked
loop (PLL) frequency synthesizer
intended for use in a frequency
generation loop with an external
dual modulus prescaler and VCO.
The VCO frequency is divided by
the dual modulus prescaler, which
is then fed to the internal A and N
counters. The reference frequency
is fed to an internal R counter to
define the channel spacing. Both
frequencies are compared in the
phase detector which drives the
charge pump. A lock detect is
provided to monitor the lock state
of the loop. All blocks are
HPLL
• High Input Sensitivity, High
Input Frequencies ( 50 MHz)
8001
YYWW
• Synchronous Programming of
the Counters ( n-, n/a-,
r-counters)
• Switchable Modulus Trigger
Edge
• Large Dividing Ratios for
Small Channel Spacing,
A counter 0 to 127, N counter
3 to 16,380, R counter 3 to
65,535
Pin Configuration
1
14
LD
REFI
PO2
PO1
AVDD
PD
VSS
EN
• Serial Control 3-wire Bus:
Data, Clock ( <10 MHz) , Enable
DATA
CLK
programmed by a serial 3-wire
bus interface.
• Switchable Polarity and
Programmable Phase Detector
Current
AVSS
VCOI
VDD
MOD
8
7
• 2 Programmable Outputs
• Digital Phase Detector
Output Signals ( e.g. for
External Charge Pump)
Functional Block Diagram
DATA
CLOCK
ENABLE
Serial
Control Logic
• DRFI, DVFI Outputs ( e.g. for
Prescaler Standby)
PD
• Lock Detect Output with
Gated Anti-backlash Pulse
( quasi digital lock detect)
16 bit R
counter
DRFI
REFI
VCOI
Phase
PO1
Detector
7 bit A
counter
Lock
Detect
Modulus
Control
LD
Charge
Pump
Applications
• GSM Handsets and Base
Stations
14 bit N
counter
DVFI
PO2
Analog
Control
Logic
• PCS/PCN
• DECT
VDD VSS AVDD AVSS
MOD
• Wireless LAN
2
HPLL-8001 Absolute Maximum Ratings[1]
Thermal Resistance[2]:
= 150°C/W
Absolute
Maximum
Symbol
Parameter
Supply Voltage
Power Dissipation [2, 3]
Units
θ
jc
VCC
PT
V
mW
dBm
°C
7
400
Notes:
1. Permanent damage may occur if
any of these limits are exceeded.
Pin
RF Input Power
+15
2. Tcase = 25°C.
Tj
Junction Temperature
Storage Temperature
150
3. Derate at 7 mW/°C for Tcase > 90°C.
TSTG
°C
-65 to 150
Recommended operating range of V = 2.7 to 5.5V, Ta = -40 to +85°C.
cc
HPLL-8001 Summary Characterization Information
Standard test conditions apply unless otherwise noted.
Current Consumption
Symbol
Parameters and Test Conditions
Current Consumption[1]
@ VDD = 4.5 – 5.5 V
Units
Typ.
I
mA
mA
µA
6.8
3.1
0.06
s
@ VDD = 2.7 – 3.0 V
Standby
Note:
1. FVF = 50 MHz, VVF = 150 mVrms, FRF = 50 MHz, VRF = 150 mVrms, IPD = 0.250 mA, IREF = 100 µA
VCO Input Frequency ( pin 8) , Reference Input Frequency ( pin 1)
Symbol
Parameters and Test Conditions
Units
Typ.
FREFI Reference Frequency Range
VREFI = 100 mVrms
VREFI = 100 mVrms
VDD = 4.5 V
VDD = 2.7 V
MHz
MHz
4 - 60
4 - 30
FVCOI Oscillator Frequency Range[2]
Dual Mode
VVCOI = 200 mVrms
VVCOI = 200 mVrms
VDD = 4.5 V
VDD = 2.7 V
MHz
MHz
4 - 65
4 - 30
Single HF Mode
Single LF Mode
VVCOI = 200 mVrms
VVCOI = 200 mVrms
VDD = 4.5 V
VDD = 2.7 V
MHz
MHz
4 - 160
4 - 100
VVCOI = 100 mVrms
VVCOI = 100 mVrms
VDD = 4.5 V
VDD = 2.7 V
MHz
MHz
4 - 90
4 - 35
Note:
2. Minimum Slew Rate = 4 V/ms, Input Capacitance = 4 pF
Input Current low = 150 µA, Input Current high = 150 µA
3
Inputs EN ( pin 3) , Data ( pin 4) , CLK ( pin 5)
Symbol
Parameters and Test Conditions
Voltage Input Low at IIL = 10 µA
Units
V
Min
Typ
Max
V
0.3VDD
IL
V
Voltage Input High at IIH = 100 µA
Clock Frequency
V
0.7VDD
IH
FCLK
MHz
µs
10
1
TR , TF
TCLW
TDS
Rise and Fall Time of CLK
CLK Pulse Width (high)
Data Setup Time
ns
60
20
20
20
60
1
ns
TCLES
TECLS
TENW
CLK-Enable Setup Time
Enable-CLK Setup Time
EN Pulse Width (high)
ns
ns
ns
Propagation Delay Time (Enable - Port 1)
µs
Note:
These values are valid under the following conditions: VDD = 2.7 to 5.5 V.
VIH
CLK
VIL
T
DS
VOH
DATA
VOL
VOH
EN
T
T
ECLS
CLES
VOL
4
Output MOD Modulus Control ( pin 7)
Symbol
VOH
Parameters and Test Conditions
Units
V
Min
Typ
Max
Voltage Output High
IOH = 2 mA, VDD = 4.5–5.5V
IOH = 1.2 mA, VDD = 2.7– 3.3V
VDD–0.4
VDD–0.4
V
VOL
Voltage Output Low IOL = 0.5 mA, VDD = 4.5–5.5V
IOL = 0.3 mA, VDD = 2.7– 3.3V
V
0.8
0.8
3
V
TR, TF
Rise and Fall Time
VDD = 4.5 –5.5V, CL = 5 pF
VDD = 2.7– 3.3 V, CL = 5 pF
ns
1
3
ns
6
TPHL, TPLH
(VCOI to MOD)
Propagation Delay from high to low and low to high
VDD = 4.5–5.5 V, CL = 5 pF
ns
ns
6
9
VDD = 2.7– 3.3 V, CL = 5 pF
15
17
VIH
FI
50%
VIL
VOH
T
T
PLH
PLH
50%
50%
MOD
pos-edge
VOL
VOH
T
T
PLH
PLH
MOD
neg-edge
50%
VOL
5
Output PD Phase Detector ( pin 10)
Symbol
Parameters and Test Conditions
B14
0
B13
B12
0
Units
mA
mA
mA
mA
mA
mA
mA
mA
nA
Typ.
0.15
0.21
0.31
0.44
0.63
0.89
1.26
1.69
0.1
0
0
0
1
0
1
0
Icp
0
1
1
(VDD = 4.5 –5.5V)
1
0
0
1
0
1
1
1
1
0
1
1
Standby
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
mA
mA
mA
mA
mA
mA
mA
mA
nA
0.14
0.20
0.29
0.40
0.58
0.79
1.06
1.26
0.1
0
1
Icp
1
(VDD = 2.7– 3.3 V)
0
0
1
1
Standby
REFI
VCOI
pos.
edge
DRFI
DVFI
neg.
edge
+lprog
tri-st.
-lprog
PD
pos.
+lprog
tri-st.
-lprog
PD
neg.
high
resist.
LOW
LD
(pos.)
PHIR
(neg.)
(pos.)
(neg.)
PHIV
fv < fr
fv > fr
fv = fr
6
Input-Output PO2 Programmable Input-Output ( pin 13)
Symbol
Parameters and Test Conditions
Units
V
Min
Typ
Max
VOH
Voltage Output High
Voltage Output Low
IOH = 2 mA, VDD = 4.5–5.5V
VDD–0.8
VDD–0.8
IOH = 1.2 mA, VDD = 2.7– 3.3V
IOL = 2 mA, VDD = 4.5–5.5V
IOL = 1.2 mA, VDD = 2.7– 3.3V
V
VOL
TF
V
0.8
0.8
4
V
Fall Time
Rise Time
VDD = 4.5 –5.5V, MF01, MF02, CL = 10 pF
VDD = 2.7– 3.3 V, MF01, MF02, CL = 10 pF
VDD = 4.5 –5.5V, MF01, MF02, CL = 10 pF
VDD = 2.7– 3.3 V, MF01, MF02, CL = 10 pF
ns
ns
ns
ns
V
3
5
6
TR
6
7
12
1.1
14
1.3
VREF
Reference Voltage, Iref = 100 µA
0.8
Output LD Lock Detect ( pin 14)
Symbol
Parameters and Test Conditions
Units
V
Min
Typ
Max
0.8
0.8
6
VOL
Voltage Output Low
Fall Time
IOL = 0.5 mA, VDD = 5V
IOL = 0.5 mA, VDD = 2.7 V
VDD = 4.5–5.5V
V
TF
ns
5
8
VDD = 2.7– 3.3V
ns
10
T
T
f
r
VIH
INPUT
VIL
90%
90%
10%
10%
T
T
PLH
PLH
VOH
50%
50%
OUTPUT
VOL
T
W
7
HPLL-8001 Pin Description Table
No. Mnemonic
Description
Typical Signal
1
REFI
Reference Frequency
High sensitivity preamplifier input for the r-counter.
The input can be AC-coupled for small input signals or
DC-coupled for large input signals.
2
3
VSS
EN
Ground for digital logic
3-wire interface: Enable
0 V
Enable line of the serial interface with internal pull-up
resistor. When EN=H, the input signal CLK and DATA are
internally disabled. When EN=L, the received data is
transferred to the latches on the positive edge of the EN
signal.
4
5
DATA
CLK
3-wire interface: Data
3-wire interface: Clock
Serial DATA input with internal pull-up resistor. The last two
bits before the EN-signal define the destination address.
Clock line with internal pull-up resistor. The serial DATA is
read into the internal shift register on the positive edge (see
pulse diagram for serial data control).
6
7
VDD
Positive supply voltage for
digital logic
MOD
Modulus Control
For an external dual modulus prescaler. The modulus output
is low at the beginning of the cycle. When the a-counter has
reached its set value, MOD switches to high. When the n-
counter has reached its set value, MOD switches to low and
the cycle starts again. When the prescaler has the counter
factor P or P+1 (P for MOD=H, P+1 for MOD=L), the overall
scaling factor is NP+A. The value of the a-counter must be
smaller than that of the n-counter. The trigger edge of the
modulus signal to the input signal can be selected (see
programming tables and MOD A, B) according to the needs
of the prescaler.
In single modulus operation and for standby operation,
the output is low.
8
VCOI
VCO frequency
High sensitivity preamplifier input for the n-counter. The
input can be AC-coupled for small input signals or
DC-coupled for large input signals.
9
AVSS
PD
Ground for analog logic
Phase detector
Pins VDD and AVDD and also pins VSS and AVSS must have
the same power supply voltage.
10
Tristate charge pump output. The level of the charge pump
output current can be programmed using the digital interface.
frequency FV<FR or FV lagging: p source active
frequency FV>FR or FV leading: n source active
frequency FV=FR & PLL locked: PD tristate
standby mode:
PD tristate
The polarity of the output signals of the phase detector can be
programmed.
11
AVDD
Positive supply voltage for
analog logic
8
HPLL-8001 Pin Description Table, continued
No. Mnemonic
Description
Typical Signal
12
PO1
Programmable output
Multifunction Output for the signals FRN , φV , φVN and
PROBIT (FRN, φV are the inverted signals of FR, φVN).
13
PO2
Programmable I/O
For the output signals FVN, φRN and the input signal IREF
- The signals φR and φV are the digital output signals of the
phase and frequency detector for use with external active
current sources.
- The signals FRN and FVN are the scaled down signals of the
reference frequency and VCO-frequencies.
- The programmed bit PROBIT is assigned to PO1 output in
the internal charge pump mode. The standby mode does not
affect this function.
- In the internal charge pump mode the input signal IREF
determines the value of the PD-output current.
14
LD
Lock detect
Unipolar output of the phase detector in the form of a pulse-
width modulated signal. The LD-pulse width corresponds
to the phase difference. In the locked state the LD-signal is at
H-level. In standby mode the output is resistive.
Programmable Reference Divider ( R Counter Register)
1
1
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10 R11 R12 R13 R14 R15 R16
Note: R16 is the MSB of the R counter value. R16 is the first bit which is transferred to the HPLL-8001.
Programmable Dividers ( N and A Counter Registers)
Dual Mode
0
1
N1 N2 N3
..........
N12 N13 N14 A1
A2
A3
A4
A5
A6 A7
Single Mode
0
1
N1
N2
N3
N4
N5
N6
N7
N8
N10 N11 N12 N13 N14
Note: N14 is the MSB of the N counter value. A7 is the MSB of the A counter value. A7 is the first bit which is transferred
to the HPLL-8001.
9
Status Registers
1
0
B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B1 is the first bit which is transferred to the HPLL-8001.
B1:
B1
0
Counter loading
asynchronous counter load
synchronous counter load
1
B2 and B3:
B2
0
B3
0
PO1
PO2
Modes
F
F
Test Modes
RN
VN
0
1
φV
φVN
φRN
φRN
External Charge Pump, Mode 1
External Charge Pump, Mode 2
Internal Charge Pump mode
1
0
1
1
PROBIT
I
REF
B4:
B2
0
PD Polarity
negative
1
positive
positive means increasing VCO
frequency with increasing voltage
B5 and B6:
B5
B6
Modes
Standby 2 Standby 1
0
0
1
0
1
0
Standby mode 1: All functions
powered down
Standby mode 2: Counters, charge pump,
and outputs are off. Only preamplifiers
stay active
1
1
Normal operation: All functions are active
B7 and B8:
Anti Backlash Pulse Width
B8
0
B7
0
Typical
Unit
ns
10
6
0
1
ns
1
0
4
ns
1
1
2
ns
10
B9 and B10:
B9
B10
Modes
Single/Dual Preamplifier
Mode
Select
0
0
1
1
0
1
0
1
VCOI input: single HF mode
VCOI input: single LF mode
VCOI input: dual mode, VCOI trigger LH edge
VCOI input: dual mode, VCOI trigger HL edge
B11:
B11
Output bit PROBIT on PO1
0
1
0
1
B12, B13, and B14:
VDD = 4.5 – 5.5V
B14 B13
B12
Charge pump current
Typ.
0.15
0.21
0.31
0.44
0.63
0.89
1.26
1.69
0.1
Units
mA
mA
mA
mA
mA
mA
mA
mA
nA
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
Standby
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
0.14
0.20
0.29
0.40
0.58
0.79
1.06
1.26
0.1
mA
mA
mA
mA
mA
mA
mA
mA
nA
0
1
VDD = 2.7 – 3.3V
1
0
0
1
1
Standby
Reduced Status Register
0
0
B14 B13 B12 B11
B11 is the first bit which is transferred to the HPLL-8001.
11
Programming
The HPLL-8001 can be
2) programming of the R counter
Functional Description
Frequency Divider
The division ratio can be
programmed through a 3-wire
interface. Four different words
can be sent over this interface to
program the internal registers. All
four words consists of a 2-bit
address and a variable data
portion. When EN= L, the data is
transferred. It is loaded into the
internal registers at the rising
edge of EN. The last two bits
which are transferred, form the
address bits. When EN=H, the
input signals, CLK and DATA, are
internally disabled.
3) programming of the N, A
counters
calculated as follows:
FVCO = ( N x P + A) / R x
FREF where,
The rising edge of EN enables the
synchronous loading of all
counters at their zero value.
FVCO: Output frequency of the
external VCO
FREF: Reference oscillator
frequency
N: divide ratio of the N counter
3 ≤ N ≤ 16380
A: divide ratio of the A counter
0 ≤ A ≤ 127
R: divide ratio of the R counter
3 ≤ R ≤ 65535
P: divide ratio of the external dual
modulus prescaler
Standby
The HPLL-8001 has two standby
modes.
In standby mode 1, the whole
device is powered down with the
exception of the serial interface.
The Status registers contains all
status information.
In standby mode 2, the serial
interface and the input amplifiers
are active. All other parts are
powered down.
The reduced Status register is a
reduced version of the status
register.
Phase Detector and
Charge Pump
The phase detector is a digital,
edge-sensitive comparator with
UP and DOWN outputs. Both
outputs can be monitored at the
outputs PO1 and PO2. The phase
detector drives a charge pump,
which is a switch with a tristate
state. The output current can be
programmed in 8 steps between
0.15 mA and 1.69 mA (VDD = 4.5
to 5.5 V) with a reference current
of 100 µA.
The N and A counter register and
the R counter register contain the
applicable counter values.
The programming of the device
must start with the loading of the
status register.
The N, A and R counters can be
loaded synchronously or asyn-
chronously. If synchronous
loading is selected, all counters
are loaded when they reach the
value zero. As a result, the phase
difference between the divided
VCOI and REFI signal remains the
same.
If VCOI < REFI, the charge pump
delivers a positive current to the
external loop filter. If VCOI >
REFI, the charge pump sinks a
negative current from the external
loop filter. The charge pump
output can be inverted by
software.
For synchronous loading the
following order of programming
must be followed:
Anti-backlash pulses are gener-
ated to extend the very short
phase difference between VCOI
and REFI.
1) programming of synchronous
loading using the status
register
Part Number Ordering Information
Part Number
HPLL-8001-BLK
HPLL-8001-TR1
No. of Devices
Container
Tube
56
1000
7" Reel
Package Dimensions
JEDEC Standard SOP-14
Device Orientation
REEL
14
DIMENSIONS
SYMBOL
MIN.
MAX.
A
A1
b
D
E
e
H
L
1.35 (0.053)
0.080 (0.003)
0.330 (0.013)
8.56 (0.337)
3.81 (0.150)
2.01 (0.079)
0.300 (0.012)
0.510 (0.020)
8.89 (0.350)
4.09 (0.161)
HPLL
8001
YYWW
E
CARRIER
TAPE
H
1.27 BSC (0.500)
USER
FEED
DIRECTION
5.79 (0.151)
0.300 (0.012)
0
6.40 (0.252)
1.27 (0.050)
10
θ
COVER TAPE
Meets JEDEC outline dimensions.
Dimensions are in millimeters (inches).
Tolerances: .XX = ±.01, .XXX = ±.002
1
2
3
D
θ
A
b
e
L
A1
Tape Dimensions and Product Orientation
4.0 ± 0.1
1.75 ± 0.1
1.5 +0.1/-0.0 DIA.
2.0 ± 0.1
0.30 ± 0.05
7.5 ± 0.1
0.30 R MAX.
1
14
8
16.0 ± 0.3
9.5 ± 0.1
2.1 ± 0.1
7
1.5 MIN
0.5 RADIUS TYP
8.0 ± 0.1
6.5 ± 0.1
DIMENSIONS ARE SHOWN IN MILLIMETERS
www.hp.com/go/rf
For technical assistance or the location of
your nearest Hewlett-Packard sales office,
distributor or representative call:
Americas/Canada: 1-800-235-0312 or
408-654-8675
Far East/Australasia: Call your local HP
sales office.
Japan: (81 3) 3335-8152
Europe: Call your local HP sales office.
Data subject to change.
Copyright © 1998 Hewlett-Packard Co.
Printed in U.S.A.
5966-1495E (1/98)
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