HWD2119_技术文档

Audio Power Amplifier

HWD2119

350mW Audio Power Amplifier with Shutdown Mode

General Description

Key Specifications

n THD+N at 1kHz, 350mW continuous average output

The HWD2119 is a mono bridged power amplifier that is ca-

pable of delivering 350mW_RMSoutput power into a 16Ω load

or 300mW_RMSoutput power into an 8Ω load with 10%

THD+N from a 5V power supply.

power into 16Ω

n THD+N at 1kHz, 300mW continuous average output

power into 8Ω

10% (max)

n Shutdown Current

0.7µA (typ)

The HWD2119 audio power amplifier is designed specifically

to provide high quality output power and minimize PCB

area with surface mount packaging and a minimal amount

of external components. Since the HWD2119 does not

require output coupling capacitors, bootstrap capacitors or

snubber networks, it is optimally suited for low-power por-

table applications.

Features

n LLP, SOP, and MSOP surface mount packaging.

n Switch on/off click suppression.

n Unity-gain stable.

n Minimum external components.

The closed loop response of the unity-gain stable HWD2119

can be configured using external gain-setting resistors. The

device is available in LLP, MSOP, and SO package types to

suit various applications.

Applications

n General purpose audio

n Portable electronic devices

n Information Appliances (IA)

Typical Application

FIGURE 1. Typical Audio Amplifier Application Circuit

1

Connection Diagrams

Small Outline (SO) Package

SO Marking

HWD 2119 M

Top View

XY - Date Code

TT - Die Traceability

Bottom 2 lines - Part Number

Top View

Order Numer HWD2119M

Mini Small Outline (MSOP) Package

MSOP Marking

Top View

Order Number HWD2119MM

19 -HWD2119MM

LLP Package

Top View

Order Number HWD2119LD

1

Absolute Maximum Ratings (Notes 2, 3)

If Military/Aerospace specified devices are required,

please contact the CSMSC Semiconductor Sales Office/

Distributors for availability and specifications.

Infrared (15 seconds)

Thermal Resistance

220˚C

θ_JC(MSOP)

θ_JA(MSOP)

θ_JC(SOP)

θ_JA(SOP)

θ_JA(LLP)

56˚C/W

210˚C/W

Supply Voltage

6.0V

−65˚C to +150˚C

−0.3V to V_DD+0.3V

Internally Limited

3.5kV

35˚C/W

Storage Temperature

170˚C/W

Input Voltage

117˚C/W (Note 10)

150˚C/W (Note 11)

Power Dissipation (P_D) (Note 4)

ESD Susceptibility (Note 5)

ESD Susceptibility (Note 6)

Junction Temperature (T_J)

Soldering Information (Note 1)

Small Outline Package

Vapor Phase (60 seconds)

θ_JA(LLP)

Operating Ratings (Notes 2, 3)

250V

150˚C

Temperature Range

T_MIN≤ T_A≤ T_MAX

−40˚C ≤ T_A≤ 85˚C

2.0V ≤ V_CC≤ 5.5V

Supply Voltage

215˚C

Electrical Characteristics V_DD= 5V (Notes 2, 3)

The following specifications apply for V_DD= 5V, R_L= 16Ω unless otherwise stated. Limits apply for T_A= 25˚C.

HWD2119

Units

Symbol

Parameter

Conditions

Typical

(Note 7)

1.5

Limit

(Limits)

(Notes 8, 9)

I_DD

Quiescent Power Supply Current

Shutdown Current

V_IN= 0V, I_o= 0A

3.0

5.0

4.0

1.0

50

mA (max)

µA (max)

V (min)

V (max)

mV (max)

mW

I_SD

V_PIN1= V_DD(Note 12)

1.0

V_SDIH

V_SDIL

V_OS

Shutdown Voltage Input High

Shutdown Voltage Input Low

Output Offset Voltage

V_IN= 0V

5

THD = 10%, f_IN= 1kHz

THD = 10%, f_IN= 1kHz, R_L= 8Ω

350

300

1

P_O

Output Power

mW

THD+N

Total Harmonic Distortion + Noise

P_O= 270mW_RMS, A_VD= 2, f_IN

1kHz

=

%

Electrical Characteristics V_DD= 3V (Notes 2, 3)

The following specifications apply for V_DD= 3V and R_L= 16Ω load unless otherwise stated. Limits apply to T_A= 25˚C.

HWD2119

Units

Symbol

Parameter

Conditions

Typical

(Note 7)

1.0

Limit

(Limits)

(Notes 8, 9)

I_DD

Quiescent Power Supply Current

Shutdown Current

V_IN= 0V, I_o= 0A

3.0

5.0

2.4

0.6

50

mA (max)

µA (max)

V (min)

V (max)

mV

I_SD

V_PIN1= V_DD(Note 12)

0.7

V_SDIH

V_SDIL

V_OS

Shutdown Voltage Input High

Shutdown Voltage Input Low

Output Offset Voltage

V_IN= 0V

5

110

90

1

THD = 10%, f_IN= 1kHz

THD = 10%, f_IN= 1kHz, R_L= 8Ω

mW

P_O

Output Power

mW

THD+N

Total Harmonic Distortion + Noise

P_O= 80mW_RMS, A_VD= 2, f_IN

1kHz

=

%

2

Electrical Characteristics V_DD= 3V (Notes 2, 3)

The following specifications apply for V_DD= 3V and R_L= 16Ω load unless otherwise stated. Limits apply to T_A

=

25˚C. (Continued)

Note 1: See AN-450 ’Surface Mounting and their Effects on Product Reliability’ for other methods of soldering surface mount devices.

Note 2: All voltages are measured with respect to the ground pin, unless otherwise specified.

Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which

guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit

is given. However, the typical value is a good indication of device’s performance.

Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

, θ , and the ambient temperature T . The maximum

A

JMAX JA

allowable power dissipation is P

= (T

–T )/θ . For the HWD2119, T

= 150˚C and the typical junction-to-ambient thermal resistance (θ ) when board

JMAX JA

DMAX

JMAX

A

JA

mounted is 210˚C/W for the MSOP package and 170˚C/W for the SOP package.

Note 5: Human body model, 100pF discharged through a 1.5 kΩ resistor.

Note 6: Machine Model, 220pF–240pF capacitor is discharged through all pins.

Note 7: Typical specifications are specified at 25˚C and represent the parametric norm.

Note 8: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 9: Datasheet min/max specification limits are guaranteed by designs, test, or statistical analysis.

Note 10: The given θ is for an HWD2119 package in an LDA08B with the Exposed-DAP soldered to a printed circuit board copper pad with an area equivalent to

JA

that of the Exposed-DAP itself. The Exposed-DAP of the LDA08B package should be electrically connected to GND or an electrically isolated copper area.

Note 11: The given θ is for an HWD2119 package in an LDA08B with the Exposed-DAP not soldered to any printed circuit board copper.

JA

Note 12: The shutdown pin (pin1) should be driven as close as possible to V

for minimum current in Shutdown Mode.

DD

External Components Description (Figure 1)

Components

Functional Description

1.

R_i

Combined with R_f, this inverting input resistor sets the closed-loop gain. R_ialso forms a high pass filter with

C_iat f_c= 1/(2πR_iC_i).

2.

C_i

This input coupling capacitor blocks DC voltage at the amplifier’s terminals. Combined with R_i, it creates a

high pass filter with R_iat f_c= 1/(2πR_iC_i). Refer to the section, Proper Selection of External Components

for an explanation of how to determine the value of C_i.

3.

4.

R_f

Combined with R_i, this is the feedback resistor that sets the closed-loop gain: A_v= 2(R_F/R_i).

C_S

This is the power supply bypass capacitor that filters the voltage applied to the power supply pin. Refer to

the Application Information section for proper placement and selection of C_s.

5.

C_B

This is the bypass pin capacitor that filters the voltage at the BYPASS pin. Refer to the section, Proper

Selection of External Components, for information concerning proper placement and selection of C_B.

Typical Performance Characteristics

THD+N vs Frequency

3

Typical Performance Characteristics (Continued)

THD+N vs Frequency

THD+N vs Output Power

THD+N vs Frequency

THD+N vs Output Power

4

Typical Performance Characteristics (Continued)

THD+N vs Output Power

Output Power vs Supply Voltage

R_L= 8Ω

R_L= 16Ω

5

Typical Performance Characteristics (Continued)

Output Power vs Supply Voltage

Output Power vs Load Resistance

R_L= 32Ω

Power Dissipation vs

Output Power

V_DD= 5V

Power Dissipation vs

Output Power

V_DD= 3V

Power Derating Curves

Frequency Response vs

Input Capacitor Size

6

Typical Performance Characteristics (Continued)

Supply Current vs

Supply Voltage

8

For the micro MUA08A package, θ_JA= 210˚C/W, for the

M08A package, θ_JA= 170˚C/W , and T_JMAX= 150˚C for the

HWD2119. For a given ambient temperature,_AT, Equation (4)

can be used to find the maximum internal power dissipation

supported by the IC packaging. If the result of Equation (3) is

greater than the result of Equation (4), then decrease the

supply voltage, increase the load impedance, or reduce the

ambient temperature. For a typical application using the

M08A packaged HWD2119 with a 5V power supply and an 8Ω

load, the maximum ambient temperature that does not vio-

late the maximum junction temperature is approximately

42˚C. If a MUA08A packaged part is used instead with the

same supply voltage and load, the maximum ambient tem-

perature is 17˚C. In both cases, it is assumed that a device

is a surface mount part operating around the maximum

power dissipation point. The assumption that the device is

operating around the maximum power dissipation point is

incorrect for an 8Ω load. The maximum power dissipation

point occurs when the output power is equal to the maximum

power dissipation or 50% efficiency. The HWD2119 is not

capable of the output power level (633mW) required to op-

erate at the maximum power dissipation point for an 8Ω load.

To find the maximum power dissipation, the graph Power

Dissipation vs. Output Power must be used. From the

graph, the maximum power dissipation for an 8Ω load and a

5V supply is approximately 575mW. Substituting this value

back into equation (4) for P_DMAXand using θ_JA= 210˚C/W

for the MUA08A package, the maximum ambient tempera-

ture is calculated to be 29˚C. Using θ_JA= 170˚C/W for the

M08A package, the maximum ambient temperature is 52˚C.

Refer to the Typical Performance Characteristics curves

for power dissipation information for lower output powers

and maximum power dissipation for each package at a given

ambient temperature.

Application Information

BRIDGE CONFIGURATION EXPLANATION

As shown in Figure 1, the HWD2119 consist of two operational

amplifiers. External resistors, R_iand R_Fset the closed-loop

gain of the first amplifier (and the amplifier overall), whereas

two internal 20kΩ resistors set the second amplifier’s gain at

-1. The HWD2119 is typically used to drive a speaker con-

nected between the two amplifier outputs.

Figure 1 shows that the output of Amp1 servers as the input

to Amp2, which results in both amplifiers producing signals

identical in magnitude but 180˚ out of phase. Taking advan-

tage of this phase difference, a load is placed between V₀₁

and V₀₂and driven differentially (commonly referred to as

’bridge mode’). This results in a differential gain of

A

_VD= 2 *(R_f/R_i)

(1)

Bridge mode is different from single-ended amplifiers that

drive loads connected between a single amplifier’s output

and ground. For a given supply voltage, bridge mode has a

distinct advantage over the single-ended configuration: its

differential output doubles the voltage swing across the load.

This results in four times the output power when compared

to a single-ended amplifier under the same conditions. This

increase in attainable output assumes that the amplifier is

not current limited or the output signal is not clipped. To

ensure minimum output signal clipping when choosing an

amplifier’s closed-loop gain, refer to the Audio Power Am-

plifier Design Example section.

Another advantage of the differential bridge output is no net

DC voltage across the load. This results from biasing V₀₁

and V₀₂at half-supply. This eliminates the coupling capacitor

that single supply, single-ended amplifiers require. Eliminat-

ing an output coupling capacitor in a single-ended configu-

ration forces a single supply amplifier’s half-supply bias volt-

age across the load. The current flow created by the half-

supply bias voltage increases internal IC power dissipation

and may permanently damage loads such as speakers.

POWER SUPPLY BYPASSING

As with any power amplifier, proper supply bypassing is

critical for low noise performance and high power supply

rejection. The capacitors connected to the bypass and power

supply pins should be placed as close to the HWD2119 as

possible. The capacitor connected between the bypass pin

and ground improves the internal bias voltage’s stability,

producing improved PSRR. The improvements to PSRR

increase as the bypass pin capacitor value increases. Typi-

cal applications employ a 5V regulator with 10µF and 0.1µF

filter capacitors that aid in supply stability. Their presence,

however, does not eliminate the need for bypassing the

supply nodes of the HWD2119. The selection of bypass ca-

pacitor values, especially C_B, depends on desired PSRR

requirements, click and pop performance as explained in the

section, Proper Selection of External Components, as

well as system cost and size constraints.

POWER DISSIPATION

Power dissipation is a major concern when designing a

successful bridged or single-ended amplifier. Equation (2)

states the maximum power dissipation point for a single-

ended amplifier operating at a given supply voltage and

driving a specified load.

2

P_DMAX= (V_DD

)

/(2π²R_L) (W) Single-ended

(2)

However, a direct consequence of the increased power de-

livered to the load by a bridged amplifier is an increase in the

internal power dissipation point for a bridge amplifier oper-

ating at the same given conditions. Equation (3) states the

maximum power dissipation point for a bridged amplifier

operating at a given supply voltage and driving a specified

load.

SHUTDOWN FUNCTION

P_DMAX= 4(V_DD)²/(2π²R_L) (W) Bridge Mode

(3)

The voltage applied to the HWD2119’s SHUTDOWN pin con-

trols the shutdown function. Activate micro-power shutdown

by applying V_DDto the SHUTDOWN pin. When active, the

HWD2119’s micro-power shutdown feature turns off the ampli-

fier’s bias circuitry, reducing the supply current. The logic

threshold is typically 1/2V_DD. The low 0.7µA typical shut-

down current is achieved by applying a voltage that is as

near as V_DDas possible to the SHUTDOWN pin. A voltage

that is less than V_DDmay increase the shutdown current.

Avoid intermittent or unexpected micro-power shutdown by

ensuring that the SHUTDOWN pin is not left floating but

connected to either V_DDor GND.

The HWD2119 has two operational amplifiers in one package

and the maximum internal power dissipation is four times

that of a single-ended amplifier. However, even with this

substantial increase in power dissipation, the HWD2119 does

not require heatsinking. From Equation (3), assuming a 5V

power supply and an 8Ω load, the maximum power dissipa-

tion point is 633mW. The maximum power dissipation point

obtained from Equation (3) must not exceed the power dis-

sipation predicted by Equation (4):

P_DMAX= (T_JMAX- T_A)/θ_JA(W)

(4)

9

f_-3dB= 1/(2 πR_iC_i) (Hz)

(5)

Application Information (Continued)

As an example when using a speaker with a low frequency

limit of 150Hz, C_i, using Equation (5) is 0.063µF. The 0.39µF

C_ishown in Figure 1 allows the HWD2119 to drive a high

efficiency, full range speaker whose response extends down

to 20Hz.

There are a few ways to activate micro-power shutdown.

These included using a single-pole, single-throw switch, a

microcontroller, or a microprocessor. When using a switch,

connect an external 10kΩ to 100kΩ pull-up resistor between

the SHUTDOWN pin and V_DD. Connect the switch between

the SHUTDOWN pin and ground. Select normal amplifier

operation by closing the switch. Opening the switch con-

nects the shutdown pin to V_DDthrough the pull-up resistor,

activating micro-power shutdown. The switch and resistor

guarantee that the SHUTDOWN pin will not float. This pre-

vents unwanted state changes. In a system with a micropro-

cessor or a microcontroller, use a digital output to apply the

control voltage to the SHUTDOWN pin. Driving the SHUT-

DOWN pin with active circuitry eliminates the pull-up resistor

Besides optimizing the input capacitor value, the bypass

capacitor value, C_Brequires careful consideration. The by-

pass capacitor’s value is the most critical to minimizing

turn-on pops because it determines how fast the HWD2119

turns on. The slower the HWD2119’s outputs ramp to their

quiescent DC voltage (nominally 1/2V_DD), the smaller the

turn-on pop. While the device will function properly (no os-

cillations or motorboating), with C_Bless than 1.0µF, the

device will be much more susceptible to turn-on clicks and

pops. Thus, a value of C_Bequal to or greater than 1.0µF is

recommended in all but the most cost sensitive designs.

PROPER SELECTION OF EXTERNAL COMPONENTS

Optimizing the HWD2119’s performance requires properly se-

lecting external components. Though the HWD2119 operates

well when using external components with wide tolerances,

best performance is achieved by optimizing component val-

ues.

Bypass Capacitor Value Selection

Besides minimizing the input capacitor size, careful consid-

eration should be paid to the value of C_B, the capacitor

connected to the BYPASS pin. Since C_Bdetermines how

fast the HWD2119 settles to quiescent operation, its value is

critical when minimizing turn-on pops. The slower the

HWD2119’s outputs ramp to their quiescent DC voltage (nomi-

nally 1/2V_DD), the smaller the turn-on pop. Choosing C_B

equal to 1.0µF along with a small value of C_i(in the range of

0.1µF to 0.39µF) produces a click-less and pop-less shut-

down function. As discussed above, choosing C_ino larger

than necessary for the desired bandwidth helps minimize

clicks and pops.

The HWD2119 is unity gain stable, giving the designer maxi-

mum design flexibility. The gain should be set to no more

than a given application requires. This allows the amplifier to

achieve minimum THD+N and maximum signal-to-noise ra-

tio. These parameters are compromised as the closed-loop

gain increases. However, low gain demands input signals

with greater voltage swings to achieve maximum output

power. Fortunately, many signal sources such as audio CO-

DECs have outputs of 1V_RMS(2.83V_P-P). Please refer to the

Audio Power Amplifier Design section for more informa-

tion on selecting the proper gain.

Optimizing Click and Pop Reduction Performance

The HWD2119 contains circuitry that minimizes turn-on and

shutdown transients or ’clicks and pops’. For this discussion,

turn on refers to either applying the power or supply voltage

or when the shutdown mode is deactivated. While the power

supply is ramping to it’s final value, the HWD2119’s internal

amplifiers are configured as unity gain buffers. An internal

current source charges the voltage of the bypass capacitor,

C_B, connected to the BYPASS pin in a controlled, linear

manner. Ideally, the input and outputs track the voltage

charging on the bypass capacitor. The gain of the internal

amplifiers remains unity until the bypass capacitor is fully

charged to 1/2V_DD. As soon as the voltage on the bypass

capacitor is stable, the device becomes fully operational.

Although the BYPASS pin current cannot be modified,

changing the size of the bypass capacitor, C_B, alters the

device’s turn-on time and magnitude of ’clicks and pops’.

Increasing the value of C_Breduces the magnitude of turn-on

pops. However, this presents a tradeoff: as the size of C_B

increases, the turn-on time (Ton) increases. There is a linear

relationship between the size of C_Band the turn on time.

Below are some typical turn-on times for various values of

C_B:

Another important consideration is the amplifier’s close-loop

bandwidth. To a large extent, the bandwidth is dictated by

the choice of external components shown in Figure 1. The

input coupling capacitor, C_i, forms a first order high pass filter

that limits low frequency response. This value should be

chosen based on needed frequency response for a few

distinct reasons discussed below

Input Capacitor Value Selection

Amplifying the lowest audio frequencies requires a high

value input coupling capacitor (C_iin Figure 1). A high value

capacitor can be expensive and may compromise space

efficiency in portable designs. In many cases the speakers

used in portable systems, whether internal or external, have

little ability to reproduce signals below 150Hz. Applications

using speakers with limited frequency response reap little

improvement by using a large input capacitor.

Besides affecting system cost and size, C_ihas an effect on

the HWD2119’s click and pop performance. When the supply

voltage is first applied, a transient (pop) is created as the

charge on the input capacitor changes from zero to a quies-

cent state. The magnitude of the pop is directly proportional

to the input capacitor’s value. Higher value capacitors need

C_B

T_ON

20ms

0.01µF

0.1µF

0.22µF

0.47µF

1.0µF

more time to reach a quiescent DC voltage (usually 1/2 V_DD

)

when charged with a fixed current. The amplifier’s output

charges the input capacitor through the feedback resistor,

R_F. Thus, selecting an input capacitor value that is no higher

than necessary to meet the desired -3dB frequency can

minimize pops.

200ms

440ms

940ms

2S

As shown in Figure 1, the input resistor (R_i) and the input

capacitor, C_iproduce a -3dB high pass filter cutoff frequency

that is found using Equation (5).

10

The last step in this design example is setting the amplifier’s

Application Information (Continued)

±

-3dB frequency bandwidth. To achieve the desired 0.25dB

In order to eliminate ’clicks and pops’, all capacitors must be

discharged before turn-on. Rapidly switching V_DDmay not

allow the capacitors to fully discharge, which may cause

’clicks and pops’.

pass band magnitude variation limit, the low frequency re-

sponse must extend to at least one-fifth the lower bandwidth

limit and the high frequency response must extend to at least

five times the upper bandwidth limit. The gain variation for

±

both response limits is 0.17dB, well with in the 0.25dB

desired limit.

AUDIO POWER AMPLIFIER DESIGN EXAMPLE

The results are:

The following are the desired operational

parameters:

f_L= 100Hz/5 = 20Hz

f_H= 20 kHz*5 = 100kHz

Given:

As mentioned in the External Components section, R_iand

C_icreate a high pass filter that sets the amplifier’s lower

band pass frequency limit. Find the coupling capacitor’s

value using Equation (8).

Power Output

Load Impedance

Input Level

100mW

16Ω

1Vrms (max)

20kΩ

Input Impedance

Bandwidth

C_i≥ 1/(2πR_if_c) (F)

(8)

±

100Hz–20kHz 0.25dB

C_i≥ 0.398µF, a standard value of 0.39µF will be used. The

product of the desired high frequency cutoff (100kHz in this

example) and the differential gain, A_VD, determines the up-

The design begins by specifying the minimum supply voltage

necessary to obtain the specified output power. To find this

minimum supply voltage, use the Output Power vs. Supply

Voltage graph in the Typical Performance Characteristics

section. From the graph for a 16Ω load, (graphs are for 8Ω,

16Ω, and 32Ω loads) the supply voltage for 100mW of output

power with 1% THD+N is approximately 3.15 volts.

per pass band response limit. With A_VD= 1.27 and f_H

=

100kHz, the closed-loop gain bandwidth product (GBWP) is

127kHz. This is less than the HWD2119’s 900kHz GBWP. With

this margin the amplifier can be used in designs that require

more differential gain while avoiding performance restricting

bandwidth limitations.

Additional supply voltage creates the benefit of increased

headroom that allows the HWD2119 to reproduce peaks in

excess of 100mW without output signal clipping or audible

distortion. The choice of supply voltage must also not create

a situation that violates maximum dissipation as explained

above in the Power Dissipation section. For example, if a

3.3V supply is chosen for extra headroom then according to

Equation (3) the maximum power dissipation point with a

16Ω load is 138mW. Using Equation (4) the maximum am-

bient temperature is 121˚C for the MUA08A package and

126˚C for the M08A package.

After satisfying the HWD2119’s power dissipation require-

ments, the minimum differential gain is found using Equation

(6).

(6)

Thus a minimum gain of 1.27 V/V allows the HWD2119 to

reach full output swing and maintain low noise and THD+N

performance. For this example, let A_VD= 1.27. The amplifi-

er’s overall gain is set using the input (R_i) and feedback (R_F)

resistors. With the desired input impedance set to 20kΩ, the

feedback resistor is found using Equation (7).

R_F/R_i= A_VD/2 (V/V)

The value of R_Fis 13kΩ.

(7)

11

Application Information (Continued)

HIGHER GAIN AUDIO AMPLIFIER

Figure 2

The HWD2119 is unity-gain stable and requires no external

components besides gain-setting resistors, an input coupling

capacitor, and proper supply bypassing in the typical appli-

cation. However, if a closed-loop differential gain of greater

than 10 is required, a feedback capacitor (C₄) may be

needed as shown in Figure 2 to bandwidth limit the amplifier.

This feedback capacitor creates a low pass filter that elimi-

nates possible high frequency oscillations. Care should be

taken when calculating the -3dB frequency in that an incor-

rect combination of R₃and C₄will cause rolloff before

20kHz. A typical combination of feedback resistor and ca-

pacitor that will not produce audio band high frequency rolloff

is R₃= 20kΩ and C₄= 25pF. These components result in a

-3dB point of approximately 320 kHz. It is not recommended

that the feedback resistor and capacitor be used to imple-

ment a band limiting filter below 100kHz.

12

Application Information (Continued)

DIFFERENTIAL AMPLIFIER CONFIGURATION FOR HWD2119

Figure 3

13

Application Information (Continued)

REFERENCE DESIGN BOARD and PCB LAYOUT GUIDELINES

Figure 4

14

Application Information (Continued)

HWD2119 SO DEMO BOARD ARTWORK

Silk Screen

Top Layer

Bottom Layer

15

Application Information (Continued)

HWD2119 LD DEMO BOARD ARTWORK

Silk Screen

Composite View

Bottom Layer

Top Layer

16

Application Information (Continued)

Mono HWD2119 Reference Design Boards

Bill of Material for all Demo Boards

Item

Part Number

Part Description

Qty

Ref Designator

1

551011208-001 HWD2119 Mono Reference Design Board

1

10

20

21

25

30

35

482911183-001

151911207-001

151911207-002

152911207-001

472911207-001

210007039-002

HWD2119 Audio AMP

Tant Cap 1uF 16V 10

1

U1

C1

1

3

2

Cer Cap 0.39uF 50V Z5U 20% 1210

Tant Cap 1uF 16V 10

C2

C3

Res 20K Ohm 1/10W 5

R1, R2, R3

J1, J2

Jumper Header Vertical Mount 2X1

0.100

PCB LAYOUT GUIDELINES

Single-Point Power / Ground Connections

This section provides practical guidelines for mixed signal

PCB layout that involves various digital/analog power and

ground traces. Designers should note that these are only

’rule-of-thumb’ recommendations and the actual results will

depend heavily on the final layout.

The analog power traces should be connected to the digital

traces through a single point (link). A ’Pi-filter’ can be helpful

in minimizing high frequency noise coupling between the

analog and digital sections. It is further recommended to put

digital and analog power traces over the corresponding digi-

tal and analog ground traces to minimize noise coupling.

General Mixed Signal Layout Recommendation

Placement of Digital and Analog Components

Power and Ground Circuits

All digital components and high-speed digital signals traces

should be located as far away as possible from analog

components and circuit traces.

For two layer mixed signal design, it is important to isolate

the digital power and ground trace paths from the analog

power and ground trace paths. Star trace routing techniques

(bringing individual traces back to a central point rather than

daisy chaining traces together in a serial manner) can have

a major impact on low level signal performance. Star trace

routing refers to using individual traces to feed power and

ground to each circuit or even device. This technique will

take require a greater amount of design time but will not

increase the final price of the board. The only extra parts

required will be some jumpers.

Avoiding Typical Design / Layout Problems

Avoid ground loops or running digital and analog traces

parallel to each other (side-by-side) on the same PCB layer.

When traces must cross over each other do it at 90 degrees.

Running digital and analog traces at 90 degrees to each

other from the top to the bottom side as much as possible will

minimize capacitive noise coupling and cross talk.

17

Physical Dimensions inches (millimeters) unless otherwise noted

MSOP

Order Number HWD2119MM

18

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

SO

Order Number HWD2119M

19

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

LLP

Order Number HWD2119LD

20


型号：	HWD2119
厂家：	ETC
描述：	350mWAudio Power Amplifier with Shutdown Mode 350mWAudio功率放大器关断模式放大器功率放大器
文件：	总21页 (文件大小：868K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HWD2119 [ETC]

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