HY62256ALR1-55_技术文档

HY62256A Series

32Kx8bit CMOS SRAM

DESCRIPTION

FEATURES

The HY62256A is a high-speed, low power and

32,786 x 8-bits CMOS Static Random Access

·

Fully static operation and Tri-state output

TTL compatible inputs and outputs

Low power consumption

Battery backup(L/LL-part)

- 2.0V(min.) data retention

Standard pin configuration

- 28 pin 600 mil PDIP

- 28 pin 330mil SOP

- 28 pin 8x13.4 mm TSOP-I

(Standard and Reversed)

Memory fabricated using

Hyundai's high

performance CMOS process technology. The

HY62256A has a data retention mode that

guarantees data to remain valid at the minimum

power supply voltage of 2.0 volt. Using the CMOS

technology, supply voltages from 2.0 to 5.5volt

has little effect on supply current in the data

retention mode. The HY62256A is suitable for use

in low voltage operation and battery back-up

application.

·

Product

No.

HY62256A

Voltage

(V)

Speed

(ns)

55/70/85

Operation

Current(mA)

50

Standby Current(uA)

Temperature

(°C)

0~70(Normal)

L

100

LL

25

5.0

1mA

Note 1. Current value is max.

PIN CONNECTION

Vcc

A14

A12

A7

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

A14

A12

A7

Vcc

/WE

A13

A8

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

/WE

A13

A8

/OE

A11

A9

A10

/CS

I/O8

I/O7

I/O6

I/O5

I/O4

Vss

I/O3

I/O2

I/O1

A0

A3

A4

A2

3

1

2

28

14

13

12

11

10

9

15

16

17

18

19

20

21

22

23

24

25

26

27

28

3

A1

27

26

25

24

23

22

21

20

19

18

17

16

15

A6

4

A6

4

A5

A0

3

A9

A5

5

A5

A9

5

A8

A6

I/O1

I/O2

I/O3

Vss

I/O4

I/O5

I/O6

I/O7

I/O8

/CS

A10

4

A4

A11

/OE

A10

/CS

I/O8

I/O7

I/O6

I/O5

I/O4

6

A11

/OE

A10

/CS

I/O8

I/O7

I/O6

I/O5

I/O4

A4

6

A13

/WE

Vcc

A14

A12

A7

5

A3

7

A3

7

A12

A14

Vcc

/WE

A13

A8

6

A2

8

A2

7

8

A1

8

7

A1

9

6

A0

10

11

12

13

14

A0

10

11

12

13

14

10

11

12

13

14

5

I/O1

I/O2

I/O3

Vss

I/O1

I/O2

I/O3

Vss

A6

4

A5

A9

A11

/OE

3

A4

A1

2

1

A3

A2

PDIP

SOP

TSOP-I(Standard)

TSOP-I(Reversed)

PIN DESCRIPTION

BLOCK DIAGRAM

ROW DECODER

I/O1

A0

Pin Name

Pin Function

Chip Select

Write Enable

/CS

/WE

MEMORY ARRAY

512x512

/OE

Output Enable

Address Inputs

Data Input/Output

Power(+5.0V)

Ground

A0 ~ A14

I/O1 ~ I/O8

Vcc

A14

I/O8

/CS

Vss

/OE

/WE

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev.02 /Jun.99

Hyundai Semiconductor

HY62256A Series

ORDERING INFORMATION

Part No.

HY62256AP

HY62256ALP

HY62256ALLP

HY62256AJ

HY62256ALJ

HY62256ALLJ

HY62256AT1

HY62256ALT1

HY62256ALLT1

HY62256AR1

HY62256ALR1

HY62256ALLR1

Speed

55/70/85

Power

Package

PDIP

SOP

L-part

LL-part

L-part

LL-part

TSOP-I Standard

TSOP-I Reversed

L-part

LL-part

L-part

LL-part

ABSOLUTE MAXIMUM RATING (1)

Symbol

Vcc, VIN, VOUT

TA

TSTG

PD

Parameter

Power Supply, Input/Output Voltage

Operating Temperature

Storage Temperature

Power Dissipation

Rating

-0.5 to 7.0

0 to 70

-65 to 150

1.0

Unit

V

°C

W

IOUT

TSOLDER

Data Output Current

Lead Soldering Temperature & Time

50

260 · 0

mA

°C·sec

Note

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent

damage to the device. This is stress rating only and the functional operation of the device under these or

any other conditions above those indicated in the operation of this specification is not implied.

Exposure to the absolute maximum rating conditions for extended period may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

TA=0°C to 70°C

Symbol

Vcc

VIH

Parameter

Min.

4.5

2.2

Typ.

5.0

-

Max.

5.5

Vcc+0.5

0.8

Unit

V

Power Supply Voltage

Input High Voltage

Input Low Voltage

VIL

-0.5(1)

V

Note

1. VIL = -3.0V for pulse width less than 30ns

TRUTH TABLE

/CS

H

L

/WE /OE

MODE

Standby

Output Disabled High-Z

Read

Write

I/O OPERATION

High-Z

X

H

L

X

H

L

Data Out

Data In

X

Note :

1. H=VIH, L=VIL, X=Don't Care

Rev.02 /Jun.99

2

HY62256A Series

DC CHARACTERISTICS

Vcc = 5V±10%, TA = 0°C to 70°C (Normal) unless otherwise specified

Symbol

ILI

ILO

Parameter

Input Leakage Current

Output Leakage Current

Test Condition

Vss < VIN <.Vcc

Vss < VOUT < Vcc, /CS = VIH or

/OE = VIH or /WE = VIL

/CS = VIL,

VIN = VIH or VIL, II/O = 0mA

/CS = VIL,

Min. Duty Cycle = 100%, II/O = 0mA

/CS= VIH VIN = VIH or VIL

Min. Typ. Max. Unit

-1

-

1

uA

Icc

Operating Power Supply

Current

Average Operating Current

-

30

40

50

70

2

mA

ICC1

ISB

TTL Standby Current

(TTL Inputs)

0.4

ISB1

CMOS Standby Current

(CMOS Inputs)

/CS > Vcc - 0.2V

-

2

1

-

1

100

25

0.4

-

mA

uA

V

VIN < 0.2V or

VIN > Vcc – 0.2V

IOL = 2.1mA

IOH = -1mA

L

LL

VOL

VOH

Output Low Voltage

Output High Voltage

-

2.4

-

V

Note : Typical values are at Vcc =5.0V, TA = 25°C

AC CHARACTERISTICS

Vcc = 5V±10%, TA = 0°C to 70°C (Normal) unless otherwise specified.

-55

-70

Max. Min

-85

#

Parameter

Unit

Symbol

Min.

Max. Min.

Max.

READ CYCLE

1

2

3

4

5

6

7

8

9

TRC

TAA

Read Cycle Time

Address Access Time

Chip Select Access Time

Output Enable to Output Valid

Chip Select to Output in Low Z

Output Enable to Output in Low Z

Chip Deselection to Output in High Z

55

-

70

-

85

-

ns

55

30

-

70

35

-

85

45

-

TACS

TOE

TCLZ

TOLZ

TCHZ

-

5

0

5

0

5

0

5

-

20

-

30

-

30

-

TOHZ Out Disable to Output in High Z

TOH

Output Hold from Address Change

WRITE CYCLE

10 TWC

11 TCW

12 TAW

13 TAS

14 TWP

15 TWR

Write Cycle Time

55

50

0

40

0

25

0

-

20

-

70

65

0

50

0

35

0

-

30

-

85

75

0

55

0

40

0

-

30

-

ns

Chip Selection to End of Write

Address Valid to End of Write

Address Set-up Time

Write Pulse Width

Write Recovery Time

16 TWHZ Write to Output in High Z

17 TDW

18 TDH

19 TOW

Data to Write Time Overlap

Data Hold from Write Time

Output Active from End of Write

5

Rev.02 /Jun.99

3

HY62256A Series

AC TEST CONDITIONS

TA = 0°C to 70°C (Normal) unless otherwise specified.

PARAMETER

Input Pulse Level

VALUE

0.8V to 2.4V

Input Rise and Fall Time

5ns

Input and Output Timing Reference Levels

1.5V

Output Load

70/85/100ns

55ns

CL = 100pF + 1TTL Load

CL = 50pF + 1TTL Load

AC TEST LOADS

TTL

CL(1)

Note : Including jig and scope capacitance

CAPACITANCE

TA = 25°C, f = 1.0MHz

Symbol

CIN

CI/O

Parameter

Input Capacitance

Input /Output Capacitance

Condition

VIN = 0V

VI/O = 0V

Max.

6

8

Unit

pF

Note : These parameters are sampled and not 100% tested

TIMING DIAGRAM

READ CYCLE 1

tRC

ADDR

tAA

OE

tOE

tOH

tOLZ

CS

tACS

tCLZ

tOHZ

tCHZ

High-Z

Data

Out

Data Valid

Rev.02 /Jun.99

4

HY62256A Series

Note(READ CYCLE):

1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not

referenced to output voltage levels.

2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device

and from device to device.

3. /WE is high for the read cycle.

READ CYCLE 2

tRC

ADDR

tAA

tOH

Data

Out

Previous Data

Data Valid

Note(READ CYCLE):

1. /WE is high for the read cycle.

2. Device is continuously selected /CS= VIL.

3. /OE =VIL.

WRITE CYCLE 1(/OE Clocked)

tWC

ADDR

OE

tAW

tCW

CS

tAS

tWR

tWP

WE

tDW

tDH

Data Valid

Data In

tOHZ

Data

Out

Rev.02 /Jun.99

5

HY62256A Series

WRITE CYCLE 2 (/OE Low Fixed)

tWC

ADDR

tAW

tCW

tWR

CS

tAS

tWP

WE

tDW

tDH

Data Valid

tOW

Data In

tWHZ

(8)

(7)

Data

Out

Notes(WRITE CYCLE):

1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition

among /CS going low and /WE going low: A write ends at the earliest transition among /CS going high

and /WE going high. tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the later of /CS going low to the end of write .

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as /CS,

or /WE going high.

5. If /OE and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state,

input of opposite phase of the output must not be applied because bus contention can occur.

6. If /CS goes low simultaneously with /WE going low, or after /WE going low, the outputs remain in high

impedance state.

7. DOUT is the same phase of latest written data in this write cycle.

8. DOUT is the read data of the new address.

DATA RETENTION CHARACTERISTIC

Symbol

VDR

ICCDR

Parameter

Vcc for Data Retention

Data Retention Current

Test Condition

/CS >Vcc-0.2V,Vss<VIN<Vcc

Vcc = 3.0V, /CS > Vcc –0.2V

Vss<VIN<Vcc

See Data Retention Timing

Diagram

Min

2

-

0

Typ

Max

-

50

15(2)

-

Unit

V

uA

ns

-

1

-

L

LL

tCDR

tR

Chip Disable to Data

Retention Time

Operating Recovery Time

tRC(3)

-

ns

Notes

1. Typical values are under the condition of TA = 25°C.

2. 3uA max. at TA=0°C to 40 °C.

3. tRC is read cycle time.

Rev.02 /Jun.99

6

HY62256A Series

Data Retention Timing Diagram

DATA RETENTION MODE

VCC

4.5V

tCDR

tR

2.2V

VDR

CS>VCC-0.2V

CS

VSS

RELIABILITY SPEC.

TEST MODE

TEST SPEC.

ESD

HBM

MM

>2000V

> 250V

LATCH - UP

< -100mA

> 100mA

PACKAGE INFORMATION

28pin 600mil Dual In-Line Package(P)

·

MAX.

UNIT : INCH(mm)

MIN.

1.467(37.262)

1.447(36.754)

0.600(15.240)BSC

0.065(1.650)

0.050(1.270)

0.090(2.286)

0.070(1.778)

0.550(13.970)

0.530(13.462)

0.155(3.937)

0.145(3.683)

0.035(0.889)

0.020(0.508)

0.140(3.556)

0.120(3.048)

3 deg

11 deg

0.014(0.356)

0.008(0.200)

0.021(0.533)

0.015(0.381)

0.100(2.54)BSC

Rev.02 /Jun.99

7

HY62256A Series

28pin 330mil Small Outline Package(J)

MAX

MIN.

UNIT : INCH(mm)

0.346(8.788)

0.338(8.585)

0.480(12.192)

0.460(11.684)

0.110(2.794)

0.094(2.388)

0.014(0.356)

0.002(0.051)

0.728(18.491)

0.720(18.288)

0.012(0.305)

0.008(0.203)

0.050(1.270)

0.030(0.762)

0.050(1.270)BSC

0.020(0.508)

0.014(0.356)

28pin 8x13.4mm Thin Small Outline Package Standard(T1)

MAX.

MIN.

UNIT : INCH(mm)

0.468(11.9)

0.460(11.7)

0.536(13.6)

0.520(13.2)

0.319(8.1)

0.311(7.9)

0.040(1.02)

0.036(0.91)

0.008(0.20)

0.002(0.05)

0.008(0.2)

0.027(0.7)

0.022(0.55 BSC)

0.004(0.1)

0.012(0.3)

Rev.02 /Jun.99

8

HY62256A Series

28pin 8x13.4mm Thin Small Outline Package Reversed(R1)

MAX.

MIN.

UNIT : INCH(mm)

0.468(11.9)

0.460(11.7)

0.536(13.6)

0.520(13.2)

0.319(8.1)

0.311(7.9)

0.040(1.02)

0.036(0.91)

0.008(0.20)

0.002(0.05)

0.008(0.2)

0.027(0.7)

0.012(0.3)

0.022(0.55 BSC)

0.004(0.1)

Rev.02 /Jun.99

9


型号：	HY62256ALR1-55
厂家：	ETC
描述：	x8 SRAM X8 SRAM\n 静态存储器
文件：	总9页 (文件大小：146K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HY62256ALR1-55 [ETC]

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