HYB25R72180C-645_技术文档

Direct RDRAM^™

®

72-Mbit (256Kx16/18x16d)

RAMBUS

Overview

The Rambus Direct RDRAM™ is a general purpose

high-performance memory device suitable for use in a

broad range of applications including computer

memory, graphics, video, and any other application

where high bandwidth and low latency are required.

The 72-Mbit Direct Rambus DRAMs (RDRAM ) are

extremely high-speed CMOS DRAMs organized as 4M

words by 18 bits. The use of Rambus Signaling Level

(RSL) technology permits 600MHz to 800MHz transfer

rates while using conventional system and board

design technologies. Direct RDRAM devices are

capable of sustained data transfers at 1.25 ns per two

bytes (10ns per sixteen bytes).

The architecture of the Direct RDRAMs allows the

highest sustained bandwidth for multiple, simulta-

neous randomly addressed memory transactions. The

separate control and data buses with independent row

and column control yield over 95% bus efficiency. The

Direct RDRAM's sixteen banks support up to four

simultaneous transactions.

Figure 1: Direct RDRAM CSP Package

The 72-Mbit Direct RDRAMs are offered in a CSP hori-

zontal package suitable for desktop as well as low-

profile add-in card and mobile applications.

System oriented features for mobile, graphics and large

memory systems include power management, byte

masking, and x18 organization. The two data bits in the

x18 organization are general and can be used for addi-

tional storage and bandwidth or for error correction.

Direct RDRAMs operate from a 2.5 volt supply.

Key Timing Parameters/Part Number

I/O Freq.

MHz

Part

Number

Organization

trac

Features

4M x 18

600

711

800

53 ns HYB25R72180C-653

45 ns HYB25R72180C-745

50 ns HYB25R72180C-750

45 ns HYB25R72180C-645

45 ns HYB25R72180C-845

40 ns HYB25R72180C-840

■

Highest sustained bandwidth per DRAM device

- 1.6GB/ s sustained data transfer rate

- Separate control and data buses for maximized

efficiency

- Separate row and column control buses for

easy scheduling and highest performance

- 16 banks: four transactions can take place simul-

taneously at full bandwidth data rates

■

Low latency features

- Write buffer to reduce read latency

- 3 precharge mechanisms for controller flexibility

- Interleaved transactions

Advanced power management:

- Multiple low power states allows flexibility in

power consumption versus time to transition to

active state

- Power-down self-refresh

■

Organization: 1Kbyte pages and 16 banks, x 18

- x18 organization allows ECC configurations or

increased storage/ bandwidth

Uses Rambus Signaling Level (RSL) for up to

800MHz operation

INFINEON Technologies Version 1.0

Preliminary Information

Page 1

Direct RAMBUS 72 Mbit (256kx18x16d)

mounted on the circuit board). The mechanical dimen-

sions of this package are shown in a later sectio. Refer

to Section "Center-Bonded uBGA Package" on page 60.

Note - pin #1 is at the A1 position. Also, note that rows

1 and 12 can be deleted for components in which these

rows do not fall within die boundaries.

Pinouts and Definitions

Center-Bonded Devices - Preliminary

This table shows the pin assignments of the center-

bonded RDRAM package from the top-side of the

package (the view looking down on the package as it is

Table 1: Center-Bonded Device (top view)

DQA7

GND

CMD

DQA4

VDD

CFM

GND

CFMN

GNDa

VDDa

RQ5

VDD

RQ6

RQ3

GND

RQ2

DQB0

VDD

DQB4

VDD

DQB7

GND

SIO1

8

7

6

5

4

3

2

1

DQA5

DQA2

DQB1

DQB5

SCK

VCMOS

DQA8

DQA6

GND

DQA1

VDD

VREF

GND

RQ7

GND

CTM

RQ1

VDD

RQ4

DQB2

GND

RQ0

DQB6

GND

SIO0

VCMOS

DQB8

DQA3

DQA0

CTMN

DQB3

A

B

C

D

E

F

G

H

J

Page 2

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

Table 2: Pin Description

# Pins

edge

# Pins

center

Signal

I/O

Type

Description

a

SIO1,SIO0

I/O

CMOS

2

1

2

1

Serial input/output. Pins for reading from and writing to the control

registers using a serial access protocol. Also used for power man-

agement.

CMD

SCK

I

CMOS

Command input. Pins used in conjunction with SIO0 and SIO1 for

reading from and writing to the control registers. Also used for

power management.

Serial clock input. Clock source used for reading from and writing to

the control registers

V

14

2

6

1

2

9

1

9

Supply voltage for the RDRAM core and interface logic.

Supply voltage for the RDRAM analog circuitry.

Supply voltage for CMOS input/output pins.

DD

DDa

CMOS

2

GND

19

2

Ground reference for RDRAM core and interface.

Ground reference for RDRAM analog circuitry.

GNDa

b

DQA8..DQA0

I/O

RSL

9

Data byte A. Nine pins which carry a byte of read or write data

between the Channel and the RDRAM. DQA8 is not used by

RDRAMs with a x16 organization.

b

CFM

I

RSL

1

Clock from master. Interface clock used for receiving RSL signals

from the Channel. Positive polarity.

b

CFMN

RSL

Clock from master. Interface clock used for receiving RSL signals

from the Channel. Negative polarity

V

1

Logic threshold reference voltage for RSL signals

REF

b

CTMN

I

RSL

Clock to master. Interface clock used for transmitting RSL signals to

the Channel. Negative polarity.

b

CTM

I

RSL

1

3

5

9

1

3

5

9

Clock to master. Interface clock used for transmitting RSL signals to

the Channel. Positive polarity.

b

RQ7..RQ5 or

ROW2..ROW0

I

RSL

Row access control. Three pins containing control and address

information for row accesses.

b

RQ4..RQ0 or

COL4..COL0

I

RSL

Column access control. Five pins containing control and address

information for column accesses.

b

DQB8..

DQB0

I/O

RSL

Data byte B. Nine pins which carry a byte of read or write data

between the Channel and the RDRAM. DQB8 is not used by

RDRAMs with a x16 organization.

Total pin count per package

74

54

a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.

b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.

INFINEON Technologies Version 1.0

Preliminary Information

Page 3

Direct RAMBUS 72 Mbit (256kx18x16d)

RQ7..RQ5 or

ROW2..ROW0

3

RQ4..RQ0 or

COL4..COL0

5

DQB8..DQB0

9

CTM CTMN SCK,CMD SIO0,SIO1 CFM CFMN

DQA8..DQA0

9

2

RCLK

1:8 Demux

TCLK

RCLK

6

Control Registers

Packet Decode

COLC

ROWR

11

ROWA

9

COLX

5

COLM

8

5

4

5

4

6

8

ROP DR BR

AV

R

REFR

DEVID

XOP DX BX COP DC BC

C

MB MA

Power Modes

M

S

Match

Mux

Match

Write

Buffer

DM

Row Decode

XOP Decode

PRER

ACT

PREX

Mux

Column Decode & Mask

PREC

RD, WR

DRAM Core

Sense Amp

32x72

512x64x144

32x72

72

Internal DQB Data Path

Internal DQA Data Path

72

Bank 0

Bank 1

Bank 2

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 8

Bank 9

Bank 10

Bank 11

Bank 12

Bank 13

Bank 14

Bank 15

72

9

Figure 2: 64/74Mbit Direct RDRAM Block Diagram

Page 4

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

ROW Pins: The principle use of these three pins is to

manage the transfer of data between the banks and the

sense amps of the RDRAM. These pins are de-multi-

plexed into a 24-bit ROWA (row-activate) or ROWR

(row-operation) packet.

General Description

Figure 2 is a block diagram of the 64/ 72Mbit Direct

RDRAM. It consists of two major blocks: a “core” block

built from banks and sense amps similar to those

found in other types of DRAM, and a Direct Rambus

interface block which permits an external controller to

access this core at up to 1.6GB/ s.

COL Pins: The principle use of these five pins is to

manage the transfer of data between the DQA/ DQB

pins and the sense amps of the RDRAM. These pins are

de-multiplexed into a 23-bit COLC (column-operation)

packet and either a 17-bit COLM (mask) packet or a 17-

bit COLX (extended-operation) packet.

Control Registers: The CMD, SCK, SIO0, and SIO1

pins appear in the upper center of Figure 2. They are

used to write and read a block of control registers.

These registers supply the RDRAM configuration

information to a controller and they select the oper-

ating modes of the device. The nine bit REFR value is

used for tracking the last refreshed row. Most impor-

tantly, the five bit DEVID specifies the device address

of the RDRAM on the Channel.

ACT Command: An ACT (activate) command from

an ROWA packet causes one of the 512 rows of the

selected bank to be loaded to its associated sense amps

(two 256 byte sense amps for DQA and two for DQB).

PRER Command: A PRER (precharge) command

from an ROWR packet causes the selected bank to

release its two associated sense amps, permitting a

different row in that bank to be activated, or permitting

adjacent banks to be activated.

Clocking: The CTM and CTMN pins (Clock-To-

Master) generate TCLK (Transmit Clock), the internal

clock used to transmit read data. The CFM and CFMN

pins (Clock-From-Master) generate RCLK (Receive

Clock), the internal clock signal used to receive write

data and to receive the ROW and COL pins.

RD Command: The RD (read) command causes one

of the 64 dualocts of one of the sense amps to be trans-

mitted on the DQA/ DQB pins of the Channel.

DQA,DQB Pins: These 18 pins carry read (Q) and

write (D) data across the Channel. They are multi-

plexed/ de-multiplexed from/ to two 72-bit data paths

(running at one-eighth the data frequency) inside the

RDRAM.

WR Command: The WR (write) command causes a

dualoct received from the DQA/ DQB data pins of the

Channel to be loaded into the write buffer. There is also

space in the write buffer for the BC bank address and C

column address information. The data in the write

buffer is automatically retired (written with optional

bytemask) to one of the 64 dualocts of one of the sense

amps during a subsequent COP command. A retire can

take place during a RD, WR, or NOCOP to another

device, or during a WR or NOCOP to the same device.

The write buffer will not retire during a RD to the same

device. The write buffer reduces the delay needed for

the internal DQA/ DQB data path turn-around.

Banks: The 8Mbyte core of the RDRAM is divided

into sixteen 0.5Mbyte banks, each organized as 512

rows, with each row containing 64 dualocts, and each

dualoct containing 16 bytes. A dualoct is the smallest

unit of data that can be addressed.

Sense Amps: The RDRAM contains 17 sense amps.

Each sense amp consists of 512 bytes of fast storage

(256 for DQA and 256 for DQB) and can hold one-half

of one row of one bank of the RDRAM. The sense amp

may hold any of the 512 half-rows of an associated

bank. However, each sense amp is shared between two

adjacent banks of the RDRAM (except for numbers 0

and 15). This introduces the restriction that adjacent

banks may not be simultaneously accessed.

PREC Precharge: The PREC, RDA and WRA

commands are similar to NOCOP, RD and WR, except

that a precharge operation is performed at the end of

the column operation. These commands provide a

second mechanism for performing precharge.

PREX Precharge: After a RD command, or after a

WR command with no byte masking (M=0), a COLX

packet may be used to specify an extended operation

(XOP). The most important XOP command is PREX.

This command provides a third mechanism for

performing precharge.

RQ Pins: These pins carry control and address infor-

mation. They are broken into two groups. RQ7..RQ5

are also called ROW2..ROW0, and are used primarily

for controlling row accesses. RQ4..RQ0 are also called

COL4..COL0, and are used primarily for controlling

column accesses.

INFINEON Technologies Version 1.0

Preliminary Information

Page 5

Direct RAMBUS 72 Mbit (256kx18x16d)

The AV (ROWA/ ROWR packet selection) bit distin-

guishes between the two packet types. Both the ROWA

and ROWR packet provide a five bit device address

and a four bit bank address. An ROWA packet uses the

remaining bits to specify a nine bit row address, and

the ROWR packet uses the remaining bits for an eleven

bit opcode field. Note the use of the “RsvX” notation to

reserve bits for future address field extension.

Packet Format

Figure 3 shows the formats of the ROWA and ROWR

packets on the ROW pins. Table 3 describes the fields

which comprise these packets. DR4T and DR4F bits are

encoded to contain both the DR4 device address bit

and a framing bit which allows the ROWA or ROWR

packet to be recognized by the RDRAM.

Table 3: Field Description for ROWA Packet and ROWR Packet

Description

Field

DR4T,DR4F

DR3..DR0

BR3..BR0

AV

Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit.

Device address for ROWA or ROWR packet.

Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the RDRAM.

Selects between ROWA packet (AV=1) and ROWR packet (AV=0).

R8..R0

Row address for ROWA packet. RsvR denotes bits ignored by the RDRAM.

Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions.

ROP10..ROP0

Figure 3 also shows the formats of the COLC, COLM,

and COLX packets on the COL pins. Table 4 describes

the fields which comprise these packets.

The remaining 17 bits are interpreted as a COLM

(M=1) or COLX (M=0) packet. A COLM packet is used

for a COLC write command which needs bytemask

control. The COLM packet is associated with the

The COLC packet uses the S (Start) bit for framing. A

COLM or COLX packet is aligned with this COLC

packet, and is also framed by the S bit.

COLC packet from a time t

earlier. An COLX

RTR

packet may be used to specify an independent

precharge command. It contains a five bit device

address, a four bit bank address, and a five bit opcode.

The COLX packet may also be used to specify some

housekeeping and power management commands.

The COLX packet is framed within a COLC packet but

is not otherwise associated with any other packet.

The 23 bit COLC packet has a five bit device address, a

four bit bank address, a six bit column address, and a

four bit opcode. The COLC packet specifies a read or

write command, as well as some power management

commands.

Table 4: Field Description for COLC Packet, COLM Packet, and COLX Packet

Description

Field

S

Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets.

Device address for COLC packet.

DC4..DC0

BC3..BC0

C5..C0

Bank address for COLC packet. RsvB denotes bits reserved for future extension (controller drives 0’s).

Column address for COLC packet. RsvC denotes bits ignored by the RDRAM.

Opcode field for COLC packet. Specifies read, write, precharge, and power management functions.

Selects between COLM packet (M=1) and COLX packet (M=0).

COP3..COP0

M

MA7..MA0

MB7..MB0

DX4..DX0

BX3..BX0

XOP4..XOP0

Bytemask write control bits. 1=write, 0=no-write. MA0 controls the earliest byte on DQA8..0.

Bytemask write control bits. 1=write, 0=no-write. MB0 controls the earliest byte on DQB8..0.

Device address for COLX packet.

Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drives 0’s).

Opcode field for COLX packet. Specifies precharge, I control, and power management functions.

OL

Page 6

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

T₀

T₁

T₂

T₃

T₈

T₉

T₁₀

T₁₁

CTM/CFM

DR2 BR0 BR3 RsvR R8

DR1 BR1 RsvB RsvR R7

DR0 BR2 RsvB AV=1 R6

R5

R4

R3

R2

R1

R0

DR2 BR0 BR3 ROP10ROP8ROP5 ROP2

DR1 BR1 RsvB ROP9 ROP7ROP4 ROP1

DR0 BR2 RsvB AV=0 ROP6ROP3 ROP0

ROW2 DR4T

ROW1

ROW0 DR3

ROW1

ROW0 DR3

DR4F

ROWA Packet

ROWR Packet

T₀

T₁

T₂

T₃

T

T T T T T T

10 11 12 13 14 15

0

1

2

3

4

5

6

7

8

9

CTM/CFM

ROW2

..ROW0

S=1

RsvC C4

ACT a0

WR b1

PRER c0

DC4

DC3

DC2

DC1

DC0

COL4

COL3

COL2

COL1

COL0

t

PACKET

MSK (b1) PREX d0

C5

C3

COL4

..COL0

COP1

COP0

COP2

RsvB BC2 C2

RsvB BC1 C1

DQA8..0

DQB8..0

COP3 BC3 BC0 C0

COLC Packet

T₈

T₉

T₁₀

T₁₁

T₁₂

T₁₃

T₁₄

T₁₅

CTM/CFM

S=1^aMA7 MA5 MA3 MA1

M=1 MA6 MA4 MA2 MA0

MB7 MB4 MB1

S=1^bDX4 XOP4 RsvB BX1

M=0 DX3 XOP3 RsvB BX0

DX2 XOP2 BX3

COL4

COL3

COL2

COL1

COL0

COL4

COL3

COL2

COL1

COL0

MB6 MB3 MB0

DX1 XOP1 BX2

MB5 MB2

DX0 XOP0

^aThe COLM is associated with a

previous COLC, and is aligned

with the present COLC, indicated

by the Start bit (S=1) position.

^bThe COLX is aligned

with the present COLC,

indicated by the Start

bit (S=1) position.

COLM Packet

COLX Packet

Figure 3: Packet Formats

INFINEON Technologies Version 1.0

Preliminary Information

Page 7

Direct RAMBUS 72 Mbit (256kx18x16d)

not selected. Note that a broadcast operation is indi-

cated when both bits are set. Broadcast operation

would typically be used for refresh and power

management commands. If the device is selected, the

DM (DeviceMatch) signal is asserted and an ACT or

ROP command is performed.

Field Encoding Summary

Table 5 shows how the six device address bits are

decoded for the ROWA and ROWR packets. The DR4T

and DR4F encoding merges a fifth device bit with a

framing bit. When neither bit is asserted, the device is

Table 5: Device Field Encodings for ROWA Packet and ROWR Packet

DR4T

DR4F

Device Selection

Device Match signal (DM)

1

0

1

0

1

0

All devices (broadcast)

One device selected

No packet present

DM is set to 1

DM is set to 1 if {DEVID4..DEVID0} == {0,DR3..DR0} else DM is set to 0

DM is set to 1 if {DEVID4..DEVID0} == {1,DR3..DR0} else DM is set to 0

DM is set to 0

Table 6 shows the encodings of the remaining fields of

the ROWA and ROWR packets. An ROWA packet is

specified by asserting the AV bit. This causes the speci-

fied row of the specified bank of this device to be

loaded into the associated sense amps.

ACT command, except the row address comes from an

internal register REFR, and REFR is incremented at the

largest bank address. The REFP (refresh-precharge)

command is identical to a PRER command.

The NAPR, NAPRC, PDNR, ATTN, and RLXR

An ROWR packet is specified when AV is not asserted.

An 11 bit opcode field encodes a command for one of

the banks of this device. The PRER command causes a

bank and its two associated sense amps to precharge,

so another row or an adjacent bank may be activated.

The REFA (refresh-activate) command is similar to the

commands are used for managing the power dissipa-

tion of the RDRAM and are described in more detail in

“Power State Management” on page 38. The TCEN

and TCAL commands are used to adjust the output

driver slew rate and they are described in more detail

in “Current and Temperature Control” on page 43.

Table 6: ROWA Packet and ROWR Packet Field Encodings

ROP10..ROP0 Field

Command Description

DM^aAV

Name

10

9

8

7

6

5

4

3

2:0

0

1

-

---

-

No operation.

1

0

Row address

ACT

Activate row R8..R0 of bank BR3..BR0 of device and move device to ATTN^b.

1

0

1

0

1

0

1

x^c

0

x

0

x

000 PRER

000 REFA

Precharge bank BR3..BR0 of this device.

Refresh (activate) row REFR8..REFR0 of bank BR3..BR0 of device.

Increment REFR if BR3..BR0 = 1111 (see Figure 50).

1

0

1

x

0

x

0

1

0

x

0

x

0

1

0

x

0

1

x

0

1

0

1

x

0

x

0

1

x

0

000 REFP

000 PDNR

000 NAPR

Precharge bank BR3..BR0 of this device after REFA (see Figure 50).

Move this device into the powerdown (PDN) power state (see Figure 47).

Move this device into the nap (NAP) power state (see Figure 47).

000 NAPRC Move this device into the nap (NAP) power state conditionally

000 ATTN^bMove this device into the attention (ATTN) power state (see Figure 45).

000 RLXR

001 TCAL

010 TCEN

Move this device into the standby (STBY) power state (see Figure 46).

Temperature calibrate this device (see Figure 52).

Temperature calibrate/ enable this device (see Figure 52).

000 NOROP No operation.

a. The DM (Device Match signal) value is determined by the DR4T,DR4F, DR3..DR0 field of the ROWA and ROWR packets. See Table 5.

b. The ATTN command does not cause a RLX-to-ATTN transition for a broadcast operation (DR4T/ DR4F=1/ 1).

c. An “x” entry indicates which commands may be combined. For instance, the three commands PRER/ NAPRC/ RLXR may be specified in one ROP value (011000111000).

Page 8

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

Table 7 shows the COP field encoding. The device

must be in the ATTN power state in order to receive

COLC packets. The COLC packet is used primarily to

specify RD (read) and WR (write) commands. Retire

operations (moving data from the write buffer to a

sense amp) happen automatically. See Figure 17 for a

more detailed description.

The COLC packet can also specify a PREC command,

which precharges a bank and its associated sense

amps. The RDA/ WRA commands are equivalent to

combining RD/ WR with a PREC. RLXC (relax)

performs a power mode transition. See “Power State

Management” on page 38.

Table 7: COLC Packet Field Encodings

S

DC4.. DC0

COP3..0 Name

Command Description

(select device)^a

0

1

----

-----

-

No operation.

/ = (DEVID4 ..0)

== (DEVID4 ..0)

-----

Retire write buffer of this device.

x000^b

x001

x010

x011

x100

x101

x110

x111

1xxx

NOCOP Retire write buffer of this device.

WR

Retire write buffer of this device, then write column C5..C0 of bank BC3..BC0 to write buffer.

Reserved, no operation.

RSRV

RD

Read column C5..C0 of bank BC3..BC0 of this device.

PREC

WRA

RSRV

RDA

RLXC

Retire write buffer of this device, then precharge bank BC3..BC0 (see Figure 14).

Same as WR, but precharge bank BC3..BC0 after write buffer (with new data) is retired.

Reserved, no operation.

Same as RD, but precharge bank BC3..BC0 afterward.

Move this device into the standby (STBY) power state (see Figure 46).

a. “/ =” means not equal, “==” means equal.

b. An “x” entry indicates which commands may be combined. For instance, the two commands WR/ RLXC may be specified in one COP value (1001).

Table 8 shows the COLM and COLX field encodings.

The M bit is asserted to specify a COLM packet with

two 8 bit bytemask fields MA and MB. If the M bit is

not asserted, an COLX is specified. It has device and

bank address fields, and an opcode field. The primary

use of the COLX packet is to permit an independent

PREX (precharge) command to be specified without

consuming control bandwidth on the ROW pins. It is

also used for the CAL(calibrate) and SAM (sample)

current control commands (see “Current and Tempera-

ture Control” on page 43), and for the RLXX power

mode command (see “Power State Management” on

page 38).

Table 8: COLM Packet and COLX Packet Field Encodings

DX4 .. DX0

(selects device)

M

XOP4..0

Name

Command Description

1

0

----

-

MSK

MB/ MA bytemasks used by WR/ WRA.

/ = (DEVID4 ..0)

== (DEVID4 ..0)

-

No operation.

00000

1xxx0^a

x10x0

x11x0

xxx10

xxxx1

NOXOP

PREX

CAL

No operation.

Precharge bank BX3..BX0 of this device (see Figure 14).

Calibrate (drive) I_OLcurrent for this device (see Figure 51).

Calibrate (drive) and Sample ( update) I_OLcurrent for this device (see Figure 51).

Move this device into the standby (STBY) power state (see Figure 46).

Reserved, no operation.

CAL/ SAM

RLXX

RSRV

a. An “x” entry indicates which commands may be combined. For instance, the two commands PREX/ RLXX may be specified in one XOP value (10010).

INFINEON Technologies Version 1.0

Preliminary Information

Page 9

Direct RAMBUS 72 Mbit (256kx18x16d)

A WR or WRA command will receive a dualoct of

DQ Packet Timing

write data D a time t

later. This time does not need

CWD

Figure 4 shows the timing relationship of COLC

packets with D and Q data packets. This document

uses a specific convention for measuring time intervals

between packets: all packets on the ROW and COL

pins (ROWA, ROWR, COLC, COLM, COLX) use the

trailing edge of the packet as a reference point, and all

packets on the DQA/ DQB pins (D and Q) use the

leading edge of the packet as a reference point.

to include the round-trip propagation time of the

Channel since the COLC and D packets are traveling in

the same direction.

When a Q packet follows a D packet (shown in the left

half of the figure), a gap (t

-t

) will automati-

CAC CWD

cally appear between them because the t

value is

CWD

always less than the t

value. There will be no gap

CAC

between the two COLC packets with the WR and RD

commands which schedule the D and Q packets.

An RD or RDA command will transmit a dualoct of

read data Q a time t

later. This time includes one to

CAC

When a D packet follows a Q packet (shown in the

right half of the figure), no gap is needed between

five cycles of round-trip propagation delay on the

Channel. The t parameter may be programmed to a

CAC

them because the t

value is less than the t

CWD

CAC

one of a range of values ( 7, 8, 9, 10, 11, or 12 t

).

CYCLE

value. However, , a gap of t

-t

or greater must

CAC CWD

The value chosen depends upon the number of

RDRAM devices on the Channel and the RDRAM

timing bin. See Figure 39 for more information.

be inserted between the COLC packets with the RD

WR commands by the controller so the Q and D

packets do not overlap.

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀

T

₂₃T₂₄

T

₂₇T₂₈

T

₃₅T₃₆

T

₃₉T₄₀

T

₄₃T₄₄T T T

45 46 47

1

2

3

5

6

7

9

10

13 14

17 18

21 22

25 26

29 30 31

33 34

37 38

41 42

32

CTM/CFM

This gap on the DQA/DQB pins appears automatically

This gap on the COL pins must be inserted by the controller

t

-t

ROW2

..ROW0

CAC CWD

t

-t

CAC CWD

WR d1

• • •

t

CWD

• • •

CWD

RD b1

COL4

WR a1

RD c1

• • •

..COL0

Q (b1)

Q (a1)

Q (c1)

Q (a1)

D (d1)

D (a1)

DQA8..0

DQB8..0

• • •

t

CAC

t

CAC

= 7, 8, 9, 10, 11, or 12 t

CYCLE

Figure 4: Read (Q) and Write (D) Data Packet - Timing for t

CAC

used as an COLX packet. This could be used for a

PREX precharge command or for a housekeeping

command (this case is not shown). The M bit is not

asserted in an COLX packet and causes all 16 bytes of

the previous WR to be written unconditionally. Note

that a RD command will never need a COLM packet,

and will always be able to use the COLX packet option

(a read operation has no need for the byte-write-enable

control bits).

COLM Packet to D Packet Mapping

Figure 5 shows a write operation initiated by a WR

command in a COLC packet. If a subset of the 16 bytes

of write data are to be written, then a COLM packet is

transmitted on the COL pins a time t

after the

RTR

COLC packet containing the WR command. The M bit

of the COLM packet is set to indicate that it contains

the MA and MB mask fields. Note that this COLM

packet is aligned with the COLC packet which causes

the write buffer to be retired. See Figure 17 for more

details.

Figure 5 also shows the mapping between the MA and

MB fields of the COLM packet and bytes of the D

packet on the DQA and DQB pins. Each mask bit

controls whether a byte of data is written (=1) or not

written (=0).

If all 16 bytes of the D data packet are to be written,

then no further control information is required. The

packet slot that would have been used by the COLM

packet (t

after the COLC packet) is available to be

RTR

Page 10

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

T₁₆

T

₂₇T₂₈

T

T₃₂

T

T T

41 42

40

T

₄₃T₄₄T T T

45 46 47

1

2

3

5

6

7

9

10

13 14 15

17 18 19

21 22 23

25 26

29 30 31

33 34 35

37 38 39

20

24

36

CTM/CFM

ROW2

ACT a0

PRER a2

ACT b0

..ROW0

t

RTR

COL4

..COL0

WR a1

retire (a1)

MSK (a1)

t

CWD

D (a1)

DQA8..0

DQB8..0

Transaction a: WR

a0 = {Da,Ba,Ra}

a1 = {Da,Ba,Ca1}

a3 = {Da,Ba}

COLM Packet

D Packet

T₁₇

T₁₈

T₁₉

T₂₀

T₁₉

T₂₀

T₂₁

T₂₂

CTM/CFM

MA7 MA5 MA3 MA1

COL4

COL3

COL2

COL1

COL0

DB17 DB26 DB35 DB45 DB53 DB62 DB71

DB8

DQB8

DQB7

M=1 MA6 MA4 MA2 MA0

MB7 MB4 MB1

MB6 MB3 MB0

MB5 MB2

DB7 DB16 DB25 DB34 DB44 DB52 DB61 DB70

DQB1

DQB0

DB10 DB19 DB28 DB37 DB46 DB55 DB64

DB9 DB18 DB27 DB36 DB45 DB54 DB63

DB1

DB0

MB0 MB1 MB2 MB3 MB4 MB5 MB6 MB7

Each bit of the MB7..MB0 field

controls writing (=1) or no writing

(=0) of the indicated DB bits when

the M bit of the COLM packet is one.

When M=1, the MA and MB

fields control writing of

individual data bytes.

When M=0, all data bytes are

written unconditionally.

DA17 DA26 DA35 DA45 DA53 DA62 DA71

DA8

DQA8

DQA7

DA16 DA25 DA34 DA44 DA52 DA61 DA70

DA7

DQA1

DQA0

DA1 DA10 DA19 DA28 DA37 DA46 DA55 DA64

DA0 DA9 DA18 DA27 DA36 DA45 DA54 DA63

MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7

Each bit of the MA7..MA0 field

controls writing (=1) or no writing

(=0) of the indicated DA bits when

the M bit of the COLM packet is one.

Figure 5: Mapping Between COLM Packet and D Packet for WR Command

INFINEON Technologies Version 1.0

Preliminary Information

Page 11

Direct RAMBUS 72 Mbit (256kx18x16d)

Cases RR1 through RR4 show two successive ACT

commands. In case RR1, there is no restriction since the

ACT commands are to different devices. In case RR2,

ROW-to-ROW Packet Interaction

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

T₁₆

T

1

2

3

5

6

7

9

10

13 14 15

17 18 19

the t restriction applies to the same device with non-

RR

adjacent banks. Cases RR3 and RR4 are illegal (as

shown) since bank Ba needs to be precharged. If a

CTM/CFM

t

PRER to Ba, Ba+1, or Ba-1 is inserted, t

is t

RC

RRDELAY

ROW2

..ROW0

ROPa a0

ROPb b0

(t

to the PRER command, and t to the next ACT).

RP

RAS

Cases RR5 through RR8 show an ACT command

followed by a PRER command. In cases RR5 and RR6,

there are no restrictions since the commands are to

different devices or to non-adjacent banks of the same

COL4

..COL0

device. In cases RR7 and RR8, the t

means the activated bank must wait before it can be

precharged.

restriction

RAS

DQA8..0

DQB8..0

Transaction a: ROPa

Transaction b: ROPb

a0 = {Da,Ba,Ra}

b0= {Db,Bb,Rb}

Cases RR9 through RR12 show a PRER command

followed by an ACT command. In cases RR9 and

RR10, there are essentially no restrictions since the

commands are to different devices or to non-adjacent

banks of the same device. RR10a and RR10b depend

upon whether a bracketed bank (Ba+-1) is precharged

or activated. In cases RR11 and RR12, the same and

Figure 6: ROW-to-ROW Packet Interaction- Timing

Figure 6 shows two packets on the ROW pins sepa-

rated by an interval t

which depends upon the

RRDELAY

packet contents. No other ROW packets are sent to

banks {Ba,Ba+1,Ba-1} between packet “a” and packet

“b” unless noted otherwise. Table 9 summarizes the

adjacent banks must all wait t for the sense amp and

RP

t

values for all possible cases.

bank to precharge before being activated.

RRDELAY

Table 9: ROW-to-ROW Packet Interaction - Rules

Case # ROPa Da

Ba

Ra

ROPb Db

Bb

Rb

t_{RRD ELAY}

Example

RR1

RR2

RR3

RR4

RR5

RR6

RR7

RR8

RR9

RR10

ACT

Da

Ba

Ra

ACT

/ = Da xxxx

x..x t_PACKET

x..x t_RR

Figure 11

Figure 10

Figure 11

Figure 10

Figure 15

Figure 12

== Da / = {Ba,Ba+1,Ba-1}

== Da == {Ba+1,Ba-1}

== Da == {Ba}

x..x

t

_RC- illegal unless PRER to Ba/ Ba+1/ Ba-1

PRER / = Da xxxx

x..x t_PACKET

x..x t_RAS

PRER == Da / = {Ba,Ba+1,Ba-1}

PRER == Da == { Ba+1,Ba-1}

PRER == Da == {Ba}

x..x t_RAS

PRER Da

ACT

/ = Da xxxx

x..x t_PACKET

== Da / = {Ba,Ba+-1,Ba+-2} x..x t_PACKET

RR10a PRER Da

RR10b PRER Da

== Da == {Ba+2}

== Da == {Ba-2}

== Da == {Ba+1,Ba-1}

== Da == {Ba}

x..x

t

_PACKET/ t_RPif Ba+1 is precharged/ activated.

_PACKET/ t_RPif Ba-1 is precharged/ activated.

RR11

RR12

RR13

RR14

RR15

RR16

PRER Da

x..x t_RP

x..x t_PACKET

x..x t_PP

Figure 10

Figure 12

PRER / = Da xxxx

PRER == Da / = {Ba,Ba+1,Ba-1}

PRER == Da == {Ba+1,Ba-1}

PRER == Da == Ba

Page 12

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

Cases RC1 through RC5 summarize the rules when the

ROW packet has an ACT command. Figure 15 and

Figure 16 show examples of RC5 - an activation

followed by a read or write. RC4 is an illegal situation,

since a read or write of a precharged banks is being

attempted (remember that for a bank to be activated,

adjacent banks must be precharged). In cases RC1,

RC2, and RC3, there is no interaction of the ROW and

COL packets.

ROW-to-ROW Interaction - continued

Cases RR13 through RR16 summarize the combina-

tions of two successive PRER commands. In case RR13

there is no restriction since two devices are addressed.

In RR14, t applies, since the same device is

PP

addressed. In RR15 and RR16, the same bank or an

adjacent bank may be given repeated PRER commands

with only the t restriction.

PP

Two adjacent banks can’t be activate simultaneously. A

precharge command to one bank will thus affect the

state of the adjacent banks (and sense amps). If bank Ba

is activate and a PRER is directed to Ba, then bank Ba

will be precharged along with sense amps Ba-1/ Ba and

Ba/ Ba+1. If bank Ba+1 is activate and a PRER is

directed to Ba, then bank Ba+1 will be precharged

along with sense amps Ba/ Ba+1 and Ba+1/ Ba+2. If

bank Ba-1 is activate and a PRER is directed to Ba, then

bank Ba-1 will be precharged along with sense amps

Ba/ Ba-1 and Ba-1/ Ba-2.

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

T₁₆

T

1

2

3

5

6

7

9

10

13 14 15

17 18 19

CTM/CFM

t

RCDELAY

ROW2

..ROW0

ROPa a0

COL4

..COL0

COPb b1

DQA8..0

DQB8..0

A ROW packet may contain commands other than

ACT or PRER. The REFA and REFP commands are

equivalent to ACT and PRER for interaction analysis

purposes. The interaction rules of the NAPR, NAPRC,

PDNR, RLXR, ATTN, TCAL, and TCEN commands are

discussed in later sections (see Table 6 for cross-ref).

Transaction a: ROPa

Transaction b: COPb

a0 = {Da,Ba,Ra}

b1= {Db,Bb,Cb1}

Figure 7: ROW-to-COL Packet Interaction- Timing

Cases RC6 through RC8 summarize the rules when the

ROW packet has a PRER command. There is either no

interaction (RC6 through RC9) or an illegal situation

with a read or write of a precharged bank (RC9).

ROW-to-COL Packet Interaction

Figure 7 shows two packets on the ROW and COL

The COL pins can also schedule a precharge operation

with a RDA, WRA, or PREC command in a COLC

packet or a PREX command in a COLX packet. The

constraints of these precharge operations may be

converted to equivalent PRER command constraints

using the rules summarized in Figure 14.

pins. They must be separated by an interval t

RCDELAY

which depends upon the packet contents. Table 10

summarizes the t values for all possible cases.

RCDELAY

Note that if the COL packet is earlier than the ROW

packet, it is considered a COL-to-ROW packet interac-

tion.

Table 10: ROW-to-COL Packet Interaction - Rules

Case # ROPa Da

Ba

Ra

COPb

NOCOP,RD,retire

Db

/ = Da

Bb

Cb1 t_{RCD ELAY}

Example

RC1

RC2

RC3

RC4

RC5

RC6

RC7

RC8

RC9

ACT

Da

Ba

Ra

xxxx

x..x

0

NOCOP

== Da

/ = Da

== Da

RD,retire

/ = {Ba,Ba+1,Ba-1} x..x

RD,retire

== {Ba+1,Ba-1}

== Ba

x..x Illegal

x..x t_RCD

RD,retire

Figure 15

PRER Da

NOCOP,RD,retire

NOCOP

xxxx

x..x

0

xxxx

RD,retire

/ = {Ba,Ba+1,Ba-1} x..x

== {Ba+1,Ba-1}

RD,retire

x..x Illegal

INFINEON Technologies Version 1.0

Preliminary Information

Page 13

Direct RAMBUS 72 Mbit (256kx18x16d)

gap is needed. For cases CC1, CC2, CC4, and CC5,

COL-to-COL Packet Interaction

there is no restriction (t

is t ).

CC

CCDELAY

In cases CC6 through CC10, COPb is a WR command

and COPc is a RD command. The t value

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

T₁₆

T

1

2

3

5

6

7

9

10

13 14 15

17 18 19

CCDELAY

needed between these two packets depends upon the

command and address in the packet with COPa. In

particular, in case CC6 when there is WR-WR-RD

command sequence directed to the same device, a gap

will be needed between the packets with COPb and

COPc. The gap will need a COLC packet with a

NOCOP command directed to any device in order to

force an automatic retire to take place. Figure 18 (right)

provides a more detailed explanation of this case.

CTM/CFM

ROW2

..ROW0

t

CCDELAY

COL4

..COL0

COPa a1 COPb b1

COPc c1

DQA8..0

DQB8..0

In case CC10, there is a RD-WR-RD sequence directed

to the same device. If a prior write to the same device is

unretired when COPa is issued, then a gap will be

needed between the packets with COPb and COPc as

in case CC6. The gap will need a COLC packet with a

NOCOP command directed to any device in order to

force an automatic retire to take place.

Transaction a: COPa

Transaction b: COPb

Transaction c: COPc

a1 = {Da,Ba,Ca1}

b1 = {Db,Bb,Cb1}

c1 = {Dc,Bc,Cc1}

Figure 8: COL-to-COL Packet Interaction- Timing

Figure 8 shows three arbitrary packets on the COL

pins. Packets “b” and “c” must be separated by an

Cases CC7, CC8, and CC9 have no restriction

interval t

which depends upon the command

CCDELAY

(t

is t ).

CC

CCDELAY

and address values in all three packets. Table 11

summarizes the t values for all possible cases.

For the purposes of analyzing COL-to-ROW interac-

tions, the PREC, WRA, and RDA commands of the

COLC packet are equivalent to the NOCOP, WR, and

RD commands. These commands also cause a

precharge operation PREC to take place. This

precharge may be converted to an equivalent PRER

command on the ROW pins using the rules summa-

rized in Figure 14.

CCDELAY

Cases CC1 through CC5 summarize the rules for every

situation other than the case when COPb is a WR

command and COPc is a RD command. In CC3, when

a RD command is followed by a WR command, a gap

of t

-t

must be inserted between the two COL

CAC CWD

packets. See Figure 4 for more explanation of why this

Table 11: COL-to-COL Packet Interaction - Rules

Case # COPa

Da

Ba

Ca1 COPb

Db Bb

Cb1 COPc

Dc

Bc

Cc1 t_CCDELAY

Example

CC1

CC2

CC3

CC4

CC5

CC6

CC7

CC8

CC9

CC10

xxxx

WR

xxxxx x..x x..x NOCOP Db

Bb

Cb1 xxxx

xxxxx x..x

x..x t_CC

xxxxx x..x x..x RD,WR

xxxxx x..x x..x RD

xxxxx x..x x..x WR

Db

Cb1 NOCOP xxxxx x..x

x..x t_CC

Cb1 WR

Cb1 RD

Cb1 WR

Cb1 RD

xxxxx x..x

== Db x..x

/ = Db x..x

== Db x..x

x..x t_CC+t_CAC-t_CWD

x..x t_CC

Figure 4

Figure 15

Figure 16

Figure 18

x..x t_CC

== Db

/ = Db

x

x..x WR

x..x t_RTR

x..x t_CC

WR

x..x t_CC

NOCOP == Db

RD == Db

x..x t_CC

pins. They must be separated by an interval t

which depends upon the command and address values

CRDELAY

COL-to-ROW Packet Interaction

Figure 9 shows arbitrary packets on the COL and ROW

Page 14

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

CR5 is illegal because an adjacent bank can’t be acti-

vated or precharged until bank Ba is precharged first.

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

T₁₆

T

1

2

3

5

6

7

9

10

13 14 15

17 18 19

In case CR6, the COLC packet contains a RD

command, and the ROW packet contains a PRER

CTM/CFM

t

CRDELAY

command for the same bank. The t

ifies the required spacing.

parameter spec-

RDP

ROW2

..ROW0

ROPb b0

Likewise, in case CR7, the COLC packet causes an

automatic retire to take place, and the ROW packet

contains a PRER command for the same bank. The t

parameter specifies the required spacing.

COL4

..COL0

COPa a1

RTP

DQA8..0

DQB8..0

Case CR8 is labeled “Hazardous” because a WR

command should always be followed by an automatic

retire before a precharge is scheduled. Figure 19 shows

an example of what can happen when the retire is not

able to happen before the precharge.

Transact ion a: COPa

Transaction b: ROPb

a1= {Da,Ba,Ca1}

b0= {Db,Bb,Rb}

Figure 9: COL-to-ROW Packet Interaction- Timing

For the purposes of analyzing COL-to-ROW interac-

tions, the PREC, WRA, and RDA commands of the

COLC packet are equivalent to the NOCOP, WR, and

RD commands. These commands also cause a

precharge operation to take place. This precharge may

converted to an equivalent PRER command on the

ROW pins using the rules summarized in Figure 14.

in the packets. Table 12 summarizes the t

value for all possible cases.

CRDELAY

Cases CR1, CR2, CR3, and CR9 show no interaction

between the COL and ROW packets, either because

one of the commands is a NOP or because the packets

are directed to different devices or to non-adjacent

banks.

A ROW packet may contain commands other than

ACT or PRER. The REFA and REFP commands are

equivalent to ACT and PRER for interaction analysis

purposes. The interaction rules of the NAPR, PDNR,

and RLXR commands are discussed in a later section.

Case CR4 is illegal because an already-activated bank

is to be re-activated without being precharged Case

Table 12: COL-to-ROW Packet Interaction - Rules

Db

Example

Case # COPa

Da

Ba

Ca1

ROPb

Bb

Rb

t_CRDELAY

CR1

CR2

CR3

CR4

CR5

CR6

CR7

CR8

CR9

NOCOP Da

RD/ WR Da

Ba

Ca1

x..x

xxxxx

/ = Da

== Da

xxxx

x..x

0

x..x

0

x..x

/ = {Ba,Ba+1,Ba-1} x..x

0

ACT

PRER

== {Ba}

x..x

Illegal

t_RDP

t_RTP

0

== {Ba+1,Ba-1}

RD

Da

== {Ba,Ba+1,Ba-1} x..x

Figure 15

Figure 16

Figure 19

retire^a

WR^b

xxxx

NOROP xxxxx

xxxx

x..x

0

a. This is any command which permits the write buffer of device Da to retire (see Table 7). “Ba” is the bank address in the write buffer.

b. This situation is hazardous because the write buffer will be left unretired while the targeted bank is precharged. See Figure 19.

INFINEON Technologies Version 1.0

Preliminary Information

Page 15

Direct RAMBUS 72 Mbit (256kx18x16d)

commands to the same bank must also satisfy the t

timing parameter (RR4).

ROW-to-ROW Examples

RC

Figure 10 shows examples of some of the the ROW-to-

ROW packet spacings from Table 9. A complete

sequence of activate and precharge commands is

directed to a bank. The RR8 and RR12 rules apply to

When a bank is activated, it is necessary for adjacent

banks to remain precharged. As a result, the adjacent

banks will also satisfy parallel timing constraints; in

the example, the RR11 and RR3 rules are analogous to

the RR12 and RR4 rules.

this sequence. In addition to satisfying the t

and t

RP

RAS

timing parameters, the separation between ACT

a0 = {Da,Ba,Ra}

a1 = {Da,Ba+1}

b0 = {Da,Ba+1,Rb}

b0 = {Da,Ba,Rb}

b0 = {Da,Ba+1,Rb}

b0 = {Da,Ba,Rb}

Same Device

Adjacent Bank

Same Bank

Adjacent Bank

Same Bank

RR7

RR3

RR4

RR11

RR12

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀

T

₂₃T₂₄

T

₂₇T₂₈

T

₃₅T₃₆

T

₃₉T₄₀

T

₄₃T₄₄T T T

45 46 47

1

2

3

5

6

7

9

10

13 14

17 18

21 22

25 26

29 30 31

33 34

37 38

41 42

32

CTM/CFM

ROW2

ACT a0

PRER a1

ACT b0

..ROW0

COL4

..COL0

t

RAS

RP

DQA8..0

DQB8..0

t

RC

Figure 10: Row Packet Example

Figure 11 shows examples of the ACT-to-ACT (RR1,

RR2) and ACT-to-PRER (RR5, RR6) command spacings

from Table 9. In general, the commands in ROW

unless they are directed to the same or adjacent banks

or unless they are a similar command type (both PRER

or both ACT) directed to the same device.

packets may be spaced an interval t

apart

PACKET

a0 = {Da,Ba,Ra}

Different Device

Same Device

Different Device

Same Device

Any Bank

Non-adjacent Bank RR2

Any Bank RR5

Non-adjacent Bank RR6

RR1

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀

T

₂₃T₂₄

T

₂₇T₂₈

T

₃₅T₃₆

T

₃₉T₄₀

T

₄₃T₄₄T T T

45 46 47

1

2

3

5

6

7

9

10

13 14

17 18

21 22

25 26

29 30 31

33 34

37 38

41 42

32

CTM/CFM

ROW2

..ROW0

ACT a0

ACT b0

ACT a0

ACT c0

ACT a0 PRER b0

PACKET

ACT a0

PRER c0

t

PACKET

t

RR

COL4

..COL0

DQA8..0

DQB8..0

Figure 11: Row Packet Example

Page 16

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

Figure 12 shows examples of the PRER-to-PRER

(RR13, RR14) and PRER-to-ACT (RR9, RR10)

commands in ROW packets may be spaced an interval

t

apart unless they are directed to the same or

PACKET

command spacings from Table 10. The RR15 and RR16

cases (PRER-to-PRER to same or adjacent banks) are

not shown, but are similar to RR14. In general, the

adjacent banks or unless they are a similar command

type (both PRER or both ACT) directed to the same

device.

a0 = {Da,Ba,Ra}

Different Device

Same Device

Different Device

Same Device

Any Bank

Non-adjacent Bank RR14

Adjacent Bank

Same Bank

Any Bank

RR13

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

c0 = {Da,Ba,Rc}

RR15

RR16 c0 = {Da,Ba+1Rc}

RR9

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

Non-adjacent Bank RR10

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀

T

₂₃T₂₄

T

₂₇T₂₈

T

₃₅T₃₆

T

₃₉T₄₀

T

₄₃T₄₄T T T

45 46 47

1

2

3

5

6

7

9

10

13 14

17 18

21 22

25 26

29 30 31

33 34

37 38

41 42

32

CTM/CFM

ROW2

..ROW0

PRER a0 PRER b0

PACKET

PRER a0

PRER c0

PRER a0 ACT b0

PACKET

PRER a0

ACT c0

t

PACKET

t

PP

COL4

..COL0

DQA8..0

DQB8..0

Figure 12: Row Packet Examples

requires the interval t

- t

to complete.

RCD,MIN

RAS,MIN

Row and Column Cycle Description

Column read and write operations are also performed

during the t - t interval (if more than

Activate: A row cycle begins with the activate (ACT)

operation. The activation process is destructive; the act

of sensing the value of a bit in a bank’s storage cell

transfers the bit to the sense amp, but leaves the orig-

inal bit in the storage cell with an incorrect value.

RAS,MIN

RCD,MIN

about four column operations are performed, this

interval must be increased). The precharge operation

requires the interval t

to complete.

RP,MIN

Adjacent Banks: An RDRAM with a “d” designation

(256Kx16dx16/ 18) indicates it contains “doubled

banks”. This means the sense amps are shared between

two adjacent banks. The only exception is that sense

amp 0 and sense amp 15 are not shared. When a row in

a bank is activated, the two adjacent sense amps are

connected to (associated with) that bank and are not

available for use by the two adjacent banks. These two

adjacent banks must remain precharged while the

selected bank goes through its activate, restore,

read/ write, and precharge operations.

Restore: Because the activation process is destructive,

a hidden operation called restore is automatically

performed. The restore operation rewrites the bits in

the sense amp back into the storage cells of the acti-

vated row of the bank.

Read/Write: While the restore operation takes place,

the sense amp may be read (RD) and written (WR)

using column operations. If new data is written into

the sense amp, it is automatically forwarded to the

storage cells of the bank so the data in the activated

row and the data in the sense amp remain identical.

For example (referring to the block diagram of

Figure 2), if bank 5 is accessed, sense amp 4/ 5 and

sense amp 5/ 6 will both be loaded with one of the 512

rows (with 512 bytes loaded into each sense amp from

the 1Kbyte row - 256 bytes to the DQA side and 256

bytes to the DQB side). While this row from bank 5 is

being accessed, no rows may be accessed in banks 4 or

6 because of the sense amp sharing.

Precharge: When both the restore operation and the

column operations are completed, the sense amp and

bank are precharged (PRE). This leaves them in the

proper state to begin another activate operation.

Intervals: The activate operation requires the interval

t

to complete. The hidden restore operation

RCD,MIN

INFINEON Technologies Version 1.0

Preliminary Information

Page 17

Direct RAMBUS 72 Mbit (256kx18x16d)

occur a time t

after the ACT command, and a time

RAS

Precharge Mechanisms

t

before the next ACT command. This timing will

RP

Figure 13 shows an example of precharge with the

ROWR packet mechanism. The PRER command must

serve as a baseline aginst which the other precharge

mechanisms can be compared.

a0 = {Da,Ba,Ra}

a5 = {Da,Ba}

b0 = {Da,Ba,Rb}

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀

T

₂₃T₂₄

T

₂₇T₂₈

T

₃₅T₃₆

T

₃₉T₄₀

T

₄₃T₄₄T T T

45 46 47

1

2

3

5

6

7

9

10

13 14

17 18

21 22

25 26

29 30 31

33 34

37 38

41 42

32

CTM/CFM

ROW2

ACT a0

PRER a5

ACT b0

..ROW0

COL4

..COL0

t

RAS

RP

DQA8..0

DQB8..0

t

RC

Figure 13: Precharge via PRER Command in ROWR Packet

Figure 14 (top) shows an example of precharge with a

RDA command. A bank is activated with an ROWA

packet on the ROW pins. Then, a series of four

analyzing interactions with other packets. Note that

the automatic retire is triggered by a COLC packet a

time t

after the COLC packet with the WR

RTR

dualocts are read with RD commands in COLC packets

on the COL pins. The fourth of these commands is a

RDA, which causes the bank to automatically

command unless the second COLC contains a RD

command to the same device. This is described in more

detail in Figure 17.

precharge when the final read has finished. The timing

of this automatic precharge is equivalent to a PRER

command in an ROWR packet on the ROW pins that is

Figure 14 (bottom) shows an example of precharge

with a PREX command in an COLX packet. A bank is

activated with an ROWA packet on the ROW pins.

Then, a series of four dualocts are read with RD

commands in COLC packets on the COL pins. The

fourth of these COLC packets includes an COLX

packet with a PREX command. This causes the bank to

precharge with timing equivalent to a PRER command

in an ROWR packet on the ROW pins that is offset a

offset a time t

from the COLC packet with the

OFFP

RDA command. The RDA command should be treated

as a RD command in a COLC packet as well as a simul-

taneous (but offset) PRER command in an ROWR

packet when analyzing interactions with other packets.

Figure 14 (middle) shows an example of precharge

with a WRA command. As in the RDA example, a

bank is activated with an ROWA packet on the ROW

pins. Then, two dualocts are written with WR

time t

from the COLX packet with the PREX

OFFP

command.

commands in COLC packets on the COL pins. The

second of these commands is a WRA, which causes the

bank to automatically precharge when the final write

has been retired. The timing of this automatic

precharge is equivalent to a PRER command in an

ROWR packet on the ROW pins that is offset a time

t

from the COLC packet that causes the automatic

OFFP

retire. The WRA command should be treated as a WR

command in a COLC packet as well as a simultaneous

(but offset) PRER command in an ROWR packet when

Page 18

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

COLC Packet: RDA Precharge Offset

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀

T

₂₃T₂₄

T

₂₇T₂₈

T

₃₅T₃₆

T

₃₉T₄₀

T

₄₃T₄₄T T T

45 46 47

1

2

3

5

6

7

9

10

13 14

17 18

21 22

25 26

29 30 31

33 34

37 38

41 42

32

CTM/CFM

The RDA precharge is equivalent to a PRER command here

ACT a0 PRER a5

ROW2

ACT b0

..ROW0

t

OFFP

COL4

..COL0

RD a1

RD a2

RD a3

RDA a4

Q (a1)

Q (a2)

Q (a3)

Q (a4)

DQA8..0

DQB8..0

Transaction a: RD

a0 = {Da,Ba,Ra}

a1 = {Da,Ba,Ca1}

a3 = {Da,Ba,Ca3}

a2 = {Da,Ba,Ca2}

a4 = {Da,Ba,Ca4}

a5 = {Da,Ba}

COLC Packet: WDA Precharge Offset

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀

T

₂₃T₂₄

T

₂₇T₂₈

T

₃₅T₃₆

T

₃₉T₄₀

T

₄₃T₄₄T T T

45 46 47

1

2

3

5

6

7

9

10

13 14

17 18

21 22

25 26

29 30 31

33 34

37 38

41 42

32

CTM/CFM

The WRA precharge (triggered by the automatic retire) is equivalent to a PRER command here

ROW2

ACT a0

PRER a5

ACT b0

..ROW0

t

OFFP

RTR

COL4

..COL0

WR a1

WRA a2 retire (a1) retire (a2)

MSK (a1) MSK (a2)

D (a1)

D (a2)

DQA8..0

DQB8..0

Transaction a: WR

a0 = {Da,Ba,Ra}

a1 = {Da,Ba,Ca1}

a2 = {Da,Ba,Ca2}

a5 = {Da,Ba}

COLX Packet: PREX Precharge Offset

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀

T

₂₃T₂₄

T

₂₇T₂₈

T

₃₅T₃₆

T

₃₉T₄₀

T

₄₃T₄₄T T T

45 46 47

1

2

3

5

6

7

9

10

13 14

17 18

21 22

25 26

29 30 31

33 34

37 38

41 42

32

CTM/CFM

The PREX precharge command is equivalent to a PRER command here

ACT a0 PRER a5

ROW2

ACT b0

..ROW0

t

OFFP

COL4

..COL0

RD a1

RD a2

RD a3

RD a4

PREX a5

Q (a1)

Q (a2)

Q (a3)

Q (a4)

DQA8..0

DQB8..0

Transaction a: RD

a0 = {Da,Ba,Ra}

a1 = {Da,Ba,Ca1}

a3 = {Da,Ba,Ca3}

a2 = {Da,Ba,Ca2}

a4 = {Da,Ba,Ca4}

a5 = {Da,Ba}

Figure 14: Offsets for Alternate Precharge Mechanisms

INFINEON Technologies Version 1.0

Preliminary Information

Page 19

Direct RAMBUS 72 Mbit (256kx18x16d)

device and bank address as the a0, a1, and a2

addresses. The PRER command must occur a time t

Read Transaction - Example

RAS

Figure 15 shows an example of a read transaction. It

begins by activating a bank with an ACT a0 command

or more after the original ACT command (the activa-

tion operation in any DRAM is destructive, and the

contents of the selected row must be restored from the

in an ROWA packet. A time t

later a RD a1

RCD

command is issued in a COLC packet. Note that the

ACT command includes the device, bank, and row

address (abbreviated as a0) while the RD command

includes device, bank, and column address (abbrevi-

two associated sense amps of the bank during the t

interval). The PRER command must also occur a time

RAS

t

or more after the last RD command. Note that the

RDP

value shown is greater than the t

specifi-

RDP

RDP,MIN

ated as a1). A time t

after the RD command the

cation in Table 22. This transaction example reads two

dualocts, but there is actually enough time to read

CAC

read data dualoct Q(a1) is returned by the device. Note

that the packets on the ROW and COL pins use the end

of the packet as a timing reference point, while the

packets on the DQA/ DQB pins use the beginning of

the packet as a timing reference point.

three dualocts before t

becomes the limiting param-

RDP

eter rather than t

. If four dualocts were read, the

RAS

packet with PRER would need to shift right (be

delayed) by one t (note - this case is not shown).

CYCLE

A time t after the first COLC packet on the COL pins

Finally, an ACT b0 command is issued in an ROWR

packet on the ROW pins. The second ACT command

CC

a second is issued. It contains a RD a2 command. The

a2 address has the same device and bank address as

the a1 address (and a0 address), but a different column

must occur a time t or more after the first ACT

RC

command and a time t or more after the PRER

RP

address. A time t

second read data dualoct Q(a2) is returned by the

device.

after the second RD command a

command. This ensures that the bank and its associ-

ated sense amps are precharged. This example

assumes that the second transaction has the same

device and bank address as the first transaction, but a

different row address. Transaction b may not be started

until transaction a has finished. However, transactions

to other banks or other devices may be issued during

transaction a.

CAC

Next, a PRER a3 command is issued in an ROWR

packet on the ROW pins. This causes the bank to

precharge so that a different row may be activated in a

subsequent transaction or so that an adjacent bank

may be activated. The a3 address includes the same

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀

T

₂₃T₂₄

T

₂₇T₂₈

T

₃₅T₃₆

T

₃₉T₄₀

T

₄₃T₄₄T T T

45 46 47

1

2

3

5

6

7

9

10

13 14

17 18

21 22

25 26

29 30 31

33 34

37 38

41 42

32

CTM/CFM

t

RC

ROW2

ACT a0

PRER a3

ACT b0

..ROW0

t

RAS

RP

COL4

RD a1

RD a2

..COL0

t

RCD

CC

RDP

Q (a1)

Q (a2)

DQA8..0

DQB8..0

t

CAC

t

CAC

Transaction a: RD

Transaction b: xx

a0 = {Da,Ba,Ra}

b0 = {Da,Ba,Rb}

a1 = {Da,Ba,Ca1}

a2 = {Da,Ba,Ca2}

a3 = {Da,Ba}

Figure 15: Read Transaction Example

Page 20

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

delayed, then the COLM packet (if used) must also be

delayed.

Write Transaction - Example

Figure 16 shows an example of a write transaction. It

begins by activating a bank with an ACT a0 command

Next, a PRER a3 command is issued in an ROWR

packet on the ROW pins. This causes the bank to

precharge so that a different row may be activated in a

subsequent transaction or so that an adjacent bank

may be activated. The a3 address includes the same

device and bank address as the a0, a1, and a2

in an ROWA packet. A time t

-t

later a WR a1

RCD RTR

command is issued in a COLC packet (note that the

interval is measured to the end of the COLC

t

RCD

packet with the first retire command). Note that the

ACT command includes the device, bank, and row

address (abbreviated as a0) while the WR command

includes device, bank, and column address (abbrevi-

addresses. The PRER command must occur a time t

RAS

or more after the original ACT command (the activa-

tion operation in any DRAM is destructive, and the

contents of the selected row must be restored from the

ated as a1). A time t

after the WR command the

CWD

write data dualoct D(a1) is issued. Note that the

packets on the ROW and COL pins use the end of the

packet as a timing reference point, while the packets on

the DQA/ DQB pins use the beginning of the packet as

a timing reference point.

two associated sense amps of the bank during the t

interval).

RAS

A PRER a3 command is issued in an ROWR packet on

the ROW pins. The PRER command must occur a time

t

or more after the last COLC which causes an auto-

RTP

A time t after the first COLC packet on the COL pins

CC

matic retire.

a second COLC packet is issued. It contains a WR a2

command. The a2 address has the same device and

bank address as the a1 address (and a0 address), but a

Finally, an ACT b0 command is issued in an ROWR

packet on the ROW pins. The second ACT command

different column address. A time t

after the second

must occur a time t or more after the first ACT

RC

CWD

WR command a second write data dualoct D(a2) is

issued.

command and a time t or more after the PRER

RP

command. This ensures that the bank and its associ-

ated sense amps are precharged. This example

assumes that the second transaction has the same

device and bank address as the first transaction, but a

different row address. Transaction b may not be started

until transaction a has finished. However, transactions

to other banks or other devices may be issued during

transaction a.

A time t

after each WR command an optional

RTR

COLM packet MSK (a1) is issued, and at the same time

a COLC packet is issued causing the write buffer to

automatically retire. See Figure 17 for more detail on

the write/ retire mechanism. If a COLM packet is not

used, all data bytes are unconditionally written. If the

COLC packet which causes the write buffer to retire is

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀

T

₂₃T₂₄

T

₂₇T₂₈

T

₃₅T₃₆

T

₃₉T₄₀

T

₄₃T₄₄

T

1

2

3

5

6

7

9

10

13 14

17 18

21 22

25 26

29 30 31

33 34

37 38

41 42

45 46 47

32

CTM/CFM

t

RC

ROW2

..ROW0

ACT a0

PRER a3

ACT b0

t

RCD

t

RAS

RP

COL4

..COL0

WR a1

WR a2

retire (a1) retire (a2)

MSK (a1) MSK (a2)

t

RTP

t

RTR

t

RTR

D (a1)

D (a2)

DQA8..0

DQB8..0

t

CC

CWD

t

CWD

Transaction a: WR

Transaction b: xx

a0 = {Da,Ba,Ra}

b0 = {Da,Ba,Rb}

a1 = {Da,Ba,Ca1}

a2 = {Da,Ba,Ca2}

a3 = {Da,Ba}

Figure 16: Write Transaction Example

INFINEON Technologies Version 1.0

Preliminary Information

Page 21

Direct RAMBUS 72 Mbit (256kx18x16d)

the specified device. The COLC packet which follows a

Write/Retire - Examples

time t

later will retire the write buffer. The retire

RTR

The process of writing a dualoct into a sense amp of an

RDRAM bank occurs in two steps. The first step

consists of transporting the write command, write

address, and write data into the write buffer. The

second step happens when the RDRAM automatically

retires the write buffer (with an optional bytemask)

into the sense amp. This two-step write process

reduces the natural turn-around delay due to the

internal bidirectional data pins.

will happen automatically unless (1) a COLC packet is

not framed (no COLC packet is present and the S bit is

zero), or (2) the COLC packet contains a RD command

to the same device. If the retire does not take place at

time t

after the original WR command, then the

RTR

device continues to frame COLC packets, looking for

the first that is not a RD directed to itself. A bytemask

MSK(a1) may be supplied in a COLM packet aligned

with the COLC that retires the write buffer at time t

after the WR command.

RTR

Figure 17 (left) shows an example of this two step

process. The first COLC packet contains the WR

command and an address specifying device, bank and

The memory controller must be aware of this two-step

write/ retire process. Controller performance can be

improved, but only if the controller design accounts for

several side effects.

column. The write data dualoct follows a time t

CWD

later. This information is loaded into the write buffer of

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀T T

21

T

₂₂T₂₃

0

T

T₄

T

T₈

T

₁₁T₁₂

T

T₁₆

T

T T T

21 22 23

20

1

2

3

5

6

7

9

10

13 14

17 18

1

2

3

5

6

7

9

10

13 14 15

17 18 19

CTM/CFM

Retire is automatic here unless:

(1) No COLC packet (S=0) or

(2) COLC packet is RD to device Da

This RD gets the old data

This RD gets the new data

ROW2

..ROW0

ROW2

..ROW0

t

CAC

COL4

..COL0

WR a1

COL4

..COL0

WR a1

retire (a1)

MSK (a1)

RD b1

retire (a1)

MSK (a1)

RD c1

t

RTR

D (a1)

Q (b1)

DQA8..0

DQB8..0

D (a1)

Q (

DQA8..0

DQB8..0

t

CWD

Transaction a: WR

a1= {Da,Ba,Ca1}

Transaction a: WR

Transaction b: RD

Transaction c: RD

a1= {Da,Ba,Ca1}

b1= {Da,Ba,Ca1}

c1= {Da,Ba,Ca1}

Figure 17: Normal Retire (left) and Retire/Read Ordering (right)

Figure 17 (right) shows the first of these side effects. tion. The read may be to any bank and column

The first COLC packet has a WR command which

loads the address and data into the write buffer. The

third COLC causes an automatic retire of the write

buffer to the sense amp. The second and fourth COLC

packets (which bracket the retire packet) contain RD

commands with the same device, bank and column

address as the original WR command. In other words,

the same dualoct address that is written is read both

before and after it is actually retired. The first RD

returns the old dualoct value from the sense amp

before it is overwritten. The second RD returns the

new dualoct value that was just written.

address; all that matters is that it is to the same device

as the WR command. The retire operation and

MSK(a1) will be delayed by a time t

as a result.

PACKET

If the RD command used the same bank and column

address as the WR command, the old data from the

sense amp would be returned. If many RD commands

to the same device were issued instead of the single

one that is shown, then the retire operation would be

held off an arbitrarily long time. However, once a RD

to another device or a WR or NOCOP to any device is

issued, the retire will take place. Figure 18 (right) illus-

trates a situation in which the controller wants to issue

a WR-WR-RD COLC packet sequence, with all

Figure 18 (left) shows the result of performing a RD

command to the same device in the same COLC packet

slot that would normally be used for the retire opera-

commands addressed to the same device, but

addressed to any combination of banks and columns.

Page 22

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

COLC packet. Therefore, it is required in this situation

that the controller issue a NOCOP command in the

third COLC packet, delaying the RD command by a

Write/Retire Examples - continued

The RD will prevent a retire of the first WR from auto-

matically happening. But the first dualoct D(a1) in the

write buffer will be overwritten by the second WR

dualoct D(b1) if the RD command is issued in the third

time of t

. This situation is explicitly shown in

PACKET

Table 12 for the cases in which t

is equal to

CCDELAY

t

.

RTR

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀

T

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

T₁₉T₂₀

1

2

3

5

6

7

9

10

13 14

17 18

21 22 23

1

2

3

5

6

7

9

10

13 14 15

17 18

16

CTM/CFM

The retire operation for a write can be

held off by a read to the same device

The controller must insert a NOCOP to retire (a1)

to make room for the data (b1) in the write buffer

ROW2

..ROW0

t

CAC

COL4

..COL0

COL4

..COL0

WR a1

RD b1

retire (a1)

MSK (a1)

WR b1 retire (a1) RD c1

MSK (a1)

t

+ t

t

RTR

PACKET

Q (b1)

D (b1)

DQA8..0

DQB8..0

D (a1)

DQA8..0

D (a1)

DQB8..0

t

CWD

Transaction a: WR

Transaction b: RD

a1= {Da,Ba,Ca1}

b1= {Da,Bb,Cb1}

Transaction a: WR

Transaction b: WR

Transaction c: RD

a1= {Da,Ba,Ca1}

b1= {Da,Bb,Cb1}

c1= {Da,Bc,Cc1}

Figure 18: Retire Held Off by Read (left) and Controller Forces WWR Gap (right)

Figure 19 shows a possible result when a retire is held

off for a long time (an extended version of Figure 18-

left). After a WR command, a series of six RD

commands are issued to the same device (but to any

combination of bank and column addresses). In the

meantime, the bank Ba to which the WR command

was originally directed is precharged, and a different

row Rc is activated. When the retire is automatically

performed, it is made to this new row, since the write

buffer only contains the bank and column address, not

the row address. The controller can insure that this

doesn’t happen by never precharging a bank with an

unretired write buffer. Note that in a system with more

than one RDRAM, there will never be more than two

RDRAMs with unretired write buffers. This is because

a WR command issued to one device automatically

retires the write buffers of all other devices written a

time t

before or earlier.

RTR

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀

T

₂₃T₂₄

T

₂₇T₂₈

T

₃₅T₃₆

T

₃₉T₄₀

T

₄₃T₄₄T T T

45 46 47

1

2

3

5

6

7

9

10

13 14

17 18

21 22

25 26

29 30 31

33 34

37 38

41 42

32

CTM/CFM

The retire operation puts the

write data in the new row

t

RC

ROW2

ACT a0

PRER a2

ACT c0

..ROW0

t

RAS

RP

COL4

..COL0

WR a1

RD b1

RD b2

RD b3

RD b4

RD b5

RD b6

retire (a1)

MSK (a1)

t

RCD

t

RTR

D (a1)

Q (b1)

Q (b2)

Q (b3)

Q (b4)

Q (b5)

DQA8..0

DQB8..0

t

CWD

CAC

WARNING

Transaction a: WR

Transaction b: RD

a0 = {Da,Ba,Ra}

b1 = {Da,Bb,Cb1}

b4 = {Da,Bb,Cb4}

c0 = {Da,Ba,Rc}

a1 = {Da,Ba,Ca1}

b2 = {Da,Bb,Cb2}

b5 = {Da,Bb,Cb5}

a2 = {Da,Ba}

b3= {Da,Bb,Cb3}

b6 = {Da,Bb,Cb6}

This sequence is hazardous

and must be used with caution

Transaction c: WR

Figure 19: Retire Held Off by Reads to Same Device, Write Buffer Retired to New Row

INFINEON Technologies Version 1.0

Preliminary Information

Page 23

Direct RAMBUS 72 Mbit (256kx18x16d)

rather than the PRER command in an ROWR packet on

the ROW pins.

Interleaved Write - Example

Figure 20 shows an example of an interleaved write

transaction. Transactions similar to the one presented

in Figure 16 are directed to non-adjacent banks of a

single RDRAM. This allows a new transaction to be

In this example, the first transaction is directed to

device Da and bank Ba. The next three transactions are

directed to the same device Da, but need to use

different, non-adjacent banks Bb, Bc, Bd so there is no

bank conflict. The fifth transaction could be redirected

back to bank Ba without interference, since the first

issued once every t interval rather than once every

RR

t

interval (four times more often). The DQ data pin

RC

efficiency is 100% with this sequence.

transaction would have completed by then (t has

RC

With two dualocts of data written per transaction, the

COL, DQA, and DQB pins are fully utilized. Banks are

precharged using the WRA autoprecharge option

elapsed). Each transaction may use any value of row

address (Ra, Rb, ..) and column address (Ca1, Ca2, Cb1,

Cb2, ...).

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀

T

₂₃T₂₄

T

₂₇T₂₈

T

₃₅T₃₆

T

₃₉T₄₀

T

₄₃T₄₄T T T

45 46 47

1

2

3

5

6

7

9

10

13 14

17 18

21 22

25 26

29 30 31

33 34

37 38

41 42

32

CTM/CFM

Transaction e can use the

same bank as transaction a

t

RC

ROW2

ACT a0

ACT b0

ACT c0

ACT d0

ACT e0

ACT f0

..ROW0

t

RCD

WR a1

MSK (y1) MSK (y2) MSK (z1) MSK (z2) MSK (a1) MSK (a2) MSK (b1) MSK (b2) MSK (c1) MSK (c2) MSK (d1) MSK (d2)

RR

COL4

..COL0

WR z1

WRA z2

WRA a2

WR b1

WRA b2

WR c1

WRA c2

WR d1

WR d2

WR e1

WR e2

t

CWD

D (z2)

D (x2)

D (y1)

D (y2)

D (z1)

D (a1)

D (a2)

D (b1)

D (b2)

D(c1)

D (c2)

D (d1)

Q (

DQA8..0

DQB8..0

Transaction y: WR

Transaction z: WR

Transaction a: WR

Transaction b: WR

Transaction c: WR

Transaction d: WR

Transaction e: WR

Transaction f: WR

y0 = {Da,Ba+4,Ry}

z0 = {Da,Ba+6,Rz}

a0 = {Da,Ba,Ra}

b0 = {Da,Ba+2,Rb} b1 = {Da,Ba+2,Cb1} b2= {Da,Ba+2,Cb2}

c0 = {Da,Ba+4,Rc} c1 = {Da,Ba+4,Cc1} c2= {Da,Ba+4,Cc2}

d0 = {Da,Ba+6,Rd} d1 = {Da,Ba+6,Cd1} d2= {Da,Ba+6,Cd2}

y1 = {Da,Ba+4,Cy1} y2= {Da,Ba+4,Cy2}

y3 = {Da,Ba+4}

z3 = {Da,Ba+6}

a3 = {Da,Ba}

b3 = {Da,Ba+2}

c3 = {Da,Ba+4}

d3 = {Da,Ba+6}

e3 = {Da,Ba}

z1 = {Da,Ba+6,Cz1}

a1 = {Da,Ba,Ca1}

z2= {Da,Ba+6,Cz2}

a2= {Da,Ba,Ca2}

e0 = {Da,Ba,Re}

f0 = {Da,Ba+2,Rf}

e1 = {Da,Ba,Ce1}

f1 = {Da,Ba+2,Cf1}

e2= {Da,Ba,Ce2}

f2= {Da,Ba+2,Cf2}

f3 = {Da,Ba+2}

Figure 20: Interleaved Write Transaction with Two Dualoct Data Length

cent banks of a single RDRAM. This is similar to the

Interleaved Read - Example

interleaved write and read examples in Figure 20 and

Figure 21 except that bubble cycles need to be inserted

by the controller at read/ write boundaries. The DQ

data pin efficiency for the example in Figure 22 is

32/ 42 or 76%. If there were more RDRAMs on the

Channel, the DQ pin efficiency would approach 32/ 34

or 94% for the two-dualoct RRWW sequence (this case

is not shown).

Figure 21 shows an example of interleaved read trans-

actions. Transactions similar to the one presented in

Figure 15 are directed to non-adjacent banks of a single

RDRAM. The address sequence is identical to the one

used in the previous write example. The DQ data pins

efficiency is also 100%. The only difference with the

write example (aside from the use of the RD command

rather than the WR command) is the use of the PREX

command in a COLX packet to precharge the banks

rather than the RDA command. This is done because

the PREX is available for a readtransaction but is not

available for a masked write transaction.

In Figure 22, the first bubble type t

is inserted by

CBUB1

the controller between a RD and WR command on the

COL pins. This bubble accounts for the round-trip

propagation delay that is seen by read data, and is

explained in detail in Figure 4. This bubble appears on

the DQA and DQB pins as t

dualoct D and read data dualoct Q. This bubble also

appears on the ROW pins as t

between a write data

DBUB1

Interleaved RRWW - Example

Figure 22 shows a steady-state sequence of 2-dualoct

RD/ RD/ WR/ WR.. transactions directed to non-adja-

.

RBUB1

Page 24

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀

T

₂₃T₂₄

T

₂₇T₂₈

T

₃₅T₃₆

T

₃₉T₄₀

T

₄₃T₄₄T T T

45 46 47

1

2

3

5

6

7

9

10

13 14

17 18

21 22

25 26

29 30 31

33 34

37 38

41 42

32

CTM/CFM

Transaction e can use the

same bank as transaction a

t

RC

ROW2

ACT a0

ACT b0

ACT c0

ACT d0

ACT e0

ACT f0

..ROW0

t

RCD

RD a1

RR

RD d1

COL4

..COL0

RD z1

Q (x2)

RD z2

PREX y3

RD a2

RD b1

RD b2

RD c1

RD c2

RDd2

PREX c3

RD e1

Q (c2)

RD e2

PREX d3

PREX z3

PREX a3

PREX b3

t

CAC

Q (z2)

Q (y1)

Q (y2)

Q (z1)

Q (a1)

Q (a2)

Q (b1)

Q (b2)

Q (c1)

Q (d1)

DQA8..0

DQB8..0

Transaction y: RD

Transaction z: RD

Transaction a: RD

Transaction b: RD

Transaction c: RD

Transaction d: RD

Transaction e: RD

Transaction f: RD

y0 = {Da,Ba+4,Ry}

z0 = {Da,Ba+6,Rz}

a0 = {Da,Ba,Ra}

b0 = {Da,Ba+2,Rb} b1 = {Da,Ba+2,Cb1} b2= {Da,Ba+2,Cb2}

c0 = {Da,Ba+4,Rc} c1 = {Da,Ba+4,Cc1} c2= {Da,Ba+4,Cc2}

d0 = {Da,Ba+6,Rd} d1 = {Da,Ba+6,Cd1} d2= {Da,Ba+6,Cd2}

y1 = {Da,Ba+4,Cy1} y2= {Da,Ba+4,Cy2}

y3 = {Da,Ba+4}

z3 = {Da,Ba+6}

a3 = {Da,Ba}

b3 = {Da,Ba+2}

c3 = {Da,Ba+4}

d3 = {Da,Ba+6}

e3 = {Da,Ba}

z1 = {Da,Ba+6,Cz1}

a1 = {Da,Ba,Ca1}

z2= {Da,Ba+6,Cz2}

a2= {Da,Ba,Ca2}

e0 = {Da,Ba,Re}

f0 = {Da,Ba+2,Rf}

e1 = {Da,Ba,Ce1}

f1 = {Da,Ba+2,Cf1}

e2= {Da,Ba,Ce2}

f2= {Da,Ba+2,Cf2}

f3 = {Da,Ba+2}

Figure 21: Interleaved Read Transaction with Two Dualoct Data Length

The second bubble type t

is inserted (as a

Figure 18. There would be no bubble if address c0 and

address d0 were directed to different devices. This

CBUB2

NOCOP command) by the controller between a WR

and RD command on the COL pins when there is a

WR-WR-RD sequence to the same device. This bubble

enables write data to be retired from the write buffer

without being lost, and is explained in detail in

bubble appears on the DQA and DQB pins as t

DBUB2

between a write data dualoct D and read data dualoct

Q. This bubble also appears on the ROW pins as

t

.

RBUB2

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

T₁₆

T

₂₇T₂₈

T

T₃₂

T

T T

41 42

40

T

₄₃T₄₄T T T

45 46 47

1

2

3

5

6

7

9

10

13 14 15

17 18 19

21 22 23

25 26

29 30 31

33 34 35

37 38 39

20

24

36

CTM/CFM

Transaction e can use the

same bank as transaction a

t

RBUB2

t

RBUB1

ROW2

ACT a0

ACT b0

ACT c0

ACT d0

ACT e0

..ROW0

t

CBUB2

t

CBUB2

RD z1

CBUB1

WR b1

COL4

..COL0

t

DQA8..0

DQB8..0

RD z2

RD a1

RD a2

PREX z3

WRA b2

WR c1

WRA c2 NOCOP NOCOP

MSK (y2) PREX a3 MSK (b1) MSK (b2) MSK (c1) MSK (c2)

RDd0

RDf

t

DBUB2

t

DBUB1

D (y2)

Q (z1)

Q (z2)

Q (a1)

Q (a2)

D (b1)

D (b2)

D (c1)

D (c2)

Transaction y: WR

Transacti on z: RD

Transacti on a: RD

Transaction b: WR

Transaction c: WR

Transaction d: RD

Transacti on e: RD

Transaction f: WR

y0 = {Da,Ba+4,Ry}

z0 = {Da,Ba+6,Rz}

a0 = {Da,Ba,Ra}

b0 = {Da,Ba+2,Rb} b1 = {Da,Ba+2,Cb1} b2= {Da,Ba+2,Cb2}

c0 = {Da,Ba+4,Rc} c1 = {Da,Ba+4,Cc1} c2= {Da,Ba+4,Cc2}

d0 = {Da,Ba+6,Rd} d1 = {Da,Ba+6,Cd1} d2= {Da,Ba+6,Cd2}

y1 = {Da,Ba+4,Cy1} y2= {Da,Ba+4,Cy2}

y3 = {Da,Ba+4}

z3 = {Da,Ba+6}

a3 = {Da,Ba}

b3 = {Da,Ba+2}

c3 = {Da,Ba+4}

d3 = {Da,Ba+6}

e3 = {Da,Ba}

z1 = {Da,Ba+6,Cz1}

a1 = {Da,Ba,Ca1}

z2= {Da,Ba+6,Cz2}

a2= {Da,Ba,Ca2}

e0 = {Da,Ba,Re}

f0 = {Da,Ba+2,Rf}

e1 = {Da,Ba,Ce1}

f1 = {Da,Ba+2,Cf1}

e2= {Da,Ba,Ce2}

f2= {Da,Ba+2,Cf2}

f3 = {Da,Ba+2}

Figure 22: Interleaved RRWW Sequence with Two Dualoct Data Length

and two CMOS input/ output pins SIO0 and SIO1.

These provide serial access to a set of control registers

Control Register Transactions

The RDRAM has two CMOS input pins SCK and CMD

INFINEON Technologies Version 1.0

Preliminary Information

Page 25

Direct RAMBUS 72 Mbit (256kx18x16d)

in the RDRAM. These control registers provide config-

uration information to the controller during the initial-

ization process. They also allow an application to select

the appropriate operating mode of the RDRAM.

SIO1 are connected (in a daisy chain fashion) from one

RDRAM to the next. In normal operation, the data on

SIO0 is repeated on SIO1, which connects to SIO0 of

the next RDRAM (the data is repeated from SIO1 to

SIO0 for a read data packet). The controller connects to

SIO0 of the first RDRAM.

SCK (serial clock) and CMD (command) are driven by

the controller to all RDRAMs in parallel. SIO0 and

T₂₀

T₃₆

T₅₂

T₆₈

T₄

SCK

1

0

1

0

1

0

1

0

next transaction

CMD

1111 0000

1111

00000000...00000000

SIO0

SIO1

SRQ - SWR command

SA

SD

SINT

Each packet is repeated

from SIO0 to SIO1

SRQ - SWR command

SA

Figure 23: Serial Write (SWR) Transaction to Control Register

Write and read transactions are each composed of four

packets, as shown in Figure 23 and Figure 24. Each

packet consists of 16 bits, as summarized in Table 14

and Table 15. The packet bits are sampled on the falling

edge of SCK. A transaction begins with a SRQ (Serial

Request) packet. This packet is framed with a 11110000

pattern on the CMD input (note that the CMD bits are

sampled on both the falling edge and the rising edge of

SCK). The SRQ packet contains the SOP3..SOP0 (Serial

Opcode) field, which selects the transaction type. The

SDEV5..SDEV0 (Serial Device address) selects one of

the 32 RDRAMs. If SBC (Serial Broadcast) is set, then

all RDRAMs are selected. The SA (Serial Address)

packet contains a 12 bit address for selecting a control

register.

A write transaction has a SD (Serial Data) packet next.

This contains 16 bits of data that is written into the

selected control register. A SINT (Serial Interval)

packet is last, providing some delay for any side-

effects to take place. A read transaction has a SINT

packet, then a SD packet. This provides delay for the

selected RDRAM to access the control register. The SD

read data packet travels in the opposite direction

(towards the controller) from the other packet types.

The SCK cycle time will accomodate the total delay.

T₂₀

T₃₆

T₅₂

T₆₈

T₄

SCK

1

0

1

0

1

0

1

0

next transaction

CMD

1111 0000

1111

00000000...00000000

addressed RDRAM drives

0/SD15..SD0/0 on SIO0

controller drives

0 on SIO0

SIO0

SIO1

0

SD

SRQ - SRD command

SA

SINT

First 3 packets are repeated

from SIO0 to SIO1

non-addressed RDRAMs pass

0/SD15..SD0/0 from SIO1 to SIO0

SD

SRQ - SRD command

SA

SINT

Figure 24: Serial Read (SRD) Transaction Control Register

Page 26

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

Control Register Packets

T₄

T₂₀

1

Table 13 summarizes the formats of the four packet

types for control register transactions. Table 14

summarizes the fields that are used within the packets.

SCK

0

1

CMD

SIO0

SIO1

1111 0000

00000000...00000000

0

Figure 25 shows the transaction format for the SETR,

CLRR, and SETF commands. These transactions

consist of a single SRQ packet, rather than four packets

like the SWR and SRD commands. The same framing

sequence on the CMD input is used, however. These

commands are used during initialization prior to any

control register read or write transactions.

1

SRQ packet - SETR/CLRR/SETF

0

1

0

The packet is repeated

from SIO0 to SIO1

SRQ packet - SETR/CLRR/SETF

Figure 25: SETR, CLRR,SETF Transaction

Table 13: Control Register Packet Formats

SCK

Cycle

SIO0 or

SIO1

SIO0 or

SIO1

SIO0 or

SIO1

SIO0 or

SIO1

SCK

Cycle

SIO0 or

SIO1

SIO0 or

SIO1

SIO0 or

SIO1

SIO0 or

SIO1

for SRQ

for SA

for SINT

for SD

for SRQ

for SA

for SINT

for SD

0

1

2

3

4

5

6

7

rsrv

SA11

SA10

SA9

SA8

0

SD15

SD14

SD13

SD12

SD11

SD10

SD9

8

SOP1

SA7

SA6

SA5

SA4

SA3

SA2

SA1

SA0

0

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

rsrv

9

SOP0

rsrv

10

11

12

13

14

15

SBC

rsrv

SDEV4

SDEV3

SDEV2

SDEV1

SDEV0

rsrv

SDEV5

SOP3

SOP2

SD8

Table 14: Field Description for Control Register Packets

Field

Description

rsrv

Reserved. Should be driven as “0” by controller.

SOP3..SOP0

0000 - SRD. Serial read of control register {SA11..SA0} of RDRAM {SDEV5..SDEV0}.

0001 - SWR. Serial write of control register {SA11..SA0} of RDRAM {SDEV5..SDEV0}.

0010 - SETR. Set Reset bit, all control registers assume their reset values.^a16 t_SCYCLEdelay until CLRR command.

0100 - SETF. Set fast (normal) clock mode. 4 t_SCYCLEdelay until next command.

1011 - CLRR. Clear Reset bit, all control registers retain their reset values.^a4 t_SCYCLEdelay until next command.

1111 - NOP. No serial operation.

0011, 0101-1010, 1100-1110 - RSRV. Reserved encodings.

SDEV5..SDEV0

Serial device. Compared to SDEVID5..SDEVID0 field of INIT control register field to select the RDRAM to which the

transaction is directed.

SBC

Serial broadcast. When set, RDRAMs ignore {SDEV5..SDEV0} for RDRAM selection.

Serial address. Selects which control register of the selected RDRAM is read or written.

Serial data. The 16 bits of data written to or read from the selected control register of the selected RDRAM.

SA11..SA0

SD15..SD0

a. The SETR and CLRR commands must always be applied in two successive transactions to RDRAMs; i.e. they may not be used in isolation. This is called “SETR/ CLRR Reset”.

INFINEON Technologies Version 1.0

Preliminary Information

Page 27

Direct RAMBUS 72 Mbit (256kx18x16d)

o

3.3 Write TEST77 Register - The TEST77 register

must be explicitly written with zeros before any

other registers are read or written.

Initialization

T₀

T₁₆

3.4 Write TCYCLE Register - The TCYCLE register

is written with the cycle time tCYCLE of the CTM

clock (for Channel and RDRAMs) in units of 64ps.

The tCYCLE value is determined in stage 1.0.

1

0

1

0

1

0

1

0

SCK

CMD

SIO0

00001100

00000000...00000000

0000000000000000

o

3.5 Write SDEVID Register - The SDEVID (serial

device identification) register of each RDRAM is

written with a unique address value so that

directed SIO read and write transactions can be

performed. This address value increases from 0 to

31 according to the distance an RDRAM is from

the ASIC component on the SIO bus (the closest

RDRAM is address 0).

The packet is repeated

from SIO0 to SIO1

SIO1

0000000000000000

Figure 26: SIO Reset Sequence

o

3.6 Write DEVID Register - The DEVID (device

identification) register of each RDRAM is written

with a unique address value so that directed

memory read and write transactions can be

Initialization refers to the process that a controller must

go through after power is applied to the system or the

system is reset. The controller prepares the RDRAM

sub-system for normal Channel operation by (prima-

rily) using a sequence of control register transactions

on the serial CMOS pins. The following steps outline

the sequence seen by the various memory subsystem

components (including the RDRAM components)

during initialization. This sequence is available in the

form of reference code. Contact Rambus Inc. for more

information.

performed. This address value increases from 0 to

31. The DEVID value is not necessarily the same as

the SDEVID value. RDRAMs are sorted into

regions of the same core configuration (number of

bank, row, and column address bits and core type).

o

3.7 Write PDNX,PDNXA Registers - The PDNX

and PDNXA registers are written with values that

are used to measure the timing intervals connected

with an exit from the PDN (powerdown) power

state.

1.0 Start Clocks - This step calculates the proper clock

frequencies for PClk (controller logic), SynClk (RAC

block), RefClk (DRCG component), CTM (RDRAM

component), and SCK (SIO block).

o

3.8 Write NAPX Register - The NAPX register is

written with values that are used to measure the

timing intervals connected with an exit from the

NAP power state.

2.0 RAC Initialization - This step causes the INIT

block to generate a sequence of pulses which resets the

RAC, performs RAC maintainance operations, and

measures timing intervals in order to ensure clock

stability.

3.9 Write TPARM Register - The TPARM register

is written with values which determine the time

interval between a COL packet with a memory

read command and the Q packet with the read

data on the Channel. The values written set each

RDRAM to the minimum value permitted for the

system. This will be adjusted later in stage 6.0.

3.0 RDRAM Initialization - This stage performs most

of the steps needed to initialize the RDRAMs. The rest

are performed in stages 5.0, 6.0, and 7.0. All of the steps

in 3.0 are carried out through the SIO block interface.

o

3.1/3.2 SIO Reset - This reset operation is

o

3.10 Write TCDLY1 Register - The TCDLY1

performed berore any SIO control register read or

write transactions. It clears six registers (TEST34,

CCA, CCB, SKIP, TEST78, and TEST79) and places

the INIT register into a special state (all bits cleared

except SKP and SDEVID fields are set to ones).

register is written with values which determine the

time interval between a COL packet with a

memory read command and the Q packet with the

read data on the Channel. The values written set

each RDRAM to the minimum value permitted for

the system. This will be adjusted later in stage 6.0.

Page 28

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

o

3.11 Write TFRM Register - The TFRM register is

written with a value that is related to the t

that are present in the system. The ConfigRMC bus

is written with a value that will be compatible with

all RDRAM devices that are present.

RCD

parameter for the system. The t

parameter is

RCD

the time interval between a ROW packet with an

activate command and the COL packet with a read

or write command.

o

4.4 Set Current Control Interval - This step deter-

mines the values of the t

RDRAM

CCTRL,MAX

timing parameter that are present in the system.

The ConfigRMC bus is written with a value that

will be compatible with all RDRAM devices that

are present.

o

3.12 SETR/CLRR - Each RDRAM is given a SETR

command and a CLRR command through the SIO

block. This sequence performs a second reset oper-

ation on the RDRAMs.

4.5 Set Slew Rate Control Interval - This step

3.13 Write CCA and CCB Registers - These regis-

ters are written with a value halfway between their

minimum and maximum values. This shortens the

time needed for the RDRAMs to reach their

determines the values of the t

RDRAM

TEMP,MAX

timing parameter that are present in the system.

The ConfigRMC bus is written with a value that

will be compatible with all RDRAM devices that

are present.

steady-state current control values in stage 5.0.

o

3.14 Powerdown Exit - The RDRAMs are in the

PDN power state at this point. A broadcast

PDNExit command is performed by the SIO block

to place the RDRAMs in the RLX (relax) power

state in which they are ready to receive ROW

packets.

4.6 Set Bank/Row/Col Address Bits - This step

determines the number of RDRAM bank, row, and

column address bits that are present in the system.

It also determines the RDRAM core types (inde-

pendent, doubled, or split) that are present. The

ConfigRMC bus is written with a value that will be

compatible with all RDRAM devices that are

present.

3.15 SETF - Each RDRAM is given a SETF

command through the SIO block. One of the oper-

ations performed by this step is to generate a value

for the AS (autoskip) bit in the SKIP register and

fix the RDRAM to a particular read domain.

5.0 RDRAM Current Control - This step causes the

INIT block to generate a sequence of pulses which

performs RDRAM maintainance operations.

4.0 Controller Configuration- This stage initializes the

controller block. Each step of this stage will set a field

of the ConfigRMC[63:0] bus to the appropriate value.

Other controller implementations will have similar

initialization requirements, and this stage may be used

as a guide.

6.0 RDRAM Core, Read Domain Initialization- This

stage completes the RDRAM initialization

o

6.1 RDRAM Core Initialization - A sequence of

192 memory refresh transactions is performed in

order to place the cores of all RDRAMs into the

proper operating state.

o

4.1 Initial Read Data Offset- The ConfigRMC bus

is written with a value which determines the time

interval between a COL packet with a memory

read command and the Q packet with the read

data on the Channel. The value written sets

RMC.d1 to the minimum value permitted for the

system. This will be adjusted later in stage 6.0.

o

6.2 RDRAM Read Domain Initialization - A

memory write and memory read transaction is

performed to each RDRAM to determine which

read domain each RDRAM occupies. The

programmed delay of each RDRAM is then

adjusted so the total RDRAM read delay (propaga-

tion delay plus programmed delay) is constant.

The TPARM and TCDLY1 registers of each

RDRAM are rewritten with the appropriate read

delay values. The ConfigRMC bus is also rewritten

with an updated value.

4.2 Configure Row/Column Timing - This step

determines the values of the t

, t

,

RAS,MIN RP,MIN

t

, t

, and t

RDRAM

PP,MIN

RC,MIN RCD,MIN RR,MIN

timing parameters that are present in the system.

The ConfigRMC busis written with values that

will be compatible with all RDRAM devices that

are present.

7.0 Other RDRAM Register Fields - This stage

rewrites the INIT register with the final values of the

LSR, NSR, and PSR fields.

4.3 Set Refresh Interval - This step determines the

values of the t

RDRAM timing parameter

REF,MAX

INFINEON Technologies Version 1.0

Preliminary Information

Page 29

Direct RAMBUS 72 Mbit (256kx18x16d)

In essence, the controller must read all the read-only

configuration registers of all RDRAMs (or it must read

the SPD device present on each RIMM), it must process

this information, and then it must write all the read-

write registers to place the RDRAMs into the proper

operating mode.

(i.e. after the TCDLY0 and TCDLY1 fields have been

written for the final time), a single final memory read

transaction should be made to each RDRAM in order

to ensure that the output pipeline stages have been

cleared.

Initialization Note [4]: The SETF command (in the

serial SRQ packet) should only be issued once during

the Initialization process, as should the SETR and

CLRR commands.

Initialization Note [1]: During the initialization

process, it is necessary for the controller to perform 128

current control operations (3xCAL, 1xCAL/ SAM) and

one temperature calibrate operation (TCEN/ TCAL)

after reset or after powerdown (PDN) exit.

Initialization Note [5]: The CLRR command (in the

serial SRQ packet) leaves some of the contents of the

memory core in an indeterminate state.

Initialization Note [2]: There are two classes of

64/ 72Mbit RDRAM. They are distinguished by the

“S28IECO” bit in the SPD. The behavior of the

RDRAM at initialization is slightly different for the

two types:

S28IECO=0: Upon powerup the device enters ATTN

state. The serial operations SETR, CLRR, and SETF are

performed without requiring a SDEVID match of the

SBC bit (broadcast) to be set.

Control Register Summary

Table 15 summarizes the RDRAM control registers.

Detail is provided for each control register in Figure 27

through Figure 43. Read-only bits which are shaded

gray are unused and return zero. Read-write bits

which are shaded gray are reserved and should always

be written with zero. The RIMM SPD Application Note

(DL-0054) describes additional read-only configuration

registers which are present on Direct RIMMs.

S28IECO=1: Upon powerup the device enters PDN

state. The serial operations SETR, CLRR, and SETF

require a SDEVID match.

See the document detailing the reference initialization

procedure for more information on how to handle this

in a system.

The state of the register fields are potentially affected

by the IO Reset operation or the SETR/ CLRR opera-

tion. This is indicated in the text accompanying each

register diagram.

Initialization Note [3]: After the step of equalizing the

total read delay of each RDRAM has been completed

Table 15: Control Register Summary

SA11..SA0 Register

Field

read-write/ read-only Description

Serial device ID. Device address for control register read/ write.

021₁₆

INIT

SDEVID

PSX

read-write, 6 bits

read-write, 1 bit

read-write, 16 bits

read-only, 3 bit

read-only, 1 bit

read-only, 6 bit

Power select exit. PDN/ NAP exit with device addr on DQA5..0.

SIO repeater. Used to initialize RDRAM.

SRP

NSR

NAP self-refresh. Enables self-refresh in NAP mode.

PDN self-refresh. Enables self-refresh in PDN mode.

Low power self-refresh. Enables low power self-refresh.

Temperature sensing enable.

PSR

LSR

TEN

TSQ

Temperature sensing output.

DIS

RDRAM disable.

022₁₆

023₁₆

TEST34

CNFGA

TEST34

REFBIT

DBL

Test register. Do not read or write after SIO reset.

Refresh bank bits. Used for multi-bank refresh.

Double. Specifies doubled-bank architecture

Manufacturer version. Manufacturer identification number.

Protocol version. Specifies version of Direct protocol supported.

MVER

PVER

Page 30

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

Table 15: Control Register Summary

SA11..SA0 Register

Field

read-write/ read-only Description

024₁₆

CNFGB

BYT

read-only, 1 bit

Byte. Specifies an 8-bit or 9-bit byte size.

DEVTYP

SPT

read-only, 3 bit

Device type. Device can be RDRAM or some other device category.

Split-core. Each core half is an individual dependent core.

Core organization. Bank, row, column address field sizes.

Stepping version. Mask version number.

read-only, 1 bit

CORG

SVER

read-only, 6 bit

040₁₆

041₁₆

042₁₆

043₁₆

DEVID

REFB

REFR

CCA

DEVID

REFB

read-write, 5 bits

read-write, 4 bits

read-write, 9 bits

read-write, 7 bits

read-write, 2 bits

read-write, 7 bits

read-write, 2 bits

read-write, 5 bits

read-write, 1 bits

read-write, 13 bits

read-write, 2 bits

read-write, 3 bits

read-write, 4 bits

read-write, 3 bits

read-write, 14 bits

read-only, 1 bit

Device ID. Device address for memory read/ write.

Refresh bank. Next bank to be refreshed by self-refresh.

Refresh row. Next row to be refreshed by REFA, self-refresh.

Current control A. Controls I_OLoutput current for DQA.

Asymmetry control. Controls asymmetry of V_OL/ V_OHswing for DQA.

Current control B. Controls I_OLoutput current for DQB.

Asymmetry control. Controls asymmetry of V_OL/ V_OHswing for DQB.

NAP exit. Specifies length of NAP exit phase A.

REFR

CCA

ASYMA

CCB

044₁₆

045₁₆

CCB

ASYMB

NAPXA

NAPX

DQS

NAPX

NAP exit. Specifies length of NAP exit phase A + phase B.

DQ select. Selects CMD framing for NAP/ PDN exit.

PDN exit. Specifies length of PDN exit phase A.

046₁₆

047₁₆

048₁₆

PDNXA

PDNX

PDNXA

PDNX

TCAS

TCLS

PDN exit. Specifies length of PDN exit phase A + phase B.

t_CAS-Ccore parameter. Determines t_OFFPdatasheet parameter.

TPARM

t

_CLS-Ccore parameter. Determines t_CACand t_OFFPparameters.

TCDLY0

TFRM

TCDLY1

TCYCLE

AS

t_CDLY0-Ccore parameter. Programmable delay for read data.

t_FRM-Ccore parameter. Determines ROW-COL packet framing interval.

t_CDLY1-Ccore parameter. Programmable delay for read data.

t_CYCLEdatasheet parameter. Specifies cycle time in 64ps units.

Autoskip value established by the SETF command.

Manual skip enable. Allows the MS value to override the AS value.

Manual skip value.

049₁₆

04a₁₆

04c₁₆

04b₁₆

TFRM

TCDLY1

TCYCLE

SKIP

MSE

read-write, 1 bit

read-write, 16 bits

vendor-specific

MS

04d_16-

04e_16-

04f_16-

TEST77

TEST78

TEST79

TEST77

TEST78

TEST79

reserved

Test register. Write with zero after SIO reset.

Test register. Do not read or write after SIO reset.

080₁₆- 0ff₁₆reserved

Vendor-specific test registers. Do not read or write after SIO reset.

INFINEON Technologies Version 1.0

Preliminary Information

Page 31

Direct RAMBUS 72 Mbit (256kx18x16d)

.

Read/ write register.

Reset values are undefined except as affected by SIO Reset as

noted below. SETR/ CLRR Reset does not affect this register.

Control Register: INIT

Address: 021

16

15 14 13 12 11 10

9

8

7

6

5

0

4

3

2

1

0

SDEVID5..0 - Serial Device Identification. Compared to SDEV5..0

serial address field of serial request packet for register read/ write

transactions. This determines which RDRAM is selected for the

SDE

VID DIS TSQ TEN LSR PSR NSR SRP PSX

5

SDEVID4..SDEVID0

0

register read or write operation. SDEVID resets to 3f₁₆

.

PSX - Power Exit Select. PDN and NAP are exited with (=0) or without (=1) a device

address on the DQA5..0 pins. PDEV5 (on DQA5) selectes broadcast (1) or directed (0) exit.

For a directed exit, PDEV4..0 (on DQA4..0) is compared to DEVID4..0 to select a device.

SRP - SIO Repeater. Controls value on SIO1; SIO1=SIO0 if SRP=1, SIO1=1 if SRP=0. SRP

resets to 1.

NAP Self-Refresh. NSR=1 enables self-refresh in NAP mode. NSR can’t be set while in

NAP mode. NSR resets to 0.

PDN Self-Refresh. PSR=1 enables self-refresh in PDN mode. PSR can’t be set while in PDN

mode. PSR resets to 0.

Low Power Self-Refresh. LSR=1 enables longer self-refresh interval. The self-refresh

supply current is reduced. LSR resets to 0.

Temperature Sensing Enable. TEN=1 enables temperature sensing circuitry, permitting the

TSQ bit to be read to determine if a thermal trip point has been exceeded. TEN resets to 0.

Temperature Sensing Output. TSQ=1 when a temperature trip point has been exceeded,

TSQ=0 when it has not. TSQ is available during a current control operation (see Figure 51).

RDRAM Disable. DIS=1 causes RDRAM to ignore NAP/ PDN exit sequence, DIS=0

permits normal operation. This mechanism disables an RDRAM. DIS resets to 0.

Figure 27: INIT Register

Control Register: CNFGA

Address: 023

16

Read-only register.

15 14 13 12 11 10

9

0

8

7

6

5

0

4

0

3

2

1

0

REFBIT2..0 - Refresh Bank Bits. Specifies the number

of bank address bits used by REFA and REFP

commands. Permits multi-bank refresh in future

RDRAMs.

PVER5..0

REFBIT2..0

0 ₌0₁₀₀0

0

₌0₀₀₀₀₀₁

0

0₌^M_m0_m^VE_m^R_m^5._m^.0_m

0

^D0^BL

1

DBL - Doubled-Bank. DBL=1 means the device uses a

doubled-bank architecture with adjacent-bank depen-

dency. DBL=0 means no dependency.

MVER5..0 - Manufacturer Version. Specifies the

manufacturer identification number.

PVER5..0 - Protocol Version. Specifies the Direct

Protocol version used by this device:

0 - Compliant with version 0.62.

1 - Compliant with version 0.7 through this version.

2 to 63 - Reserved.

Note: In RDRAMs with protocol version 1 PVER[5:0] = 000001,

the range of the PDNX field (PDNX[2:0] in the PDNX register)

may not be large enough to specify the location of the restricted

interval in Figure 47. In this case, the effective t_S4parameter must

increase and no row or column packets may overlap the restricted

interval. See Figure 47 and Table 19.

Figure 28: CNFGA Register

Page 32

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

. .

Read-only register.

Control Register: CNFGB

Address: 024

16

15 14 13 12 11 10

9

0

8

7

6

5

0

4

3

2

1

0

BYT - Byte width. B=1 means the device reads and

writes 9-bit memory bytes. B=0 means 8 bits.

SVER5..0

CORG4..0

0 _{= xxxxx}

DEVTYP2..0

0

_{= ssss}0_ss

0

^S0^PT

₌0₀₀₀

0

^B0^YT

0

B

DEVTYP2..0 - Device type. DEVTYP = 000 means

that this device is an RDRAM.

SPT - Split-core. SPT=1 means the core is split, SPT=0 means it is not.

CORG4..0 - Core organization. This field specifies the number of

bank (3, 4, 5, or 6 bits), row (9, 10, 11, or 12 bits), and column (5, 6, or

7 bits) address bits. The encoding of this field will be specified in a

later version of this document.

SVER5..0 - Stepping version. Specifies the mask version number of

this device.

Figure 29: CNFGB Register

Control Register: TEST34

Control Register: DEVID

Address: 022

Address: 040

16

0

15 14 13 12 11 10

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

15 14 13 12 11 10

9

0

8

0

7

0

6

0

5

0

4

3

2

1

DEVID4..DEVID0

0

Read/ write register.

Reset value of TEST34 is zero (from SIO Reset)

This register are used for testing purposes. It must

not be read or written after SIO Reset.

Read/ write register.

Reset value is undefined.

Device Identification register.

DEVID4..DEVID0 is compared to DR4..DR0,

DC4..DC0, and DX4..DX0 fields for all memory

read or write transactions. This determines which

RDRAM is selected for the memory read or write

transaction.

Figure 30: TEST Register

Figure 31: DEVID Register

INFINEON Technologies Version 1.0

Preliminary Information

Page 33

Direct RAMBUS 72 Mbit (256kx18x16d)

Control Register: REFB

Control Register: REFR

Address: 041

Address: 042

16

0

15 14 13 12 11 10

9

0

8

0

7

0

6

0

5

0

4

0

3

2

1

0

15 14 13 12 11 10

9

0

8

7

6

5

4

3

2

1

REFB3..REFB0

REFR8..REFR0

0

Read/ write register.

Reset value is zero (from SETR/ CLRR).

Refresh Bank register.

Reset value is zero (from SETR/ CLRR).

Refresh Row register.

REFB3..REFB0 is the bank that will be refreshed

next during self-refresh. REFB3..0 is incremented

after each self-refresh activate and precharge

operation pair.

REFR8..REFR0 is the row that will be refreshed

next by the REFA command or by self-refresh.

REFR8..0 is incremented when BR3..0=1111 for the

REFA command. REFR8..0 is incremented when

REFB3..0=1111 for self-refresh.

Figure 32: REFB Register

Figure 34: REFR Register

Control Register: CCA

Control Register: CCB

Address: 043

Address: 044

16

0

16

0

15 14 13 12 11 10

9

0

8

7

6

5

4

3

2

1

15 14 13 12 11 10

9

0

8

7

6

5

4

3

2

1

0^ASYMA

0

0^ASYMB

CCA6..CCA0

CCB6..CCB0

0

.0

..0

Read/ write register.

Reset value is zero (SETR/ CLRR or SIO Reset).

CCA6..CCA0 - Current Control A. Controls the

Reset value is zero (SETR/ CLRR or SIO Reset).

CCB6..CCB0 - Current Control B. Controls the I

output current for the DQB8..DQB0 pins.

OL

I

output current for the DQA8..DQA0 pins.

OL

ASYMB0 control the asymmetry of the V / V

OL

OH

voltage swing about the V

for the DQA8..0 pins.

reference voltage

voltage swing about the V

for the DQB8..0 pins.

reference voltage

REF

Figure 33: CCA Register

Figure 35: CCB Register

Page 34

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

.

Read/ write register.

Control Register: NAPX

Address: 045

16

Reset value is undefined

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Note - t

is t

(SCK cycle time).

CYCLE1

SCYCLE

DQS

0

NAPX4..0

NAPXA4..0

0

NAPXA4..0 - Nap Exit Phase A. This field speci-

fies the number of SCK cycles during the first

phase for exiting NAP mode. It must satisfy:

NAPXA• t

≥ t

NAPXA,MAX

SCYCLE

Do not set this field to zero.

NAPX4..0 - Nap Exit Phase A plus B. This field specifies the number of

SCK cycles during the first plus second phases for exiting NAP mode. It

must satisfy:

NAPX• t

≥ NAPXA• t

+t

SCYCLE NAPXB,MAX

SCYCLE

Do not set this field to zero.

DQS - DQ Select. This field specifies the number of SCK cycles (0 => 0.5

cycles, 1 => 1.5 cycles) between the CMD pin framing sequence and the

device selection on DQ5..0. See Figure 48 - This field must be written

with a “1” for this RDRAM.

Figure 36: NAPX Register

Control Register: PDNXA

Address: 046

Control Register: PDNX

Address: 047

16

0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

PDNXA12..0

PDNX12..0

0

Read/ write register.

Reset value is undefined

PDNX4..0 - PDN Exit Phase A plus B. This field

specifies the number of (256• SCK cycle) units

during the first plus second phases for exiting

PDN mode. It should satisfy:

Read/ write register.

Reset value is undefined

PDNXA4..0 - PDN Exit Phase A. This field speci-

fies the number of (64• SCK cycle) units during

the first phase for exiting PDN mode. It must

satisfy:

PDNX• 256• t

≥ PDNXA• 64• t

+

SCYCLE

t

PDNXB,MAX

PDNXA• 64• t

≥ t

SCYCLE

PDNXA,MAX

If this cannot be satisfied, then the maximum

PDNX value should be written, and the t / t

timing window will be modified (see Figure 49).

Do not set this field to zero.

Note - only PDNXA5..0 are implemented.

S4 H4

Note - t

is t

(SCK cycle time).

CYCLE1

SCYCLE

Note - only PDNX2..0 are implemented.

Note - t

is t

(SCK cycle time).

CYCLE1

SCYCLE

Figure 37: PDNXA Register

Figure 38: PDNX Register

INFINEON Technologies Version 1.0

Preliminary Information

Page 35

Direct RAMBUS 72 Mbit (256kx18x16d)

.

The equations relating the core parameters to the

datasheet parameters follow:

Control Register: TPARM

Address: 048

16

15 14 13 12 11 10

9

0

8

0

7

0

6

0

5

4

0

3

2

1

0

t

= 2• t

= 1• t

CAS-C

CLS-C

CPS-C

CYCLE

TCDLY0

0

TCLS

TCAS

0

Not programmable

+ t - 1• t

CYCLE

Read/ write register.

t

= t

+ t

CPS-C

Reset value is undefined.

TCAS1..0 - Specifies the t

OFFP

CAS-C

CYCLE

CLS-C

= 4• t

core parameter in

CAS-C

t

units. This should be “10” (2• t

).

CYCLE

t

= t

+ 1• t

- t

RCD

RCD-C

CYCLE CLS-C

- 1• t

CYCLE

TCLS1..0 - Specifies the t

core parameter in

CLS-C

t

units. Should be “10” (2• t

).

CYCLE

TCDLY0 - Specifies the t

core parameter in

CDLY0-C

t

= 3• t

+ t

CDLY0-C CDLY1-C

CAC

CYCLE

CLS-C

t

units. This adds a programmable delay to

CYCLE

(see table below for programming ranges)

Q (read data) packets, permitting round trip read

delay to all devices to be equalized. This field may

be written with the values “010” (2• t

TCDLY0

010

TCDLY1

000

t_CDLY0-C

2• t_CYCLE

3• t_CYCLE

4• t_CYCLE

5• t_CYCLE

t_CDLY1-Ct_CAC@ t_CYCLE= 3.3ns t_CAC@ t_CYCLE= 2.5ns

0• t_CYCLE

1• t_CYCLE

2• t_CYCLE

7• t_CYCLE

8• t_CYCLE

9• t_CYCLE

10• t_CYCLE

11• t_CYCLE

12• t_CYCLE

not allowed

8• t_CYCLE

)

CYCLE

011

000

through “101” (5• t

).

CYCLE

011

001

9• t_CYCLE

011

010

10• t_CYCLE

11• t_CYCLE

12• t_CYCLE

100

010

101

010

Figure 39: TPARM Register

Control Register: TFRM

Control Register: TCDLY1

Address: 049

Address: 04a

16

0

16

0

15 14 13 12 11 10

9

0

8

0

7

0

6

0

5

0

4

0

3

2

1

15 14 13 12 11 10

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

1

TFRM3..0

0

0^TCDLY1

Read/ write register.

Reset value is undefined.

TFRM3..0 - Specifies the position of the framing

point in t units. This value must be greater

Read/ write register.

Reset value is undefined.

TCDLY1 - Specifies the value of the t

core

CDLY1-C

parameter in t

units. This adds a program-

CYCLE

than or equal to the t

parameter. This is

mable delay to Q (read data) packets, permitting

round trip read delay to all devices to be equal-

ized. This field may be written with the values

FRM,MIN

the minimum offset between a ROW packet

(which places a device at ATTN) and the first

COL packet (directed to that device) which must

be framed. This field may be written with the

“000” (0• t

) through “010” (2• t

). Refer

CYCLE

to Figure 39 for more details.

values “0111” (7• t

) through “1010”

CYCLE

(10• t

). TFRM is usually set to the value

CYCLE

which matches the largest t

parameter

RCD,MIN

(modulo 4• t

) that is present in an RDRAM

CYCLE

in the memory system. Thus, if an RDRAM with

= 11• t were present, then TFRM

t

RCD,MIN

CYCLE

would be programmed to 7• t

.

CYCLE

Figure 40: TFRM Register

Figure 41: TRDLY Register

Page 36

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

Control Register: SKIP

Address: 04b

Control Register: TCYCLE

Address: 04c

16

0

15 14 13 12 11 10

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

AS MSE MS

TCYCLE13..TCYCLE0

0

Read/ write register (except AS field).

Reset value is zero (SIO Reset).

Read/ write register.

Reset value is undefined

TCYCLE13..0 - Specifies the value of the t

AS - Autoskip. Read-only value determined by

autoskip circuit and stored when SETF serial

command is received by RDRAM during initial-

ization. In figure 58, AS=1 corresponds to the

early Q(a1) packet and AS=0 to the Q(a1) packet

CYCLE

datasheet parameter in 64ps units. For the

of 2.5ns (2500ps), this field should be

t

CYCLE,MIN

written with the value “00027 ” (39• 64ps).

one t

later for the four uncertain cases.

16

CYCLE

MSE - Manual skip enable (0=auto, 1=manual).

MS - Manual skip (MS must be 1 when MSE=1).>

During initialization, the RDRAMs at the furthest

point in the fifth read domain may have selected

the AS=0 value, placing them at the closest point

in a sixth read domain. Setting the MSE/ MS fields

to 1/ 1 overrides the autoskip value and returns

them to the furthest point of the fifth read

domain.

Figure 42: SKIP Register

Figure 44: TCYCLE Register

Control Register: TEST77

Control Register: TEST78

Control Register: TEST79

Address: 04d

Address: 04e

Address: 04f

16

0

15 14 13 12 11 10

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Read/ write registers.

Reset value of TEST78,79 is zero ( SIO Reset).

Do not read or write TEST78,79 after SIO reset.

TEST77 must be written with zero after SIO reset.

These registers must only be used for testing

purposes.

Figure 43: TEST Registers

INFINEON Technologies Version 1.0

Preliminary Information

Page 37

Direct RAMBUS 72 Mbit (256kx18x16d)

long exit latency because the TCLK/ RCLK block must

resynchronize itself to the external clock signal.

Power State Management

Table 16 summarizes the power states available to a

Direct RDRAM. In general, the lowest power states

have the longest operational latencies. For example,

the relative power levels of PDN state and STBY state

have a ratio of about 1:110, and the relative access

latencies to get read data have a ratio of about 250:1.

NAP state is another low-power state in which either

self-refresh or REFA-refresh are used to maintain the

core. See “Refresh” on page 42 for a description of the

two refresh mechanisms. NAP has a shorter exit

latency than PDN because the TCLK/ RCLK block

maintains its synchronization state relative to the

external clock signal at the time of NAP entry. This

PDN state is the lowest power state available. The

information in the RDRAM core is usually maintained

with self-refresh; an internal timer automatically

refreshes all rows of all banks. PDN has a relatively

imposes a limit (t

) on how long an RDRAM may

NLIMIT

remain in NAP state before briefly returning to STBY

or ATTN to update this synchronization state.

Table 16: Power State Summary

Power

State

Blocks consuming

power

Power

State

Blocks consuming

power

Description

PDN

Powerdown state.

Self-refresh

NAP

Nap state. Similar to

PDN except lower

wake-up latency.

Self-refresh or

REFA-refresh

TCLK/ RCLK-Nap

STBY

Standby state.

Ready for ROW

packets.

REFA-refresh

TCLK/ RCLK

ROW demux receiver

ATTN

Attention state.

Ready for ROW and

COL packets.

REFA-refresh

TCLK/ RCLK

ROW demux receiver

COL demux receiver

ATTNR

Attention read state.

Ready for ROW and

COL packets.

Sending Q (read data)

packets.

REFA-refresh

TCLK/ RCLK

ROW demux receiver

COL demux receiver

DQ mux transmitter

Core power

ATTNW

Attention write state.

Ready for ROW and

COL packets.

Ready for D (write data)

packets.

REFA-refresh

TCLK/ RCLK

ROW demux receiver

COL demux receiver

DQ demux receiver

Core power

Figure 45 summarizes the transition conditions needed

for moving between the various power states. Note

that NAP and PDN have been divided into two

substates (NAP-A/ NAP-S and PDN-A/ PDN-S) to

account for the fact that a NAP or PDN exit may be

made to either ATTN or STBY states.

RDRAM returns to the ATTN or STBY state it was orig-

inally in when it first entered NAP or PDN.

An RDRAM may only remain in NAP state for a time

t

. It must periodically return to ATTN or STBY.

NLIMIT

The NAPRC command causes a napdown operation if

the RDRAM’s NCBIT is set. The NCBIT is not directly

visible. It is undefined on reset. It is set by a NAPR

command to the RDRAM, and it is cleared by an ACT

command to the RDRAM. It permits a controller to

manage a set of RDRAMs in a mixture of power states.

At initialization, the SETR/ CLRR Reset sequence will

put the RDRAM into PDN-S state. The PDN exit

sequence involves an optional PDEV specification and

bits on the CMD and SIO pins.

IN

Once the RDRAM is in STBY, it will move to the

ATTN/ ATTNR/ ATTNW states when it receives a non-

broadcast ROWA packet or non-broadcast ROWR

packet with the ATTN command. The RDRAM returns

to STBY from these three states when it receives a RLX

command. Alternatively, it may enter NAP or PDN

state from ATTN or STBY states with a NAPR or

PDNR command in an ROWR packet. The PDN or

NAP exit sequence involves an optional PDEV specifi-

cation and bits on the CMD and SIO0 pins. The

STBY state is the normal idle state of the RDRAM. In

this state all banks and sense amps have usually been

left precharged and ROWA and ROWR packets on the

ROW pins are being monitored. When a non-broadcast

ROWA packet or non-broadcast ROWR packet (with

the ATTN command) packet addressed to the RDRAM

is seen, the RDRAM enters ATTN state (see the right

side of Figure 46). This requires a time t during

SA

which the RDRAM activates the specified row of the

specified bank. A time TFRM• t

after the ROW

CYCLE

Page 38

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

packet, the RDRAM will be able to frame COL packets

(TFRM is a control register field - see Figure 40). Once

in ATTN state, the RDRAM will automatically transi-

tion to the ATTNW and ATTNR states as it receives

WR and RD commands.

Figure 47 shows the NAP entry sequence (left). NAP

state is entered by sending a NAPR command in a

ROW packet. A time t

is required to enter NAP

ASN

state (this specification is provided for power calcula-

tion purposes). The clock on CTM/ CFM must remain

stable for a time t after the NAPR command.

CD

automatic

The RDRAM may be in ATTN or STBY state when the

NAPR command is issued. When NAP state is exited,

the RDRAM will return to the original starting state

(ATTN or STBY). If it is in ATTN state and a RLXR

command is specified with NAPR, then the RDRAM

will return to STBY state when NAP is exited.

ATTNR

ATTN

ATTNW

automatic

t_NLIMIT

Figure 47 also shows the PDN entry sequence (right).

PDN state is entered by sending a PDNR command in

NAPR • RLXR

NAP-A

a ROW packet. A time t

is required to enter PDN

ASP

PDEV.CMD• SIO0

NAPR • RLXR

state (this specification is provided for power calcula-

tion purposes). The clock on CTM/ CFM must remain

NAP

NAP-S

stable for a time t after the PDNR command.

PDEV.CMD• SIO0

CD

The RDRAM may be in ATTN or STBY state when the

PDNR command is issued. When PDN state is exited,

the RDRAM will return to the original starting state

(ATTN or STBY). If it is in ATTN state and a RLXR

command is specified with PDNR, then the RDRAM

will return to STBY state when PDN is exited. The

current- and slew-rate-control levels are re-established.

PDNR • RLXR

PDEV.CMD• SIO0

PDNR • RLXR

PDN-A

PDN

PDN-S

PDEV.CMD• SIO0

SETR/ CLRR

The RDRAM’s write buffer must be retired with the

appropriate COP command before NAP or PDN are

entered. Also, all the RDRAM’s banks must be

STBY

Notation:

SETR/ CLRR - SETR/ CLRR Reset sequence in SRQ packets

PDNR - PDNR command in ROWR packet

NAPR - NAPR command in ROWR packet

RLXR - RLX command in ROWR packet

RLX - RLX command in ROWR,COLC,COLX packets

SIO0 - SIO0 input value

PDEV.CMD - (PDEV=DEVID)• (CMD=01)

ATTN - ROWA packet (non-broadcast) or ROWR packet

(non-broadcast) with ATTN command

precharged before NAP or PDN are entered. The

exception to this is if NAP is entered with the NSR bit

of the INIT register cleared (disabling self-refresh in

NAP). The commands for relaxing, retiring, and

precharging may be given to the RDRAM as late as the

ROPa0, COPa0, and XOPa0 packets in Figure 47. No

broadcast packets nor packets directed to the RDRAM

entering Nap or PDN may overlay the quiet window.

Figure 45: Power State Transition Diagram

Once the RDRAM is in ATTN, ATTNW, or ATTNR

states, it will remain there until it is explicitly returned

to the STBY state with a RLX command. A RLX

command may be given in an ROWR, COLC , or

COLX packet (see the left side of Figure 46). It is

usually given after all banks of the RDRAM have been

precharged; if other banks are still activated, then the

RLX command would probably not be given.

This window extends for a time t

with the NAPR or PDNR command.

after the packet

NPQ

Figure 48 shows the NAP and PDN exit sequences.

These sequences are virtually identical; the minor

differences will be highlighted in the following

description.

Before NAP or PDN exit, the CTM/ CFM clock must be

stable for a time t . Then, on a falling and rising edge

CE

If a broadcast ROWA packet or ROWR packet (with the

ATTN command) is received, the RDRAM’s power

state doesn’t change. If a broadcast ROWR packet with

RLXR command is received, the RDRAM goes to STBY.

of SCK, if there is a “01” on the CMD input, NAP or

PDN state will be exited. Also, on the falling SCK edge

the SIO0 input must be at a 0 for NAP exit and 1 for

PDN exit.

INFINEON Technologies Version 1.0

Preliminary Information

Page 39

Direct RAMBUS 72 Mbit (256kx18x16d)

If the PSX bit of the INIT register is 0, then a device

PDEV5..0 is specified for NAP or PDN exit on the

DQA5..0 pins. This value is driven on the rising SCK

edge 0.5 or 1.5 SCK cycles after the original falling

edge, depending upon the value of the DQS bit of the

NAPX register. If the PSX bit of the INIT register is 1,

then the RDRAM ignores the PDEV5..0 address packet

and exits NAP or PDN when the wake-up sequence is

presented on the CMD wire. The ROW and COL pins

be directed to the RDRAM which is now in ATTN or

STBY state.

Figure 49 shows the constraints for entering and

exiting NAP and PDN states. On the left side, an

RDRAM exits NAP state at the end of cycle T . This

3

RDRAM may not re-enter NAP or PDN state for an

interval of t

. The RDRAM enters NAP state at the

NU0

end of cycle T . This RDRAM may not re-exit NAP

13

state for an interval of t

. The equations for these

NU1

must be quiet at a time t / t around the indicated

S4 H4

two parameters depend upon a number of factors, and

are shown at the bottom of the figure. NAPX is the

value in the NAPX field in the NAPX register.

falling SCK edge (timed with the PDNX or NAPX

register fields). After that, ROW and COL packets may

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀T T

21

T

₂₂T₂₃

0

T

T₄

T

T₈

T

₁₁T₁₂

T

T₁₆

T

T T T

21 22 23

20

1

2

3

5

6

7

9

10

13 14

17 18

1

2

3

5

6

7

9

10

13 14 15

17 18 19

CTM/CFM

ROP = non-broadcast

ROWA or ROWR/ATTN

a0 = {d0,b0,r0}

a1 = {d1,b1,c1}

ROW2

RLXR

ROP a0

..ROW0

No COL packets may be

placed in the three

COP a1

XOP a1

indicated positions; i.e. at

(TFRM - {1,2,3})• t_CYCLE

COP a1

COL4

..COL0

COL4

..COL0

XOP a1

RLXC

RLXX

COP a1 COP a0

.

XOP a1

XOP a0

A COL packet to device d0

(or any other device) is okay

at

TFRM• t

CYCLE

DQA8..0

DQB8..0

DQA8..0

DQB8..0

(TFRM)• t_CYCLE

or later.

t

SA

AS

A COL packet to another

device (d1!= d0) is okay at

(TFRM - 4)• t_CYCLE

or earlier.

Power

State

Power

State

ATTN

STBY

ATTN

Figure 46: STBY Entry (left) and STBY Exit (right)

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀T T

21

T

₂₂T₂₃

0

T

T₄

T

T₈

T

₁₁T₁₂

T

T₁₆

T

T T T

21 22 23

20

1

2

3

5

6

7

9

10

13 14

17 18

1

2

3

5

6

7

9

10

13 14 15

17 18 19

CTM/CFM

a0 = {d0,b0,r0,c0}

a1 = {d1,b1,r1,c1}

t

CD

No ROW or COL packets

directed to device d0 may

overlap the restricted

interval. No broadcast

ROW packets may overlap

the quiet interval.

ROW2

..ROW0

ROW2

..ROW0

ROP a0 restricted ROP a1

ROP a0

(PDNR)

ROP a1

quiet

^rq^esu^trii^ce^tet^d

(NAPR)

t

NPQ

COL4

..COL0

COL4

..COL0

COP a0

XOP a0

COP a1

XOP a1

COP a0

XOP a0

COP a1

XOP a1

restricted

quiet

^rq^esu^trii^ce^tet^d

ROW or COL packets to a

device other than d0 may

overlap the restricted

interval.

DQA8..0

DQB8..0

DQA8..0

DQB8..0

ROW or COL packets

directed to device d0 after

the restricted interval will

be ignored.

t

ASP

ASN

Power

State

Power

State

a

ATTN/STBY

NAP

ATTN/STBY

PDN

a

The (eventual) NAP/PDN exit will be to the same ATTN/STBY state the RDRAM was in prior to NAP/PDN entry

Figure 47: NAP Entry (left) and PDN Entry (right)

On the right side of Figure 48, an RDRAM exits PDN

state at the end of cycle T . This RDRAM may not re-

enter PDN or NAP state for an interval of t

RDRAM enters PDN state at the end of cycle T . This

. The

PU0

3

13

Page 40

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

RDRAM may not re-exit PDN state for an interval of

. The equations for these two parameters depend

of the figure. PDNX is the value in the PDNX field in

the PDNX register.

t

PU1

upon a number of factors, and are shown at the bottom

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀

T

₂₃T₂₄

T

₂₇T₂₈

T

₃₅T₃₆

T

₃₉T₄₀

T

₄₃T₄₄T T T

45 46 47

1

2

3

5

6

7

9

10

13 14

17 18

21 22

25 26

29 30 31

33 34

37 38

41 42

32

CTM/CFM

If PSX=1 in Init register,

then NAP/PDN exit is

broadcast (no PDEV field).

ROW2

..ROW0

No ROW packets may

overlap the restricted

interval

ROP

restricted

ROP

t

S4 H4

No COL packets may

overlap the restricted

interval if device PDEV is

exiting the NAP-A or PDN-

A states

COL4

..COL0

COP

XOP

COP

XOP

restricted

t

S3 H3 S3 H3

t

S4 H4

DQA8..0

DQB8..0

PDEV5..0^bPDEV5..0^b

DQS=0 ^{b ,c}

t

CE

DQS=1 ^b

SCK

CMD

SIO0

SIO1

0

1

Effective hold becomes

_H4’=t_H4+[PDNXA• 64• t_SCYCLE+t_{PDNXB,M AX}]-[PDNX• 256• t_SCYCLE

if [PDNX• 256• t_SCYCLE] < [PDNXA• 64• t_SCYCLE+t_PDNXB,MAX].

t

]

0/1^a

The packet is repeated

from SIO0 to SIO1

0/1^a

(NAPX)• t_SCYCLE)/(256• PDNX• t_SCYCLE

)

Power

State

d

NAP/PDN

STBY/ATTN

DQS=0 ^bDQS=1^b

^cThe DQS field must be written with “1” for this RDRAM.

Exit to STBY or ATTN depends upon whether RLXR was

^aUse 0 for NAP exit, 1 for PDN exit

d

b

asserted at NAP or PDN entry time

Device selection timing slot is selected by DQS field of NAPX register

Figure 48: NAP and PDN Exit

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀

T

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

T₁₆

T

2

1

2

3

5

6

7

9

10

13 14

17 18

21 22 23

1

2

3

5

6

7

9

10

13 14 15

17 18 19

20

CTM/CFM

NAP entry

PDN entry

ROW2

NAPR

PDNR

..ROW0

SCK

NAP exit

PDN exit

0

1

0

1

0

1

0

1

CMD

t

PU0

no entry to NAP or PDN

PU1

NU0

NU1

no exit

no entry to NAP or PDN

no exit

t_NU0= 5• t_CYCLE+ (2+NAPX)• t_SCYCLE

t_PU0= 5• t_CYCLE+ (2+256• PDNX)• t_SCYCLE

t_NU1= 8• t_CYCLE- (0.5• t_SCYCLE

= 23• t_CYCLE

)

t_PU1= 8• t_CYCLE- (0.5• t_SCYCLE

= 23• t_CYCLE

)

if NSR=0

if NSR=1

if PSR=0

if PSR=1

Figure 49: NAP Entry/Exit Windows (left) and PDN Entry/Exit Windows (right)

INFINEON Technologies Version 1.0

Preliminary Information

Page 41

Direct RAMBUS 72 Mbit (256kx18x16d)

precharge the refreshed bank in all RDRAMs. After a

bank is given a REFA command, no other core opera-

tions (activate or precharge) should be issued to it until

it receives a REFP.

Refresh

RDRAMs, like any other DRAM technology, use vola-

tile storage cells which must be periodically refreshed.

This is accomplished with the REFA command.

Figure 50 shows an example of this.

It is also possible to interleave refresh transactions (not

shown). In the figure, the ACT b0 command would be

replaced by a REFA b0 command. The b0 address

would be broadcast to all devices, and would be

{Broadcast,Ba+2,REFR}. Note that the bank address

should skip by two to avoid adjacent bank interfer-

ence. A possible bank incrementing pattern would be:

{13, 11, 9, 7, 5, 3, 1, 8, 10, 12, 14, 0, 2, 4, 6, 15}. Every time

bank 15 is reached, the REFA command would auto-

matically increment the REFR register.

The REFA command in the transaction is typically a

broadcast command (DR4T and DR4F are both set in

the ROWR packet), so that in all devices bank number

Ba is activated with row number REFR, where REFR is

a control register in the RDRAM. When the command

is broadcast and ATTN is set, the power state of the

RDRAMs (ATTN or STBY) will remain unchanged.

The controller increments the bank address Ba for the

next REFA command. When Ba is equal to its

A second refresh mechanism is available for use in

PDN and NAP power states. This mechanism is called

self-refresh mode. When the PDN power state is

entered, or when NAP power state is entered with the

NSR control register bit set, then self-refresh is auto-

matically started for the RDRAM.

maximum value, the RDRAM automatically incre-

ments REFR for the next REFA command.

On average, these REFA commands are sent once

BBIT+RBIT

every t

/ 2

(where BBIT are the number of

REF

bank address bits and RBIT are the number of row

address bits) so that each row of each bank is refreshed

once every t

Self-refresh uses an internal time base reference in the

interval.

REF

RDRAM. This causes an activate and precharge to be

BBIT+RBIT

The REFA command is equivalent to an ACT

command, in terms of the way that it interacts with

other packets (see Table 10). In the example, an ACT

carried out once in every t

/ 2

interval. The

REF

REFB and REFR control registers are used to keep track

of the bank and row being refreshed.

command is sent after t to address b0, a different

(non-adjacent) bank than the REFA command.

RR

Before a controller places an RDRAM into self-refresh

mode, it should perform REFA/ REFP refreshes until

the bank address is equal to the maximum value. This

ensures that no rows are skipped. Likewise, when a

controller returns an RDRAM to REFA/ REFP refresh,

it should start with the minimum bank address value

(zero).

A second ACT command can be sent after a time t to

RC

address c0, the same bank (or an adjacent bank) as the

REFA command.

Note that a broadcast REFP command is issued a time

t

after the initial REFA command in order to

RAS

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀

T

₂₃T₂₄

T

₂₇T₂₈

T

₃₅T₃₆

T

₃₉T₄₀

T

₄₃T₄₄T T T

45 46 47

1

2

3

5

6

7

9

10

13 14

17 18

21 22

25 26

29 30 31

33 34

37 38

41 42

32

CTM/CFM

t

RC

ROW2

REFA a0

ACT b0

REFP a1

ACT c0

REFA d0

..ROW0

t

RAS

RP

COL4

..COL0

t

RR

BBIT+RBIT

t

/2

REF

DQA8..0

DQB8..0

a1 = {Broadcast,Ba}

BBIT = # bank address bits

RBIT = # row address bits

REFB = REFB3..REFB0

REFR = REFR8..REFR0

Transaction a: REFA

Transaction b: xx

Transaction c: xx

a0 = {Broadcast,Ba,REFR}

b0 = {Db, /={Ba,Ba+1,Ba-1}, Rb}

c0 = {Dc, ==Ba, Rc}

Transaction d: REFA d0 = {Broadcast,Ba+1,REFR}

Figure 50: REFA/REFP Refresh Transaction Example

Page 42

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

CAL command). The RDRAM samples the last calibra-

Current and Temperature Control

tion packet and adjusts its I current value.

OL

Figure 51 shows an example of a transaction which

performs current control calibration. It is necessary to

perform this operation once to every RDRAM in every

Unlike REF commands, CAL and SAM commands

cannot be broadcast. This is because the calibration

packets from different devices would interfere. There-

fore, a current control transaction must be sent every

t

interval in order to keep the I output current

OL

CCTRL

in its proper range.

t

/ N, where N is the number of RDRAMs on the

CCTRL

This example uses four COLX packets with a CAL

command. These cause the RDRAM to drive four cali-

Channel. The device field Da of the address a0 in the

CAL/ SAM command should be incremented after

each transaction.

bration packets Q(a0) a time t

later. An offset of

CAC

t

must be placed between the Q(a0) packet and

RDTOCC

Figure 23 shows an example of a temperature calibra-

tion sequence to the RDRAM. This sequence is broad-

read data Q(a1)from the same device. These calibration

packets are driven on the DQA4..3 and DQB4..3 wires.

The TSQ bit of the INIT register is driven on the DQA5

wire during same interval as the calibration packets.

The remaining DQA and DQB wires are not used

during these calibration packets. The last COLX packet

also contains a SAM command (concatenated with the

cast once every t

interval to all the RDRAMs on

TEMP

the Channel. The TCEN and TCAL are ROP

commands, and cause the slew rate of the output

drivers to adjust for temperature drift. During the

quiet interval t

the devices being calibrated

TCQUIET

can’t be read, but they can be written.

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀

T

₂₃T₂₄

T

₂₇T₂₈

T

₃₅T₃₆

T

₃₉T₄₀

T

₄₃T₄₄T T T

45 46 47

1

2

3

5

6

7

9

10

13 14

17 18

21 22

25 26

29 30 31

33 34

37 38

41 42

32

CTM/CFM

Read data from a different

device from a later RD

command can be

anywhere after to the

Q(a0) packet.

Read data from the same

device from a later RD

command must be at this

packet position or later.

Read data from the same

device from an earlier RD

command must be at this

packet position or earlier.

Read data from a different

device from an earlier RD

command can be anywhere

prior to the Q(a0) packet. .

ROW2

..ROW0

t

CCTRL

COL4

..COL0

CAL a0

CAL/SAM a0

CAL a2

CAL

t

CAC

CCSAMTOREAD

Q (a1)

Q (a0)

DQA8..0

DQB8..0

DQA5 of the first calibrate packet has the inverted TSQ bit of INIT

control register; i.e. logic 0 or high voltage means hot temperature.

When used for monitoring, it should be enabled with the DQA3

bit (current control one value) in case there is no RDRAM present:

HotTemp = DQA5• DQA3

t

READTOCC

Transaction a0: CAL/SAM

Transaction a1: RD

Transaction a2: CAL/SAM

a0 = {Da, Bx}

a1 = {Da, Bx}

a2 = {Da, Bx}

Note that DQB3 could be used instead of DQA3.

Figure 51: Current Control CAL/SAM Transaction Example

T₀

T

T₄

T

T₈

T

₁₁T₁₂

T

₁₅T₁₆

T

₁₉T₂₀

T

₂₃T₂₄

T

₂₇T₂₈

T

₃₅T₃₆

T

₃₉T₄₀

T

₄₃T₄₄T T T

45 46 47

1

2

3

5

6

7

9

10

13 14

17 18

21 22

25 26

29 30 31

33 34

37 38

41 42

32

CTM/CFM

t

TEMP

ROW2

..ROW0

TCEN

TCAL

t_TCEN

TCEN

t

TCAL

t

TCQUIET

COL4

..COL0

Any ROW packet may be

placed in the gap between the

ROW packets with the TCEN

and TCAL commands.

DQA8..0

DQB8..0

No read data from devices

being calibrated

Figure 52: Temperature Calibration (TCEN-TCAL) Transactions to RDRAM

INFINEON Technologies Version 1.0

Preliminary Information

Page 43

Direct RAMBUS 72 Mbit (256kx18x16d)

Electrical Conditions

Table 17: Electrical Conditions

Parameter and Conditions

Junction temperature under bias

Symbol

Min

Max

Unit

T_J

TBD

2.50 - 0.13

-

TBD

2.50 + 0.13

2.0

°C

V

_DD,V_DDA

Supply voltage

_DD,N,V_DDA,N

Supply voltage droop (DC) during NAP interval (t_NLIMIT

Supply voltage ripple (AC) during NAP interval (t_{N LIMIT}

)

%

v

_{DD,N ,}v_DDA,N

-2.0

2.0

V_CMOS

Supply voltage for CMOS pins (2.5V controllers)

Supply voltage for CMOS pins (1.8V controllers)

2.50 - 0.13

1.80 - 0.1

2.50 + 0.25

1.80 + 0.2

V

V_TERM

V_REF

Termination voltage

1.80 - 0.1

1.80 + 0.1

1.40 + 0.2

V_REF- 0.2

V_REF+ 0.5

1.0

V

%

V

Reference voltage

1.40 - 0.2

V_DIL

RSL data input - low voltage

RSL data input - high voltage

RSL data input swing: V_DIS= V_DIH- V_DIL

V_REF- 0.5

V_DIH

V_REF+ 0.2

V_DIS

0.4

A_DI

RSL data asymmetry: A_DI= [(V_DIH- V_REF) + (V_DIL- V_REF)]/ V_DIS

RSL clock input - crossing point of true and complement signals

RSL clock input - common mode V_CM= (V_CIH+V_CIL)/ 2

RSL clock input swing: V_CIS= V_CIH- V_CIL(CTM,CTMN pins).

RSL clock input swing: V_CIS= V_CIH- V_CIL(CFM,CFMN pins).

CMOS input low voltage

0

-20

V_X

1.3

1.8

V_CM

1.4

0.35

1.7

V_CIS,CTM

V_CIS,CFM

V_IL,CMOS

V_IH,CMOS

0.70

0.125

0.70

- 0.3

V_CMOS/ 2 - 0.25

V_CMOS+0.3

CMOS input high voltage

V_CMOS/ 2 + 0.25

Timing Conditions

Table 18: Timing Conditions

Symbol

Parameter

Min

Max

Unit

Figure(s)

t_CYCLE

CTM and CFM cycle times (-600)

CTM and CFM cycle times (-711)

CTM and CFM cycle times (-800)

3.33

2.80

2.50

3.83

ns

Figure 53

t_CR, t_CF

CTM and CFM input rise and fall times

CTM and CFM high and low times

0.2

0.5

ns

Figure 53

t

_CH, t_CL

40%

60%

t_CYCLE

t_TR

CTM-CFM differential (MSE/ MS=0/ 0)

CTM-CFM differential (MSE/ MS=1/ 1)^a

0.0

0.9

1.0

Figure 42

Figure 53

t_DCW

Domain crossing window

-0.1

0.2

0.1

t_CYCLE

ns

Figure 59

Figure 54

t

_DR, t_DF

DQA/ DQB/ ROW/ COL input rise/ fall times

0.65

Page 44

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

Table 18: Timing Conditions

Symbol

Parameter

Min

Max

Unit

Figure(s)

t_S, t_H

DQA/ DQB/ ROW/ COL-to-CFM set/ hold @ t_CYCLE=3.33ns

DQA/ DQB/ ROW/ COL-to-CFM set/ hold @ t_CYCLE=2.81ns

DQA/ DQB/ ROW/ COL-to-CFM set/ hold @ t_CYCLE=2.50ns

0.275^b,d

0.240^c,d

0.200^d

-

ns

Figure 54

t_DR1,t_DF1

SIO0, SIO1 input rise and fall times

-

5.0

ns

Figure 56

t

_DR2,t_DF2

CMD, SCK input rise and fall times

2.0

-

t_CYCLE1

SCK cycle time - Serial control register transactions

SCK cycle time - Power transitions

1000

10

4.25

1

ns

-

ns

t

_CH1, t_CL1

SCK high and low times

-

ns

t_S1

CMD setup time to SCK rising or falling edge^e

CMD hold time to SCK rising or falling edge^c

SIO0 setup time to SCK falling edge

-

ns

t_H1

1

-

ns

t_S2

40

0

-

ns

t_H2

SIO0 hold time to SCK falling edge

-

ns

t_S3

PDEV setup time on DQA5..0 to SCK rising edge.

PDEV hold time on DQA5..0 to SCK rising edge.

ROW2..0, COL4..0 setup time for quiet window

ROW2..0, COL4..0 hold time for quiet window^f

-

ns

Figure 48,

Figure 57

t_H3

5.5

-1

-

ns

t_S4

-

t_CYCLE

V

Figure 48

t_H4

5

-

v_IL,CMOS

CMOS input low voltage - over/ undershoot voltage dura-

tion is less than or equal to 5ns

- 0.7

V_CMOS/ 2

- 0.6

v_IH,CMOS

CMOS input high voltage - over/ undershoot voltage dura-

tion is less than or equal to 5ns

V_CMOS/ 2

+ 0.6

V_CMOS

0.7

+

V

t_NPQ

Quiet on ROW/ COL bits during NAP/ PDN entry

Offset between read data and CC packets (same device)

Offset between CC packet and read data (same device)

CTM/ CFM stable before NAP/ PDN exit

CTM/ CFM stable after NAP/ PDN entry

ROW packet to COL packet ATTN framing delay

Maximum time in NAP mode

4

12

8

-

t_CYCLE

µs

Figure 47

Figure 51

Figure 48

Figure 47

Figure 46

Figure 45

Figure 50

Figure 51

Figure 23

page 28

t_READTOCC

t_CCSAMTOREAD

t_CE

-

2

-

t_CD

100

7

-

t_FRM

-

10.0

32

t_NLIMIT

t_REF

t_CCTRL

t_TEMP

Refresh interval

ms

Current control interval

34 t_CYCLE

100ms

100

-

ms/ t_CYCLE

ms

Temperature control interval

t_TCEN

TCE command to TCAL command

TCAL command to quiet window

150

2

t_CYCLE

µs

t_TCAL

2

t_TCQUIET

t_PAUSE

Quiet window (no read data)

140

-

RDRAM delay (no RSL operations allowed)

200.0

a. MSE/ MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0.

INFINEON Technologies Version 1.0

Preliminary Information

Page 45

Direct RAMBUS 72 Mbit (256kx18x16d)

b. This parameter also applies to a -800 or -711 part when operated with t_CYCLE=3.33ns.

c. This parameter also applies to a -800 part when operated with t_CYCLE=2.81ns.

d. t_S,MINand t_H,MINfor other t_CYCLEvalues can be interpolated between or extrapolated from the timings at the 3 specified t_CYCLEvalues.

e. With V_IL,CMOS=0.5V_CMOS-0.6V and V_IH,CMOS=0.5V_CMOS+0.6V

f. Effective hold becomes t_H4’=t_H4+[PDNXA• 64• t_SCYCLE+t_PDNXB,MAX]-[PDNX• 256• t_SCYCLE

]

if [PDNX• 256• t_SCYCLE] < [PDNXA• 64• t_SCYCLE+t_PDNXB,MAX]. See Figure 48.

Page 46

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

Electrical Characteristics

Table 19: Electrical Characteristics

Symbol

Parameter and Conditions

Min

Max

Unit

Θ_JC

Junction-to-Case thermal resistance

V_REFcurrent @ V_REF,MAX

TBD

10

°C/ Watt

µA

I_REF

-10

I_OH

RSL output high current @ (0≤V_OUT≤V_DD

)

-10

10

µA

a

I_ALL

RSL I_OLcurrent @ V_OL= 0.9V, V_DD,MIN, T_J,MAX

RSL I_OLcurrent resolution step

30.0

90.0

2.0

-

mA

Ω

∆I_OL

-

150

r_OUT

Dynamic output impedance

I_I,CMOS

V_OL,CMOS

V_OH,CMOS

CMOS input leakage current @ (0≤V_I,CMOS≤V_CMOS

CMOS output voltage @ I_OL,CMOS= 1.0mA

CMOS output high voltage @ I_OH,CMOS= -0.25mA

)

-10.0

-

10.0

0.3

-

µA

V

V_CMOS-0.3

V

a. This measurement is made in manual current control mode; i.e. with all output device legs sinking current.

Timing Characteristics

Table 20: Timing Characteristics

Symbol

Parameter

Min

Max

Unit

Figure(s)

t_Q

CTM-to-DQA/ DQB output time @ t_CYCLE=3.33ns

CTM-to-DQA/ DQB output time @ t_CYCLE=2.81ns

CTM-to-DQA/ DQB output time @ t_CYCLE=2.50ns

-0.350^a,c

-0.300^b,c

-0.260^c

+0.350^a,c

+0.300^b,c

+0.260^c

ns

Figure 55

t_QR, t_QF

t_Q1

DQA/ DQB output rise and fall times

SCK(neg)-to-SIO0 delay @ C_LOAD,MAX= 20pF (SD read data valid).

SCK(pos)-to-SIO0 delay @ C_LOAD,MAX= 20pF (SD read data hold).

SIO_OUTrise/ fall @ C_LOAD,MAX= 20pF

SIO0-to-SIO1 or SIO1-to-SIO0 delay @ C_LOAD,MAX= 20pF

NAP exit delay - phase A

0.2

-

0.45

10

-

ns

Figure 55

Figure 58

Figure 48

Figure 46

Figure 47

t_HR

2

-

ns

t

_QR1, t_QF1

5

ns

t_PROP1

t_NAPXA

t_NAPXB

t_{PDN XA}

t_{PDN XB}

t_AS

-

10

50

40

4

ns

-

ns

NAP exit delay - phase B

-

ns

PDN exit delay - phase A

-

µs

PDN exit delay - phase B

-

9000

1

t_CYCLE

ATTN-to-STBY power state delay

-

t_SA

STBY-to-ATTN power state delay

-

0

t_ASN

ATTN/ STBY-to-NAP power state delay

ATTN/ STBY-to-PDN power state delay

-

8

t_ASP

-

8

a. This parameter also applies to a -800 or -711 part when operated with t_CYCLE=3.33ns.

b. This parameter also applies to a -800 part when operated with t_CYCLE=2.81ns.

c. t_Q,MINand t_Q,MAXfor other t_CYCLEvalues can be interpolated between or extrapolated from the timings at the 3 specified t_CYCLEvalues.

INFINEON Technologies Version 1.0

Preliminary Information

Page 47

Direct RAMBUS 72 Mbit (256kx18x16d)

outputs. Most timing is measured relative to the points

RSL - Clocking

where they cross. The t

parameter is measured

CYCLE

Figure 53 is a timing diagram which shows the

detailed requirements for the RSL clock signals on the

Channel.

from the falling CTM edge to the falling CTM edge.

The t and t parameters are measured from falling

CL

CH

to rising and rising to falling edges of CTM. The t

CR

and t rise- and fall-time parameters are measured at

the 20% and 80% points.

CF

The CTM and CTMN are differential clock inputs used

for transmitting information on the DQA and DQB,

t

CYCLE

t

CH

CL

t

CR

CTM

V

CIH

80%

50%

20%

V

X-

V

CM

V

X+

V

CIL

CTMN

CFM

t

CF

t

TR

t

CR

V

CIH

80%

50%

20%

V

X-

V

CM

V

X+

V

CIL

CFMN

t

CF

t

CH

CL

t

CYCLE

Figure 53: RSL Timing - Clock Signals

The CFM and CFMN are differential clock outputs

used for receiving information on the DQA, DQB,

ROW and COL outputs. Most timing is measured rela-

edges of CFM. The t and t rise- and fall-time

CR CF

parameters are measured at the 20% and 80% points.

The t parameter specifies the phase difference that

TR

tive to the points where they cross. The t

param-

CYCLE

may be tolerated with respect to the CTM and CFM

differential clock inputs (the CTM pair is always

earlier).

eter is measured from the falling CFM edge to the

falling CFM edge. The t and t parameters are

CL

CH

measured from falling to rising and rising to falling

Page 48

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

points is t / t The sample points are centered at the

0% and 50% points of a cycle, measured relative to the

crossing points of the falling CFM clock edge. The set

RSL - Receive Timing

S

H.

Figure 54 is a timing diagram which shows the

detailed requirements for the RSL input signals on the

Channel.

and hold parameters are measured at the V

point of the input transition.

voltage

REF

The DQA, DQB, ROW, and COL signals are inputs

which receive information transmitted by a Direct

RAC on the Channel. Each signal is sampled twice per

The t and t rise- and fall-time parameters are

measured at the 20% and 80% points of the input tran-

sition.

DR

DF

t

interval. The set/ hold window of the sample

CYCLE

CFM

V

CIH

80%

50%

20%

V

X-

V

CM

V

X+

V

CIL

CFMN

0.5•t

DQA

DQB

ROW

COL

CYCLE

t

DR

t

H

t

S

H

V

DIH

80%

even

odd

V

REF

20%

V

DIL

t

DF

Figure 54: RSL Timing - Data Signals for Receive

INFINEON Technologies Version 1.0

Preliminary Information

Page 49

Direct RAMBUS 72 Mbit (256kx18x16d)

end of the odd transmit window is at the 25% point

and at the 75% point of the current cycle. These

transmit points are measured relative to the crossing

points of the falling CTM clock edge. The size of the

RSL - Transmit Timing

Figure 55 is a timing diagram which shows the

detailed requirements for the RSL output signals on

the Channel.

actual transmit window is less than the ideal t

/ 2,

CYCLE

as indicated by the non-zero values of t

and

Q,MIN

The DQA and DQB signals are outputs to transmit

information that is received by a Direct RAC on the

t

. The t parameters are measured at the 50%

Q

Q,MAX

voltage point of the output transition.

Channel. Each signal is driven twice per t

CYCLE

interval. The beginning and end of the even transmit

window is at the 75% point of the previous cycle and at

the 25% point of the current cycle. The beginning and

The t and t rise- and fall-time parameters are

measured at the 20% and 80% points of the output

transition.

QR

QF

CTM

V

CIH

80%

50%

20%

V

X-

V

CM

V

X+

V

CIL

CTMN

0.75•t

CYCLE

0.25•t

CYCLE

t

Q,MAX

DQA

DQB

t

QR

t

Q,MIN

V

QH

80%

50%

20%

even

odd

V

QL

t

QF

Figure 55: RSL Timing - Data Signals for Transmit

Page 50

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

and SIO0 are t

80% levels.

and t

, measured at the 20% and

DF1

CMOS - Receive Timing

DR1

Figure 56 is a timing diagram which shows the

detailed requirements for the CMOS input signals .

The CMD signal is sampled twice per t

on the rising edge (odd data) and the falling edge

interval,

CYCLE1

The CMD and SIO0 signals are inputs which receive

information transmitted by a controller (or by another

RDRAM’s SIO1 output. SCK is the CMOS clock signal

driven by the controller. All signals are high true.

(even data). The set/ hold window of the sample points

is t / t

The SCK and CMD timing points are

S1 H1.

measured at the 50% level.

The SIO0 signal is sampled once per t

interval

CYCLE1

The cycle time, high phase time, and low phase time of

on the falling edge. The set/ hold window of the

sample points is t / t The SCK and SIO0 timing

the SCK clock are t

, t

and t

, all measured

CL1

CYCLE1 CH1

S2 H2.

at the 50% level. The rise and fall times of SCK, CMD,

points are measured at the 50% level.

t

DR2

V

IH,CMOS

SCK

80%

50%

20%

t

CYCLE1

V

IL,CMOS

t

CH1

CL1

DF2

t

H1

t

DR2

S1

H1

V

IH,CMOS

CMD

80%

even

odd

50%

20%

V

IL,CMOS

t

DF2

t

DR1

S2

H2

V

IH,CMOS

SIO0

80%

50%

20%

V

IL,CMOS

t

DF1

Figure 56: CMOS Timing - Data Signals for Receive

INFINEON Technologies Version 1.0

Preliminary Information

Page 51

Direct RAMBUS 72 Mbit (256kx18x16d)

The SCK clock is also used for sampling data on RSL

inputs in one situation. Figure 48 shows the PDN and

NAP exit sequences. If the PSX field of the INIT

register is one (see Figure 27), then the PDN and NAP

exit sequences are broadcast; i.e. all RDRAMs that are

in PDN or NAP will perform the exit sequence. If the

PSX field of the INIT register is zero, then the PDN and

NAP exit sequences are directed; i.e. only one RDRAM

that is in PDN or NAP will perform the exit sequence.

The address of that RDRAM is specified on the

DQA[5:0] bus in the set hold window t / t around

S3 H3

the rising edge of SCK. This is shown in Figure 57. The

SCK timing point is measured at the 50% level, and the

DQA[5:0] bus signals are measured at the V

level.

REF

V

IH,CMOS

SCK

80%

50%

20%

V

IL,CMOS

t

S3

H3

V

DIH

DQA[5:0]

80%

PDEV

V

REF

20%

V

DIL

Figure 57: CMOS Timing - Device Address for NAP or PDN Exit

Page 52

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

the falling edge. The clock-to-output window is

CMOS - Transmit Timing

t

/ t

The SCK and SIO0 timing points are

Q1,MIN Q1,MAX.

Figure 58 is a timing diagram which shows the

measured at the 50% level. The rise and fall times of

detailed requirements for the CMOS output signals.

SIO0 are t

levels.

and t

, measured at the 20% and 80%

QF1

QR1

The SIO0 signal is driven once per t

interval on

CYCLE1

V

IH,CMOS

SCK

80%

50%

20%

V

IL,CMOS

t

Q1,MAX

HR,MIN

t

QR1

V

OH,CMOS

SIO0

80%

50%

20%

V

OL,CMOS

t

QF1

t

DR1

V

IH,CMOS

SIO0

or

80%

SIO1

50%

20%

V

IL,CMOS

t

PROP1,MIN

t

PROP1,MAX

DF1

t

QR1

V

OH,CMOS

SIO1

or

80%

SIO0

50%

20%

V

OL,CMOS

t

QF1

Figure 58: CMOS Timing - Data Signals for Transmit

INFINEON Technologies Version 1.0

Preliminary Information

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Direct RAMBUS 72 Mbit (256kx18x16d)

Figure 58 also shows the combinational path

RD command packet and read data packet varies as a

connecting SIO0 to SIO1 and the path connecting SIO1

function of the t value.

TR

to SIO0 (read data only). The t

fied this propagation delay. The rise and fall times of

SIO0 and SIO1 inputs must be t and t , measured

parameter speci-

PROP1

Figure 59 shows this timing for five distinct values of

t

. Case A (t =0) is what has been used throughout

TR

DR1

DF1

this document. The delay between the RD command

and read data is t . As t varies from zero to t

CYCLE

at the 20% and 80% levels. The rise and fall times of

CAC

TR

SIO0 and SIO1 outputs are t

the 20% and 80% levels.

and t

, measured at

QF1

QR1

(cases A through E), the command to data delay is

(t

-t ). When the t value is in the range 0 to

TR

CAC TR

t

(t

, the command to data delay can also be

DCW,MAX

RSL - Domain Crossing Window

-t -t

). This is shown as cases A’ and B’ (the

CAC TR CYCLE

gray packets). Similarly, when the t value is in the

TR

When read data is returned by the RDRAM, imforma-

tion must cross from the receive clock domain (CFM)

range (t

+t

) to t

, the command to

CYCLE DCW,MIN

CYCLE

data delay can also be (t

-t +t

). This is

CAC TR CYCLE

to the transmit clock domain (CTM). The t param-

TR

shown as cases D’ and E’ (the gray packets). The

RDRAM will work reliably with either the white or

gray packet timing. The delay value is selected at

initialization, and remains fixed thereafter.

eter permits the CFM to CTM phase to vary through an

entire cycle; i.e. there is no restriction on the alignment

of these two clocks. A second parameter t

is

DCW

needed in order to describe how the delay between a

CFM

•••

t

COL

CYCLE

RD a1

CTM

t

=0

Case A

DQA/B

TR

t

-t

Q(a1)

CAC TR

t

TR

t

Case A’

TR

-t -t

Q(a1)

CAC TR CYCLE

•••

CTM

t

=t

Case B

Case B’

DQA/B

TR DCW,MAX

t

-t

Q(a1)

CAC TR

t

TR

=t

TR DCW,MAX

-t -t

Q(a1)

CAC TR CYCLE

•••

CTM

t

TR

t

=0.5•t

CYCLE

Case C

DQA/B

TR

t

-t

Q(a1)

CAC TR

CTM

t

=t

+t

Case D

Case D’

DQA/B

t

TR CYCLE DCW,MIN

t

-t

Q(a1)

TR

CAC TR

t

=t

+t

TR CYCLE DCW,MIN

t

-t +t

Q(a1)

CAC TR CYCLE

•••

CTM

t

=t

Case E

Case E’

DQA/B

t

TR CYCLE

t

-t

TR

CAC TR

t

=t

TR CYCLE

t

-t +t

CAC TR CYCLE

Figure 59: RSL Transmit - Crossing Read Domains

Page 54

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

Timing Parameters

Table 21: Timing Parameter Summary

Min Min Min Min Min Min Min

-40 -45 -50 -45 -50 -45 -53 Max Units

-800 -800 -800 -711 -711 -600 -600

Parameter Description

Figure(s)

t_RC

Row Cycle time of RDRAM banks -the interval between

ROWA packets with ACT commands to the same bank.

28

34

28

22

28

-

t_CYCLEFigure 15

Figure 16

t_RAS

RAS-asserted time of RDRAM bank - the interval between 20

ROWA packet with ACT command and next ROWR

packet with PRER^acommand to the same bank.

20

24

20

16

20

64µs t_CYCLEFigure 15

b

Figure 16

t_RP

Row Precharge time of RDRAM banks - the interval

between ROWR packet with PRER^acommand and next

ROWA packet with ACT command to the same bank.

8

7

8

9

10

8

7

8

9

6

8

5

8

7

-

t_CYCLEFigure 15

Figure 16

t_PP

Precharge-to-precharge time of RDRAM device - the inter-

val between successive ROWR packets with PRER^acom-

mands to any banks of the same device.

t_CYCLEFigure 12

t_RR

RAS-to-RAS time of RDRAM device - the interval

between successive ROWA packets with ACT commands

to any banks of the same device.

8

t_CYCLEFigure 13

t_RCD

RAS-to-CAS Delay - the interval from ROWA packet with

ACT command to COLC packet with RD or WR com-

mand). Note - the RAS-to-CAS delay seen by the RDRAM

core (t_RCD-C) is equal to t_RCD-C= 1 + t_RCDbecause of dif-

ferences in the row and column paths through the

RDRAM interface.

11

t_CYCLEFigure 15

Figure 16

t_CAC

CAS Access delay - the interval from RD command to Q

read data. The equation for t_CACis given in the TPARM

register in Figure 39.

8

7

8

12

t_CYCLEFigure 4

Figure 39

t_CWD

CAS Write Delay (interval from WR command to D write

data.

6

4

6

4

6

4

6

4

6

4

6

4

6

4

6

-

t_CYCLEFigure 4

t_CC

CAS-to-CAS time of RDRAM bank - the interval between

successive COLC commands).

t_CYCLEFigure 15

Figure 16

t_PACKET

t_RTR

Length of ROWA, ROWR, COLC, COLM or COLX packet.

4

8

4

8

4

8

4

8

4

8

4

8

4

8

4

-

t_CYCLEFigure 3

t_CYCLEFigure 17

Interval from COLC packet with WR command to COLC

packet which causes retire, and to COLM packet with

bytemask.

t_OFFP

The interval (offset) from COLC packet with RDA com-

mand, or from COLC packet with retire command (after

WRA automatic precharge), or from COLC packet with

PREC command, or from COLX packet with PREX com-

mand to the equivalent ROWR packet with PRER. The

equation for t_OFFPis given in the TPARM register in

Figure 39.

4

t_CYCLEFigure 14

Figure 39

t_RDP

Interval from last COLC packet with RD command to

ROWR packet with PRER.

4

-

t_CYCLEFigure 15

t_CYCLEFigure 16

t_RTP

Interval from last COLC packet with automatic retire com-

mand to ROWR packet with PRER.

a. Or equivalent PREC or PREX command. See Figure 14.

b. This is a constraint imposed by the core, and is therefore in units of µs rather than t_CYCLE

.

INFINEON Technologies Version 1.0

Preliminary Information

Page 55

Direct RAMBUS 72 Mbit (256kx18x16d)

Absolute Maximum Ratings

Table 22: Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Unit

V_I,ABS

Voltage applied to any RSL or CMOS pin with respect to Gnd

Voltage on VDD and VDDA with respect to Gnd

Storage temperature

- 0.3

- 0.5

- 50

V_DD+0.3

V_DD+1.0

100

V

_DD,ABS, V_DDA,ABS

T_STORE

°C

I_DD- Supply Current Profile

Table 23: Supply Current Profile

a

I

value

RDRAM blocks consuming power @ t

=2.5ns

CYCLE

Min

Max

Unit

DD

I_DD,PDN

Self-refresh only for INIT.LSR=0

Self-refresh only for INIT.LSR= 1

T/ RCLK-Nap

TBD

1500

700

µA

I_DD,PDN,L

I_DD,NAP

4.2

mA

I_DD,STBY

I_DD,ATTN

I_DD,ATTN-W

I_DD,ATTN-R

T/ RCLK, ROW-demux

101

T/ RCLK, ROW-demux, COL-demux

148

T/ RCLK, ROW-demux,COL-demux,DQ-demux,1• WR-SenseAmp,4• ACT-Bank

575/ 635^b

567/ 575^b

c

T/ RCLK, ROW-demux,COL-demux,DQ-mux,1• RD-SenseAmp,4• ACT-Bank

a. The CMOS interface consumes power in all power states.

b. x16/ x18 RDRAM data width.

c. This does not include the I_OLsink current. The RDRAM dissipates I_OL• V_OLin each output driver when a logic one is driven.

a

I

value

RDRAM blocks consuming power @ t

=3.3ns

CYCLE

Min

Max

Unit

DD

I_DD,PDN

Self-refresh only for INIT.LSR=0

Self-refresh only for INIT.LSR= 1

Refresh, T/ RCLK-Nap

TBD

1500

700

µA

I_DD,PDN,L

I_DD,NAP

TBD

mA

I_DD,STBY

I_DD,ATTN

I_DD,ATTN-W

I_DD,ATTN-R

Refresh, T/ RCLK, ROW-demux

Refresh, T/ RCLK, ROW-demux, COL-demux

Refresh,T/ RCLK, ROW-demux,COL-demux,DQ-demux,1• WR-SenseAmp,4• ACT-Bank

b

Refresh,T/ RCLK, ROW-demux,COL-demux,DQ-mux,1• RD-SenseAmp,4• ACT-Bank

a. The CMOS interface consumes power in all power states.

b. This does not include the I_OLsink current. The RDRAM dissipates I_OL• V_OLin each output driver when a logic one is driven.

Page 56

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

Capacitance and Inductance

Figure 60 shows the equivalent load circuit of the RSL

and CMOS pins. The circuit models the load that the

device presents to the Channel.

Pad

L_I

DQA,DQB,RQ Pin

C_I

R_I

Gnd Pin

Pad

L_I

CTM,CTMN,

CFM,CFMN Pin

C_I

R_I

Gnd Pin

Pad

L_I,CMOS

SCK,CMD Pin

C_I,CMOS

Gnd Pin

Pad

L_I,CMOS

SIO0,SIO1 Pin

C_I,CMOS,SIO

Gnd Pin

Figure 60: Equivalent Load Circuit for RSL Pins

INFINEON Technologies Version 1.0

Preliminary Information

Page 57

Direct RAMBUS 72 Mbit (256kx18x16d)

This circuit does not include pin coupling effects that

are often present in the packaged device. Because

coupling effects make the effective single-pin induc-

ment places each RSL signal adjacent to an AC ground

(a Gnd or Vdd pin), the effective inductance must be

defined based on this configuration. Therefore, L

I

tance L , and capacitance C , a function of neighboring

pins, these parameters are intrinsically data-depen-

dent. For purposes of specifying the device electrical

assumes a loop with the RSL pin adjacent to an AC

ground.

I

C is defined as the effective pin capacitance based on

I

loading on the Channel, the effective L and C are

I

the device pin assignment. It is the sum of the effective

package pin capacitance and the IO pad capacitance.

defined as the worst-case values over all specified

operating conditions.

L is defined as the effective pin inductance based on

I

the device pin assignment. Because the pad assign-

Table 24: RSL Pin Parasitics

Parameter and Conditions - RSL pins

RSL effective input inductance

Symbol

Min

Max

Unit

L

4.0

0.2

0.6

1.8

nH

I

Mutual inductance between any DQA or DQB RSL signals.

Mutual inductance between any ROW or COL RSL signals.

12

∆L

Difference in L value between any RSL pins of a single

-

I

device.

a

C

RSL effective input capacitance

-800 2.0

2.4

2.6

pF

I

a

RSL effective input capacitance

-711

-600

2.0

a

C

Mutual capacitance between any RSL signals.

-

0.1

pF

12

∆C

Difference in C value between average of CTM/ CFM and

0.06

I

any RSL pins of a single device.

R

RSL effective input resistance

4

15

Ω

I

a. This value is a combination of the device IO circuitry and package capacitances.

Table 25: CMOS Pin Parasitics

Symbol

Parameter and Conditions - CMOS pins

CMOS effective input inductance

CMOS effective input capacitance (SCK,CMD)

Min

Max

Unit

L

8.0

2.1

7.0

nH

I ,CMOS

a

C

1.7

pF

I ,CMOS

I ,CMOS,SIO

a

CMOS effective input capacitance (SIO1, SIO0)

-

a. This value is a combination of the device IO circuitry and package capacitances.

Page 58

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

Center-Bonded uBGA Package

Figure 61 shows the form and dimensions of the

recommended package for the center-bonded CSP

device class.

D

Top

Bottom

A

B

C

D

E

F

G

H

J

1

2

3

4

5

6

7

8

A

e2

e1

d

Bottom

E1

E

Figure 61: Center-Bonded uBGA Package

Table 26 lists the numerical values corresponding to

dimensions shown in Figure 61.

Table 26: Center-Bonded uBGA Package Dimensions

Symbol

Parameter

Min

Max

1.00

Unit

mm

e1

e2

A

Ball pitch (x-axis)

Ball pitch (y-axis)

Package body length

Package body width

Package total thickness

Ball height

1.00

0.8

mm

-

a

note

0.65

0.20

0.33

note

1.20

0.43

0.50

D

-

E

mm

E1

d

Ball diameter

a. Package length and width vary with die size for chip scale packages.

INFINEON Technologies Version 1.0

Preliminary Information

Page 59

Direct RAMBUS 72 Mbit (256kx18x16d)

controller

A logic-device which drives the ROW/COL

/DQ wires for a Channel of RDRAMs.

Glossary of Terms

ACT

Activate command from AV field.

COP

Column opcode field in COLC packet.

The banks and sense amps of an RDRAM.

Clock pins for transmitting packets.

activate

adjacent

To access a row and place in sense amp.

core

Two RDRAM banks which share sense

amps (also called doubled banks).

CTM,CTMN

current control Periodic operations to update the proper

value of RSL output drivers.

ASYM

ATTN

ATTNR

ATTNW

AV

CCA register field for RSL V /V

.

I

OL OH

OL

Power state - ready for ROW/COL packets.

Power state - transmitting Q packets.

Power state - receiving D packets.

D

Write data packet on DQ pins.

CNFGB register field - doubled-bank.

Device address field in COLC packet.

An RDRAM on a Channel.

DBL

DC

Opcode field in ROW packets.

device

DEVID

RBIT CBIT

bank

A block of 2

•2

storage cells in the

Control register with device address that is

matched against DR, DC, and DX fields.

core of the RDRAM.

BC

Bank address field in COLC packet.

CNFGA register field - # bank address bits.

An operation executed by all RDRAMs.

Bank address field in ROW packets.

DM

Device match for ROW packet decode.

BBIT

doubled-bank RDRAM with shared sense amp.

broadcast

BR

DQ

DQA and DQB pins.

DQA

DQB

DQS

Pins for data byte A.

bubble

Idle cycle(s) on RDRAM pins needed

because of a resource constraint.

Pins for data byte B.

NAPX register field - PDN/NAP exit.

BYT

BX

CNFGB register field - 8/9 bits per byte.

Bank address field in COLX packet.

Column address field in COLC packet.

DR,DR4T,DR4F Device address field and packet framing

fields in ROWA and ROWR packets.

C

dualoct

DX

16 bytes - the smallest addressable datum.

Device address field in COLX packet.

A collection of bits in a packet.

CAL

CBIT

Calibrate (I ) command in XOP field.

OL

CNFGB register field - # column address

bits.

field

INIT

Control register with initialization fields.

CCA

Control register - current control A.

Control register - current control B.

Clock pins for receiving packets.

initialization Configuring a Channel of RDRAMs so

CCB

they are ready to respond to transactions.

CFM,CFMN

Channel

CLRR

CMD

LSR

CNFGA register field - low-power self-

refresh.

ROW/COL/DQ pins and external wires.

Clear reset command from SOP field.

CMOS pin for initialization/power control.

Control register with configuration fields.

Pins for column-access control.

M

Mask opcode field (COLM/COLX packet).

Field in COLM packet for masking byte A.

Field in COLM packet for masking byte B.

Mask command in M field.

MA

MB

CNFGA

CNFGB

COL

MSK

MVER

NAP

Control register - manufacturer ID.

Power state - needs SCK/CMD wakeup.

Nap command in ROP field.

COL

COLC,COLM,COLX packet on COL pins.

Column operation packet on COL pins.

Write mask packet on COL pins.

NAPR

NAPRC

NAPXA

NAPXB

NOCOP

NOROP

NOXOP

COLC

COLM

column

Conditional nap command in ROP field.

NAPX register field - NAP exit delay A.

NAPX register field - NAP exit delay B.

No-operation command in COP field.

No-operation command in ROP field.

No-operation command in XOP field.

Rows in a bank or activated row in sense

CBIT

amps have 2

dualocts column storage.

command

COLX

A decoded bit-combination from a field.

Extended operation packet on COL pins.

Page 60

Preliminary Information

Version 1.0 INFINEON Technologies

Direct RAMBUS 72 Mbit (256kx18x16d)

NSR

INIT register field- NAP self-refresh.

A collection of bits carried on the Channel.

Power state - needs SCK/CMD wakeup.

Powerdown command in ROP field.

Control register - PDN exit delay A.

Control register - PDN exit delay B.

RQ

Alternate name for ROW/COL pins.

Rambus Signaling Levels.

packet

PDN

RSL

SAM

SA

Sample (I ) command in XOP field.

OL

PDNR

PDNXA

PDNXB

Serial address packet for control register

transactions w/ SA address field.

SBC

SCK

SD

Serial broadcast field in SRQ.

CMOS clock pin..

pin efficiency The fraction of non-idle cycles on a pin.

Serial data packet for control register

transactions w/ SD data field.

PRE

PREC,PRER,PREX precharge commands.

Precharge command in COP field.

PREC

precharge

PRER

PREX

PSX

SDEV

Serial device address in SRQ packet.

INIT register field - Serial device ID.

Refresh mode for PDN and NAP.

Prepares sense amp and bank for activate.

Precharge command in ROP field.

SDEVID

self-refresh

sense amp

SETF

Precharge command in XOP field.

Fast storage that holds copy of bank’s row.

Set fast clock command from SOP field.

Set reset command from SOP field.

INIT register field - PDN/NAP exit.

INIT register field - PDN self-refresh.

CNFGB register field - protocol version.

Read data packet on DQ pins.

PSR

SETR

PVER

Q

SINT

Serial interval packet for control register

read/write transactions.

SIO0,SIO1

SOP

CMOS serial pins for control registers.

Serial opcode field in SRQ.

R

Row address field of ROWA packet.

CNFGB register field - # row address bits.

Read (/precharge) command in COP field.

Operation of accesssing sense amp data.

RBIT

RD/RDA

read

SRD

Serial read opcode command from SOP.

INIT register field - Serial repeat bit.

SRP

SRQ

Serial request packet for control register

read/write transactions.

receive

Moving information from the Channel into

the RDRAM (a serial stream is demuxed).

STBY

Power state - ready for ROW packets.

Control register - stepping version.

Serial write opcode command from SOP.

REFA

Refresh-activate command in ROP field.

Control register - next bank (self-refresh).

SVER

REFB

REFBIT

SWR

CNFGA register field - ignore bank bits

(for REFA and self-refresh).

TCAS

TCLSCAS register field - t

core delay.

CAS

CLS

REFP

REFR

refresh

retire

Refresh-precharge command in ROP field.

Control register - next row for REFA.

Periodic operations to restore storage cells.

TCLS

TCLSCAS

TCYCLE

TDAC

Control register - t

and t

delays.

CLS

CAS

delay.

CYCLE

The automatic operation that stores write

buffer into sense amp after WR command.

delay.

DAC

TEST77

TEST78

TRDLY

transaction

transmit

Control register - for test purposes.

RLX

RLXC,RLXR,RLXX relax commands.

Relax command in COP field.

Relax command in ROP field.

Relax command in XOP field.

RLXC

RLXR

RLXX

ROP

Control register - t

delay.

RDLY

ROW,COL,DQ packets for memory access.

Moving information from the RDRAM

onto the Channel (parallel word is muxed).

Row-opcode field in ROWR packet.

CBIT

row

2

dualocts of cells (bank/sense amp).

WR/WRA

write

Write (/precharge) command in COP field.

Operation of modifying sense amp data.

Extended opcode field in COLX packet.

ROW

ROWA

ROWR

Pins for row-access control

ROWA or ROWR packets on ROW pins.

Activate packet on ROW pins.

XOP

Row operation packet on ROW pins.

INFINEON Technologies Version 1.0

Preliminary Information

Page 61

Direct RAMBUS 72 Mbit (256kx18x16d)

Capacitance and Inductance . . . . . . . . . . . . . . . .56-57

Center-Bonded mBGA Package . . . . . . . . . . . . . . . 58

Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . .59-60

Table Of Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Key Timing Parameters/Part Numbers. . . . . . . . . . . . 1

Pinouts and Definitions . . . . . . . . . . . . . . . . . . . . . . . 2

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6,7

Field Encoding Summary. . . . . . . . . . . . . . . . . . . . .8,9

DQ Packet Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10

COLM Packet to D Packet Mapping. . . . . . . . . . .10,11

ROW-to-ROW Packet Interaction . . . . . . . . . . . . 12, 13

ROW-to-COL Packet Interaction . . . . . . . . . . . . . . . 13

COL-to-COL Packet Interaction . . . . . . . . . . . . . . . . 14

COL-to-ROW Packet Interaction . . . . . . . . . . . . . . . 15

ROW-to-ROW Examples . . . . . . . . . . . . . . . . . . .16,17

Row and Column Cycle Description . . . . . . . . . . . . 17

Precharge Mechanisms . . . . . . . . . . . . . . . . . . . .18,19

Read Transaction - Example . . . . . . . . . . . . . . . . . . 20

Write Transaction - Example . . . . . . . . . . . . . . . . . . 21

Write/Retire - Examples. . . . . . . . . . . . . . . . . . . 22, 23

Interleaved Write - Example. . . . . . . . . . . . . . . . . . . 24

Interleaved Read - Example. . . . . . . . . . . . . . . . . . . 25

Interleaved RRWW. . . . . . . . . . . . . . . . . . . . . . . . . . 25

Control Register Transactions . . . . . . . . . . . . . . . . . 26

Control Register Packets . . . . . . . . . . . . . . . . . . . . . 27

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-29

Control Register Summary. . . . . . . . . . . . . . . . . 30-37

Power State Management . . . . . . . . . . . . . . . . . 38-41

Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Current and Temperature Control . . . . . . . . . . . . . . 43

Electrical Conditions . . . . . . . . . . . . . . . . . . . . . . . . 44

Timing Conditions . . . . . . . . . . . . . . . . . . . . . . . .44-45

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 46

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . 46

RSL Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

RSL - Receive Timing . . . . . . . . . . . . . . . . . . . . . . . 48

RSL - Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . 49

CMOS - Receive Timing . . . . . . . . . . . . . . . . . . .50-51

CMOS - Transmit Timing . . . . . . . . . . . . . . . . . . .52-53

RSL - Domain Crossing Window . . . . . . . . . . . . . . . 53

Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . 54

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . 55

I

- Supply Current Profile . . . . . . . . . . . . . . . . . . . 55

DD

Page 62

Preliminary Information

Version 1.0 INFINEON Technologies


型号：	HYB25R72180C-645
厂家：	ETC
描述：	RAMBUS DRAM RAMBUS DRAM\n 动态存储器
文件：	总62页 (文件大小：2626K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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