HYM71V32C735AT4-K [ETC]

x72 SDRAM Module ; X72 SDRAM模块\n


型号：	HYM71V32C735AT4-K
厂家：	ETC
描述：	x72 SDRAM Module X72 SDRAM模块\n 动态存储器
文件：	总14页 (文件大小：223K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

32Mx72 bits

PC133 SDRAM Registered DIMM

with PLL, based on 32Mx4 SDRAM with LVTTL, 4 banks & 4K Refresh

HYM71V32C735AT4 Series

DESCRIPTION

The Hynix HYM71V32C735AT4 Series are 32Mx72bits ECC Synchronous DRAM Modules. The modules are composed of eighteen

32Mx4bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin

glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB.

The Hynix HYM71V32C735AT4 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 256Mbytes

memory. The Hynix HYM71V32C735AT4 Series are fully synchronous operation referenced to the positive edge of the clock . All

inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high

bandwidth.

FEATURES

•

PC133/PC100MHz support

•

SDRAM internal banks : four banks

Module bank : one physical bank

Auto refresh and self refresh

168pin SDRAM Registered DIMM

Serial Presence Detect with EEPROM

1.70” (43.18mm) Height PCB with double sided

components

4096 refresh cycles / 64ms

Programmable Burst Length and Burst Type

- 1, 2, 4 or 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

Single 3.3±0.3V power supply

All device pins are compatible with LVTTL interface

Data mask function by DQM

•

Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Clock

Frequency

Internal

Bank

SDRAM

Package

Part No.

Ref.

Power

Plating

HYM71V32C735AT4-K

HYM71V32C735AT4-H

133MHz

4 Banks

Normal

TSOP-II

Gold

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of

circuits described. No patent licenses are implied.

Rev. 1.3/Sep. 01

PC133 SDRAM Registered DIMM

HYM71V32C735AT4 Series

PIN DESCRIPTION

PIN NAME

Clock Inputs

DESCRIPTION

The system clock input. All other inputs are registered to the SDRAM on the

rising edge of CLK

CK0~CK3

Controls internal clock signal and when deactivated, the SDRAM will be one

of the states among power down, suspend or self refresh

CKE0

Clock Enable

/S0, /S2

BA0, BA1

Chip Select

Enables or disables all inputs except CK, CKE and DQM

Selects bank to be activated during /RAS activity

Selects bank to be read/written during /CAS activity

SDRAM Bank Address

Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9, CA11

Auto-precharge flag : A10

A0 ~ A11

Address

Row Address Strobe, Column

Address Strobe, Write Enable

/RAS, /CAS and /WE define the operation

Refer function truth table for details

/RAS, /CAS, /WE

REGE

when REGE input is Low, in Registered Mode when REGE input is High

DQM0~DQM7

DQ0 ~ DQ63

CB0 ~ CB7

VCC

Data Input/Output Mask

Data Input/Output

Check Bit Input/Output

Power Supply (3.3V)

Ground

Controls output buffers in read mode and masks input data in write mode

Multiplexed data input / output pin

Check bits for ECC

Power supply for internal circuits and input buffers

Ground

VSS

SCL

SPD Clock Input

Serial Presence Detect Clock input

Serial Presence Detect Data input/output

Serial Presence Detect Address Input

Write Protect for Serial Presence Detect on DIMM

No connection

SDA

SPD Data Input/Output

SPD Address Input

Write Protect for SPD

No Connection

SA0~2

Rev. 1.3/Sep. 01

PC133 SDRAM Registered DIMM

HYM71V32C735AT4 Series

PIN ASSIGNMENTS

FRONT SIDE

BACK SIDE

FRONT SIDE

BACK SIDE

PIN NO.

NAME

PIN NO.

NAME

PIN NO.

NAME

PIN NO.

NAME

VSS

DQ0

DQ1

DQ2

DQ3

VCC

DQ4

DQ5

DQ6

DQ7

VSS

VCC

CK0

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

*CK1

DQ32

DQ33

DQ34

DQ35

VCC

VSS

CKE0

/S2

DQM2

DQM3

DQM6

DQM7

DQ36

DQ37

DQ38

DQ39

VCC

Architecture Key

CB2

CB6

DQ8

VSS

DQ9

DQ10

DQ11

DQ12

DQ13

VCC

DQ14

DQ15

CB0

CB1

VSS

DQ40

VSS

DQ41

DQ42

DQ43

DQ44

DQ45

VCC

DQ46

DQ47

CB4

CB5

VSS

CB3

CB7

VSS

DQ16

DQ17

DQ18

DQ19

VCC

DQ20

VSS

DQ48

DQ49

DQ50

DQ51

VCC

DQ52

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

REGE

VSS

DQ21

DQ22

DQ23

VSS

DQ24

DQ25

DQ26

DQ27

VCC

DQ28

DQ29

DQ30

DQ31

VSS

*CK2

DQ53

DQ54

DQ55

VSS

VCC

/WE

DQM0

DQM1

/S0

VCC

/CAS

DQM4

DQM5

DQ56

DQ57

DQ58

DQ59

VCC

DQ60

DQ61

DQ62

DQ63

VSS

/RAS

VSS

*CK3

A10/AP

BA1

VCC

BA0

A11

SA0

VCC

SDA

SCL

SA1

SA2

Voltage Key

VCC

Note : * CK1 ~ CK3 are connected with termination R/C (Refer to the block diagram)

Rev. 1.3/Sep. 01

PC133 SDRAM Registered DIMM

HYM71V32C735AT4 Series

BLOCK DIAGRAM

Note : 1. The serial resistor values of DQs are 10ohms

2. The padding capacitance of termination R/C for CK1~CK3 is 12pF

Rev. 1.3/Sep. 01

PC133 SDRAM Registered DIMM

HYM71V32C735AT4 Series

SERIAL PRESENCE DETECT

FUNCTION

VALUE

BYTE

NUMBER

FUNCTION

DESCRIPTION

NOTE

-K

-H

-K

-H

# of Bytes Written into Serial Memory at Module

Manufacturer

BYTE0

128 Bytes

80h

BYTE1

BYTE2

BYTE3

BYTE4

BYTE5

BYTE6

BYTE7

BYTE8

BYTE9

BYTE10

BYTE11

Total # of Bytes of SPD Memory Device

256 Bytes

SDRAM

08h

04h

0Ch

0Bh

01h

48h

00h

01h

Fundamental Memory Type

# of Row Addresses on This Assembly

# of Column Addresses on This Assembly

# of Module Banks on This Assembly

Data Width of This Assembly

1 Bank

72 Bits

Data Width of This Assembly (Continued)

Voltage Interface Standard of This Assembly

SDRAM Cycle Time @/CAS Latency=3

Access Time from Clock @/CAS Latency=3

DIMM Configuration Type

LVTTL

7.5ns

5.4ns

7.5ns

5.4ns

75h

54h

75h

54h

ECC

02h

80h

15.625us

/ Self Refresh Supported

BYTE12

Refresh Rate/Type

BYTE13

BYTE14

Primary SDRAM Width

04h

Error Checking SDRAM Width

Minimum Clock Delay Back to Back Random Column

Address

BYTE15

tCCD = 1 CLK

01h

BYTE16

BYTE17

BYTE18

BYTE19

BYTE20

BYTE21

Burst Lenth Supported

1,2,4,8,Full Page

4 Banks

8Fh

04h

06h

01h

1Fh

# of Banks on Each SDRAM Device

SDRAM Device Attributes, /CAS Lataency

SDRAM Device Attributes, /CS Lataency

SDRAM Device Attributes, /WE Lataency

SDRAM Module Attributes

/CAS Latency=2,3

/CS Latency=0

/WE Latency=0

Registered/Buffered inputs, with PLL

+/- 10% voltage tolerence, Burst Read

Single Bit Write, Precharge All, Auto

Precharge, Early RAS Precharge

BYTE22

SDRAM Device Attributes, General

0Eh

BYTE23

BYTE24

BYTE25

BYTE26

BYTE27

BYTE28

BYTE29

BYTE30

BYTE31

BYTE32

BYTE33

BYTE34

BYTE35

SDRAM Cycle Time @/CAS Latency=2

Access Time from Clock @/CAS Latency=2

SDRAM Cycle Time @/CAS Latency=1

Access Time from Clock @/CAS Latency=1

Minimum Row Precharge Time (tRP)

Minimum Row Active to Row Active Delay (tRRD)

Minimum /RAS to /CAS Delay (tRCD)

Minimum /RAS Pulse Width (tRAS)

Module Bank Density

7.5ns

5.4ns

10ns

6ns

75h

54h

00h

0Fh

2Dh

A0h

60h

00h

14h

0Fh

14h

2Dh

15ns

45ns

20ns

15ns

20ns

45ns

256MB

40h

Command and Address Signal Input Setup Time

Command and Address Signal Input Hold Time

Data Signal Input Setup Time

1.5ns

0.8ns

1.5ns

0.8ns

1.5ns

0.8ns

1.5ns

0.8ns

15h

08h

15h

08h

15h

08h

15h

08h

Data Signal Input Hold Time

BYTE36

~61

Superset Information (may be used in future)

00h

12h

BYTE62

BYTE63

BYTE64

SPD Revision

Intel SPD 1.2B

3, 8

Checksum for Byte 0~62

Manufacturer JEDEC ID Code

B8h

F9h

Hynix JEDED ID

Unused

ADh

FFh

BYTE65

~71

....Manufacturer JEDEC ID Code

HSI (Korea Area)

HSA (United States Area)

HSE (Europe Area)

HSJ (Japan Area)

Singapore

0*h

1*h

2*h

3*h

4*h

5*h

BYTE72

Manufacturing Location

ASIA Area

Rev. 1.3/Sep. 01

PC133 SDRAM Registered DIMM

HYM71V32C735AT4 Series

Continued

FUNCTION

VALUE

BYTE

NUMBER

FUNCTION

DESCRIPTION

NOTE

-K

-H

BYTE73

BYTE74

BYTE75

BYTE76

BYTE77

BYTE78

BYTE79

BYTE80

BYTE81

BYTE82

BYTE83

BYTE84

BYTE85

BYTE86

Manufacturer’s Part Number (Component)

Manufacturer’s Part Number (128Mb based)

Manufacturer’s Part Number (Voltage Interface)

Manufacturer’s Part Number (Memory Width)

....Manufacturer’s Part Number (Memory Width)

Manufacturer’s Part Number (Module Type)

Manufacturer’s Part Number (Data Width)

....Manufacturer’s Part Number (Data Width)

Manufacturer’s Part Number (Refresh, SDRAM Bank)

Manufacturer’s Part Number (Generation)

Manufacturer’s Part Number (Package Type)

Manufacturer’s Part Number (Component Configuration)

Manufacturer’s Part Number (Hyphen)

7 (SDRAM)

37h

31h

56h

33h

32h

43h

37h

33h

35h

41h

54h

34h

2Dh

4, 5

V (3.3V, LVTTL)

C (RCC Registered with PLL)

4, 5

5 (4K Refresh, 4Banks)

4 (x4 based)

- (Hyphen)

Manufacturer’s Part Number (Min. Cycle Time)

4Bh

48h

BYTE87

~90

Manufacturer’s Part Number

Blanks

20h

4, 5

BYTE91

BYTE92

BYTE93

BYTE94

Revision Code (for Component)

....Revision Code (for PCB)

Manufacturing Date

Process Code

Work Week

Year

4, 6

3, 6

....Manufacturing Date

BYTE95

~98

BYTE99

~125

Assembly Serial Number

Serial Number

None

Manufacturer Specific Data (may be used in future)

00h

BYTE126

BYTE127

Reserved

100MHz

7, 8, 9

64h

8Fh

Refer to Note7

BYTE128

~256

Unused Storage Locations

00h

Note :

1. The bank address is excluded

2. 1, 2, 4, 8 for Interleave Burst Type

3. BCD adopted

4. ASCII adopted

5. Basically Hynix writes Part No. except for ‘HYM’ in Byte 73~90 to use the limited 18 bytes from byte 73 to byte 90

6. Not fixed but dependent

7. CK0 connected to DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge support

8. Refer to the most recent Intel and JEDEC SPD Specification

9. These values are applied to PC100 applications only per Intel PC SDRAM specification

10. Refer to HSI Web site.

Rev. 1.3/Sep. 01

PC133 SDRAM Registered DIMM

HYM71V32C735AT4 Series

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Rating

Unit

Ambient Temperature

0 ~ 70

-55 ~ 125

-1.0 ~ 4.6

°C

Storage Temperature

TSTG

°C

Voltage on Any Pin relative to VSS

Voltage on VDD relative to VSS

Short Circuit Output Current

Power Dissipation

VIN, VOUT

VDD, VDDQ

IOS

Soldering Temperature Time

TSOLDER

260 10

°C Sec

Note : Operation at above absolute maximum rating can adversely affect device reliability.

DC OPERATING CONDITION ^(TA=0 to 70°C)

Parameter

Symbol

Min

Typ

Max

Unit

Note

Power Supply Voltage

Input High voltage

Input Low voltage

VDD, VDDQ

VIH

3.0

2.0

3.3

3.0

3.6

VDDQ + 0.3

0.8

1,2

1,3

VIL

-0.3

Note :

1.All voltages are referenced to VSS = 0V

2.VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.

3.VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.

AC OPERATING TEST CONDITION ^(TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)

Parameter

Symbol

Value

Unit

Note

AC Input High / Low Level Voltage

VIH / VIL

Vtrip

2.4/0.4

1.4

Input Timing Measurement Reference Level Voltage

Input Rise / Fall Time

tR / tF

Voutref

Output Timing Measurement Reference Level Voltage

Output Load Capacitance for Access Time Measurement

1.4

Note :

1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output

load circuit

Rev. 1.3/Sep. 01

PC133 SDRAM Registered DIMM

HYM71V32C735AT4 Series

CAPACITANCE ^{(TA=25°C, f=1MHz)}

-K/H

Unit

Parameter

Symbol

Min

Max

CK0

CI1

CI2

CI3

CI4

CI5

CI6

CI/O

CKE0

/S0, /S2

Input Capacitance

A0~11, BA0, BA1

/RAS, /CAS, /WE

DQM0~DQM7

DQ0 ~ DQ63

Data Input / Output Capacitance

OUTPUT LOAD CIRCUIT

Vtt=1.4V

RT=250 Ω

Output

50pF

DC Output Load Circuit

AC Output Load Circuit

Rev. 1.3/Sep. 01

PC133 SDRAM Registered DIMM

HYM71V32C735AT4 Series

DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V)

Parameter

Symbol

Min.

Max

Unit

Note

Input Leakage Current

Output Leakage Current

Output High Voltage

Output Low Voltage

ILI

-10

-1

ILO

VOH

VOL

2.4

IOH = -4mA

IOL = +4mA

0.4

Note :

1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V

2.DOUT is disabled, VOUT=0 to 3.6

DC CHARACTERISTICS II

Speed

Parameter

Symbol

Test Condition

Unit Note

-K

-H

Burst length=1, One bank active

tRC ≥ tRC(min), IOL=0mA

Operating Current

IDD1

2700

2400

IDD2P

CKE ≤ VIL(max), tCK = 15ns

CKE ≤ VIL(max), tCK = ∞

356

Precharge Standby Current

in Power Down Mode

IDD2PS

CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns

Input signals are changed one time during

30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V

IDD2N

760

270

Precharge Standby Current

in Non Power Down Mode

CKE ≥ VIH(min), tCK = ∞

Input signals are stable.

IDD2NS

IDD3P

CKE ≤ VIL(max), tCK = 15ns

446

216

Active Standby Current

in Power Down Mode

IDD3PS CKE ≤ VIL(max), tCK = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns

IDD3N

Input signals are changed one time during

30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V

1120

810

Active Standby Current

in Non Power Down Mode

CKE ≥ VIH(min), tCK = ∞

Input signals are stable.

IDD3NS

IDD4

CL=3

3000

5800

3000

2800

4900

Burst Mode Operating

Current

tCK ≥ tCK(min), IOL=0mA

All banks active

CL=2

Auto Refresh Current

Self Refresh Current

IDD5

IDD6

tRRC ≥ tRRC(min), All banks active

CKE ≤ 0.2V

276

Note :

1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open

2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II

3. All values are measured with Registered and PLL

Rev. 1.3/Sep. 01

PC133 SDRAM Registered DIMM

HYM71V32C735AT4 Series

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

-K

-H

Parameter

Symbol

Unit

Note

Min

7.5

2.5

Max

Min

7.5

2.5

Max

CAS Latency = 3 tCK3

CAS Latency = 2 tCK2

System Clock

Cycle Time

1000

Clock High Pulse Width

Clock Low Pulse Width

tCHW

tCLW

CAS Latency = 3 tAC3

CAS Latency = 2 tAC2

tOH

5.4

Access Time

From Clock

5.4

Data-Out Hold Time

2.7

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

2.7

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

Data-Input Setup Time

Data-Input Hold Time

Address Setup Time

Address Hold Time

tDS

tDH

tAS

tAH

CKE Setup Time

tCKS

tCKH

tCS

CKE Hold Time

Command Setup Time

Command Hold Time

CLK to Data Output in Low-Z Time

tCH

tOLZ

CAS Latency = 3 tOHZ3

CAS Latency = 2 tOHZ2

2.7

5.4

2.7

5.4

CLK to Data

Output in High-Z

Time

Note :

1. In Registered DIMM, data is delayed an additional clock cycle due to the register (this is, Device CL + 1 = DIMM CL)

2. Assume tR / tF (input rise and fall time ) is 1ns, If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter

3. Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v

If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter

Rev. 1.3/Sep. 01

PC133 SDRAM Registered DIMM

HYM71V32C735AT4 Series

AC CHARACTERISTICS II

-K

-H

Parameter

Symbol

Unit

Note

Min

Max

Min

Max

Operation

Auto Refresh

tRC

RAS Cycle Time

tRRC

tRCD

tRAS

tRP

RAS to CAS Delay

RAS Active Time

100K

RAS Precharge Time

RAS to RAS Bank Active Delay

CAS to CAS Delay

tRRD

tCCD

tWTL

tDPL

tDAL

tDQZ

tDQM

tMRD

CLK

Write Command to Data-In Delay

Data-In to Precharge Command

Data-In to Active Command

DQM to Data-Out Hi-Z

DQM to Data-In Mask

MRS to New Command

CAS Latency = 3 tPROZ3

CAS Latency = 2 tPROZ2

Precharge to Data

Output Hi-Z

Power Down Exit Time

Self Refresh Exit Time

Refresh Time

tPDE

tSRE

tREF

Note :

1. Timing delay due to the register is considered in a registered DIMM

2. A new command can be given tRRC after self refresh exit

Rev. 1.3/Sep. 01

PC133 SDRAM Registered DIMM

HYM71V32C735AT4 Series

DEVICE OPERATING OPTION TABLE

HYM71V32C735AT4-K

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

133MHz(7.5ns)

125MHz(8ns)

100MHz(10ns)

2CLKs

3CLKs

2CLKs

3CLKs

2CLKs

6CLKs

5CLKs

8CLKs

9CLKs

7CLKs

2CLKs

3CLKs

2CLKs

5.4ns

6ns

2.7ns

3ns

6ns

3ns

HYM71V32C735AT4-H

CAS Latency

3CLKs

tRCD

tRAS

tRC

tRP

tAC

tOH

133MHz(7.5ns)

125MHz(8ns)

100MHz(10ns)

3CLKs

2CLKs

6CLKs

5CLKs

9CLKs

7CLKs

3CLKs

2CLKs

5.4ns

6ns

2.7ns

3ns

3CLKs

2CLKs

6ns

3ns

Note : DIMM/CAS Latency = Device CL + 1 (Registered Mode)

Rev. 1.3/Sep. 01

PC133 SDRAM Registered DIMM

HYM71V32C735AT4 Series

COMMAND TRUTH TABLE

A10/

Command

Mode Register Set

No Operation

CKEn-1

CKEn

RAS

CAS

DQM

ADDR

Note

OP code

Bank Active

Read

Read with Autoprecharge

Write

Write with Autoprecharge

Precharge All Banks

Precharge selected Bank

Burst Stop

DQM

Auto Refresh

Burst-Read-Single-

WRITE

A9 Pin High

(Other Pins OP code)

Entry

Self Refresh

Exit

Entry

Precharge

power down

Exit

Entry

Exit

Clock

Suspend

Note :

1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high

2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,

Opcode = Operand Code, NOP = No Operation

Rev. 1.3/Sep. 01

PC133 SDRAM Registered DIMM

HYM71V32C735AT4 Series

PACKAGE DEMENSION

Rev. 1.3/Sep. 01

HYM71V32C735AT4-K [ETC]

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