HYM7V73AC801BTHG [ETC]

8Mx72|3.3V|P/S|x9|SDR SDRAM - Registered DIMM 64MB ; 8Mx72 | 3.3V | P / S | X9 | SDR SDRAM - 注册DIMM内存64MB\n


型号：	HYM7V73AC801BTHG
厂家：	ETC
描述：	8Mx72\|3.3V\|P/S\|x9\|SDR SDRAM - Registered DIMM 64MB 8Mx72 \| 3.3V \| P / S \| X9 \| SDR SDRAM - 注册DIMM内存64MB\n 动态存储器
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中文：	中文翻译
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8Mx72 bits

PC133 SDRAM Registered DIMM

with PLL, based on 8Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh

HYM7V73AC801B H-Series

DESCRIPTION

The Hynix HYM7V73AC801B H-Series are 8Mx72bits ECC Synchronous DRAM Modules. The modules are composed

of nine 8Mx8bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, two 18bits driver ICs in 56pin TSSOP

package, one PLL clock driver in 24pin TSSOP package and one 2Kbits EEPROM in 8pin TSSOP package on a 168pin

glass-epoxy printed circuit board. A 0.22uF and a 0.0022uF decoupling capacitors per each SDRAM are mounted on the

PCB.

The HYM7V73AC801B H-Series are Dual In-line Memory Modules suitable for easy interchange and addition of

64Mbytes memory. The HYM7V73AC801B H-Series are offering fully synchronous operation referenced to a positive

edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are

internally pipelined to achieve very high bandwidth. The DIMM /CAS latency in registered mode is one clock later than

the device /CAS latency because of the register.

FEATURES

· PC133/100MHz support

· SDRAM internal banks : four banks

· Module bank : one physical bank

· Auto refresh and self refresh

· 4096 refresh cycles / 64ms

· 168pin SDRAM Registered DIMM

· Serial Presence Detect with EEPROM

· 1.50” (38.10mm) Height PCB with Double Sided

components

· Programmable Burst Length and Burst Type

-. 1, 2, 4, 8, or Full Page for Sequential Burst

-. 1, 2, 4 or 8 for Interleave Burst

· Single 3.3 ± 0.3V power supply

· All devices pins are compatible with LVTTL interface

· Data mask function by DQM

· Programmable /CAS Latency

-. Device /CAS Latency : 2, 3 clocks

-. DIMM /CAS Latency : 3, 4 clocks (registered mode)

ORDERING INFORMATION

MAX.

FREQUENCY

INTERNAL

BANK

SDRAM

PACKAGE

PART NO.

REF.

POWER

PLATING

HYM7V73AC801BTHGC-75

133MHz

4 Banks

Normal

TSOP-II

Gold

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume

any responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.1/Apr.01

1999 Hyundai Electronics

PC133 SDRAM Registered DIMM

HYM7V73AC801B H-Series

PIN DESCRIPTION

PIN NAME

DESCRIPTION

The System Clock Input. All other inputs are registered to the

SDRAM on the rising edge of CLK.

CK0~CK3

CKE0

Clock Inputs

Controls internal clock signal and when deactivated, the SDRAM

will be one of the states among power down, suspend or self

refresh.

Clock Enable

/S0, /S2

Chip Select

Enables or disables all inputs except CK, CKE and DQM.

Select bank to be activated during /RAS activity.

Select bank to be read/written during /CAS activity

Row address : RA0~RA11, Column address : CA0~CA8

Auto-precharge flag : A10

BA0, BA1

SDRAM Bank Address

A0~A11

/RAS

/CAS

/WE

Address Inputs

/RAS define the operation.

Row Address Strobe

Column Address Strobe

Write Enable

Refer to the function truth table for details.

/CAS define the operation.

Refer to the function truth table for details.

/WE define the operation.

Refer to the function truth table for details.

Buffered Mode when REGE input is Low, in Registered Mode

when REGE input is High.

REGE

Controls output buffers in read mode and masks input data in

write mode.

DQM0~DQM7

Data Input/Output Mask

DQ0~DQ63

CB0~CB7

VCC

Data Input/Output

ECC Data Input/Output

Power Supply (3.3V)

Ground

Multiplexed data input/output pins

Error Checking and Correction Bits

Power supply for internal circuits and input/output buffers

Ground

VSS

SCL

SPD Clock Input

SPD Data Input/Output

SPD Address Input

Write Protect for SPD

No Connect

Serial Presence Detect Clock Input

Serial Presence Detect Data input/output

Serial Presence Detect Address input

Write Protect for Serial Presence Detect on DIMM

No Connect or Don’ t Use

SDA

SA0~SA2

Rev. 0.1/Apr.01

PC133 SDRAM Registered DIMM

HYM7V73AC801B H-Series

PIN ASSIGNMENTS

FRONT SIDE

BACK SIDE

NAME

FRONT SIDE

BACK SIDE

NAME

PIN NO.

NAME

PIN NO.

NAME

PIN NO.

VSS

DQ0

DQ1

DQ2

DQ3

VCC

DQ4

DQ5

DQ6

DQ7

VSS

DQ32

DQ33

DQ34

DQ35

VCC

CK0

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

*CK1

VSS

CKE0

/S2

DQM2

DQM3

DQM6

DQM7

DQ36

DQ37

DQ38

DQ39

VCC

Architecture Key

CB2

CB6

DQ8

VSS

DQ9

DQ10

DQ11

DQ12

DQ13

VCC

DQ14

DQ15

CB0

CB1

VSS

DQ40

VSS

DQ41

DQ42

DQ43

DQ44

DQ45

VCC

DQ46

DQ47

CB4

CB5

VSS

CB3

CB7

VSS

DQ16

DQ17

DQ18

DQ19

VCC

DQ20

VSS

DQ48

DQ49

DQ50

DQ51

VCC

DQ52

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

REGE

VSS

DQ53

DQ54

DQ55

VSS

DQ56

DQ57

DQ58

DQ59

VCC

DQ60

DQ61

DQ62

DQ63

VSS

*CK3

VSS

DQ21

DQ22

DQ23

VSS

DQ24

DQ25

DQ26

DQ27

VCC

DQ28

DQ29

DQ30

DQ31

VSS

*CK2

VCC

/WE

DQM0

DQM1

/S0

VCC

/CAS

DQM4

DQM5

VSS

/RAS

VSS

A10/AP

BA1

VCC

BA0

A11

SA0

SA1

SA2

VCC

SDA

SCL

Voltage Key

VCC

Note : *. CK1~CK3 are connected with termination R/C. (Refer to the Block Diagram.)

Rev. 0.1/Apr.01

PC133 SDRAM Registered DIMM

HYM7V73AC801B H-Series

BLOCK DIAGRAM

Note : 1. The serial resistor values of DQs are 10 Ohms.

2. The padding capacitance of termination R/C for CK1~CK3 is 12pF.

Rev. 0.1/Apr.01

PC133 SDRAM Registered DIMM

HYM7V73AC801B H-Series

SERIAL PRESENCE DETECT

BYTE

FUNCTION

-75

VALUE

-75

NOTE

NUMBER

DESCRIBED

# of Bytes Written into Serial Memory

at Module Manufacturer

BYTE0

128 Bytes

80h

BYTE1

BYTE2

BYTE3

BYTE4

BYTE5

BYTE6

BYTE7

BYTE8

BYTE9

BYTE10

BYTE11

Total # of Bytes of SPD Memory Device

Fundamental Memory Type

256 Bytes

SDRAM

08h

04h

0Ch

09h

01h

48h

00h

01h

75h

54h

02h

# of Row Addresses on This Assembly

# of Column Addresses on This Assembly

# of Module Banks on This Assembly

Data Width of This Assembly

1 Bank

72 Bits

Data Width of This Assembly (Continued)

Voltage Interface Standard of This Assembly

SDRAM Cycle Time @ /CAS Latency=3

Access Time from Clock @ /CAS Latency=3

DIMM Configuration Type

LVTTL

7.5ns

5.4ns

ECC

15.625ms

/ Self Refresh Supported

BYTE12

Refresh Rate/Type

80h

BYTE13

BYTE14

Primary SDRAM Width

08h

Error Checking SDRAM Width

Minimum Clock Delay Back to Back Random

Column Address

BYTE15

tCCD = 1 CLK

01h

BYTE16

BYTE17

BYTE18

BYTE19

BYTE20

Burst Lengths Supported

1,2,4,8,Full Page

4 Banks

8Fh

04h

06h

01h

# of Banks on Each SDRAM Device

SDRAM Device Attributes, CAS # Latency

SDRAM Device Attributes, CS # Latency

SDRAM Device Attributes, Write Latency

/CAS Latency=2,3

/CS Latency=0

/WE Latency=0

Registered/Buffered Inputs,

with PLL

BYTE21

SDRAM Module Attributes

1Fh

+/-10% voltage tolerance, Burst

Read Single bit Write, Precharge

All, Auto Precharge, Early RAS

Precharge

BYTE22

SDRAM Device Attributes, General

0Eh

BYTE23

BYTE24

BYTE25

BYTE26

BYTE27

BYTE28

BYTE29

BYTE30

BYTE31

BYTE32

BYTE33

BYTE34

SDRAM Cycle Time @ /CAS Latency=2

Access Time from Clock @ /CAS Latency=2

SDRAM Cycle Time @ /CAS Latency=1

Access Time from Clock @ /CAS Latency=1

Minimum Row Precharge Time (tRP)

Minimum Row Active to Row Active Delay (tRRD)

Minimum /RAS to /CAS Delay (tRCD)

Minimum /RAS Pulse width (tRAS)

10ns

6ns

A0h

60h

00h

14h

0Fh

14h

2Dh

10h

15h

08h

15h

08h

20ns

15ns

20ns

45ns

64MB

1.5ns

0.8ns

1.5ns

0.8ns

Module Bank Density

Command and Address Signal Input Setup Time

Command and Address Signal Input Hold Time

Data Signal Input Setup Time

BYTE35

BYTE36

–61

Data Signal Input Hold Time

Superset Information (may be used in future)

00h

BYTE62

BYTE63

SPD Revision

Intel SPD 1.2

12h

CFh

ADh

3, 4

Checksum for Bytes 0~62

Manufacturer JEDEC ID Code

BYTE64

BYTE65

~71

Hynix JEDEC ID

....Manufacturer JEDEC ID Code

Unused

FFh

Hynix (Korea Area)

HSA (United States Area)

HSU (Europe Area)

HSJ (Japan Area)

Asia Area

0*h

1*h

2*h

3*h

4*h

BYTE72

Manufacturing Location

Rev. 0.1/Apr.01

PC133 SDRAM Registered DIMM

HYM7V73AC801B H-Series

Continued

BYTE

NUMBER

BYTE73

BYTE74

BYTE75

BYTE76

BYTE77

BYTE78

BYTE79

BYTE80

BYTE81

BYTE82

BYTE83

BYTE84

BYTE85

BYTE86

BYTE87

BYTE88

BYTE89

~90

FUNCTION

VALUE

-75

NOTE

DESCRIBED

-75

Manufacturer’ s Part Number (Component)

Manufacturer’ s Part Number (Voltage Interface)

Manufacturer’ s Part Number (Data Width)

....Manufacturer’ s Part Number (Data Width)

Manufacturer’ s Part Number (ECC)

7 (SDRAM)

37h

56h

37h

33h

41h

43h

38h

30h

31h

42h

54h

48h

47h

2Dh

37h

35h

20h

5, 6

V (3.3V, LVTTL)

Manufacturer’ s Part Number (Reg. DIMM Type)

Manufacturer’ s Part Number (Memory Depth)

Manufacturer’ s Part Number (Refresh)

Manufacturer’ s Part Number (Internal Banks)

Manufacturer’ s Part Number (Generation)

Manufacturer’ s Part Number (Package Type)

Manufacturer’ s Part Number (Module Type)

Manufacturer’ s Part Number (Plating Type)

Manufacturer’ s Part Number (Hyphen)

Manufacturer’ s Part Number (Min. Cycle Time)

....Manufacturer’ s Part Number (Min. Cycle Time)

Manufacturer’ s Part Number

C (RCC Registered with PLL)

0 (4K Refresh)

1 (4 Banks)

T (TSOPII)

H (x8 based Registered DIMM)

G (Gold)

- (Hyphen)

Blank

BYTE91

BYTE92

BYTE93

BYTE94

Revision Code (for Component)

....Revision Code (for PCB)

Manufacturing Date

Process Code

Work Week

Year

5, 7

3, 7

....Manufacturing Date

BYTE95

~98

Assembly Serial Number

Serial Number

None

BYTE99

~125

Manufacturer Specific Data (may be used in

future)

00h

BYTE126

Reserved

Refer to Note8

64h

87h

4, 8

BYTE127

BYTE128

~256

Intel specification details for 100MHZ support

Unused Storage Locations

00h

Note: 1. The bank address is excluded.

2. 1,2,4,8 for Interleave Burst Type

3. BCD adopted.

4. Refer to the most recent version of the Intel and JEDEC SPD Specification.

5. ASCII adopted.

6. Basically Hynix writes Part No. except for ` HYM ` in Byte 73-90 to use the limited 18 bytes from byte 73 to 90 efficiently.

7. Not fixed but dependent.

8. These values apply to PC100 applications only, per Intel PC SDRAM SPD specification

9. In a registered DIMM, data is delayed an additional clock cycle due to the register (that is, Device CL + 1 = DIMM CL)

10. Refer to Hynix Web Site.

Rev. 0.1/Apr.01

PC133 SDRAM Registered DIMM

HYM7V73AC801B H-Series

ABSOLUTE MAXIMUM RATINGS

PARAMETER

Ambient Temperature

SYMBOL

RATING

0 ~ 70

UNIT

°C

Storage Temperature

TSTG

-55 ~ 125

°C

Voltage on any Pin relative to VSS

Voltage on VDD relative to VSS

Short Circuit Output Current

Power Dissipation

VIN, VOUT

VDD, VDDQ

IOS

-1.0 ~ 4.6

Soldering Temperature· Time

TSOLDER

260 · 10

°C · Sec

Note :Operation at above absolute maximum can adversely affect device reliability.

DC OPERATING CONDITION

(TA = 0 to 70°C)

PARAMETER

SYMBOL

VCC

MIN

TYP.

MAX

UNIT

NOTE

Power Supply Voltage

Input High Voltage

Input Low Voltage

3.0

2.0

3.3

3.0

3.6

VCC + 2.0

0.8

VIH

VIL

1, 2

1, 3

VSS – 2.0

Note :1. All voltage are referenced to VSS = 0V.

2. VIH (max) is acceptable 5.6V AC pulse width with £ 3ns of duration.

3. VIL (min) is acceptable –2.0V AC pulse width with £ 3ns of duration.

AC OPERATING CONDITION

(TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V)

PARAMETER

SYMBOL

VIH / VIL

VALUE

UNIT

AC Input High / Low Level Voltage

2.4 / o.4

1.4

Input Timing Measurement Reference Level Voltage

Input Rise / Fall Time

Vtrip

tR / tF

Voutref

Output Timing Measurement Reference Level Voltage

Output Load Capacitance for Access Time Measurement

1.4

*Note

Note :*. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF).

For details, refer to AC/DC output circuit.

Rev. 0.1/Apr.01

PC133 SDRAM Registered DIMM

HYM7V73AC801B H-Series

CAPACITANCE

(TA = 25°C, f = 1MHz)

PARAMETER

SYMBOL

MIN

MAX

TYP.

UNIT

CK0

CIN1

CIN2

CIN3

CIN4

CIN5

CIN6

CI/O

CKE0

/S0, /S1

Input Capacitance

A0~A11, BA0, BA1

/RAS, /CAS, /WE

DQM0~DQM7

Data Input/Output Capacitance

DQ0~DQ63, CB0~CB7

OUTPUT LOAD CIRCUIT

Rev. 0.1/Apr.01

PC133 SDRAM Registered DIMM

HYM7V73AC801B H-Series

DC CHARACTERISTICS I

(TA = 0 to 70°C, VDD = 3.3 ± 0.3V)

PARAMETER

SYMBOL

MIN

MAX

UNIT

NOTE

Input Leakage Current

Output Leakage Current

Output High Voltage

Output Low Voltage

ILI

-10

-1

ILO

VOH

VOL

2.4

IOH = -4mA

IOL = +4mA

0.4

Note :1. VIN = 0 to 3.6V. All other pins are not tested under VIN = 0V.

2. DOUT is disabled. VOUT = 0 to 3.6V.

DC CHARACTERISTICS II

(TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V)

SPEED

PARAMETER

SYMBOL

TEST CONDITION

UNIT

NOTE

-75

Burst Length = 1, One bank active

tRC ³ tRC(min), IOL = 0mA

Operating Current

IDD1

1130

IDD2P

338

108

CKE £ VIL(max), tCK = min

CKE £ VIL(max), tCK = ¥

Precharge Standby Current

in Power Down Mode

IDD2PS

CKE ³ VIH(min), /CS ³ VIH(min), tCK = min

Input signals are changed one time during

2clks. All other pins ³ VDD – 0.2V or £ 0.2V

IDD2N

535

225

Precharge Standby Current

in Non Power Down Mode

CKE ³ VIH(max), tCK = ¥

Input signals are stable.

IDD2NS

IDD3P

365

135

CKE £ VIL(max), tCK = min

CKE £ VIL(max), tCK = ¥

Active Standby Current

in Power Down Mode

IDD3PS

CKE ³ VIH(min), /CS ³ VIH(min), tCK = min

Input signals are changed one time during

2clks. All other pins ³ VDD – 0.2V or £ 0.2V

IDD3N

670

360

Active Standby Current

in Non Power Down Mode

CKE ³ VIH(max), tCK = ¥

Input signals are stable.

IDD3NS

CL = 3

1400

1130

2000

258

Burst

Current

Mode

Operating

tCK ³ tCK(min), IOL = 0mA

IDD4

IDD5

IDD6

All banks active

tRRC ³ tRRC(min), All banks active

tCK = min

tCK = ¥

CL = 2

Auto Refresh Current

Self Refresh Current

CKE £ 0.2V

Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.

2. Min. of tRRC (Refresh /RAS cycle time) is shown at AC CHARACTERISTICS II.

3. All values are measured with Registers and PLL.

Rev. 0.1/Apr.01

PC133 SDRAM Registered DIMM

HYM7V73AC801B H-Series

AC CHARACTERISTICS I

(AC operating conditions unless otherwise noted)

-75

PARAMETER

SYMBOL

UNIT

NOTE

MIN

MAX

/CAS Latency = 3

/CAS Latency = 2

tCK3

tCK2

tCHW

tCLW

tAC3

tAC2

tOH

7.5

System Clock

Cycle Time

1000

Clock High Pulse Width

Clock Low Pulse Width

2.5

/CAS Latency = 3

/CAS Latency = 2

5.4

Access Time

from Clock

Data-Out Hold Time

Data-Input Setup Time

Data-Input Hold Time

Address Setup Time

Address Hold Time

2.7

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

tDS

tDH

tDS

tDH

CKE Setup Time

tDS

CKE Hold Time

tDH

Command Setup Time

Command Hold Time

CLK to Data Output in Low-Z time

tDS

tDH

tOLZ

tOHZ3

tOHZ2

CLK to Data

/CAS Latency = 3

/CAS Latency = 2

2.7

5.4

Output

High-Z time

Note : 1. In a registered DIMM, data is delayed an additional clock cycle due to the register (that is, Device CL + 1 = DIMM CL).

2. Assume tR / tF (input rise and fall time) is 1ns.

3. Access times to be measured with input signals of 1v/ns edge rate.

Rev. 0.1/Apr.01

PC133 SDRAM Registered DIMM

HYM7V73AC801B H-Series

AC CHARACTERISTICS II

-75

PARAMETER

SYMBOL

UNIT

NOTE

MIN

MAX

Operation

Auto Refresh

tRC

/RAS

Time

Cycle

tRRC

tRCD

tRAS

tRP

/RAS to /CAS Delay

/RAS Active Time

100K

/RAS Precharge Time

/RAS to /RAS Bank Active Delay

/CAS to /CAS Delay

tRRD

tCCD

tWTL

tDPL

CLK

Write Command to Data-in Delay

Data-in to Precharge Command

Data-in to Active Command

DQM to Data-out Hi-Z

tDAL

tDQZ

tDQM

tMRD

tPROZ3

tPROZ2

DQM to Data-in Mask

MRS to New Command

Precharge to

Data

Hi-Z

/CAS Latency = 3

/CAS Latency = 2

Output

CLK

Power Down Exit Time

Self Refresh Exit Time

Refresh Time

tPDE

tSRE

tREF

CLK

Note : 1. Timing delay due to the register is considered in a registered DIMM.

2. A new command can be given tRRC after self refresh exit.

Rev. 0.1/Apr.01

PC133 SDRAM Registered DIMM

HYM7V73AC801B H-Series

OPERATING OPTION TABLE

/CAS

tRCD

tRAS

tRC

tRP

tAC

tOH

LATENCY

133MHz (7.5ns)

125MHz (8.0ns)

100MHz (10.0ns)

3CLKS

2CLKS

3CLKS

2CLKS

6CLKS

5CLKS

9CLKS

7CLKS

3CLKS

2CLKS

5.4ns

6ns

2.7ns

3ns

6ns

3ns

Note :DIMM /CAS Latency = Device CL + 1 (Registered mode)

COMMAND TRUTH TABLE

A10/

CKEn-1

CKEn

/CS

/RAS

/CAS

/WE

DQM

ADDR

NOTE

Mode Register Set

No Operation

OP code

Bank Active

Read

Read with Autoprecharge

Write

Write withAutoprecharge

Precharge All Banks

Precharge Selected Bank

Burst Stop

DQM

Auto Refresh

Entry

Self Refresh

Exit

Entry

Precharge

Power Down

Exit

Entry

Clock Suspend

Exit

Note : 1. Existing Self Refresh occurs by asynchronously bringing CKE from low to high.

2. X = Don’ t care, H = Logic High, L = logic Low, BA = Bank Address, CA = Column Address, OP code = Operand code,

NOP = No operation

Rev. 0.1/Apr.01

PC133 SDRAM Registered DIMM

HYM7V73AC801B H-Series

PACKAGE DIMENSIONS

Rev. 0.1/Apr.01

HYM7V73AC801BTHG [ETC]

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