HYM7V75A1601BTFG [ETC]
16Mx72|3.3V|P/S|x18|SDR SDRAM - Unbuffered DIMM 128MB ; 16Mx72 | 3.3V | P / S | X18 | SDR SDRAM - 无缓冲DIMM 128MB\n型号: | HYM7V75A1601BTFG |
厂家: | ETC |
描述: | 16Mx72|3.3V|P/S|x18|SDR SDRAM - Unbuffered DIMM 128MB
|
文件: | 总14页 (文件大小:199K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
16Mx72 bits
PC100 SDRAM Unbuffered DIMM
based on 8Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM7V75A1601B F-Series
DESCRIPTION
The Hynix HYM7V75A1601B F-Series are 16Mx72bits ECC Synchronous DRAM Modules. The modules are composed
of eighteen 8Mx8bit CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP
package on a 168pin glass-epoxy printed circuit board. A 0.33uF and a 0.1uF decoupling capacitors per each SDRAM
are mounted on the PCB.
The HYM7V75A1601B F-Series are Dual In-line Memory Modules suitable for easy interchange and addition of
128Mbytes memory. The HYM7V75A1601B F-Series are offering fully synchronous operation referenced to a positive
edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are
internally pipelined to achieve very high bandwidth.
FEATURES
· PC100MHz support
· SDRAM internal banks : four banks
· Module banks : two banks
· 168pin SDRAM Unbuffered DIMM
· Serial Presence Detect with EEPROM
· Auto refresh and self refresh
· 4096 refresh cycles / 64ms
· 1.375” (34.93mm) Height PCB with Double Sided
components
· Programmable Burst Length and Burst Type
-. 1, 2, 4, 8, or Full Page for Sequential Burst
-. 1, 2, 4 or 8 for Interleave Burst
· Single 3.3 ± 0.3V power supply
· All devices pins are compatible with LVTTL interface
· Data mask function by DQM
· Programmable /CAS Latency
-. 2, 3 Clocks
ORDERING INFORMATION
MAX.
FREQUENCY
INTERNAL
BANK
SDRAM
PACKAGE
PART NO.
REF.
POWER
PLATING
HYM7V75A1601BTFG-8
HYM7V75A1601BTFG-10P
HYM7V75A1601BTFG-10S
125MHz
100MHz
100MHz
4 Banks
4K
Normal
TSOP-II
Gold
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1/Apr.01
1999 Hyundai Electronics
PC100 SDRAM Unbuffered DIMM
HYM7V75A1601B F-Series
PIN DESCRIPTION
PIN NAME
DESCRIPTION
The System Clock Input. All other inputs are registered to the
SDRAM on the rising edge of CLK.
CK0~CK3
Clock Inputs
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
CKE0, CKE1
Clock Enable
/S0~/S3
Chip Select
Enables or disables all inputs except CK, CKE and DQM.
Select bank to be activated during /RAS activity.
Select bank to be read/written during /CAS activity
Row address : RA0~RA11, Column address : CA0~CA8
Auto-precharge flag : A10
BA0, BA1
SDRAM Bank Address
A0~A11
/RAS
Address Inputs
/RAS define the operation.
Row Address Strobe
Column Address Strobe
Refer to the function truth table for details.
/CAS define the operation.
/CAS
Refer to the function truth table for details.
/WE define the operation.
/WE
Write Enable
Refer to the function truth table for details.
Controls output buffers in read mode and masks input data in
write mode.
DQM0~DQM7
Data Input/Output Mask
DQ0~DQ63
CB0~CB7
VCC
Data Input/Output
ECC Data Input/Output
Power Supply (3.3V)
Ground
Multiplexed data input/output pins
Error Checking and Correction Bits
Power supply for internal circuits and input/output buffers
Ground
VSS
SCL
SPD Clock Input
SPD Data Input/Output
SPD Address Input
Write Protect for SPD
No Connect
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address input
Write Protect for Serial Presence Detect on DIMM
No Connect or Don’ t Use
SDA
SA0~SA2
WP
NC
2
Rev. 1.1/Apr.01
PC100 SDRAM Unbuffered DIMM
HYM7V75A1601B F-Series
PIN ASSIGNMENTS
FRONT SIDE
BACK SIDE
NAME
FRONT SIDE
BACK SIDE
NAME
PIN NO.
NAME
PIN NO.
PIN NO.
NAME
PIN NO.
1
2
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
85
86
87
88
89
90
91
92
93
94
VSS
DQ32
DQ33
DQ34
DQ35
VCC
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VCC
CK0
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
CK1
NC
3
4
VSS
NC
VSS
CKE0
/S3
5
/S2
6
DQM2
DQM3
NC
DQM6
DQM7
NC
7
DQ36
DQ37
DQ38
DQ39
8
9
VCC
NC
VCC
NC
10
NC
NC
Architecture Key
CB2
CB6
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
CB0
CB1
VSS
NC
95
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
CB4
CB5
VSS
NC
CB3
CB7
96
VSS
DQ16
DQ17
DQ18
DQ19
VCC
DQ20
NC
VSS
DQ48
DQ49
DQ50
DQ51
VCC
DQ52
NC
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
NC
NC
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
CK2
NC
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
CK3
NC
NC
VCC
/WE
DQM0
DQM1
/S0
VCC
/CAS
DQM4
DQM5
/S1
NC
VSS
A0
/RAS
VSS
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
BA1
VCC
BA0
A11
NC
NC
WP
SA0
SA1
SA2
VCC
VCC
SDA
SCL
Voltage Key
VCC
3
Rev. 1.1/Apr.01
PC100 SDRAM Unbuffered DIMM
HYM7V75A1601B F-Series
BLOCK DIAGRAM
Note : The serial resistor values of DQs are 10 Ohms.
4
Rev. 1.1/Apr.01
PC100 SDRAM Unbuffered DIMM
HYM7V75A1601B F-Series
SERIAL PRESENCE DETECT
BYTE
FUNCTION
FUNCTION
-10P
VALUE
-10P
NOTE
NUMBER
DESCRIBED
# of Bytes Written into Serial Memory
at Module Manufacturer
-8
-10S
-8
-10S
BYTE0
128 Bytes
80h
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
BYTE8
BYTE9
BYTE10
BYTE11
Total # of Bytes of SPD Memory Device
Fundamental Memory Type
256 Bytes
SDRAM
12
08h
04h
0Ch
09h
02h
48h
00h
01h
A0h
60h
02h
# of Row Addresses on This Assembly
# of Column Addresses on This Assembly
# of Module Banks on This Assembly
Data Width of This Assembly
1
9
2 Banks
72 Bits
-
Data Width of This Assembly (Continued)
Voltage Interface Standard of This Assembly
SDRAM Cycle Time @ /CAS Latency=3
Access Time from Clock @ /CAS Latency=3
DIMM Configuration Type
LVTTL
10ns
8ns
6ns
10ns
6ns
80h
60h
A0h
60h
6ns
ECC
15.625ms
/ Self Refresh Supported
x8
BYTE12
Refresh Rate/Type
80h
BYTE13
BYTE14
Primary SDRAM Width
08h
08h
Error Checking SDRAM Width
x8
Minimum Clock Delay Back to Back Random
Column Address
BYTE15
tCCD = 1 CLK
01h
BYTE16
BYTE17
BYTE18
BYTE19
BYTE20
BYTE21
Burst Lengths Supported
1,2,4,8,Full Page
4 Banks
8Fh
04h
06h
01h
01h
00h
2
# of Banks on Each SDRAM Device
SDRAM Device Attributes, CAS # Latency
SDRAM Device Attributes, CS # Latency
SDRAM Device Attributes, Write Latency
SDRAM Module Attributes
/CAS Latency=2,3
/CS Latency=0
/WE Latency=0
Neither Buffered nor Registered
+/-10% voltage tolerance, Burst
Read Single bit Write, Precharge
All, Auto Precharge, Early RAS
Precharge
BYTE22
SDRAM Device Attributes, General
0Eh
BYTE23
BYTE24
BYTE25
BYTE26
BYTE27
BYTE28
BYTE29
BYTE30
BYTE31
BYTE32
BYTE33
BYTE34
BYTE35
SDRAM Cycle Time @ /CAS Latency=2
Access Time from Clock @ /CAS Latency=2
SDRAM Cycle Time @ /CAS Latency=1
Access Time from Clock @ /CAS Latency=1
Minimum Row Precharge Time (tRP)
Minimum Row Active to Row Active Delay (tRRD)
Minimum /RAS to /CAS Delay (tRCD)
Minimum /RAS Pulse width (tRAS)
10ns
6ns
-
10ns
6ns
-
12ns
6ns
-
A0h
60h
00h
00h
14h
10h
14h
30h
A0h
60h
00h
00h
14h
14h
14h
32h
10h
20h
10h
20h
10h
C0h
60h
00h
00h
14h
14h
14h
32h
-
-
-
20ns
16ns
20ns
48ns
20ns
20ns
20ns
50ns
64MB
2ns
1ns
2ns
1ns
20ns
20ns
20ns
50ns
Module Bank Density
Command and Address Signal Input Setup Time
Command and Address Signal Input Hold Time
Data Signal Input Setup Time
2ns
1ns
2ns
1ns
2ns
1ns
2ns
1ns
20h
10h
20h
10h
20h
10h
20h
10h
Data Signal Input Hold Time
BYTE36
–61
Superset Information (may be used in future)
-
00h
BYTE62
SPD Revision
Intel SPD 1.2A
12h
18h
ADh
3, 8
BYTE63
BYTE64
Checksum for Bytes 0~62
Manufacturer JEDEC ID Code
-
F2h
38h
Hynix JEDEC ID
BYTE65
~71
....Manufacturer JEDEC ID Code
Unused
FFh
Hynix (Korea Area)
HSA (United States Area)
HSU (Europe Area)
HSJ (Japan Area)
Asia Area
0*h
1*h
2*h
3*h
4*h
BYTE72
Manufacturing Location
9
5
Rev. 1.1/Apr.01
PC100 SDRAM Unbuffered DIMM
HYM7V75A1601B F-Series
Continued
BYTE
NUMBER
BYTE73
BYTE74
BYTE75
BYTE76
BYTE77
BYTE78
BYTE79
BYTE80
BYTE81
BYTE82
BYTE83
BYTE84
BYTE85
BYTE86
BYTE87
BYTE88
BYTE89
BYTE90
BYTE91
BYTE92
BYTE93
BYTE94
FUNCTION
FUNCTION
VALUE
-10P
37h
56h
37h
35h
41h
31h
36h
30h
31h
42h
54h
46h
47h
2Dh
31h
30h
50h
20h
-
NOTE
DESCRIBED
-8
-10P
-10S
-8
-10S
Manufacturer’ s Part Number (Component)
Manufacturer’ s Part Number (Voltage Interface)
Manufacturer’ s Part Number (Data Width)
....Manufacturer’ s Part Number (Data Width)
Manufacturer’ s Part Number (ECC)
Manufacturer’ s Part Number (Memory Depth)
....Manufacturer’ s Part Number (Memory Depth)
Manufacturer’ s Part Number (Refresh)
Manufacturer’ s Part Number (Internal Banks)
Manufacturer’ s Part Number (Generation)
Manufacturer’ s Part Number (Package Type)
Manufacturer’ s Part Number (Module Type)
Manufacturer’ s Part Number (Plating Type)
Manufacturer’ s Part Number (Hyphen)
Manufacturer’ s Part Number (Min. Cycle Time)
....Manufacturer’ s Part Number (Min. Cycle Time)
....Manufacturer’ s Part Number (Min. Cycle Time)
Manufacturer’ s Part Number
7 (SDRAM)
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 6
4, 6
3, 6
3, 6
V (3.3V, LVTTL)
7
5
A
1
6
0 (4K Refresh)
1 (4 Banks)
B
T (TSOPII)
F (x8 based Unbuffered DIMM)
G (Gold)
- (Hyphen)
8
1
0
1
0
38h
20h
20h
31h
30h
53h
Blank
Blank
P
S
Blanks
Revision Code (for Component)
Process Code
Process Code
Work Week
Year
....Revision Code (for PCB)
-
Manufacturing Date
-
....Manufacturing Date
-
BYTE95
~98
Assembly Serial Number
Serial Number
None
-
6
BYTE99
~125
Manufacturer Specific Data (may be used in
future)
00h
BYTE126
System Frequency Support
100MHz
64h
F7h
8
BYTE127
BYTE128
~256
Intel Specification Details for 100MHz Support
Refer to Note7
F7h
F5h
7, 8
Unused Storage Locations
-
00h
Note: 1. The bank address is excluded.
2. 1,2,4,8 for Interleave Burst Type
3. BCD adopted.
4. ASCII adopted.
5. Basically Hynix writes Part No. except for ` HYM ` in Byte 73-90 to use the limited 18 bytes from byte 73 to 90 efficiently.
6. Not fixed but dependent.
7. CLK0~CLK3 connected on the DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge support
8. Refer to Intel SPD Specification Rev.1.2A.
9. Refer to Hynix Web Site
6
Rev. 1.1/Apr.01
PC100 SDRAM Unbuffered DIMM
HYM7V75A1601B F-Series
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Ambient Temperature
SYMBOL
RATING
0 ~ 70
UNIT
TA
°C
Storage Temperature
TSTG
-55 ~ 125
°C
V
Voltage on any Pin relative to VSS
Voltage on VDD relative to VSS
Short Circuit Output Current
Power Dissipation
VIN, VOUT
VDD, VDDQ
IOS
-1.0 ~ 4.6
-1.0 ~ 4.6
50
V
MA
W
PD
18
Soldering Temperature· Time
TSOLDER
260 · 10
°C · Sec
Note :Operation at above absolute maximum can adversely affect device reliability.
DC OPERATING CONDITION
(TA = 0 to 70°C)
PARAMETER
SYMBOL
VCC
MIN
TYP.
MAX
UNIT
NOTE
Power Supply Voltage
Input High Voltage
Input Low Voltage
3.0
2.0
3.3
3.0
0
3.6
VCC + 2.0
0.8
V
V
V
1
VIH
VIL
1, 2
1, 3
VSS – 2.0
Note :1. All voltage are referenced to VSS = 0V.
2. VIH (max) is acceptable 5.6V AC pulse width with £ 3ns of duration.
3. VIL (min) is acceptable –2.0V AC pulse width with £ 3ns of duration.
AC OPERATING CONDITION
(TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V)
PARAMETER
SYMBOL
VIH / VIL
VALUE
UNIT
AC Input High / Low Level Voltage
2.4 / o.4
1.4
V
V
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
Vtrip
tR / tF
Voutref
CL
1
ns
V
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
1.4
*Note
pF
Note :*. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF).
For details, refer to AC/DC output circuit.
7
Rev. 1.1/Apr.01
PC100 SDRAM Unbuffered DIMM
HYM7V75A1601B F-Series
CAPACITANCE
(TA = 25°C, f = 1MHz)
PARAMETER
PIN
SYMBOL
MIN
MAX
TYP.
UNIT
CK0~CK3
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CI/O
-
-
-
-
-
-
-
50
65
45
95
95
25
25
-
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
pF
CKE0, CKE1
/S0~/S3
Input Capacitance
A0~A11, BA0, BA1
/RAS, /CAS, /WE
DQM0~DQM7
Data Input/Output Capacitance
DQ0~DQ63, CB0~CB7
OUTPUT LOAD CIRCUIT
8
Rev. 1.1/Apr.01
PC100 SDRAM Unbuffered DIMM
HYM7V75A1601B F-Series
DC CHARACTERISTICS I
(TA = 0 to 70°C, VDD = 3.3 ± 0.3V)
PARAMETER
SYMBOL
MIN
MAX
UNIT
NOTE
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
ILI
-18
-2
18
2
uA
uA
V
1
ILO
VOH
VOL
2
2.4
-
-
IOH = -4mA
IOL = +4mA
0.4
V
Note :1. VIN = 0 to 3.6V. All other pins are not tested under VIN = 0V.
2. DOUT is disabled. VOUT = 0 to 3.6V.
DC CHARACTERISTICS II
(TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V)
SPEED
PARAMETER
SYMBOL
TEST CONDITION
UNIT
NOTE
-8
-10P
-10S
Burst Length = 1, One bank active
tRC ³ tRC(min), IOL = 0mA
Operating Current
IDD1
990
900
900
mA
1
IDD2P
36
36
mA
mA
CKE £ VIL(max), tCK = min
CKE £ VIL(max), tCK = ¥
Precharge Standby Current
in Power Down Mode
IDD2PS
CKE ³ VIH(min), /CS ³ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ³ VDD – 0.2V or £ 0.2V
IDD2N
270
270
mA
mA
Precharge Standby Current
in Non Power Down Mode
CKE ³ VIH(max), tCK = ¥
Input signals are stable.
IDD2NS
IDD3P
90
90
mA
mA
CKE £ VIL(max), tCK = min
CKE £ VIL(max), tCK = ¥
Active Standby Current
in Power Down Mode
IDD3PS
CKE ³ VIH(min), /CS ³ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ³ VDD – 0.2V or £ 0.2V
IDD3N
IDD3NS
IDD4
540
mA
mA
mA
Active Standby Current
in Non Power Down Mode
CKE ³ VIH(max), tCK = ¥
Input signals are stable.
540
990
CL = 3
1260
990
tCK ³ tCK(min), IOL = 0mA
Burst
Current
Mode
Operating
1
2
All banks active
CL = 2
990
990
990
Auto Refresh Current
Self Refresh Current
IDD5
IDD6
3600
3240
3240
mA
mA
tRRC ³ tRRC(min), All banks active
CKE £ 0.2V
36
Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
2. Min. of tRRC (Refresh /RAS cycle time) is shown at AC CHARACTERISTICS II.
9
Rev. 1.1/Apr.01
PC100 SDRAM Unbuffered DIMM
HYM7V75A1601B F-Series
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
-8
-10P
-10S
PARAMETER
SYMBOL
UNIT
NOTE
MIN
MAX
MIN
MAX
MIN
MAX
/CAS Latency = 3
/CAS Latency = 2
tCK3
tCK2
tCHW
tCLW
tAC3
tAC2
tOH
8
10
3
3
-
10
10
3
3
-
10
12
3
3
-
System Clock
Cycle Time
1000
1000
1000
ns
Clock High Pulse Width
Clock Low Pulse Width
-
-
-
-
-
-
ns
ns
I
I
/CAS Latency = 3
/CAS Latency = 2
6
6
-
6
6
-
6
6
-
Access Time
from Clock
ns
2
-
-
-
Data-Out Hold Time
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
3
2
1
2
1
2
1
2
1
1
3
3
3
2
1
2
1
2
1
2
1
1
3
3
3
2
1
2
1
2
1
2
1
1
3
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDS
-
-
-
1
1
1
1
1
1
1
1
tDH
-
-
-
tDS
-
-
-
tDH
-
-
-
CKE Setup Time
tDS
-
-
-
CKE Hold Time
tDH
-
-
-
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z time
tDS
-
-
-
tDH
-
-
-
tOLZ
tOHZ3
tOHZ2
-
-
-
CLK to Data
/CAS Latency = 3
/CAS Latency = 2
6
6
6
6
6
6
Output
in
ns
High-Z time
Note : 1. Assume tR / tF (input rise and fall time) is 1ns.
2. Access times to be measured with input signals of 1v/ns edge rate.
10
Rev. 1.1/Apr.01
PC100 SDRAM Unbuffered DIMM
HYM7V75A1601B F-Series
AC CHARACTERISTICS II
-8
-10P
-10S
PARAMETER
SYMBOL
UNIT
NOTE
MIN
MAX
MIN
MAX
MIN
MAX
Operation
Auto Refresh
tRC
68
68
20
48
20
16
1
70
70
20
50
20
20
1
70
70
20
50
20
20
1
/RAS
Time
Cycle
-
-
-
ns
tRRC
tRCD
tRAS
tRP
/RAS to /CAS Delay
/RAS Active Time
-
-
-
ns
100K
100K
100K
ns
/RAS Precharge Time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
/RAS to /RAS Bank Active Delay
/CAS to /CAS Delay
tRRD
tCCD
tWTL
tDPL
ns
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Write Command to Data-in Delay
Data-in to Precharge Command
Data-in to Active Command
DQM to Data-out Hi-Z
0
0
0
1
1
1
tDAL
4
3
3
tDQZ
tDQM
tMRD
tPROZ3
tPROZ2
2
2
2
DQM to Data-in Mask
0
0
0
MRS to New Command
2
2
2
Precharge to
Data
Hi-Z
/CAS Latency = 3
/CAS Latency = 2
3
3
3
Output
CLK
2
2
2
Power Down Exit Time
Self Refresh Exit Time
Refresh Time
tPDE
tSRE
tREF
1
1
-
-
-
1
1
-
-
-
1
1
-
-
-
CLK
CLK
ms
1
64
64
64
Note : 1. A new command can be given tRRC after self refresh exit.
11
Rev. 1.1/Apr.01
PC100 SDRAM Unbuffered DIMM
HYM7V75A1601B F-Series
OPERATING OPTION TABLE
HYM7V75A1601BTFG-8
/CAS
tRCD
tRAS
tRC
tRP
tAC
tOH
LATENCY
125MHz (8.0ns)
100MHz (10.0ns)
83MHz (12.0ns)
3CLKS
2CLKS
2CLKS
3CLKS
2CLKS
2CLKS
6CLKS
5CLKS
4CLKS
9CLKS
7CLKS
6CLKS
3CLKS
2CLKS
2CLKS
6ns
6ns
6ns
3ns
3ns
3ns
HYM7V75A1601BTFG-10P
/CAS
LATENCY
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz (10.0ns)
83MHz (12.0ns)
66MHz (15.0ns)
2CLKS
2CLKS
2CLKS
2CLKS
2CLKS
2CLKS
5CLKS
5CLKS
4CLKS
7CLKS
7CLKS
6CLKS
2CLKS
2CLKS
2CLKS
6ns
6ns
6ns
3ns
3ns
3ns
HYM7V75A1601BTFG-10S
/CAS
LATENCY
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz (10.0ns)
83MHz (12.0ns)
66MHz (15.0ns)
3CLKS
2CLKS
2CLKS
2CLKS
2CLKS
2CLKS
5CLKS
5CLKS
4CLKS
7CLKS
7CLKS
6CLKS
2CLKS
2CLKS
2CLKS
6ns
6ns
6ns
3ns
3ns
3ns
12
Rev. 1.1/Apr.01
PC100 SDRAM Unbuffered DIMM
HYM7V75A1601B F-Series
COMMAND TRUTH TABLE
A10/
AP
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
DQM
ADDR
BA
NOTE
Mode Register Set
No Operation
H
X
L
H
L
L
L
L
L
X
OP code
X
H
L
X
H
H
X
H
H
H
H
X
X
X
X
X
Bank Active
RA
V
V
Read
L
H
H
H
X
X
L
L
H
H
L
L
L
H
L
X
X
X
CA
CA
X
Read with Autoprecharge
Write
H
L
V
Write withAutoprecharge
Precharge All Banks
Precharge Selected Bank
Burst Stop
H
H
L
X
V
X
X
L
L
H
H
L
L
H
H
H
H
H
X
L
X
V
X
X
X
X
X
DQM
Auto Refresh
Entry
H
L
L
L
L
H
H
X
H
X
H
X
H
X
V
L
L
Self Refresh
Exit
H
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
X
L
H
L
X
X
X
X
X
1
H
L
Entry
H
L
Precharge
Power Down
X
H
L
Exit
H
L
H
L
Entry
Clock Suspend
Exit
H
L
X
H
X
Note : 1. Existing Self Refresh occurs by asynchronously bringing CKE from low to high.
2. X = Don’ t care, H = Logic High, L = logic Low, BA = Bank Address, CA = Column Address, OP code = Operand code,
NOP = No operation
13
Rev. 1.1/Apr.01
PC100 SDRAM Unbuffered DIMM
HYM7V75A1601B F-Series
PACKAGE DIMENSIONS
14
Rev. 1.1/Apr.01
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