HYS72D32501GR-7 [ETC]
x72 SDRAM Module ; X72 SDRAM模块\n
| 型号： | HYS72D32501GR-7 |
| 厂家： | 
ETC |
| 描述： | x72 SDRAM Module
|
| 文件： | 总24页 (文件大小：454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HYS 72Dxx5xxGR
Low Profile Registered DDR-I SDRAM-Modules
2.5 V Low Profile 184-pin Registered DDR-I SDRAM Modules
128MB, 256MB, 512MB, 1GByte & 2GByte Modules
PC1600 & PC2100
Target Datasheet Rev. 0.6 (10.01)
•
184-pin Registered 8-Byte Dual-In-Line
DDR-I SDRAM Module for “1U” PC,
Workstation and Server main memory
applications
•
•
•
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Re-drive for all input signals using register
and PLL devices.
•
•
One bank 16M x 72, 32M × 72, 64M x 72 and
two bank 128M × 72 and 256M x 72
organization
•
•
Serial Presence Detect with E2PROM
Low Profile Modules form factor:
133.35 mm x 30,40 mm (1.2”) x 4.00 mm
(6,80 mm with stacked components)
JEDEC standard Double Data Rate
Synchronous DRAMs (DDR-I SDRAM) with a
single + 2.5 V (± 0.2 V) power supply
•
•
Based on Jedec standard reference card
layouts RawCard “L”, “M”
•
•
Built with DDR-I SDRAMs in 66-Lead TSOPII
package
Gold plated contacts
Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
•
Performance:
-7
-8
Unit
Component Speed Grade
Module Speed Grade
DDR266A DDR200
PC2100
143
PC1600
125
fCK
fCK
Clock Frequency (max.) @ CL = 2.5
Clock Frequency (max.) @ CL = 2
MHz
MHz
133
100
The HYS72Dxx5x0GR are low profile versions of the standard Registered DIMM modules with 1.2”
inch (30,40 mm) height for 1U Server Applications. The Low Profile DIMM versions are available as
16M x 72 (128MB), 32M x 72 (256MB), 64M x 72 (512MB), 128M x 72 (1 GB) and 256M x 72 (2GB).
The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications.
All control and address signals are re-driven on the DIMM using register devices and a PLL for the
clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the
SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs
feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The
first 128 bytes are programmed with configuration data and the second 128 bytes are available to
the customer.
INFINEON Technologies
1
10.01
HYS 72Dxx5xxGR
Registered DDR-I SDRAM-Modules
Ordering Information
Type
Compliance Code Description
SDRAM
Module
Technology height
PC2100 (CL=2):
HYS72D16500GR-7
HYS 72D32501GR-7
HYS 72D32500GR-7
HYS 72D64500GR-7
HYS 72D128520GR-7
PC2100R-20330-L
PC2100R-20330-M
PC2100R-20330-L
PC2100R-20330-M
PC2100R-20330- *)
one bank 128 MB Reg. DIMM
128 MBit (x8) 1.2”
128 MBit (x4) 1.2”
256 MBit (x8) 1.2”
256 Mbit (x4) 1.2”
one bank 256 MB Reg. DIMM
one bank 256 MB Reg. DIMM
one bank 512 MB Reg. DIMM
two banks 1 GByte Reg. DIMM
256 MBit (x4) 1.2”
(stacked)
HYS 72D256520GR-7
PC2100R-20330-*)
two banks 2 GByte Reg. DIMM
512 MBit (x4) 1.2”
(stacked)
PC1600 (CL=2):
HYS72D16500GR-8
HYS 72D32501GR-8
HYS 72D32500GR-8
HYS 72D64500GR-8
HYS 72D128520GR-8
PC1600R-20220-L
PC1600R-20220-M
PC1600R-20220-L
PC1600R-20220-M
PC1600R-20220-*)
one bank 128 MB Reg. DIMM
one bank 256 MB Reg. DIMM
one bank 256 MB Reg. DIMM
one bank 512 MB Reg. DIMM
two banks 1 GByte Reg. DIMM
128 MBit (x8) 1.2”
128 MBit (x4) 1.2”
256 MBit (x8) 1.2”
256 Mbit (x4) 1.2”
256 MBit (x4) 1.2”
(stacked)
HYS 72D256520GR-8
Notes:
PC1600R-20220-*)
two banks 2 GByte Reg. DIMM
512 MBit (x4) 1.2”
(stacked)
1. All part numbers end with a place code (not shown), designating the silicon-die revision. Reference information available
on request. Example: HYS 72D32500GR-8-A, indicating Rev.A die are used for SDRAM components.
2. The Compliance Code is printed on the module labels and describes the speed sort fe. “PC2100R”, the latencies (f.e.
“20330” means CAS latency = 2.5, trcd latency = 3 and trp latency =3 ) and the Raw Card used for this module
3. *) n.d.y..
INFINEON Technologies
2
10.01
HYS 72Dxx5xxGR
Registered DDR-I SDRAM-Modules
Pin Definitions and Functions
A0 - A11,A12
Address Inputs
VDD
Power (+ 2.5 V)
(A12 for 256Mb & 512Mb based modules)
BA0, BA1
DQ0 - DQ63
CB0 - CB7
RAS
Bank Selects
VSS
Ground
Data Input/Output
VDDQ
VDDID
VDDSPD
VREF
I/O Driver power supply
VDD Indentification flag
EEPROM power supply
I/O reference supply
Serial bus clock
Check Bits (x72 organization only)
Row Address Strobe
Column Address Strobe
Read/Write Input
CAS
WE
SCL
CKE0, CKE1
DQS0 - DQS8
CK0, CK0
Clock Enable
SDA
SA0 - SA2
NC
Serial bus data line
slave address select
no connect
SDRAM low data strobes
Differential Clock Input
DM0 - DM8
DQS9 - DQS17
SDRAM low data mask/
high data strobes
DU
don’t use
CS0 - CS1
Chip Selects
RESET
Reset pin (forces register
inputs low) *)
*) for detailed description of the Power Up and Power Management on DDR Registered DIMMs see the
Application Note at the end of this datasheet
Address Format
Density Organization
128 MB 16M x 72
256 MB 32M x 72
256 MB 32M x 72
512 MB 64M × 72
Memory SDRAMs
Banks
# of
# of row/bank/
Refresh Period Interval
SDRAMs columns bits
1
1
1
1
2
2
(128Mb)
16M x 8
9
12/2/10
12/2/11
13/2/10
13/2/11
13/2/11
13/2/12
4k
4k
8k
8k
8k
8k
64 ms 15.6 µs
64 ms 15.6 µs
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
(128 Mb)
32M x 4
18
9
(256Mb)
32M x 8
(256Mb)
64M × 4
18
1 GB
2 GB
128M × 72
(256Mb)
64M × 4
36
(stacked)
256M x 72
(512Mb)
36
128M × 4
(stacked)
INFINEON Technologies
3
10.01
HYS 72Dxx5xxGR
Registered DDR-I SDRAM-Modules
Pin Configuration
Symbol
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
PIN#
48
49
50
51
Symbol
A0
CB2
VSS
CB3
PIN#
93
94
95
96
97
98
99
Symbol
VSS
DQ4
Symbol
DM8/DQS17
A10
CB6
VDDQ
CB7
PIN#
1
2
3
4
5
6
7
140
141
142
143
144
DQ5
VDDQ
DM0/DQS9
DQ6
DQ7
VSS
NC
NC
NC
52
BA1
KEY
KEY
VSS
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
8
9
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
DQ36
DQ37
VDD
DM4/DQS13
DQ38
DQ39
VSS
DQ44
RAS
DQ45
VDDQ
CS0
CS1
DM5/DQS14
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
RESET
VSS
DQ8
DQ9
DQS1
VDDQ
DU
VDDQ
DQ12
DQ13
DM1/DQS10
VDD
DQ14
DQ15
CKE1
VDDQ
NC
DQ20
NC / A12
VSS
DQ21
A11
DM2/DQS11
VDD
DQ22
A8
DQ23
VSS
A6
DQ28
DQ29
VDDQ
DM3/DQS12
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
CK0
VSS
BA0
DQ35
DQ40
VDDQ
WE
DQ41
CAS
DU
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
DU
DU
VDD
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
DM6/DQS15
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7/DQS16
DQ62
DQ63
VDDQ
SA0
NC
SDA
SCL
SA1
SA2
VDDSPD
VDD
DQS8
Note: A12 is used for 256Mbit and 512Mbit based modules only
INFINEON Technologies
4
10.01
HYS 72Dxx5xxGR
Registered DDR-I SDRAM-Modules
RS0
DQS0
DQS4
DM4/DQS13
DM0/DQS9
DM
I/O 0
DQS
CS
D4
DQS
CS
D0
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ1
DQ2
DQ3
DQ36
DQ37
DQ38
DQ39
DQ4
DQ5
DQ6
DQ7
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS
DQS
CS
D5
CS
D1
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ8
DQ9
DQ10
DQ11
I/O 4
I/O 5
I/O 6
I/O 7
DQ44
DQ45
DQ46
DQ47
DQ12
DQ13
DQ14
DQ15
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D6
DQS
DM
CS DQS
D2
DQ48
DQ49
DQ50
DQ51
I/O 0
DQ16
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ17
DQ18
DQ19
DQ52
DQ53
DQ54
DQ55
DQ20
DQ21
DQ22
DQ23
DQS7
DM7/DQS16
DQS3
DM3/DQS12
DM
I/O 0
CS DQS
D7
CS
D3
DM
DQS
DQ56
DQ57
DQ58
DQ59
I/O 0
DQ24
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ60
DQ61
DQ62
DQ63
DQS8
DM8/DQS17
V
EEPROM
D0 - D8
DDSPD
Serial PD
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
D8
DQS
V
V
CB0
CB1
CB2
CB3
DD, DDQ
D0 - D8
D0 - D8
SDA
SCL
VREF
A0
SA0 SA1 SA2
A1
A2
V
SS
D0 - D8
CB4
CB5
CB6
CB7
V
DDID
Strap: see Note 4
CS0
RS0 -> CS : SDRAMs D0-D8
R
E
G
I
S
T
E
R
Notes:
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D8
BA0-BA1
A0-A12
RAS
1. DQ-to-I/O wiring may be changed within a byte.
RA0-RA12 -> A0-A12: SDRAMs D0 - D8
RRAS -> RAS : SDRAMs D0 - D8
RCAS -> CAS : SDRAMs D0 - D8
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
CAS
CKE0
WE
RCKE0 -> CKE: SDRAMs D0 - D8
RWE -> WE : SDRAMs D0 - D8
STRAP OUT (OPEN): VDD = VDDQ
5. SDRAM placement alternates between the back
and front of the DIMM.
CK0, CK 0 --------- PLL*
* Wire per Clock Loading Table/Wiring Diagrams
PCK
PCK
RESET
Block Diagram: One Bank 16M x 72 & 32M x 72 DDR-I SDRAM DIMM Module (x8 components)
HYS72D16500GR & HYS72D32500GR on Raw Card L
INFINEON Technologies
5
10.01
HYS 72Dxx5xxGR
Registered DDR-I SDRAM-Modules
VSS
RS0B
RS0A
DQS0
DM0/DQS9
DM
DQS
CS
D0
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D9
DM
DQ0
DQ1
DQ2
DQ3
DQ4
I/O 0
I/O 1
I/O 2
I/O 3
DQ5
DQ6
DQ7
DQS1
DQS2
DQS3
DM1/DQS10
DM
DM
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D1
DM
DQS
CS
DQ8
DQ9
DQ10
DQ11
DQ12
I/O 0
I/O 1
I/O 2
I/O 3
DQ13
DQ14
DQ15
D10
DM2/DQS11
DQS
DQS
CS
CS
D2
DM
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
D11
DM3/DQS12
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D3
DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
D12
DQS4
DM4/DQS13
V
EEPROM
D0 - D17
DDSPD
DQS
DM
CS
DM
DQS
CS
D4
I/O 0
I/O 1
I/O 2
I/O 3
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
V
V
DD, DDQ
D13
VREF
D0 - D17
D0 - D17
V
DQS5
DQS6
SS
DM5/DQS14
DQS
CS DM
DQS
CS DM
D5
V
DDID
Strap: see Note 4
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D14
Serial PD
DM6/DQS15
CS DM
D15
DQS
CS DM
D6
DQS
SDA
DQ48
DQ49
DQ50
DQ51
I/O 0
I/O 1
I/O 2
I/O 3
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
SCL
A0
SA0 SA1
A1 A2
SA2
DQS7
DQS8
DM7/DQS16
DM
DM
DM
CS
DQS
DQS
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
D7
D16
Notes:
1. DQ-to-I/O wiring may be changed within a byte.
DM8/DQS17
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
DQS
CS
D8
DM
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
D17
STRAP OUT (OPEN): VDD = VDDQ
5. SDRAM placement alternates between the back
and front of the DIMM.
CS0
RS 0 -> CS : SDRAMs D0-D17
R
E
G
I
S
T
E
R
BA0-BA1
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17
A0-A11,A12
RAS
CAS
RA0-RA11,RA12 -> A0-A11,A12: SDRAMs D0 - D17
RRAS -> RAS : SDRAMs D0 - D17
RCAS -> CAS : SDRAMs D0 - D17
RCKE0A -> CKE: SDRAMs D0 - D8
RCKEB -> CKE: SDRAMs D9 - D17
RWE -> WE: SDRAMs D0 - D17
CKE0
WE
CK0, CK 0 --------- PLL*
* Wire per Clock Loading Table/Wiring Diagrams
PCK
PCK
RESET
Block Diagram: One Bank 32M x 72 and 64M x 72 DDR-I SDRAM DIMM Modules (x4 comp.)
HYS72D32501GR & HYS72D64500GR on Raw Card M
INFINEON Technologies
6
10.01
HYS 72Dxx5xxGR
Registered DDR-I SDRAM-Modules
V
SS
1
RS
0
RS
DQS0
DM0/DQS9
DM
DM
DM
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D0
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D18
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D9
DM
DM
CS
DM
DM
DQ0
DQ4
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
D27
DQS1
DM1/DQS10
DQS
CS
D1
DQS
CS
DQS
CS
DQS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ8
DQ9
DQ10
DQ11
I/O 0
I/O 1
I/O 2
I/O 3
DQ12
DQ13
DQ14
DQ15
D19
D10
D28
DM2/DQS11
DQS2
DQS3
DM
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
CS
CS DM
D2
CS DM
D20
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D11
D29
DM3/DQS12
DM
CS
DM
CS
CS
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D12
D30
D3
D21
DQS4
DM4/DQS13
DQS
DQS
DM
CS
DM
CS
DM
DM
DM
DM
DQS
DQS
CS
CS
DQ32
DQ33
DQ34
DQ35
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
D4
D22
D13
D31
DQS5
DQS6
DM5/DQS14
DQS
DQS
S
S
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS DM
D5
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS DM
D23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D14
D32
DM6/DQS15
CS DM
D15
CS DM
D33
DQS
CS
D6
DQS
CS
DQS
DQS
DM
DM
DM
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
D24
DQS7
DQS8
DM7/DQS16
DM
DM
DM
DM
CS
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D7
DQS
CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQ56
DQ57
DQ58
DQ59
I/O 0
I/O 1
I/O 2
I/O 3
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
D25
D16
D34
DM8/DQS17
DM
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
D8
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
CS
CS
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CB0
CB1
CB2
CB3
I/O 0
I/O 1
I/O 2
I/O 3
CB4
CB5
CB6
CB7
D26
D17
D35
CK0, CK 0 --------- PLL*
Serial PD
A0
V
V
EEPROM
DDSPD
* Wire per Clock Loading Table/Wiring Diagrams
SDA
CS0
RS0 -> CS : SDRAMs D0-D17
SCL
V
DD,
D0 - D35
A1 A2
DDQ
CS1
R
E
G
I
RS1 -> CS : SDRAMs D18 -D35
VREF
D0 - D35
D0 - D35
BA0-BA1
A0-A12
RAS
SA0 SA1 SA2
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D35
RA0-RA12 -> A0-A12: SDRAMs D0 - D35
RRAS -> RAS : SDRAMs D0 - D35
RCAS -> CAS : SDRAMs D0 - D35
RCKE0 -> CKE: SDRAMs D0 - D17
RCKE1 -> CKE: SDRAMs D18 - D35
RWE -> WE: SDRAMs D0 - D35
V
SS
V
DDID
Strap: see Note 4
Notes:
S
T
E
R
CAS
1. DQ-to-I/O wiring may be changed within a byte.
CKE0
CKE1
WE
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, Adress and control resistors: 22 Ohms.
PC
K
PC
RESET
4. VDDID strap connections
K
STRAP OUT (OPEN): VDD = VDDQ
5. SDRAM placement alternates between the back
and front of the DIMM.
Block Diagram: Two Bank 128M x 72 and 256M x 72 DDR-I SDRAM DIMM Modules (x4 comp.)
HYS72D128520GR and HYS72D256520GR on Raw Card (t.b.d.)
INFINEON Technologies
7
10.01
HYS 72Dxx5xxGR
Registered DDR-I SDRAM-Modules
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
min.
– 0.5
– 0.5
-55
–
max.
3.6
3.6
+150
1
Input / Output voltage relative to VSS
Power supply voltage on VDD/VDDQ to VSS
Storage temperature range
VIN, VOUT
VDD, VDDQ
TSTG
V
V
oC
W
mA
Power dissipation (per SDRAM component)
Data out current (short circuit)
PD
IOS
–
50
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
Supply Voltage Levels
Parameter
Symbol
Limit Values
nom.
Unit
Notes
min.
max.
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
Termination Voltage
VDD
2.3
2.5
2.7
V
V
V
V
V
-
VDDQ
VREF
VTT
2.3
2.5
2.7
1)
2)
3)
0.49 x VDDQ
VREF – 0.04
2.3
0.5 x VDDQ
VREF
0.51 x VDDQ
VREF + 0.04
3.6
EEPROM supply voltage
VDDSPD
2.5
1
2
Under all conditions, VDDQ must be less than or equal to VDD
Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC)
VREF is also expected to track noise variations in VDDQ
VTT of the transmitting device must track VREF of the receiving device.
.
.
3
DC Operating Conditions (SSTL_2 Inputs)
(VDDQ = 2.5 V, TA = 70 °C, Voltage Referenced to VSS)
Parameter
Symbol
Limit Values
max.
Unit
Notes
min.
DC Input Logic High
DC Input Logic Low
Input Leakage Current
Output Leakage Current
VIH (DC)
VIL (DC)
IIL
VREF + 0.18
– 0.30
– 5
VDDQ + 0.3
V
1)
–
VREF – 0.18
V
5
5
µA
µA
1)
2)
IOL
– 5
1) The relationship between the VDDQ of the driving device and the VREF of the receiving device is what
determines noise margins. However, in the case of VIH (max) (input overdrive), it is the VDDQ of the receiving
device that is referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but
has no SSTL_2 outputs (such as a translator), and therefore no VDDQ supply voltage connection, inputs must
tolerate input overdrive to 3.0 V (High corner VDDQ + 300 mV).
2) For any pin under test input of 0 V ≤ VIN ≤ VDDQ + 0.3 V. Values are shown per DDR-SDRAM component.
INFINEON Technologies
8
10.01
HYS 72Dxx5xxGR
Registered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (PC1600)
Sym-
bol
Parameter/Condition
Unit Notes
Mb
DRAM Technology:
128
256
512
Operating Current - One bank Active - Precharge;
tRC = tRC MIN; tCK = 10 ns; DQ, DM, and DQS inputs changing
once per clock cycle; address and control inputs changing once
per every two cycles
mA
1,3
IDD0
tbd. tbd. 815 1401 1668 tbd.
Operating Current - One bank Active / Read / Precharge;
Burst = 4; Reads; Refer to the detailed test conditions in the
component datasheet
mA
mA
1,3
1,4
IDD1
tbd. tbd. 899 1552 2022 tbd.
tbd. tbd. 442 578 862 tbd.
Precharge Power-Down Standby Current: all banks idle;
power-down mode; CKE ≤ VIL MAX; tCK = 10 ns
IDD2P
Precharge Floating Standby Current: CS ≥ VIH MIN, all banks
idle; CKE ≥ VIH MIN; tCK = 10 ns, address and other control inputs
changing once per clock cycle,
mA
1,4
IDD2F
tbd. tbd. 573 845 1390 tbd.
VIN = VREF for DQ, DQS and DM.
Precharge Quiet Standby Current: CS ≥ VIH MIN, all banks
idle; CKE ≥ VIH MIN; tCK = 10 ns,address and other control inputs
stable at ≥ VIH MIN or ≤ VIL MAX; VIN = VREF for DQ, DQS and DM.
mA
mA
1,4
1,4
IDD2Q
tbd. tbd. 573 845 1390 tbd.
tbd. tbd. 426 566 824 tbd.
Active Power-Down Standby Current: one bank active;
power-down mode; CKE ≤ VIL MAX; tCK = 10 ns
IDD3P
Active Standby Current: one bank; active / precharge;CS ≥
VIH MIN; CKE ≥ VIH MIN; tRC = tRAS MAX; tCK = 10 ns; DQ, DM, and
DQS inputs changing twice per clock cycle; address and control
inputs changing once per clock cycle
mA
1,4
1,3
IDD3N
IDD4R
IDD4W
tbd. tbd. 712 1152 1645 tbd.
Operating Current - Burst Read: one bank; Burst = 2; reads;
continuous burst; address and control inputs changing once per
clock cycle; DQ and DQS outputs changing twice per clock
cycle; CL = 2; tCK = 10 ns;IOUT = 0mA
tbd. tbd. 1529 2167 2661 tbd. mA
Operating Current - Burst Write: one bank; Burst = 2; writes;
continuous burst; address and control inputs changing once per
clock cycle; DQ and DQS inputs changing twice per clock cycle;
CL = 2; tCK = 10 ns
mA
mA
1,3
1,3
tbd. tbd. 1126 1824 2380 tbd.
Auto-Refresh Current: tRC = tRFC MIN, distributed refresh
IDD5
tbd. tbd. 1299 2350 4647 tbd.
tbd. tbd. 364 417 550 tbd.
Self-Refresh Current with PLL-on:
CKE ≤ 0.2V, PLL on, address and control signals toggling
mA 1,2,4
IDD6
Self-Refresh Current with PLL-off:
1,2,4
1,3
IDD6A
tbd. tbd. tbd. tbd. tbd. tbd. mA
CKE ≤ 0.2V, PLL off, no toggling of address and control signals
Operating Current - Four bank operation; four bank inter-
leaving with BL=4; Refer to the detailed test conditions in the
component datasheet
mA
IDD7
tbd. tbd. 2346 3869 4201 tbd.
1. IDD currents are measured after the device is properly initialized. Typical values are obtained from characterisation data mea-
sured at VDD = 2.5 V and R.T. with an input slew rate = 1V/ns.
2. Enables on-chip refresh and address counters.
3. For two bank modules only : the other bank is in IDD3N mode
4. For two bank modules only : both banks operate in the same current mode
INFINEON Technologies
9
10.01
HYS 72Dxx5xxGR
Registered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (PC2100)
Sym-
bol
Parameter/Condition
Unit Notes
Mb
DRAM Technology:
128
256
512
Operating Current - One bank Active - Precharge;
tRC = tRC MIN; tCK = 7.5 ns; DQ, DM, and DQS inputs changing
once per clock cycle; address and control inputs changing once
per every two cycles
mA
1,3
IDD0
tbd. tbd. tbd. tbd. tbd. tbd.
Operating Current - One bank Active / Read / Precharge;
Burst = 4; Reads; Refer to the detailed test conditions in the
component datasheet
mA
mA
1,3
1,4
IDD1
tbd. tbd. tbd. tbd. tbd. tbd.
tbd. tbd. tbd. tbd. tbd. tbd.
Precharge Power-Down Standby Current: all banks idle;
power-down mode; CKE ≤ VIL MAX; tCK = 7.5 ns
IDD2P
Precharge Floating Standby Current: CS ≥ VIH MIN, all banks
idle; CKE ≥ VIH MIN; tCK = 7.5 ns, address and other control
inputs changing once per clock cycle,
mA
1,4
IDD2F
tbd. tbd. tbd. tbd. tbd. tbd.
VIN = VREF for DQ, DQS and DM.
Precharge Quiet Standby Current: CS ≥ VIH MIN, all banks
idle; CKE ≥ VIH MIN; tCK = 7.5 ns,address and other control inputs
stable at ≥ VIH MIN or ≤ VIL MAX; VIN = VREF for DQ, DQS and DM.
mA
mA
1,4
1,4
IDD2Q
tbd. tbd. tbd. tbd. tbd. tbd.
tbd. tbd. tbd. tbd. tbd. tbd.
Active Power-Down Standby Current: one bank active;
power-down mode; CKE ≤ VIL MAX; tCK = 7.5 ns
IDD3P
Active Standby Current: one bank; active / precharge;CS ≥
VIH MIN; CKE ≥ VIH MIN; tRC = tRAS MAX; tCK = 7.5 ns; DQ, DM, and
DQS inputs changing twice per clock cycle; address and control
inputs changing once per clock cycle
mA
1,4
1,3
IDD3N
IDD4R
IDD4W
tbd. tbd. tbd. tbd. tbd. tbd.
Operating Current - Burst Read: one bank; Burst = 2; reads;
continuous burst; address and control inputs changing once per
clock cycle; DQ and DQS outputs changing twice per clock
cycle; CL = 2; tCK = 7.5 ns;IOUT = 0mA
tbd. tbd. tbd. tbd. tbd. tbd. mA
Operating Current - Burst Write: one bank; Burst = 2; writes;
continuous burst; address and control inputs changing once per
clock cycle; DQ and DQS inputs changing twice per clock cycle;
CL = 2; tCK = 7.5 ns
mA
mA
1,3
1,3
tbd. tbd. tbd. tbd. tbd. tbd.
Auto-Refresh Current: tRC = tRFC MIN, distributed refresh
Self-Refresh Current: CKE ≤ 0.2V
IDD5
IDD6
tbd. tbd. tbd. tbd. tbd. tbd.
tbd. tbd. tbd. tbd. tbd. tbd.
mA 1,2,4
Self-Refresh Current with PLL-off:
1,2,4
1,3
IDD6A
tbd. tbd. tbd. tbd. tbd. tbd. mA
CKE ≤ 0.2V, PLL off, no toggling of address and control signals
Operating Current - Four bank operation; four bank inter-
leaving with BL=4; Refer to the detailed test conditions in the
component datasheet
mA
IDD7
tbd. tbd. tbd. tbd. tbd. tbd.
1. IDD currents are measured after the device is properly initialized. Typical values are obtained from characterisation data mea-
sured at VDD = 2.5 V and R.T. with an input slew rate = 1V/ns.
2. Enables on-chip refresh and address counters.
3. For two bank modules only : the other bank is in IDD3N mode
4. For two bank modules only : both banks operate in the same current mode
INFINEON Technologies
10
10.01
HYS 72Dxx5xxGR
Registered DDR-I SDRAM-Modules
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V)
DDR266A
-7
DDR200
-8
Symbol
tAC
Parameter
Unit Notes
Min
Max
Min
Max
+ 0.8
+ 0.8
0.55
0.55
DQ output access time from CK/CK
− 0.75 + 0.75
− 0.75 + 0.75
− 0.8
− 0.8
0.45
0.45
ns
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
1-4
1-4
tDQSCK DQS output access time from CK/CK
tCH
tCL
CK high-level width
CK low-level width
Clock Half Period
0.45
0.45
0.55
0.55
1-4
1-4
tHP
tCK
tCK
tDH
tDS
tIPW
min (tCL, tCH)
min (tCL, tCH)
1-4
CL = 2.5
CL = 2.0
7
12
12
8
10
12
12
1-4
Clock cycle time
7.5
0.5
0.5
2.2
1.75
1-4
DQ and DM input hold time
DQ and DM input setup time
0.6
1-4
0.6
1-4
Control and Addr. input pulse width (each input)
2.5
1, 10
1-4,11
1-4, 5
1-4, 5
1-4
tDIPW DQ and DM input pulse width (each input)
2
tHZ
tLZ
Data-out high-impedence time from CK/CK
Data-out low-impedence time from CK/CK
− 0.75 + 0.75
− 0.75 + 0.75
− 0.8
− 0.8
0.75
+ 0.8
+ 0.8
1.25
tDQSS Write command to 1st DQS latching transition
0.75
1.25
+ 0.5
DQS-DQ skew
tDQSQ
+ 0.6
ns
1-4
(for DQS & associated DQ signals)
tQHS
tQH
Data hold skew factor
+ 0.75
+ 1.0
ns
ns
tCK
tCK
tCK
ns
ns
tCK
tCK
ns
ns
ns
ns
tCK
tCK
ns
ns
1-4
1-4
Data Output hold time from DQS
tHP-tQHS
0.35
0.2
tHP-tQHS
0.35
0.2
tDQSL,H DQS input low (high) pulse width (write cycle)
1-4
tDSS
tDSH
tMRD
DQS falling edge to CK setup time (write cycle)
DQS falling edge hold time from CK (write cycle)
Mode register set command cycle time
1-4
0.2
0.2
1-4
14
16
1-4
tWPRES Write preamble setup time
tWPST Write postamble
0
0
1-4, 7
1-4, 6
1-4
0.40
0.25
0.9
0.60
0.40
0.25
1.1
0.60
tWPRE Write preamble
fast slew rate
slow slew rate
fast slew rate
slow slew rate
tIS
Address and control input setup time
Address and control input hold time
1.0
1.1
2-4,
10,11
0.9
1.1
tIH
1.0
1.1
tRPRE Read preamble
tRPST Read postamble
0.9
1.1
0.60
0.9
1.1
0.60
1-4
1-4
1-4
1-4
0.40
45
0.40
50
120,000
tRAS
tRC
Active to Precharge command
120,000
Active to Active/Auto-refresh command period
65
70
Auto-refresh to Active/Auto-refresh
command period
tRFC
tRCD
75
20
80
20
ns
ns
1-4
1-4
Active to Read or Write delay
INFINEON Technologies
11
10.01
HYS 72Dxx5xxGR
Registered DDR-I SDRAM-Modules
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V)
DDR266A
-7
DDR200
-8
Symbol
Parameter
Unit Notes
Min
Max
Min
Max
tRP
tRRD
tWR
Precharge command period
20
15
15
20
15
15
ns
ns
ns
1-4
1-4
1-4
Active bank A to Active bank B command
Write recovery time
Auto precharge write recovery
+ precharge time
tDAL
(twr/tck) + (trp/tck)
tCK
1-4,9
tWTR
Internal write to read command delay
1
1
tCK
ns
tCK
1-4
1-4
1-4
tXSNR Exit self-refresh to non-read command
tXSRD Exit self-refresh to read command
75
80
200
200
15.6
7.8
15.6
7.8
µs
µs
1-4, 8
1-4, 8
128Mb based
tREFI
Average Periodic Refresh Interval
256 & 512 Mb based
1. Input slew rate >=1V/ns for DDR266 and = 1V/ns for DDR200.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are >= 1.0 V/ns.
3. Inputs are not recognized as valid until VREF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT
5. HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
.
t
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS
.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
10. These parameters guarantee device timing, but they are not necessarily tested on each device
11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew rate >1.0 V/
ns, measured between VOH(ac) and VOL(ac)
INFINEON Technologies
12
10.01
HYS 72Dxx5xxGR
Registered DDR-I SDRAM-Modules
SPD Codes for PC1600 Modules “-8”
Description
SPD Entry
Value
Hex
Byt
e#
0
Number of SPD Bytes
128
80
08
07
1
2
3
4
5
6
7
8
9
10
Total Bytes in Serial PD
Memory Type
256
DDR-SDRAM
12/13
10/ 11/12
1 / 2
Number of Row Addresses
Number of Column Addresses
Number of DIMM Banks
Module Data Width
0C
0A
01
0C
0B
01
0D
0A
01
0D
0B
01
0D
0B
02
0D
0C
02
72
48
00
04
80
80
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL = 2.5
0
SSTL_2.5
8 ns
SDRAM Access Time from Clock at
CL = 2.5
0.8 ns
11
12
DIMM Config
ECC
02
Refresh Rate/Type
Self-Refresh,
80
80
82
82
82
82
15.6 / 7.8 µs
13
14
15
SDRAM Width, Primary
x4 / x8
08
08
04
04
08
08
04
04
04
04
04
04
Error Checking SDRAM Data Width
x4 / x8
Minimum Clock Delay for Back-to-Back
Random Column Address
tCCD = 1 CLK
01
16
17
18
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
2, 4 & 8
4
0E
04
0C
CAS latency = 2
& 2.5
19
20
21
22
23
24
25
26
27
28
CS Latencies
CS latency = 0
01
02
26
C0
A0
80
00
00
50
3C
WE Latencies
Write latency = 1
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Min. Clock Cycle Time at CAS Latency = 2 10.0 ns
Access Time from Clock for CL = 2
Minimum Clock Cycle Time at CL = 1.5
Access Time from Clock at CL = 1.5
Minimum Row Precharge Time
0.8 ns
not supported
not supported
20 ns
Minimum Row Active to Row Active Delay 15 ns
tRRD
29
30
31
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (per bank)
20 ns
50
32
50 ns
128 / 256 /
512 MByte
20
40
40
80
80
01
32
33
34
35
Addr. and Command Setup Time
Addr. and Command Hold Time
Data Input Setup Time
1.1 ns
1.1 ns
0.6 ns
0.6 ns
B0
B0
60
60
Data Input Hold Time
INFINEON Technologies
13
10.01
HYS 72Dxx5xxGR
Registered DDR-I SDRAM-Modules
Description
SPD Entry
Value
Hex
Byt
e#
36-40 Superset Information
–
00
46
50
41
42
Minimum Core Cycle Time tRC
70 ns
80 ns
Min. Auto Refresh Cmd Cycle Time
tRFC
43
44
45
Maximum Clock Cycle Time tck
Max. DQS-DQ Skew tDDSQ
X-Factor tQHS
12 ns
30
3C
A0
00
00
0.6 ns
1.0 ns
46-61 Superset Information
-
62
63
64
SPD Revision
Revision 0.0
Checksum for Bytes 0 - 62
Manufacturers JEDEC ID Code
–
–
9C
B5
BF
F8
C1
INFINEO(N)
F9
7B
65-71 Manufacturer
72
Module Assembly Location
73-90 Module Part Number
91-92 Module Revision Code
93-94 Module Manufacturing Date
95-98 Module Serial Number
99-
Superset Information
127
128- Open for Customer Use
256
Note: 256MByte one bank *) = HYS72D32501GR (128Mbit based) , one bank **) = HYS72D32/500GR (256Mbit
based)
INFINEON Technologies
14
10.01
HYS 72Dxx5xxGR
Registered DDR-I SDRAM-Modules
SPD Codes for PC2100 Modules “-7”
Description
SPD Entry
Value
Hex
Byt
e#
0
Number of SPD Bytes
Total Bytes in Serial PD
Memory Type
128
80
08
07
1
256
2
DDR-SDRAM
12/13
10/ 11 /12
1 / 2
3
Number of Row Addresses
Number of Column Addresses
Number of DIMM Banks
Module Data Width
0C
0A
01
0C
0B
01
0D
0A
01
0D
0B
01
0D
0B
02
0D
0C
02
4
5
6
72
48
00
04
70
75
02
7
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL = 2.5
Access Time from Clock at CL = 2.5
DIMM Config
0
8
SSTL_2.5
7 ns
9
10
11
12
0.75 ns
ECC
Refresh Rate/Type
Self-Refresh,
80
80
82
82
82
82
15.6 / 7.8 µs
13
14
15
SDRAM Width, Primary
x4 / x8
08
08
04
04
08
08
04
04
04
04
04
04
Error Checking SDRAM Data Width
x4 / x8
Minimum Clock Delay for Back-to-Back
Random Column Address
tCCD = 1 CLK
01
16
17
18
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
2, 4 & 8
4
0E
04
0C
CAS latency = 2
& 2.5
19
20
21
22
23
24
25
26
27
28
CS Latencies
CS latency = 0
01
02
26
C0
75
75
00
00
50
3C
WE Latencies
Write latency = 1
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Min. Clock Cycle Time at CAS Latency = 2 7.5 ns
Access Time from Clock for CL = 2
Minimum Clock Cycle Time at CL = 1.5
Access Time from Clock at CL = 1.5
Minimum Row Precharge Time
0.75 ns
not supported
not supported
20 ns
Minimum Row Active to Row Active Delay 15 ns
tRRD
29
30
31
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (per bank)
20 ns
50
45 ns
2D
128 / 256/
512 MByte
20
40
40
80
80
01
32
33
34
35
Addr. and Command Setup Time
Addr. and Command Hold Time
Data Input Setup Time
0.9 ns
0.9 ns
0.5 ns
0.5 ns
–
90
90
50
50
00
Data Input Hold Time
36-40 Superset Information
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Registered DDR-I SDRAM-Modules
Description
SPD Entry
Value
Hex
Byt
e#
41
Minimum Core Cycle Time tRC
65 ns
75 ns
41
4B
42
Min. Auto Refresh Cmd Cycle Time
tRFC
43
44
45
Maximum Clock Cycle Time tck
Max. DQS-DQ Skew tDDSQ
X-Factor tQHS
12 ns
30
32
75
00
00
0.5 ns
0.75 ns
46-61 Superset Information
-
62
63
64
SPD Revision
Revision 0.0
Checksum for Bytes 0 - 62
Manufacturers JEDEC ID Code
–
–
A7
C0
CA
03
C1
INFINEO(N)
04
86
65-71 Manufacturer
72
Module Assembly Location
73-90 Module Part Number
91-92 Module Revision Code
93-94 Module Manufacturing Date
95-98 Module Serial Number
99-
Superset Information
127
128- Open for Customer Use
256
Note: 256MByte one bank *) = HYS72D32501GR (128Mbit based) , one bank **) = HYS72D32500GR (256Mbit
based)
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Package Outlines Raw Card L
Module Package
DDR-I Registered DIMM Modules 1.2” Low Profile Raw Card L
128MB & 256MB (one physical bank, 9 components)
+ 0.15
-
133.35
4.0 max.
Front View
4.0
Register
Register
53
PLL
92
52
pin 1
2.3 typ.
+ 0.1
-
1.27
64.77
49.53
6.62
Backside View
144
pin 93
145
184
2.5D
3
3
*) on ECC modules only
Detail of Contacts B
6.35
Detail of Contacts A
0.9R
+ 0.05
-
1
1.27
1.8
2.175
L-DIM-184-13 Raw Card L Reg. 1U
note: all outline dimensions and tolerances are in accordance with the JEDEC standard
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Registered DDR-I SDRAM-Modules
Package Outlines Raw Card M
Module Package
DDR-I Registered DIMM Modules 1.2” Low Profile Raw Card M
256MB & 512 MB (one physical bank, 18 components)
+ 0.15
-
133.35
4.0 max.
Front View
4.0
PLL
92
53
52
pin 1
2.3 typ.
1.27+ 0.1
-
64.77
49.53
6.62
Backside View
144
pin 93
145
184
2.5D
Register
3
3
*) on ECC modules only
Detail of Contacts B
6.35
Detail of Contacts A
0.9R
+ 0.05
-
1
1.27
1.8
2.175
L-DIM-184-12 Raw Card M Reg. 1U
note: all outline dimensions and tolerances are in accordance with the JEDEC standard
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Registered DDR-I SDRAM-Modules
Package Outlines Raw Card with stacked components
Module Package
DDR-I Registered DIMM Modules 1.2” Low Profile Raw Card (t.b.d.)
1GB & 2GB(two physical banks, 36 components)
+ 0.15
-
133.35
6.8 max.
Front View
4.0
PLL
92
53
52
pin 1
2.3 typ.
+ 0.1
-
1.27
64.77
49.53
6.62
Backside View
pin 93
144
145
184
2.5D
Register
3
3
*) on ECC modules only
Detail of Contacts B
6.35
Detail of Contacts A
0.9R
+ 0.05
-
1
1.27
1.8
2.175
L-DIM-184-14 Raw Card Reg. 1U
note: all outline dimensions and tolerances are in accordance with the JEDEC standard
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APPLICATION NOTE:
Power Up and Power Management on DDR Registered DIMMs
(according to JEDEC ballot JC-42.5 Item 1173)
184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up
and to minimize power consumption during low power mode. One feature is externally controlled via a system-
generated RESET signal; the second is based on module detection of the input clocks. These enhancements
permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipa-
tions and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-
Locked Loop) when the memory is in Self-Refresh mode.
The new RESET pin controls power dissipation on the module’s registers and ensures that CKE and other
SDRAM inputs are maintained at a valid ‘low’ level during power-up and self refresh. When RESET is at a low
level, all the register outputs are forced to a low level, and all differential register input receivers are powered
down, resulting in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven
from the system as an asynchronous signal according to the attached details. Using this function also permits the
system and DIMM clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs
stay in Self Refresh mode.
The function for RESET is as follows:
Register
Register Inputs
Outputs
RESET
CK
CK
Data in (D)
Data out (Q)
H
H
H
Rising
Rising
L or H
Falling
Falling
L or H
H
L
H
L
X
Qo
Illegal input
conditions
H
High Z
High Z
X
L
X or Hi-Z
X or Hi-Z
X or Hi-Z
L
X : Don’t care, Hi-Z : High Impedance, Qo: Data latched at the previous of CK
risning and CK falling
As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are
maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low
maintains a high impedance state on the SDRAM DQ, DQS and DM outputs — where they will remain until acti-
vated by a valid ‘read’ cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable.
The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of
20MHz or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operat-
ing frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz
(actual detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are
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made High-Z, and the differential inputs are powered down — resulting in a total PLL current consumption of less
than 1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is
tied inactive on the DIMM.
This application note describes the required and optional system sequences associated with the DDR Regis-
tered DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for
a 2-bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely
control CKE to one physical DIMM bank through the use of the RESET pin.
Power-Up Sequence with RESET — Required
1. The system sets RESET at a valid low level.
This is the preferred default state during power-up. This input condition forces all register outputs to a low
state independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable
low-level at the DDR SDRAMs.
2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR
SDRAMs.
3. Stabilization of Clocks to the SDRAM
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches 20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM
PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When
a stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 µsec prior
to SDRAM operation.
4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM con-
nector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these com-
mands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command (with
CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would be a
‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be consistent
with the state of the register outputs.
5. The system switches RESET to a logic ‘high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs
must remain stable).
6. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows their clock receivers, data input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE
outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time
(t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDEC-
pproved initialization sequence).
Self Refresh Entry (RESET low, clocks powered off) — Optional
Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down
and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking.
Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption
(RESET low deactivates register CK and CK, data input receivers, and data output drivers).
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1. The system applies Self Refresh entry command.
(CKE→Low, CS→Low, RAS → Low, CAS→ Low, WE→ High)
Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares— with the exception of CKE.
2. The system sets RESET at a valid low level.
This input condition forces all register outputs to a low state, independent of the condition on the registerm
inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable low-
level at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation to
a specific clock edge is not required.
3. The system turns off clock inputs to the DIMM. (Optional)
a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock
inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the reg-
ister (t (INACT) ). The deactivate time defines the time in which the clocks and the control and address sig-
nals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM
documentation.
b. The system may release DIMM address and control inputs to High-Z.
This can be done after the RESET deactivate time of the register. The deactivate time defines the time in
which the clocks and the control and the address signals must maintain valid levels after RESET low has
been applied. It is highly recommended that CKE continue to remain low during this operation.
4. The DIMM is in lowest power Self Refresh mode.
Self Refresh Exit (RESET low, clocks powered off) — Optional
1. Stabilization of Clocks to the SDRAM.
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches ~20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM
PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds.
2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM con-
nector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these com-
mands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command (with
CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this would
be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs, to be con-
sistent with the state of the register outputs.
3. The system switches RESET to a logic ‘high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
RESET timing relationship to a specific clock edge is not required (during this period, register inputs must
remain stable).
4. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows the clock receivers, input receivers, and output drivers suffi-
cient time to be turned on and become stable. During this time the system must maintain the valid logic levels
described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE out-
puts to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t
(ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry (RESET low, clocks running) — Optional
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Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh,
this is an alternate operating mode for these DIMMs.
1. System enters Self Refresh entry command.
(CKE→ Low, CS→ Low, RAS→ Low, CAS→ Low, WE→ High)
Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares — with the exception of CKE.
2. The system sets RESET at a valid low level.
This input condition forces all register outputs to a low state, independent of the condition on the data and
clock register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs.
3. The system may release DIMM address and control inputs to High-Z.
This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes
the time in which the clocks and the control and the address signals must maintain valid levels after RESET
low has been applied. It is highly recommended that CKE continue to remain low during the operation.
4. The DIMM is in a low power, Self Refresh mode.
Self Refresh Exit (RESET low, clocks running) — Optional
1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM con-
nector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these com-
mands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command (with
CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this would be a
‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be consistent
with the state of the register outputs.
2. The system switches RESET to a logic ’high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
it does not need to be tied to a particular clock edge (during this period, register inputs must continue to
remain stable).
3. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows the clock receivers, input receivers, and output drivers suffi-
cient time to be turned on and become stable. During this time the system must maintain the valid logic levels
described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE out-
puts in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation
time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to
accept an input signal, is t (ACT ) as specified in the register and DIMM documentation.
4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry/Exit (RESET high, clocks running) — Optional
As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification
explains in detail the method for entering and exiting Self Refresh for this case.
Self Refresh Entry (RESET high, clocks powered off) — Not Permissible
In order to maintain a valid low level on the register output, it is required that either the clocks be running and the
system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the
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sequence defined in this application note. In the case where RESET remains high and the clocks are powered
off, the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown
DIMM state will result.
INFINEON Technologies
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