HYS72D64000GU-8-A_技术文档

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

2.5 V 184-pin Unbuffered DDR-I SDRAM Modules

512 MByte & 1024 MByte Modules

PC1600, PC2100 & PC2700

Preliminary datasheet rev. 0.81

•

184-pin Unbuffered 8-Byte Dual-In-Line

DDR-I SDRAM non-parity and ECC-Modules

for PC and Server main memory applications

•

Auto Refresh (CBR) and Self Refresh

All inputs and outputs SSTL_2 compatible

Serial Presence Detect with E²PROM

•

One bank 64M x 64, 64M x 72 and two bank

128M x 64, 128M × 72 organization

Jedec standard MO-206 form factor:

133.35 mm × 31.75 mm × 4.00 mm max.

JEDEC standard Double Data Rate

Synchronous DRAMs (DDR-I SDRAM)

Single + 2.5 V (± 0.2 V) power supply

•

Jedec standard reference layout

Gold plated contacts

•

Built with 512 Mbit DDR-I SDRAMs organized

as 64Mb x 8 in 66-Lead TSOPII package

Programmable CAS Latency, Burst Length,

and Wrap Sequence (Sequential &

Interleave)

•

Performance:

-6

-7

-8

Unit

Component Speed Grade

Module Speed Grade

DDR333B DDR266A DDR200

PC2700

166

PC2100

143

PC1600

125

f_CK

Clock Frequency (max.) @ CL = 2.5

Clock Frequency (max.) @ CL = 2

MHz

133

100

The HYS64/72D64000GU and HYS64/72D128020GU are industry standard 184-pin 8-byte Dual

in-line Memory Modules (DIMMs) organized as 64M × 64 and 128M × 64 for non-parity and 64M x

72 and 128M x 72 for ECC main memory applications. The memory array is designed with 512Mbit

Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the PC

board. The DIMMs feature serial presence detect based on a serial E²PROM device using the 2-pin

I²C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes

are available to the customer.

INFINEON Technologies

1

2002-09-10 (rev.0.81)

HYS64/72D64000/128x20GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

Ordering Information

Type

Compliance Code

Description

SDRAM

Technology

PC2700 (CL=2.5):

HYS64D128320GU-6-A

HYS72D128320GU-6-A

PC2100 (CL=2):

PC2700-25330-B1

two banks 1024 MB DIMM

512 MBit

two banks 1024 MB ECC-DIMM

HYS64D64000GU-7-A

HYS72D64000GU-7-A

HYS64D128020GU-7-A

HYS72D128020GU-7-A

PC1600 (CL=2):

PC2100-20330-A1

PC2100-20330-B1

one bank 512 MB DIMM

512 MBit

512 Mbit

512 MBit

one bank 512 MB ECC-DIMM

two banks 1024 MB DIMM

two banks 1024 MB ECC-DIMM

HYS64D64000GU-8-A

HYS72D64000GU-8-A

HYS64D128020GU-8-A

HYS72D128020GU-8-A

PC1600-20220-A1

PC1600-20220-B1

one bank 512 MB DIMM

512 MBit

512 Mbit

512 MBit

one bank 512 MB ECC-DIMM

two banks 1024 MB DIMM

two banks 1024 MB ECC-DIMM

Note: All part numbers end with a place code, designating the silicon-die revision. Reference information

available on request. Example: HYS 72D64000GU-8-A, indicating Rev.A dies are used for the SDRAM

components.

The Compliance Code is printed on the module labels and describes the speed sort fe. “PC2100”, the

latencies (f.e. “20330” means CAS latency = 2, trcd latency = 3 and trp latency =3 ) and the Raw Card

used for this module.

INFINEON Technologies

2

2002-09-10 (rev.0.81)

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

Pin Definitions and Functions

A0 - A12

Address Inputs

S0, S1

Chip Selects

BA0, BA1

DQ0 - DQ63

CB0 - CB7

RAS

Bank Selects

V_DD

Power (+ 2.5 V)

Data Input/Output

V_SS

Ground

Check Bits (x72 organization only)

Row Address Strobe

Column Address Strobe

Read/Write Input

V_DDQ

V_DDID

V_REF

I/O Driver power supply

VDD Indentification flag

I/O reference supply

Serial EEPROM power supply

Serial bus clock

CAS

WE

V_DDSPD

SCL

CKE0 - CKE1

DQS0 - DQS8

CLK0 - CLK2,

CLK0 - CLK2

Clock Enable

SDRAM low data strobes

SDRAM clock (positive lines)

SDRAM clock (negative lines)

SDA

SA0 - SA2

NC

Serial bus data line

slave address select

no connect

DM0 - DM8

DQS9 - DQS17

SDRAM low data mask/

high data strobes

note: S1 and CKE1 are used on two bank modules only

Address Format

Density Organization

Memory SDRAMs

Banks

# of

# of row/bank/

Refresh Period Interval

SDRAMs columns bits

512 MB 64M x 64

512 MB 64M x 72

1024 MB 128M × 64

1024 MB 128M × 72

1

2

64M x 8

8

13/2/11

8k

64 ms 7.8 µs

9

16

18

INFINEON Technologies

3

2002-09-10 (rev.0.81)

HYS64/72D64000/128x20GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

Pin Configuration

Frontside

Backside

PIN#

1

Symbol

VREF

DQ0

PIN#

48

Symbol

A0

PIN#

93

Symbol

VSS

PIN#

140

141

142

143

144

Symbol

NC / DM8/DQS17

A10

2

49

NC / CB2

VSS

94

DQ4

3

VSS

50

95

DQ5

NC / CB6

VDDQ

NC / CB7

KEY

4

DQ1

51

NC / CB3

BA1

96

VDDQ

DM0/DQS9

DQ6

5

DQS0

DQ2

52

97

6

KEY

98

7

VDD

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

99

DQ7

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

VSS

8

DQ3

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

VSS

DQ36

9

NC

DQ37

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

NC

VDD

VSS

NC

DM4/DQS13

DQ38

DQ8

VDDQ

DQ12

DQ13

DM1/DQS10

VDD

DQ9

BA0

DQ39

DQS1

VDDQ

CLK1

VSS

DQ35

DQ40

VDDQ

WE

VSS

DQ44

RAS

DQ14

DQ15

CKE1

VDDQ

NC (BA2)

DQ20

NC / A12

VSS

DQ45

DQ41

CAS

VDDQ

S0

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

S1

DQS5

DQ42

DQ43

VDD

DM5/DQS14

VSS

DQ46

DQ47

NC

DQ21

A11

NC

DQ48

DQ49

VSS

VDDQ

DQ52

A9

DM2/DQS11

VDD

DQ18

A7

DQ53

CLK2

VDDQ

DQS6

DQ50

DQ51

VSS

DQ22

A8

NC (A13)

VDD

VDDQ

DQ19

A5

DQ23

VSS

DM6/DQS15

DQ54

DQ24

VSS

A6

DQ55

DQ28

DQ29

VDDQ

DM3/DQS12

A3

VDDQ

NC

DQ25

DQS3

A4

VDDID

DQ56

DQ57

VDD

DQ60

DQ61

VDD

VSS

DQ26

DQ27

A2

DQ30

VSS

DM7/DQS16

DQ62

DQS7

DQ58

DQ59

VSS

DQ31

NC / CB4

NC / CB5

VDDQ

CK0

DQ63

VSS

VDDQ

SA0

A1

NC / CB0

NC / CB1

VDD

NC

SA1

SDA

SA2

SCL

CK0

VDDSPD

NC / DQS8

VSS

Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“no-connects”) on x64 organised non-ECC

modules.

INFINEON Technologies

4

2002-09-10 (rev.0.81)

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

S0

DQS0

DQS4

DM4/DQS13

DM0/DQS9

CS

D4

DM

I/O 7

DQS

DM

I/O 7

CS

D0

DQ32

DQ33

DQ34

DQ35

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ36

DQ37

DQ38

DQ39

DQS5

DQS1

DM5/DQS14

DM1/DQS10

CS DQS

D5

DM

DQS

CS

D1

DM

DQ40

DQ41

DQ42

DQ43

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ8

DQ9

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ44

DQ45

DQ46

DQ47

I/O 3

I/O 2

DQS6

DM6/DQS15

DQS2

DM2/DQS11

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

CS

D6

CS DQS

D2

DM

I/O 7

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS3

DM3/DQS12

DQS7

DM7/DQS16

DQS

DM

I/O 7

CS

D7

DM

CS DQS

D3

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ24

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

* Clock Wiring

Clock

Input

SDRAMs

Serial PD

2 SDRAMs

3 SDRAMs

*CK0/CK0

*CK1/CK1

*CK2/CK2

SDA

SCL

A0

SA0

A1

A2

* Wire per Clock Loading

Table/Wiring Diagrams

SA1

SA2

BA0 - BA1

BA0, BA1: SDRAMs D0

- D7

Notes:

A0 - A11,A12: SDRAMs D0 - D7

A0 -A11, A12

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

4. VDDID strap connections

RAS

RAS: SDRAMs D0 - D7

V

DD, DDQ

D0 - D7

CAS

CKE0

WE

CAS: SDRAMs D0 - D7

CKE: SDRAMs D0 - D7

VREF

V

SS

: SDRAMs D0 - D7

WE

DDID

(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

Block Diagram: One Bank 64M x 64 DDR-I SDRAM DIMM Module

HYS64D64000GU using x8 organized SDRAMs

INFINEON Technologies

5

2002-09-10 (rev.0.81)

HYS64/72D64000/128x20GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

S1

S0

DQS4

DM4/DQS13

DQS0

DM0/DQS9

CS

D4

CS

DM

I/O 7

DQS

DM

I/O 0

DQS

CS

D0

DM

CS DQS

D8

DM

I/O 7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ0

DQ1

DQ2

DQ3

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

D12

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ4

DQ5

DQ6

DQ7

DQS5

DQS1

DM5/DQS14

DM1/DQS10

CS

DM

CS

D5

DQS

CS

D1

CS DQS

D9

DM

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ40

DQ41

DQ42

DQ43

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

D13

DQ44

DQ45

DQ46

DQ47

I/O 4

I/O 5

I/O 3

I/O 2

DQS6

DM6/DQS15

DQS2

DM2/DQS11

DM

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

CS

D6

DQS

CS DQS

D14

CS DQS

D2

DM

I/O 0

CS DQS

D10

DM

I/O 7

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ16

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS7

DM7/DQS16

DQS3

DM3/DQS12

DM

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DM

DQS

CS

D7

DM

CS DQS

D3

DM

CS

DQS

DQ56

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ24

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

D15

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

D11

* Clock Wiring

Clock

Input

SDRAMs

BA0, BA1: SDRAMs D0, D15

A0 - A12: SDRAMs D0 - D15

BA0, BA1

A0 - A12

Serial PD

A1

4 SDRAMs

6 SDRAMs

*CK0/CK0

*CK1/CK1

*CK2/CK2

SDA

V

DD, DDQ

D0 - D15

SCL

A0

SA0

A2

VREF

* Wire per Clock Loading

Table/Wiring Diagrams

SA1

SA2

V

SS

D0 - D15

V

DDID

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.

CKE1

RAS

CKE: SDRAMs D8 - D15

RAS: SDRAMs D0 - D15

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

4. VDDID strap connections

(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

CAS

CKE0

WE

CAS: SDRAMs D0 - D15

CKE: SDRAMs D0 - D7

WE: SDRAMs D0 - D15

Block Diagram: Two Bank 128M x 64 DDR-I SDRAM DIMM Modules

HYS64D128020GU using x8 Organized SDRAMs

INFINEON Technologies

6

2002-09-10 (rev.0.81)

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

S0

DQS0

DQS4

DM4/DQS13

DM0/DQS9

DM

I/O 7

DQS

CS

D0

CS

D4

DM

I/O 7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS5

DQS1

DM5/DQS14

DM1/DQS10

CS

D5

DM

DQS

CS

D1

DM

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

DQ14

DQ15

I/O 3

I/O 2

DQS6

DM6/DQS15

DQS2

DM2/DQS11

DM

I/O 7

CS DQS

D6

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CS DQS

D2

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ16

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS3

DM3/DQS12

DQS7

DM7/DQS16

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

CS

D3

CS

D7

DQS

DM

DQ56

DQ57

DQ58

DQ59

DQ24

I/O 7

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ60

DQ61

DQ62

DQ63

DQS8

DM8/DQS17

Serial PD

A1

DM

DQS

CS

D8

CB0

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CB1

CB2

CB3

CB4

CB5

CB6

CB7

SDA

SCL

A0

SA0

A2

SA2

SA1

BA0, BA1: SDRAMs D0

- D8

BA0, BA1

* Clock Wiring

A0 - A11,A12

A0 - A11, A12: SDRAMs D0 - D8

Clock

Input

SDRAMs

RAS

RAS: SDRAMs D0 - D8

V

DD, DDQ

D0 - D8

3 SDRAMs

*CK0/CK0

*CK1/CK1

*CK2/CK2

CAS

CAS: SDRAMs D0 - D8

CKE: SDRAMs D0 - D8

VREF

CKE0

V

SS

WE

WE: SDRAMs D0 - D8

* Wire per Clock Loading

Table/Wiring Diagrams

V

DDID

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

4. VDDID strap connections

(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

Block Diagram: One Bank 64M x 72 DDR-I SDRAM DIMM Module

HYS72D64000GU using x8 organized SDRAMs

INFINEON Technologies

7

2002-09-10 (rev.0.81)

HYS64/72D64000/128x20GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

S1

S0

DQS4

DM4/DQS13

DQS0

DM0/DQS9

DM

I/O 0

DM

I/O 7

CS DQS

D4

CS DQS

D13

DQS

CS

D0

CS

D9

DM

DQS

DM

I/O 7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ0

DQ1

DQ2

DQ3

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ4

DQ5

DQ6

DQ7

DQS5

DM5/DQS14

DQS1

DM1/DQS10

CS

DM

CS

DM

DQS

CS

DQS

DM

CS

D1

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ40

DQ41

DQ42

DQ43

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

DQ8

DQ9

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

D5

D14

D10

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ44

DQ45

DQ46

DQ47

I/O 4

I/O 5

I/O 3

I/O 2

DQS6

DM6/DQS15

DQS2

DM2/DQS11

CS

D6

CS

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

DM

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQS

DM

I/O 0

DQS

DM

I/O 7

CS

D2

CS

DQ48

DQ49

DQ50

DQ51

DQ16

D15

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

D11

DQ52

DQ53

DQ54

DQ55

DQS7

DQS3

DM3/DQS12

DM7/DQS16

CS

D7

DM

I/O 0

CS

DQS

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

DM

CS

D3

CS

DQ56

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ24

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

D16

DQ25

DQ26

DQ27

D12

DQ28

DQ29

DQ30

DQ31

DQS8

DM8/DQS17

CS

DM

CS

D8

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

D17

* Clock Wiring

Clock

Input

SDRAMs

BA0, BA1

A0 - A12

BA0, BA1: SDRAMs D0 - D17

A0 - A12: SDRAMs D0 - D17

Serial PD

A1

6 SDRAMs

*CK0/CK0

*CK1/CK1

*CK2/CK2

SDA

SCL

A0

SA0

A2

V

DD,

DDQ

D0 - D17

* Wire per Clock Loading

Table/Wiring Diagrams

VREF

SA1

SA2

V

SS

D0 - D17

Notes:

V

DDID

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.

CKE1

RAS

CKE: SDRAMs D9 - D17

RAS: SDRAMs D0 - D17

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

4. VDDID strap connections

(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

CAS

CKE0

WE

CAS: SDRAMs D0 - D17

CKE: SDRAMs D0 - D8

WE: SDRAMs D0 - D17

Block Diagram: Two Bank 128M x 72 DDR-I SDRAM DIMM Modules

HYS72D128020GU using x8 Organized SDRAMs

INFINEON Technologies

8

2002-09-10 (rev.0.81)

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

Clock Net Wiring

4 DRAM Loads

6 DRAM Loads

DRAM 1

DR AM 1

DRAM2

DRAM3

DRAM2

R = 120

CK

R =

120

Cap.

DIMM

Connector

DR AM4

DR AM5

Cap.

CK

DRAM5

DR AM6

DRAM6

DRAM 1

2 DRAM Loads

3 DRAM Loads

DRAM 1

Cap.

R =120

DIMM

Connector

DRAM3

DIMM

Connector

Cap.

DR AM5

Cap.

Absolute Maximum Ratings

Parameter

Symbol

Limit Values

Unit

min.

max.

3.6

+150

1

Input / Output voltage relative to V_SS

Power supply voltage on V_DD/V_DDQto V_SS

Storage temperature range

V_IN,V_OUT– 0.5

V_DD,V_DDQ– 0.5

V

T_STG

P_D

-55

–

^oC

W

mA

Power dissipation (per SDRAM component)

Data out current (short circuit)

I_OS

–

50

Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.

Functional operation should be restricted to recommended operation conditions.

Exposure to higher than recommended voltage for extended periods of time affect device reliability

INFINEON Technologies

9

2002-09-10 (rev.0.81)

HYS64/72D64000/128x20GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

Supply Voltage Levels

Parameter

Symbol

Limit Values

nom.

Unit

Notes

min.

max.

Device Supply Voltage

Output Supply Voltage

Input Reference Voltage

Termination Voltage

V_DD

2.3

2.5

2.7

V

–

1)

V_DDQ

V_REF

V_TT

2.3

2.5

2.7

2)

3)

0.49 x V_DDQ

V_REF– 0.04

2.3

0.5 x V_DDQ

V_REF

0.51 x V_DDQ

V_REF+ 0.04

3.6

EEPROM supply voltage

V_DDSPD

2.5

1)

Under all conditions, V_DDQmust be less than or equal to V_DD

.

2)

Peak to peak AC noise on V_REFmay not exceed ± 2% V_{REF (DC)}. V_REFis also expected to track noise variations

in V_DDQ

V_TTof the transmitting device must track V_REFof the receiving device.

.

3)

DC Operating Conditions (SSTL_2 Inputs)

(V_DDQ= 2.5 V, T_A= 70 °C, Voltage Referenced to V_SS

)

Parameter

Symbol

Limit Values

max.

Unit

Notes

min.

1)

DC Input Logic High

DC Input Logic Low

Input Leakage Current

Output Leakage Current

V_{IH (DC)}

V_{IL (DC)}

I_IL

V_REF+ 0.15

– 0.30

– 5

V_DDQ+ 0.3

V

V_REF– 0.15

V

–

2)

5

µA

2)

I_OL

– 5

1)

The relationship between the V_DDQof the driving device and the V_REFof the receiving device is what determines

noise margins. However, in the case of V_{IH (max)}(input overdrive), it is the V_DDQof the receiving device that is

referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but has no SSTL_2

outputs (such as a translator), and therefore no V_DDQsupply voltage connection, inputs must tolerate input

overdrive to 3.0 V (High corner V_DDQ+ 300 mV).

2)

For any pin under test input of 0 V ≤ V_IN≤ V_DDQ+ 0.3 V. Values are shown per DDR-SDRAM component.

INFINEON Technologies

10

2002-09-10 (rev.0.81)

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

Operating, Standby and Refresh Currents (PC1600)

512MB

x64

1bank

-8

512MB

x72

1bank

-8

1GB

x64

2bank

-8

1GB

x72

2bank

-8

Notes

Symbol

Parameter/Condition

Unit

mA

4

1

MAX

: one bank; active / precharge; tRC = tRC MIN; tCK =

Operating Current

IDD0

tCK MIN; DQ, DM, and DQS inputs changing once per clock cycle;

1280

1440

1680

1890

address and control inputs changing once every two clock cycles

: one bank; active/read/precharge; Burst = 4;

Operating Current

IDD1

1360

96

1530

108

1760

192

1980

216

mA

1, 3

2

Refer to the following page for detailed test conditions.

: all banks idle; power-down

Precharge Power-Down Standby Current

IDD2P

mode; CKE <= VIL MAX; tCK = tCK MIN

: /CS >= VIH MIN, all banks idle;

Precharge Floating Standby Current

CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs

changing once per clock cycle, VIN = VREF for DQ, DQS and DM.

320

360

640

720

IDD2F

IDD2Q

mA

2

: /CS >= VIH MIN, all banks idle;

Precharge Quiet Standby Current

CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs

stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM.

200

128

225

144

400

256

450

288

mA

2

: one bank active; power-down

Active Power-Down Standby Current

IDD3P mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and

DM.

: one bank active; active / precharge;CS >= VIH

Active Standby Current

MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and

DQS inputs changing twice per clock cycle; address and control inputs

changing once per clock cycle

IDD3N

IDD4R

IDD4W

400

450

800

900

mA

2

: one bank active; Burst = 2; reads; continuous burst;

Operating Current

address and control inputs changing once per clock cycle; 50% of data

outputs changing on every clock edge; CL = 2 for DDR200, and

DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA

1320

1280

1485

1440

1720

1680

1935

1890

1, 3

: one bank active; Burst = 2; writes; continuous burst;

Operating Current

address and control inputs changing once per clock cycle; 50% of data

outputs changing on every clock edge; CL = 2 for DDR200, and

DDR266A, CL=3 for DDR333; tCK = tCK MIN

1

: tRC = tRFC MIN, distributed refresh

Auto-Refresh Current

2320

40

2610

45

2720

80

3060

90

IDD5

IDD6

mA

: CKE <= 0.2V; external clock on; tCK = tCK MIN

Self-Refresh Current

: four bank; four bank interleaving with BL=4;

Refer to the following page for detailed test conditions.

Operating Current

IDD7

2800

3150

3200

3600

mA

1, 3

1. The module IDD values are calculated from the component IDD datasheet values as:

n * IDDx[component]

for single bank modules (n: number of components per module bank)

n * IDDx[component] + n * IDD3N[component]

for two bank modules (n: number of components per module bank)

2. The module IDD values are calculated from the component IDD datasheet values as:

n * IDDx[component]

2 * n * IDDx[component]

for single bank modules (n: number of components per module bank)

for two bank modules (n: number of components per module bank)

3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions

4. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C

INFINEON Technologies

11

2002-09-10 (rev.0.81)

HYS64/72D64000/128x20GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

Operating, Standby and Refresh Currents (PC2100 and PC2700)

512MB 512MB 1GB

x64 x72 x64

1bank 1bank 2bank 2bank 2bank 2bank

-7 -7 -6 -6 -7 -7

MAX MAX MAX MAX MAX MAX

1GB

x72

1GB

x64

1GB

x72

Notes

Symbol

Parameter/Condition

Unit

mA

4

1

: one bank; active / precharge; tRC = tRC MIN; tCK =

Operating Current

IDD0

tCK MIN; DQ, DM, and DQS inputs changing once per clock cycle;

1360

1530

2200

2475

1920

2160

address and control inputs changing once every two clock cycles

: one bank; active/read/precharge; Burst = 4;

Operating Current

IDD1

1440

112

1620

126

2320

288

2610

324

2000

224

2250

252

mA

1, 3

2

Refer to the following page for detailed test conditions.

: all banks idle; power-down

Precharge Power-Down Standby Current

IDD2P

mode; CKE <= VIL MAX; tCK = tCK MIN

: /CS >= VIH MIN, all banks idle;

Precharge Floating Standby Current

CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs

changing once per clock cycle, VIN = VREF for DQ, DQS and DM.

400

450

960

1080

800

900

IDD2F

IDD2Q

mA

2

: /CS >= VIH MIN, all banks idle;

Precharge Quiet Standby Current

CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs

stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM.

224

144

252

162

640

368

720

414

448

288

504

324

mA

2

: one bank active; power-down

Active Power-Down Standby Current

IDD3P mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and

DM.

: one bank active; active / precharge;CS >= VIH

Active Standby Current

MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and

DQS inputs changing twice per clock cycle; address and control inputs

changing once per clock cycle

IDD3N

IDD4R

IDD4W

560

630

1200

2560

2480

1350

2880

2790

1120

2160

2120

1260

2430

2385

mA

2

: one bank active; Burst = 2; reads; continuous burst;

Operating Current

address and control inputs changing once per clock cycle; 50% of data

outputs changing on every clock edge; CL = 2 for DDR200, and

DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA

1600

1560

1800

1755

1, 3

: one bank active; Burst = 2; writes; continuous burst;

Operating Current

address and control inputs changing once per clock cycle; 50% of data

outputs changing on every clock edge; CL = 2 for DDR200, and

DDR266A, CL=3 for DDR333; tCK = tCK MIN

1

: tRC = tRFC MIN, distributed refresh

Auto-Refresh Current

2480

40

2790

45

3280

80

3690

90

3040

80

3420

90

IDD5

IDD6

mA

: CKE <= 0.2V; external clock on; tCK = tCK MIN

Self-Refresh Current

: four bank; four bank interleaving with BL=4;

Refer to the following page for detailed test conditions.

Operating Current

IDD7

3040

3420

3840

4320

3600

4050

mA

1, 3

1. The module IDD values are calculated from the component IDD datasheet values as:

n * IDDx[component]

for single bank modules (n: number of components per module bank)

n * IDDx[component] + n * IDD3N[component]

for two bank modules (n: number of components per module bank)

2. The module IDD values are calculated from the component IDD datasheet values as:

n * IDDx[component]

2 * n * IDDx[component]

for single bank modules (n: number of components per module bank)

for two bank modules (n: number of components per module bank)

3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions

4. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C

INFINEON Technologies

12

2002-09-10 (rev.0.81)

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

Electrical Characteristics & AC Timing for DDR-I components

(for reference only)

(0 °C ≤ T_A≤ 70 °C; V_DDQ= 2.5V ± 0.2V; V_DD= 2.5V ± 0.2V)

DDR333

-6

DDR266A

-7

DDR200

-8

Symbol

t_AC

Parameter

Unit Notes

Min

− 0.7

0.45

Max

+ 0.7

0.55

Min

Max

Min

Max

+ 0.8

0.55

DQ output access time from CK/CK

− 0.75 + 0.75

− 0.8

0.45

ns

t_CK

ns

1-4

t_DQSCKDQS output access time from CK/CK

t_CH

t_CL

t_HP

t_CK

t_DH

t_DS

CK high-level width

CK low-level width

Clock Half Period

0.45

0.55

min (t_CL,t_CH)

CL = 2.5

CL = 2.0

6

12

7

12

8

12

Clock cycle time

7.5

0.5

10

0.6

DQ and DM input hold time

DQ and DM input setup time

0.45

–

Control and Addr. input pulse width (each

input)

t_IPW

2.2

2.5

2

ns

1, 10

1-4,

11

t_DIPWDQ and DM input pulse width (each input)

1.75

t_HZ

t_LZ

Data-out high-impedence time from CK/CK

Data-out low-impedence time from CK/CK

− 0.7

0.75

+ 0.7

1.25

− 0.75 + 0.75

− 0.8

0.75

+ 0.8

1.25

ns

t_CK

1-4, 5

1-4

t_DQSSWrite command to 1st DQS latching transition

0.75

1.25

+ 0.5

DQS-DQ skew

t_DQSQ

+ 0.4

+ 0.6

ns

1-4

(for DQS & associated DQ signals)

t_QHS

t_QH

Data hold skew factor

+ 0.55

t_HP-t_QHS

0.35

–

+ 0.75

+ 1.0

ns

t_CK

1-4

Data Output hold time from DQS

t_HP-t_QHS

0.35

t_HP-t_QHS

0.35

t_DQSL,HDQS input low (high) pulse width (write cycle)

DQS falling edge to CK setup time (write

t_DSS

0.2

t_CK

1-4

cycle)

DQS falling edge hold time from CK (write

cycle)

t_DSH

t_MRDMode register set command cycle time

t_WPRESWrite preamble setup time

t_WPSTWrite postamble

12

0

14

0

16

0

ns

t_CK

ns

t_CK

ns

1-4

1-4, 7

1-4, 6

1-4

0.40

0.25

0.75

0.60

0.40

0.25

0.9

1.0

0.9

1.0

0.9

0.40

45

0.60

0.40

0.25

1.1

0.9

0.40

50

0.60

t_WPREWrite preamble

fast slew rate

Address and control

t_IS

input setup time

slow slew rate

2-4,

10,11

fast slew rate

0.75

Address and control

t_IH

input hold time

slow slew rate

t_RPRERead preamble

t_RPSTRead postamble

0.9

0.40

42

1.1

0.60

1.1

0.60

1-4

t_RAS

t_RC

Active to Precharge command

120,000

Active to Active/Auto-refresh command period

60

65

70

INFINEON Technologies

13

2002-09-10 (rev.0.81)

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

Electrical Characteristics & AC Timing for DDR-I components

(for reference only)

(0 °C ≤ T_A≤ 70 °C; V_DDQ= 2.5V ± 0.2V; V_DD= 2.5V ± 0.2V)

DDR333

-6

DDR266A

-7

DDR200

-8

Symbol

Parameter

Unit Notes

Min

72

Max

Min

Max

Min

Max

Auto-refresh to Active/Auto-refresh

command period

t_RFC

75

80

ns

1-4

t_RCD

t_RP

t_RRD

t_WR

Active to Read or Write delay

Precharge command period

Active bank A to Active bank B command

Write recovery time

18

12

15

20

15

20

15

ns

1-4

(twr/tck)

+ (trp/

tck)

(twr/tck)

+ (trp/

tck)

Auto precharge write recovery

+ precharge time

t_DAL

t_CK

1-4,9

t_WTRInternal write to read command delay

t_XSNRExit self-refresh to non-read command

t_XSRDExit self-refresh to read command

Average Periodic

1

t_CK

ns

t_CK

1-4

75

80

200

t_REFI

7.8

µs

1-4, 8

512 Mbit based

Refresh Interval

1. Input slew rate >=1V/ns for DDR266 and = 1V/ns for DDR200.

2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference

level for signals other than CK/CK, is V_REF.CK/CK slew rate are >= 1.0 V/ns.

3. Inputs are not recognized as valid until V_REFstabilizes.

4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V_TT

5. _HZand t_LZtransitions occur in the same access time windows as valid data transitions. These parameters are not referred

to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

.

t

6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but

system performance (bus turnaround) degrades accordingly.

7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.

A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were

previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,

DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t_DQSS

.

8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.

9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock

cycle time.

10. These parameters guarantee device timing, but they are not necessarily tested on each device

11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew rate >1.0 V/

ns, measured between VOH(ac) and VOL(ac)

INFINEON Technologies

14

2002-09-10 (rev.0.81)

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

SPD Codes for PC1600 Modules “-8”

512MB

x64

1bank

-8

512MB

x72

1bank

-8

1GB

x64

2bank

-8

1GB

x72

2bank

-8

Byte#

Description

HEX

80

HEX

80

HEX

80

HEX

80

0

1

Number of SPD Bytes

128

Total Bytes in Serial PD

Memory Type

256

08

2

DDR-SDRAM

07

3

Number of Row Addresses

Number of Column Addresses

Number of DIMM Banks

13

0D

0B

0D

0B

0D

0B

02

0D

0B

02

4

11

5

1 / 2

01

6

Module Data Width

x64 / x72

40

48

40

48

7

Module Data Width (cont’d)

Module Interface Levels

0

SSTL_2.5

8 ns

00

8

04

9

SDRAM Cycle Time at CL = 2.5

Access Time from Clock at CL = 2.5

DIMM Config

80

10

11

12

13

14

0.8 ns

80

non-ECC / ECC

Self-Refresh, 7.8 ms

x8

00

02

00

02

Refresh Rate/Type

82

SDRAM Width, Primary

08

Error Checking SDRAM Data Width

Minimum Clock Delay for Back-to-Back

Random Column Address

Burst Length Supported

na / x8

00

08

00

08

15

tccd = 1 CLK

01

16

17

2, 4 & 8

0E

04

0E

04

0E

04

0E

04

Number of SDRAM Banks

Supported CAS Latencies

CS Latencies

4

18

CAS latency = 2 & 2.5

0C

01

0C

01

0C

01

0C

01

19

CS latency = 0

20

WE Latencies

Write latency = 1

02

21

SDRAM DIMM Module Attributes

SDRAM Device Attributes: General

Min. Clock Cycle Time at CAS Latency = 2

Access Time from Clock for CL = 2

Minimum Clock Cycle Time at CL = 1.5

Access Time from Clock at CL = 1.5

Minimum Row Precharge Time

Minimum Row Act. to Row Act. Delay tRRD

Minimum RAS to CAS Delay tRCD

Minimum RAS Pulse Width tRAS

Module Bank Density (per bank)

Addr. and Command Setup Time

Addr. and Command Hold Time

Data Input Setup Time

unbuffered

20

22

–

C0

A0

C0

A0

C0

A0

C0

A0

23

10.0 ns

24

0.8 ns

80

25

not supported

00

26

not supported

00

27

20 ns

50

28

15 ns

3C

50

3C

50

3C

50

3C

50

29

20 ns

30

50 ns

32

31

512MByte

80

32

1.1 ns

B0

33

1.1 ns

B0

34

0.6 ns

60

35

Data Input Hold Time

0.6 ns

60

36-40

41

Superset Information

–

00

Minimum Core Cycle Time tRC

Min. Auto Refresh Cmd Cycle Time tRFC

Maximum Clock Cycle Time tck

Max. DQS-DQ Skew tDQSQ

X-Factor tQHS

70 ns

46

42

80 ns

50

43

12 ns

30

44

0.6 ns

3C

A0

3C

A0

3C

A0

3C

A0

45

1.0 ns

46-61

62

Superset Information

-

00

SPD Revision

Revision 0.0

00

63

Checksum for Bytes 0 - 62

Manufacturers JEDEC ID Code

Manufacturer

–

E8

FA

C1

INFINEON

E9

FB

C1

INFINEON

64

C1

INFINEON

C1

INFINEON

65-71

72

Module Assembly Location

Module Part Number

73-90

91-92

93-94

95-98

99-127

Module Revision Code

Module Manufacturing Date

Module Serial Number

–

128-255

open for Customer use

–

INFINEON Technologies

15

2002-09-10 (rev.0.81)

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

SPD Codes for PC2100 & PC2700 Modules “-7” & “-6”

512MB

x72

1bank

-7

1GB

x64

2bank

-7

1GB

x72

2bank

-7

1GB

x64

2bank

-6

1GB

x72

2bank

-6

x64

1bank

-7

Byte#

Description

HEX

80

HEX

80

HEX

80

HEX

80

HEX

80

HEX

80

0

1

Number of SPD Bytes

128

Total Bytes in Serial PD

Memory Type

256

08

2

DDR-SDRAM

07

3

Number of Row Addresses

Number of Column Addresses

Number of DIMM Banks

13

0D

0B

01

0D

0B

0D

0B

02

0D

0B

02

0D

0B

0D

0B

02

4

11

5

1 / 2

x64 / x72

0

01

02

6

Module Data Width

40

48

40

48

40

48

7

Module Data Width (cont’d)

Module Interface Levels

00

8

SSTL_2.5

7 ns

04

9

SDRAM Cycle Time at CL = 2.5

Access Time from Clock at CL = 2.5

DIMM Config

70

60

10

11

12

13

14

0.75 ns

75

70

non-ECC / ECC

Self-Refresh, 7.8 ms

x8

00

02

00

02

00

02

Refresh Rate/Type

82

SDRAM Width, Primary

08

Error Checking SDRAM Data Width

Minimum Clock Delay for Back-to-Back

Random Column Address

Burst Length Supported

na / x8

00

08

00

08

00

08

15

tccd = 1 CLK

01

16

17

2, 4 & 8

0E

04

0E

04

0E

04

0E

04

0E

04

0E

04

Number of SDRAM Banks

Supported CAS Latencies

CS Latencies

4

CAS latency = 2 & 2.5

CS latency = 0

Write latency = 1

unbuffered

–

18

0C

01

0C

01

0C

01

0C

01

0C

01

0C

01

19

20

WE Latencies

02

21

SDRAM DIMM Module Attributes

SDRAM Device Attributes: General

Min. Clock Cycle Time at CAS Latency = 2

Access Time from Clock for CL = 2

Minimum Clock Cycle Time at CL = 1.5

Access Time from Clock at CL = 1.5

Minimum Row Precharge Time

Minimum Row Act. to Row Act. Delay tRRD

Minimum RAS to CAS Delay tRCD

Minimum RAS Pulse Width tRAS

Module Bank Density (per bank)

Addr. and Command Setup Time

Addr. and Command Hold Time

Data Input Setup Time

20

22

C0

75

C0

75

C0

75

C0

75

C0

75

C0

75

23

7.5 ns

24

0.75 ns

not supported

20 ns

75

70

25

00

26

00

27

50

48

28

15 ns

3C

50

3C

50

3C

50

3C

50

30

29

20 ns

48

30

45 ns

2D

80

2D

80

2D

80

2D

80

2A

80

2A

80

31

512MByte

0.9 ns

32

90

75

33

0.9 ns

90

75

34

0.5 ns

50

45

35

Data Input Hold Time

0.5 ns

50

45

36-40

41

Superset Information

–

00

Minimum Core Cycle Time tRC

Min. Auto Refresh Cmd Cycle Time tRFC

Maximum Clock Cycle Time tck

Max. DQS-DQ Skew tDQSQ

X-Factor tQHS

65 ns

41

3C

48

3C

48

42

75 ns

4B

30

4B

30

4B

30

4B

30

43

12 ns

30

44

0.5 ns

32

2D

55

2D

55

45

0.75 ns

–

75

46-61

62

Superset Information

00

SPD Revision

Revision 0.0

–

00

63

Checksum for Bytes 0 - 62

Manufacturers JEDEC ID Code

F3

05

F4

06

42

54

64

–

C1

INFI-

NEON

C1

INFI-

NEON

C1

INFI-

NEON

C1

INFI-

NEON

C1

INFI-

NEON

C1

INFI-

NEON

65-71

Manufacturer

–

72

Module Assembly Location

Module Part Number

Module Revision Code

Module Manufacturing Date

Module Serial Number

–

73-90

91-92

93-94

95-98

99-127

128-255

open for Customer use

–

INFINEON Technologies

16

2002-09-10 (rev.0.81)

HYS64/72D64000/128020GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

Package Outlines -Raw Card A1 (One Bank Modules)

DDR-SDRAM DIMM Module Package

+ 0.15

-

133.35

4.0 max.

Front View

4.0

*)

53

92

52

pin 1

+ 0.1

-

1.27

64.77

49.53

2.3 typ.

6.62

Backside View

144

pin 93

145

184

2.5D

3

*) on ECC modules only

Detail of Contacts B

6.35

Detail of Contacts A

0.9R

+ 0.05

-

1

1.27

1.8

2.175

L-DIM-184-

29

INFINEON Technologies

17

2002-09-10 (rev.0.81)

HYS64/72D64000/128x20GU-7/8-A

Unbuffered DDR-I SDRAM-Modules

Package Outlines - Raw Card B1 (Two Bank Modules)

DDR-SDRAM DIMM Module Package

two bank modules

+ 0.15

-

133.35

4.0 max.

Front View

4.0

*)

92

53

52

pin 1

+ 0.1

-

1.27

64.77

49.53

2.3 typ.

6.62

Backside View

144

pin 93

145

184

2.5D

*)

3

*) on ECC modules only

Detail of Contacts A

Detail of Contacts B

6.35

0.9R

+ 0.05

-

1

1.27

1.8

2.175

L-DIM-184-

9d

INFINEON Technologies

18

2002-09-10 (rev.0.81)


型号：	HYS72D64000GU-8-A
厂家：	Infineon
描述：	2.5 V 184-pin Unbuffered DDR-I SDRAM Modules 2.5 V 184针无缓冲DDR- SDRAM我模块光电二极管动态存储器双倍数据速率时钟
文件：	总18页 (文件大小：288K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HYS72D64000GU-8-A [INFINEON]

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