IBM25PPC405GP3EE266CZ [ETC]
MICROPROCESSOR|32-BIT|CMOS|BGA|413PIN|PLASTIC ;
| 型号： | IBM25PPC405GP3EE266CZ |
| 厂家： | 
ETC |
| 描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|413PIN|PLASTIC 外围集成电路 时钟 |
| 文件： | 总58页 (文件大小：1218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PowerPC 405GP Embedded Processor Data Sheet
Features
• IBM PowerPC 405 32-bit RISC processor core
to 66MHz)
operating up to 266MHz
- Synchronous or asynchronous PCI Bus
interface
• PC-133 synchronous DRAM (SDRAM) interface
- 32-bit interface for non-ECC applications
- Use internal or external PCI Bus Arbiter
• Ethernet 10/100Mbps (full-duplex) support with
media independent interface (MII)
- 40-bit interface serves 32 bits of data plus 8
check bits for ECC applications
• Programmable interrupt controller supports
seven external and 19 internal edge triggered or
level-sensitive interrupts
• 4KB on-chip memory (OCM)
• External peripheral bus
- Flash ROM/Boot ROM interface
• Programmable timers
- Direct support for 8-, 16-, or 32-bit SRAM
and external peripherals
• Two serial ports (16550 compatible UART)
• One IIC interface
- Up to eight devices
• General purpose I/O (GPIO) available
• Supports JTAG for board level testing
- External Mastering supported
• DMA support for external peripherals, internal
UART and memory
• Internal processor local Bus (PLB) runs at
SDRAM interface frequency
- Scatter-gather chaining supported
- Four channels
• Supports PowerPC processor boot from PCI
memory
• PCI Revision 2.2 compliant interface (32-bit, up
Description
Designed specifically to address embedded
applications, the PowerPC 405GP (PPC405GP)
provides a high-performance, low-power solution
that interfaces to a wide range of peripherals by
incorporating on-chip power management features
and lower power dissipation requirements.
support, serial ports, IIC interface, and general
purpose I/O.
Technology: IBM CMOS SA-12E, 0.25 µm
(0.18 µm Leff)
Package: 456-ball (35mm or 27mm), or 413-ball
(25mm) enhanced plastic ball grid array (E-PBGA)
This chip contains a high-performance RISC
processor core, SDRAM controller, PCI bus
interface, Ethernet interface, control for external
ROM and peripherals, DMA with scatter-gather
Power (typical): 1.5W at 200MHz, 2W at 266MHz
While the information contained herein is believed to be accurate, such information is preliminary, and should not be
relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
1
PowerPC 405GP Embedded Processor Data Sheet
Contents
Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Address Map Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
On-Chip Memory (OCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PLB to PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
10/100 Mbps Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Tables
System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Signals Listed by Ball Assignment—413-Ball Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Signals Listed by Ball Assignment—456-Ball Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
I/O Specifications—All speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
I/O Specifications—200MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . . . . . 53
I/O Specifications—266MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . . . . . 54
PPC405GP Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2
PowerPC 405GP Embedded Processor Data Sheet
Figures
PPC405GP Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
25mm, 413-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
27mm, 456-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
35mm, 456-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5V-Tolerant Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3
PowerPC 405GP Embedded Processor Data Sheet
Ordering, PVR, and JTAG Information
Processor
Rev
Level
1
Product Name
Package
PVR Value
JTAG ID
Order Part Number
Frequency
200MHz
200MHz
200MHz
200MHz
200MHz
200MHz
266MHz
266MHz
266MHz
266MHz
266MHz
266MHz
PPC405GP IBM25PPC405GP-3BE200C
PPC405GP IBM25PPC405GP3BE200CZ
PPC405GP IBM25PPC405GP-3DE200C
PPC405GP IBM25PPC405GP-3DE200CZ
PPC405GP IBM25PPC405GP-3EE200C
PPC405GP IBM25PPC405GP-3EE200CZ
PPC405GP IBM25PPC405GP-3BE266C
PPC405GP IBM25PPC405GP-3BE266CZ
PPC405GP IBM25PPC405GP-3DE266C
PPC405GP IBM25PPC405GP-3DE266CZ
PPC405GP IBM25PPC405GP-3EE266C
PPC405GP IBM25PPC405GP-3EE266CZ
35mm, 456 E-PBGA
35mm, 456 E-PBGA
27mm, 456 E-PBGA
27mm, 456 E-PBGA
25mm, 413 E-PBGA
25mm, 413 E-PBGA
35mm, 456 E-PBGA
35mm, 456 E-PBGA
27mm, 456 E-PBGA
27mm, 456 E-PBGA
25mm, 413 E-PBGA
25mm, 413 E-PBGA
E
E
E
E
E
E
E
E
E
E
E
E
0x40110145
0x40110145
0x40110145
0x40110145
0x40110145
0x40110145
0x40110145
0x40110145
0x40110145
0x40110145
0x40110145
0x40110145
0x42050049
0x42050049
0x42050049
0x42050049
0x42050049
0x42050049
0x42050049
0x42050049
0x42050049
0x42050049
0x42050049
0x42050049
Note 1: Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray.
This section provides the part number nomenclature. For availability, contact your local IBM sales office.
The part number contains a part modifier. Included in the modifier is a revision code. This refers to the die
mask revision number and is specified in the part numbering scheme for identification purposes only.
The PVR (Processor Version Register) is software accessible and contains additional information about the
revision level of the part. Refer to the PowerPC 405GP Embedded Processor User’s Manual for details on the
register content.
Order Part Number Key
IBM25PPC405GP-3BE200Cx
Shipping Package
Blank = Tray
Z
= Tape and reel
Operational Case Temperature
Range
IBM Part Number
Grade 3 Reliability
(-40°C to +85°C)
Processor Speed
200MHz
266MHz
Revision Level
Package
B: 35mm, 456 E-PBGA
D: 27mm, 456 E-PBGA
E: 25mm, 413 E-PBGA
4
PowerPC 405GP Embedded Processor Data Sheet
PPC405GP Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
OCM
SRAM
Power
Mgmt
DCRs
Timers
MMU
DOCM
IOCM
OCM
Control
PPC405
Processor Core
GPIO
IIC
UART
UART
DCR Bus
Trace
ICU
JTAG
DCU
16KB
I-Cache
8KB
D-Cache
On-chip Peripheral Bus (OPB)
OPB
Arb
DMA
Controller
(4-Channel)
MAL
Ethernet
Bridge
Arb
Processor Local Bus (PLB)
Code
Decompression
(CodePack)
External
Bus
Controller
External
SDRAM
Controller
Bus Master
PCI Bridge
Controller
66 MHz max (async)
33 MHz max (sync)
MII
13-bit addr
32-bit data
32-bit addr
32-bit data
The PPC405GP is designed using the IBM Microelectronics Blue LogicTM methodology in which major
functional blocks are integrated together to create an application-specific ASIC product. This approach
provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture.
5
PowerPC 405GP Embedded Processor Data Sheet
Address Map Support
The PPC405GP incorporates two simple and separate address maps. The first address map defines the
possible use of address regions that the processor can access. The second address map is for Device
Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC405GP processor
through the use of mtdcr and mfdcr instructions.
System Memory Address Map 4GB System Memory
Function
Subfunction
Start Address
0x00000000
0xE8010000
0xEC000000
0xEEE00000
0xEF500000
0xEF900000
0xFFE00000
End Address
0xE7FFFFFF
0xE87FFFFF
0xEEBFFFFF
0xEF3FFFFF
0xEF5FFFFF
0xFFFFFFFF
0xFFFFFFFF
Size
3712MB
8MB
SDRAM, External Peripherals, and PCI
Memory
44MB
6MB
General Use
Note: Any of the address ranges listed at
right may be use for any of the above
functions.
1MB
263MB
2MB
1
Peripheral Bus Boot
Boot-up
PCI
2
0xFFFE0000
0xFFFFFFFF
128KB
PCI Boot
PCI I/O
0xE8000000
0xE8800000
0xEEC00000
0xEED00000
0xEF400000
0xEF600300
0xEF600400
0xEF600500
0xEF600600
0xEF600700
0xEF600800
0xE800FFFF
0xEBFFFFFF
0xEEC00007
0xEED00003
0xEF40003F
0xEF600307
0xEF600407
0xEF60051F
0xEF60063F
0xEF60077F
0xEF6008FF
64KB
56MB
8B
PCI I/O
Configuration Registers
Interrupt Acknowledge and Special Cycle
Local Configuration Registers
UART0
4B
64B
8B
UART1
8B
IIC0
32B
64B
128B
256B
Internal Peripherals
OPB Arbiter
GPIO Controller Registers
Ethernet Controller Registers
Notes:
1. When peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above.
2. If PCI boot is selected, a PLB-to-PCI mapping is automatically configured at reset to the address range listed above.
3. After the boot process, software may reassign the boot memory regions for other uses.
4. All address ranges not listed above are reserved.
6
PowerPC 405GP Embedded Processor Data Sheet
DCR Address Map 4KB Device Configuration Registers
Function
Start Address
End Address
Size
1
1
0x000
0x3FF
1KW (4KB)
Total DCR Address Space
By function:
Reserved
0x000
0x010
0x012
0x014
0x016
0x018
0x020
0x080
0x090
0x0A0
0x0A8
0x0B0
0x0B8
0x0C0
0x0D0
0x100
0x140
0x180
0x200
0x00F
0x011
0x013
0x015
0x017
0x01F
0x07F
0x08F
0x09F
0x0A7
0x0AF
0x0B7
0x0BF
0x0CF
0x0FF
0x13F
0x17F
0x1FF
0x3FF
16W
2W
Memory Controller Registers
External Bus Controller Registers
Decompression Controller Registers
Reserved
2W
2W
2W
On-Chip Memory Controller Registers
Reserved
8W
96W
16W
16W
8W
PLB Registers
Reserved
OPB Bridge Out Registers
Reserved
6W
Clock, Control, and Reset
Power Management
Interrupt Controller
Reserved
8W
8W
16W
48W
64W
64W
128W
512W
DMA Controller Registers
Reserved
Ethernet MAL Registers
Reserved
Notes:
1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single
32-bit (word) register, or 1 kiloword (KW) (which equals 4 KB).
7
PowerPC 405GP Embedded Processor Data Sheet
On-Chip Memory (OCM)
The OCM feature comprises a memory controller and a one-port 4KB static RAM (SRAM) accessed by the
processor core.
Features include:
• Low-latency access to critical instructions and data
• Performance identical to cache hits without misses
• Contents change only under program control
PLB to PCI Interface
The PLB to PCI interface core provides a mechanism for connecting PCI devices to the local PowerPC
processor and local memory. This interface is compliant with version 2.2 of the PCI Specification.
Features include:
• Internal PCI bus arbiter for up to six external devices at PCI bus speeds up to 66MHz. Internal arbiter use
is optional and can be disabled for systems which employ an external arbiter.
• PCI bus frequency up to 66MHz
- Synchronous operation at 1/n fractions of PLB speed (n = 1 to 4) to 33MHz maximum
- Asynchronous operation from 1/8 PLB frequency to 66MHz maximum
• 32-bit PCI address/data bus
• Power Management:
- PCI Bus Power Management v1.1 compliant
• Supports 1:1, 2:1, 3:1, 4:1 clock ratios from PLB to PCI
• Buffering between PLB and PCI:
- PCI target 64-byte write post buffer
- PCI target 96-byte read prefetch buffer
- PLB slave 32-byte write post buffer
- PLB slave 64-byte read prefetch buffer
• Error tracking/status
• Supports PCI target side configuration
• Supports processor access to all PCI address spaces:
- Single-byte PCI I/O reads and writes
- PCI memory single-beat and prefetch-burst reads and single-beat writes
- Single-byte PCI configuration reads and writes (type 0 and type 1)
8
PowerPC 405GP Embedded Processor Data Sheet
- PCI interrupt acknowledge
- PCI special cycle
• Supports PCI target access to all PLB address spaces
• Supports PowerPC processor boot from PCI memory
SDRAM Memory Controller
The PPC405GP Memory Controller core provides a low latency access path to SDRAM memory. A variety of
system memory configurations are supported. The memory controller supports up to four physical banks. Up
to 256MB per bank are supported, up to a maximum of 1GB. Memory timings, address and bank sizes, and
memory addressing modes are programmable.
Features include:
• 11x8 to 13x11 addressing for SDRAM (2- and 4-bank)
• 32-bit memory interface support
• Programmable address compare for each bank of memory
• Industry standard 168-pin DIMMS are supported (some configurations)
• 200 MHz PPC405GP supports up to 100 MHz memory with PC-100 support
• 266 MHz PPC405GP supports up to 133 MHz memory with PC-133 support
• 4MB to 256MB per bank
• Programmable address mapping and timing
• Auto refresh
• Page mode accesses with up to 4 open pages
• Power management (self-refresh)
• Error checking and correction (ECC) support
- Standard single-error correct, double-error detect coverage
- Aligned nibble error detect
- Address error logging
External Peripheral Bus Controller (EBC)
• Supports eight banks of ROM, EPROM, SRAM, Flash memory, or slave peripherals
• Up to 66MHz operation
• Burst and non-burst devices
• 8-, 16-, 32-bit byte-addressable data bus width support
9
PowerPC 405GP Embedded Processor Data Sheet
• Latch data on Ready, synchronous or asynchronous
• Programmable 2K clock time-out counter with disable for Ready
• Programmable access timing per device
- 0–255 wait states for non-bursting devices
- 0–31 burst wait states for first access and up to 7 wait states for subsequent accesses
- Programmable CSon, CSoff relative to address
- Programmable OEon, WEon, WEoff (0 to 3 clock cycles) relative to CS
• Programmable address mapping
• Peripheral Device pacing with external “Ready”
• External master interface
- Write posting from external master
- Read prefetching on PLB for external master reads
- Bursting capable from external master
- Allows external master access to all non-EBC PLB slaves
- External master can control EBC slaves for own access and control
DMA Controller
• Supports the following transfers:
- Memory-to-memory transfers
- Buffered peripheral to memory transfers
- Buffered memory to peripheral transfers
• Four channels
• Scatter/gather capability for programming multiple DMA operations
• 8-, 16-, 32-bit peripheral support (OPB and external)
• 32-bit addressing
• Address increment or decrement
• Internal 32-byte data buffering capability
• Supports internal and external peripherals
• Support for memory mapped peripherals
• Support for peripherals running on slower frequency buses
10
PowerPC 405GP Embedded Processor Data Sheet
Serial Interface
• One 8-pin UART and one 4-pin UART interface provided
• Selectable internal or external serial clock to allow a wide range of baud rates
• Register compatibility with NS16550 register set
• Complete status reporting capability
• Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode
• Fully programmable serial-interface characteristics
• Supports DMA using internal DMA engine
IIC Bus Interface
• Compliant with Phillips® Semiconductors I2C Specification, dated 1995
• Operation at 100kHz or 400kHz
• 8-bit data
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Supports fixed VDD IIC interface
• Two independent 4 x 1 byte data buffers
• Twelve memory-mapped, fully programmable configuration registers
• One programmable interrupt request signal
• Provides full management of all IIC bus protocol
• Programmable error recovery
11
PowerPC 405GP Embedded Processor Data Sheet
General Purpose IO (GPIO) Controller
• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus
master accesses
• 23 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO
capabilities acts as a GPIO or is used for another purpose. The 23 GPIOs are multiplexed with:
- 7 of 8 chip selects
- All seven external interrupts
- All nine instruction trace pins
• Each GPIO output is separately programmable to emulate an open-drain driver (i.e., drives to zero, three-
stated if output bit is 1)
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between
the various sources of interrupts and the local PowerPC processor.
Features include:
• Supports seven external and 19 internal interrupts
• Edge triggered or level-sensitive
• Positive or negative active
• Non-critical or critical interrupt to processor core
• Programmable critical interrupt priority ordering
• Programmable critical interrupt vector for faster vector processing
10/100 Mbps Ethernet MAC
• Capable of handling full/half duplex 100Mbps and 10Mbps operation
• Uses the medium independent interface (MII) to the physical layer (PHY not included on chip)
JTAG
• IEEE 1149.1 test access port
• IBM RISCWatch debugger support
• JTAG Boundary Scan Description Language (BSDL)
12
PowerPC 405GP Embedded Processor Data Sheet
25mm, 413-Ball E-PBGA Package
Top View
A1 ball corner
15.7 MAX
C
Note: All dimensions are in mm.
C
0.20
0.25 C
0.35
0.20
C
25.0
Bottom View
22.0
2.223 REF
AC
AA
W
U
1.00
AB
Y
Thermal balls
V
GLOB
TOP
T
R
P
N
25.0
M
K
L
J
H
F
G
E
D
B
C
A
B
1
3
5
7
9 11 13 15 17
19 21 23
0.5 ± 0.1 TYP
8 10
6
12 14
16 18
4
22
20
2
0.539 REF
0.635 SOLDER BALL x 413
M
B
0.30 C A
M
0.10
C
A
13
PowerPC 405GP Embedded Processor Data Sheet
27mm, 456-Ball E-PBGA Package
Ejector Mark
1.80 x 0.10
Top View
Small Radius Corner
Corresponds to
A1 Ball Location
Index Mark
1.10
16.00
24.0 REF
16.00
C
Note: All dimensions are in mm.
0.15 C
0.20
27.0
25.0
0.35
C
Bottom View
AF
AE
AD
AC
AB
AA
Y
1.00
W
V
Thermal Balls
U
T
R
P
27.0
N
L
M
K
H
F
J
G
E
C
A
D
B
B
19 21 23
1
3
5
7
9 11 13 15 17
8 10
25
26
0.45
2.21
6
12 14
16 18
4
22
2
20
24
0.55 ± 0.15 SOLDERBALL x 456
s
s
s
B
0.40 C A
s
0.20
C
A
14
PowerPC 405GP Embedded Processor Data Sheet
35mm, 456-Ball E-PBGA Package
Reserved Area for Ejector Pin Mark x 4 TYP
Top View
Corner Shape is Chamferred or Rounded
Gold Gate Release
Corresponds to
A1 Ball Location
33.5 REF
17.5 TYP
C
Note: All dimensions are in mm.
C
0.20
0.20
A
C
0.25
35.0
0.35
C
31.75
Bottom View
AF
AD
AB
Y
1.27 TYP
AE
AC
AA
W
U
Mold
Compound
V
Thermal Balls
T
R
P
35.0±0.2
N
PCB
Substrate
M
K
L
J
H
G
E
F
D
C
B
A
19 21 23
B
1
3
5
7
9 11 13 15 17
25
26
0.6±0.1
8 10
6
12 14
16 18
4
22
2
20
24
2.49 REF
2.65 max
0.65 ± 0.05 SOLDERBALL x 456
s
s
s
B
0.30 C A
s
0.15
C
15
PowerPC 405GP Embedded Processor Data Sheet
Pin Lists
The PPC405GP embedded controller is available as a 456-ball or a 413-ball E-PBGA package. The 456-ball
package is available in two sizes—35 millimeters and 27 millimeters. The 413-ball package size is 25
millimeters. In this section there are three tables that correlate the external signals to the physical package
pin (ball) on which they appear.
The following table lists all the external signals in alphabetical order and shows the ball number on which the
signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the
alternate signal in brackets. Multiplexed signals appear alphabetically multiple times in the list—once for each
signal name on the ball. The page number listed gives the page in “Signal Functional Description” on page 34
where the signals in the indicated interface group begin.
Signals Listed Alphabetically (Part 1 of 10)
Signal Name
413-Ball 456-Ball
Interface Group
Page
AV
L21
D25 System
39
DD
BA0
BA1
N16
N17
AB24
AC24
SDRAM
36
BankSel0
BankSel1
BankSel2
BankSel3
AC19
AB17
AC17
AB14
AD17
AF17
AE15
AC14
SDRAM
36
[BE0]PCIC0
[BE1]PCIC1
[BE2]PCIC2
[BE3]PCIC3
D16
C22
E23
P23
D19
F24
K24
R26
PCI
34
BusReq
CAS
T1
R3
External Master Peripheral
38
36
R15
AB23 SDRAM
ClkEn0
ClkEn1
AB22
Y20
AB25
SDRAM
AC25
36
DMAAck0
DMAAck1
DMAAck2
DMAAck3
A17
B14
A15
A8
D16
B15
B14
C12
External Slave Peripheral
36
DMAReq0
DMAReq1
DMAReq2
DMAReq3
C13
A16
B9
C16
D14
C11
A7
External Slave Peripheral
SDRAM
36
36
C6
DQM0
DQM1
DQM2
DQM3
U12
AC5
AC2
AA2
AC12
AC10
AC6
AA3
DQMCB
AB13
AC15 SDRAM
36
39
DrvrInh1
DrvrInh2
H17
G17
E24
System
E23
ECC0
ECC1
ECC2
ECC3
ECC4
ECC5
ECC6
ECC7
AA12
AC15
AB12
AC14
AC12
AC10
AC9
AE14
AF15
AF14
AD13
SDRAM
AF13
36
AF12
AE13
AD12
AB11
EMCMDClk
J20
T17
H24 Ethernet
AD26 Ethernet
35
35
EMCMDIO[PHYMDIO]
16
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 2 of 10)
Signal Name
413-Ball 456-Ball
Interface Group
Page
EMCTxD0
F22
K21
J22
R23
J26
L25
L24
P25
EMCTxD1
EMCTxD2
EMCTxD3
Ethernet
35
EMCTxEn
EMCTxErr
J21
K20
K23 Ethernet
K25 Ethernet
35
35
EOT0/TC0
EOT1/TC1
EOT2/TC2
EOT3/TC3
C2
G4
U3
V3
F3
G2
V2
Y1
External Slave Peripheral
36
ExtAck
U4
V4
R2
Y3
Y4
T3
External Master Peripheral
External Master Peripheral
External Master Peripheral
38
38
38
ExtReq
ExtReset
A1
A6
A1
A2
A18
A6
A23
C14
D14
F1
F23
J11
J13
K11-K13
L1
L4
L11-L13
M4
M11-M13
M20
N11-N13
N20
N23
P11-P13
R11
R13
V1
A11
A16
1
A19
A21
A26
B2
B25
B26
C3
C24
D4
D23
E5
E9
E13
E14
E18
E22
F1
Ground
Notes:
1. Reserved on 27mm package. GND on 35mm package.
2. On the 456-ball packages, L11-L16, M11-M16, N11-N16,
P11-P16, R11-R16, and T11-T16 are also thermal balls.
3. On the 413-ball package, J11, J13, K11-K13, L11-L13, M11-N13,
N11-N13, P11-P13, R11, and R13 are also thermal balls.
F26
GND
41
1
H1
V23
Y10
J5
J22
L1
AA10
AC1
AC6
AC18
AC23
L11-L16
L26
M11-M16
N5
N11-N16
N22
P5
P11-P16
P22
R11-R16
T1
T11-T16
T26
V5
V22
1
W26
AA1
AA26
AB5
17
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 3 of 10)
Signal Name
413-Ball 456-Ball
Interface Group
Page
AB9
AB13
AB14
AB18
AB22
AC4
AC23
AD3
AD24
AE1
Ground
Notes:
1. Reserved on 27mm package. GND on 35mm package.
2. On the 456-ball packages, L11-L16, M11-M16, N11-N16,
P11-P16, R11-R16, and T11-T16 are also thermal balls.
3. On the 413-ball package, J11, J13, K11-K13, L11-L13, M11-N13,
N11-N13, P11-P13, R11, and R13 are also thermal balls.
GND
41
AE2
AE25
AF1
AF6
1
AF8
AF11
AF16
AF21
AF25
AF26
Gnt[PCIReq0]
D15
C19 PCI
34
39
GPIO1[TS1E]
GPIO2[TS2E]
GPIO3[TS1O]
GPIO4[TS2O]
GPIO5[TS3]
GPIO6[TS4]
GPIO7[TS5]
GPIO8[TS6]
GPIO9[TrcClk]
A20
C19
A21
AB18
AC4
AB4
AC3
Y6
D18
C20
A22
AF18
AC9 System
AE8
AF5
AC7
AB3
T7
[GPIO10]PerCS1
[GPIO11]PerCS2
[GPIO12]PerCS3
[GPIO13]PerCS4
[GPIO14]PerCS5
[GPIO15]PerCS6
[GPIO16]PerCS7
H11
G8
D5
C7
D10
B6
C4
C5
A4
B9
B10
A9
System
39
39
C10
B11
[GPIO17]IRQ0
[GPIO18]IRQ1
[GPIO19]IRQ2
[GPIO20]IRQ3
[GPIO21]IRQ4
[GPIO22]IRQ5
[GPIO23]IRQ6
U21
Y23
R20
Y22
W21
U20
AA22
V25
V23
W24
W25 System
Y24
Y25
AA24
Halt
AA23
P4
AB26 System
39
38
38
38
38
38
HoldAck
HoldPri
HoldReq
IICSCL
IICSDA
U2
T2
V1
External Master Peripheral
P3
External Master Peripheral
External Master Peripheral
V2
AB3
Y7
AD6 Internal Peripheral
AE7 Internal Peripheral
IRQ0[GPIO17]
IRQ1[GPIO18]
IRQ2[GPIO19]
IRQ3[GPIO20]
IRQ4[GPIO21]
IRQ5[GPIO22]
IRQ6[GPIO23]
U21
Y23
R20
Y22
W21
U20
AA22
V25
V23
W24
W25 Interrupts
Y24
Y25
AA24
39
18
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 4 of 10)
Signal Name
413-Ball 456-Ball
Interface Group
Page
MemAddr0
AA21
AC22
AA20
AB21
AA19
AB20
AC21
Y16
AE22
AC21
AE21
AD21
AF22
AE20
AC19
AE19
AD19
AC18
AF19
AD18
AC17
MemAddr1
MemAddr2
MemAddr3
MemAddr4
MemAddr5
MemAddr6
MemAddr7
MemAddr8
MemAddr9
MemAddr10
MemAddr11
MemAddr12
SDRAM
36
Note: During a CAS cycle MemAddr0 is the least significant bit (lsb) on
this bus.
Y15
AB19
AC20
AA16
AA15
MemClkOut0
MemClkOut1
W20
AB23
AC26
AA23
SDRAM
36
MemData0
MemData1
MemData2
MemData3
MemData4
MemData5
MemData6
MemData7
MemData8
MemData9
MemData10
MemData11
MemData12
MemData13
MemData14
MemData15
MemData16
MemData17
MemData18
MemData19
MemData20
MemData21
MemData22
MemData23
MemData24
MemData25
MemData26
MemData27
MemData28
MemData29
MemData30
MemData31
AC8
AB10
AA11
AC7
AB7
AB9
AB8
AB6
AA9
AA7
Y9
AA6
Y8
AA5
AA4
AB2
Y4
AC13
AE12
AD11
AC11
AF10
AE11
AD10
AF9
AD9
AE9
AD8
AF7
AC8
AD7
AE6
AE5
AE4
AD5
AD4
AC5
AD1
AB2
AA4
AA2
AB1
Y2
SDRAM
36
Note: MemData0 is the most significant bit (msb) on this bus.
T11
U11
R9
M9
AA3
AB1
Y3
W3
Y2
AA1
T4
R4
W2
Y1
W4
W2
W3
V4
W1
V3
T3
19
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 5 of 10)
Signal Name
413-Ball 456-Ball
Interface Group
Page
1
A11
D11
G10
G15
H9
H10
H14
H15
J7
B17
1
C13
E6
E7
E8
E19
E20
E21
F5
F22
G5
J8
J10
J14
J16
J17
K3
K4
K8
K16
L23
N1
G22
H5
H22
1
K2
1
N24
1
P3
Output driver voltage
1
OV
U25
Notes:
41
DD
W5
W22
Y5
1. Reserved on 27mm package. OV on 35mm package.
P8
DD
P16
P20
P21
R7
Y22
AA5
AA22
AB6
AB7
AB8
AB19
AB20
AB21
R8
R10
R14
R16
R17
T9
T10
T14
T15
U9
1
AD14
1
AE10
U14
Y13
AC13
20
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 6 of 10)
Signal Name
413-Ball 456-Ball
Interface Group
Page
PCIAD0
PCIAD1
PCIAD2
PCIAD3
PCIAD4
PCIAD5
PCIAD6
PCIAD7
B17
B15
B16
B18
A19
C15
C17
C18
C20
D19
A22
B22
D20
H13
M15
D21
G22
H22
G23
L22
M21
J23
M22
K23
N22
M16
T23
P22
N21
U22
R22
V22
A17
B16
C17
A18
D17
C18
B18
A20
B21
A23
D21
B22
B23
C22
C26
F25
K26
L23
M25
M23
N25
M26
N26
P24
R24
R23
P23
R25
T24
U26
T25
V26
PCIAD8
PCIAD9
PCIAD10
PCIAD11
PCIAD12
PCIAD13
PCIAD14
PCIAD15
PCIAD16
PCIAD17
PCIAD18
PCIAD19
PCIAD20
PCIAD21
PCIAD22
PCIAD23
PCIAD24
PCIAD25
PCIAD26
PCIAD27
PCIAD28
PCIAD29
PCIAD30
PCIAD31
PCI
34
Note: PCIAD31 is the most significant bit (msb) on this bus.
D16
C22
E23
P23
PCIC0[BE0]
PCIC1[BE1]
PCIC2[BE2]
PCIC3[BE3]
D19
F24
K24
R26
PCI
34
PCIClk
D17
H20
H21
B20 PCI
H25 PCI
34
34
34
PCIDevSel
PCIFrame
J24
PCI
PCIGnt0[Req]
PCIGnt1
PCIGnt2
PCIGnt3
PCIGnt4
W23
U23
B23
D23
K22
H23
U23
T23
F23
H26
N23
M24
PCI
34
PCIGnt5
PCIIDSel
M23
G13
E22
E21
D22
P26 PCI
C23 PCI
34
34
34
34
34
PCIINT[PerWE]
PCIIRDY
J23
PCI
PCIParity
PCIPErr
E26 PCI
G25 PCI
PCIReq0[Gnt]
PCIReq1
PCIReq2
PCIReq3
PCIReq4
PCIReq5
D15
B21
B20
G16
F20
G21
C19
C21
B19
PCI
A24
G23
J25
34
PCIReset
PCISErr
K14
G20
B24 PCI
G24 PCI
34
34
21
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 7 of 10)
Signal Name
413-Ball 456-Ball
Interface Group
Page
34
PCIStop
C23
F21
H23 PCI
PCITRDY
G26 PCI
34
PerAddr0
PerAddr1
PerAddr2
PerAddr3
PerAddr4
PerAddr5
PerAddr6
PerAddr7
PerAddr8
PerAddr9
PerAddr10
PerAddr11
PerAddr12
PerAddr13
PerAddr14
PerAddr15
PerAddr16
PerAddr17
PerAddr18
PerAddr19
PerAddr20
PerAddr21
PerAddr22
PerAddr23
PerAddr24
PerAddr25
PerAddr26
PerAddr27
PerAddr28
PerAddr29
PerAddr30
PerAddr31
G7
J12
C11
C3
A2
C4
B3
D6
C5
B4
D7
A3
D8
D9
B5
A4
C8
C9
D5
A3
B4
B5
D6
B6
C6
D7
A5
B7
C7
D8
B8
C8
D9
External Slave Peripheral
A8
C9
36
Note: PerAddr0 is the most significant bit (msb) on this bus.
D10
C10
A10
D11
B12
D13
D12
B13
A12
A13
C14
A14
A15
C15
D15
A5
B7
B8
A7
B10
B11
C12
A9
B12
A10
A12
A14
B13
G12
PerBLast
PerClk
D3
J9
F2
E4
External Slave Peripheral
External Master Peripheral
36
38
PerCS0
G11
H11
G8
D5
C7
D10
B6
C10
B3
C4
C5
A4
B9
B10
A9
B11
PerCS1[GPIO10]
PerCS2[GPIO11]
PerCS3[GPIO12]
PerCS4[GPIO13]
PerCS5[GPIO14]
PerCS6[GPIO15]
PerCS7[GPIO16]
External Slave Peripheral
36
22
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 8 of 10)
Signal Name
413-Ball 456-Ball
Interface Group
Page
PerData0
PerData1
PerData2
PerData3
PerData4
PerData5
PerData6
PerData7
PerData8
PerData9
PerData10
PerData11
PerData12
PerData13
PerData14
PerData15
PerData16
PerData17
PerData18
PerData19
PerData20
PerData21
PerData22
PerData23
PerData24
PerData25
PerData26
PerData27
PerData28
PerData29
PerData30
PerData31
R3
W1
U2
T2
U1
P2
N2
M3
R1
M2
P1
M1
K1
J1
U4
U3
U1
T4
R2
P4
R4
P2
R1
P1
N3
N1
M1
N2
M3
M4
N4
M2
L3
L4
K1
L2
K3
J1
K4
J3
J2
J4
H3
G1
H2
H4
L2
External Slave Peripheral
M8
H1
K2
L3
G1
G2
J2
H2
F2
E1
J3
G3
D1
J4
36
Note: PerData0 is the most significant bit (msb) on this bus.
F3
D2
H4
PerErr
PerOE
H8
B1
C2
External Master Peripheral
External Slave Peripheral
38
36
K10
PerPar0
PerPar1
PerPar2
PerPar3
L7
F4
E3
C1
D3
G4
G3
E1
External Slave Peripheral
36
PerReady
PerR/W
L8
E3
C1
External Slave Peripheral
External Slave Peripheral
36
36
H7
PerWBE0
PerWBE1
PerWBE2
PerWBE3
D4
B2
B1
E4
D2
E2
F4
D1
External Slave Peripheral
36
[PerWE]PCIINT
PHYCol
G13
Y21
T20
C23 External Slave Peripheral
AA25 Ethernet
W23 Ethernet
AF20 Ethernet
AD26 Ethernet
AE23
36
35
35
35
35
PHYCrS
PHYRxClk
AA18
T17
[PHYMDIO]EMCMDIO
PHYRxD0
PHYRxD1
PHYRxD2
PHYRxD3
AA13
Y19
Y18
Y17
AF23
Ethernet
AC20
35
AD20
PHYRxDV
PHYRxErr
PHYTxClk
R21
T22
C21
V24 Ethernet
U24 Ethernet
E25 Ethernet
35
35
35
23
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 9 of 10)
Signal Name
413-Ball 456-Ball
Interface Group
Page
36
RAS
R12
L17
AF24 SDRAM
RcvrInh
C25 System
U23 PCI
39
[Req]PCIGnt0
W23
34
2
B19
C16
D18
E2
A19
3
B17
3
C13
D20
H3
2
H1
T21
V20
V21
W22
3
Other
K2
3
Notes:
N24
3
1. Y5 (on the 413-ball package) and AF4 must be tied to OV or
GND. All other reserved pins should be left unconnected.
2. Reserved on 27mm package. GND on 35mm package.
P3
DD
1
Reserved
41
Y5
3
2
U25
AA8
AB5
W26
Y23
Y26
3. Reserved on 27mm package. OV on 35mm package.
DD
1
AF4
AF8
2
3
AD14
3
AE10
SysClk
SysErr
SysReset
TCK
H16
P14
J15
U16
U13
T13
E20
L16
U17
T7
A25 System
AD25 System
D22 System
AD22 JTAG
AE24 JTAG
AD23 JTAG
D26 System
D24 System
AC22 JTAG
AB3 System
AE26 JTAG
39
39
39
39
39
39
39
39
39
39
39
TDI
TDO
TestEn
TmrClk
TMS
[TrcClk]GPIO9
TRST
T16
[TS1E]GPIO1
[TS2E]GPIO2
[TS1O]GPIO3
[TS2O]GPIO4
[TS3]GPIO5
[TS4]GPIO6
[TS5]GPIO7
[TS6]GPIO8
A20
C19
A21
AB18
AC4
AB4
AC3
Y6
D18
C20
A22
AF18
Trace
AC9
AE8
AF5
AC7
40
UART0_CTS
U7
AA17
P10
T8
AB4 Internal Peripheral
AE18 Internal Peripheral
AE3 Internal Peripheral
AF2 Internal Peripheral
AD15 Internal Peripheral
AD16 Internal Peripheral
AE16 Internal Peripheral
AF3 Internal Peripheral
AC3 Internal Peripheral
AC3 Internal Peripheral
AD2 Internal Peripheral
38
38
38
38
38
38
38
38
38
38
38
UART0_DCD
UART0_DSR
UART0_DTR
UART0_RI
AC16
AB15
AA14
U8
UART0_RTS
UART0_Rx
UART0_Tx
UART1_CTS/UART1_DSR
UART1_DSR/UART1_CTS
UART1_DTR/UART1_RTS
N8
N8
N7
24
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 10 of 10)
Signal Name
UART1_RTS/UART1_DTR
UART1_Rx
413-Ball 456-Ball
Interface Group
Page
38
N7
W4
N3
AD2 Internal Peripheral
AC1 Internal Peripheral
AC2 Internal Peripheral
AE17 Internal Peripheral
38
UART1_Tx
38
UARTSerClk
Y14
38
A13
D12
D13
K9
K15
L9
L10
L14
L15
L20
M10
M14
N4
E10
E11
E12
E15
E16
E17
K5
K22
L5
L22
M5
M22
R5
V
Logic voltage
41
DD
N9
R22
T5
T22
U5
U22
N10
N14
N15
P9
P15
Y11
Y12
AC11
AB10
AB11
AB12
AB15
AB16
AB17
WE
AB16
AC16 SDRAM
36
25
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed by Ball Assignment—413-Ball Package (Part 1 of 3)
Ball
Signal Name
Ball
B17
B18
Signal Name
Ball
D10
D11
Signal Name
Ball
G13
G15
Signal Name
A1
GND
PCIAD0
PerCS5[GPIO14]
PCIINT[PerWE]
OV
OV
A2
PerAddr4
PCIAD3
DD
DD
V
A3
PerAddr11
B19
Reserved
D12
G16
PCIReq3
DD
V
A4
A5
PerAddr15
PerAddr18
GND
B20
B21
B22
B23
C1
PCIReq2
PCIReq1
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
E1
G17
G20
G21
G22
G23
H1
DrvrInh2
PCISErr
PCIReq5
PCIAD16
PCIAD18
PerData16
PerData22
Reserved
PerData31
PerR/W
DD
GND
PCIReq0[Gnt]
PCIC0[BE0]
PCIClk
A6
PCIAD11
A7
PerAddr21
DMAAck3
PerAddr25
PerAddr27
PCIGnt2
A8
PerPar3
A9
C2
EOT0/TC0
PerAddr3
Reserved
PCIAD9
A10
A11
A12
A13
A14
A15
C3
H2
OV
C4
PerAddr5
PCIAD12
PCIAD15
PCIPErr
H3
DD
PerAddr28
C5
PerAddr8
H4
V
C6
DMAReq3
PerCS4[GPIO13]
PerAddr16
H7
DD
PerAddr29
DMAAck2
C7
PCIGnt3
H
8
PerErr
OV
C8
PerData24
H9
DD
OV
A16
A17
A18
A19
DMAReq1
DMAAck0
GND
C9
PerAddr17
PerCS7[GPIO16]
PerAddr2
E2
E3
Reserved
PerPar2
PerWBE3
TestEn
H10
H11
H13
H14
DD
C10
C11
C12
PerCS1[GPIO10]
PCIAD13
E4
OV
PCIAD4
PerAddr24
E20
DD
OV
A20
A21
A22
A23
B1
GPIO1[TS1E]
GPIO3[TS1O]
PCIAD10
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
D1
DMAReq0
GND
E21
E22
E23
F1
PCIParity
PCIIRDY
PCIC2[BE2]
GND
H15
H16
H17
H20
H21
H22
H23
J1
DD
SysClk
PCIAD5
DrvrInh1
GND
Reserved
PCIAD6
PCIDevSel
PCIFrame
PCIAD17
PCIGnt5
PerWBE2
F2
PerData23
PerData29
PerPar1
B2
PerWBE1
PCIAD7
F3
B3
PerAddr6
GPIO2[TS2E]
PCIAD8
F4
B4
PerAddr9
F20
F21
F22
F23
G1
PCIReq4
PCITRDY
EMCTxD0
GND
PerData13
PerData21
PerData25
PerData28
B5
PerAddr14
PerCS6[GPIO15]
PerAddr19
PerAddr20
PHYTxClk
PCIC1[BE1]
PCIStop
J2
B6
J3
B7
J4
OV
B8
PerData27
PerData19
J7
DD
OV
B9
DMAReq2
PerAddr22
PerAddr23
PerAddr26
PerAddr30
DMAAck1
D2
D3
D4
D5
D6
D7
PerData30
PerBLast
G2
G3
PerData20
PerData26
J8
J9
DD
B10
B11
B12
B13
B14
PerClk
OV
PerWBE0
G4
EOT1/TC1
J10
J11
J12
J13
DD
PerCS3[GPIO12]
PerAddr7
G7
PerAddr0
GND
PerAddr1
GND
G8
PerCS2[GPIO11]
OV
PerAddr10
G10
DD
OV
B15
B16
PCIAD1
PCIAD2
D8
D9
PerAddr12
PerAddr13
G11
G12
PerCS0
J14
J15
DD
PerAddr31
SysReset
26
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed by Ball Assignment—413-Ball Package (Part 2 of 3)
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
OV
V
J16
L20
N22
PCIAD24
T1
BusReq
DD
DD
OV
AV
J17
J20
J21
J22
J23
K1
L21
L22
L23
M1
M2
M3
N23
P1
P2
P3
P4
P8
GND
T2
T3
T4
T7
T8
T9
PerData3
MemData31
MemData27
GPIO9[TrcClk]
UART0_DTR
DD
DD
EMCMDClk
EMCTxEn
EMCTxD2
PCIAD21
PCIAD19
PerData10
PerData5
HoldPri
OV
DD
PerData11
PerData9
PerData7
HoldAck
OV
OV
PerData12
DD
DD
V
OV
K2
K3
PerData17
M4
M8
GND
P9
T10
T11
T13
T14
T15
T16
DD
DD
OV
PerData15
MemData20
P10
P11
P12
P13
P14
UART0_DSR
GND
MemData17
TDO
DD
OV
K4
M9
DD
OV
V
OV
K8
M10
M11
M12
GND
DD
DD
DD
V
OV
K9
GND
GND
GND
DD
DD
K10
PerOE
GND
SysErr
TRST
EMCMDIO
[PHYMDIO]
V
K11
M13
GND
P15
T17
DD
V
OV
K12
K13
K14
K15
GND
GND
M14
M15
M16
M20
P16
P20
P21
P22
T20
T21
T22
T23
PHYCrS
Reserved
PHYRxErr
PCIAD26
DD
DD
OV
PCIAD14
PCIAD25
GND
DD
OV
PCIReset
DD
V
PCIAD27
DD
OV
K16
K20
K21
K22
K23
L1
M21
M22
M23
N1
PCIAD20
PCIAD22
PCIIDSel
P23
R1
R2
R3
R4
R7
PCIC3[BE3]
PerData8
U1
U2
U3
U4
U7
U8
PerData4
PerData2
DD
EMCTxErr
EMCTxD1
PCIGnt4
PCIAD23
GND
ExtReset
EOT2/TC2
ExtAck
OV
PerData0
DD
N2
PerData6
MemData28
UART0_CTS
UART0_Tx
OV
N3
UART1_Tx
DD
V
OV
OV
L2
L3
PerData14
PerData18
N4
N7
R8
R9
U9
DD
DD
DD
UART1_RTS/
UART1_DTR
MemData19
U11
MemData18
UART1_DSR/
UART1_CTS
OV
L4
GND
N8
R10
U12
DQM0
TDI
DD
V
L7
L8
PerPar0
N9
R11
R12
R13
R14
R15
R16
R17
R20
GND
RAS
GND
U13
U14
U16
U17
U20
U21
U22
U23
DD
V
OV
PerReady
N10
N11
N12
N13
N14
N15
N16
DD
DD
V
L9
GND
GND
GND
TCK
TMS
DD
V
OV
L10
L11
L12
L13
L14
DD
DD
GND
GND
GND
CAS
IRQ5[GPIO22]
IRQ0[GPIO17]
PCIAD29
PCIGnt1
V
OV
DD
DD
V
OV
DD
DD
V
BA0
IRQ2[GPIO19]
DD
V
L15
L16
L17
N17
N20
N21
BA1
GND
R21
R22
R23
PHYRxDV
PCIAD30
EMCTxD3
V1
V2
V3
GND
DD
TmrClk
RcvrInh
HoldReq
EOT3/TC3
PCIAD28
27
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed by Ball Assignment—413-Ball Package (Part 3 of 3)
Ball
Signal Name
Ball
Signal Name
MemAddr8
MemAddr7
PHYRxD3
PHYRxD2
PHYRxD1
ClkEn1
Ball
AA19
AA20
AA21
AA22
AA23
AB1
Signal Name
MemAddr4
MemAddr2
MemAddr0
IRQ6[GPIO23]
Halt
Ball
AB23
AC1
Signal Name
MemClkOut1
GND
V4
ExtReq
Y15
V20
V21
V22
V23
W1
W2
W3
W4
W20
W21
W22
W23
Y1
Reserved
Y16
Reserved
Y17
AC2
DQM2
PCIAD31
Y18
AC3
GPIO7[TS5]
GPIO5[TS3]
DQM1
GND
Y19
AC4
PerData1
Y20
MemData22
MemData15
IICSCL
AC5
MemData29
MemData24
UART1_Rx
MemClkOut0
IRQ4[GPIO21]
Reserved
Y21
PHYCol
AB2
AC6
GND
Y22
IRQ3[GPIO20]
IRQ1[GPIO18]
MemData26
DQM3
AB3
AC7
MemData3
MemData0
ECC6
Y23
AB4
GPIO6[TS4]
Reserved
MemData7
MemData4
MemData6
MemData5
MemData1
ECC7
AC8
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AB5
AC9
AB6
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
ECC5
V
MemData21
MemData14
MemData13
MemData11
MemData9
Reserved
AB7
DD
PCIGnt0[Req]
MemData30
MemData25
MemData23
MemData16
Reserved
AB8
ECC4
OV
AB9
DD
Y2
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
ECC3
ECC1
Y3
Y4
ECC2
UART0_RI
BankSel2
GND
Y5
MemData8
GND
DQMCB
Y6
GPIO8[TS6]
IICSDA
BankSel3
UART0_RTS
WE
Y7
MemData2
ECC0
BankSel0
MemAddr10
MemAddr6
MemAddr1
GND
Y8
MemData12
MemData10
GND
Y9
PHYRxD0
UART0_Rx
MemAddr12
BankSel1
GPIO4[TS2O]
MemAddr9
Y10
Y11
V
DD
V
Y12
Y13
Y14
AA16
AA17
AA18
MemAddr11
UART0_DCD
PHYRxClk
AB20
AB21
AB22
MemAddr5
MemAddr3
ClkEn0
DD
OV
DD
UARTSerClk
28
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed by Ball Assignment—456-Ball Package (Part 1 of 3)
Ball
Signal Name
Ball
B14
B15
Signal Name
Ball
Signal Name
Ball
E14
E15
Signal Name
A1
GND
DMAAck2
D1
PerWBE3
GND
V
A2
GND
DMAAck1
D2
PerWBE0
DD
V
A3
A4
A5
A6
A7
PerAddr1
PerCS3[GPIO12]
PerAddr8
B16
B17
B18
B19
B20
PCIAD1
D3
D4
D5
D6
D7
PerPar0
GND
E16
E17
E18
E19
E20
DD
Res – 27/OV – 35
V
DD
DD
PCIAD6
PCIReq2
PCIClk
PerAddr0
PerAddr4
PerAddr7
GND
OV
GND
DD
OV
DMAReq3
DD
OV
A8
PerAddr15
PerCS6[GPIO15]
PerAddr19
GND
B21
B22
B23
B24
B25
B26
C1
PCIAD8
PCIAD11
PCIAD12
PCIReset
GND
D8
PerAddr11
PerAddr14
PerAddr17
PerAddr20
PerAddr23
PerAddr22
DMAReq1
PerAddr31
DMAAck0
PCIAD4
E21
E22
E23
E24
E25
E26
F1
DD
A9
D9
GND
A10
A11
A12
A13
A14
A15
A16
A17
A18
D10
D11
D12
D13
D14
D15
D16
D17
D18
DrvrInh2
DrvrInh1
PHYTxClk
PCIParity
GND
PerAddr25
PerAddr26
PerAddr28
PerAddr29
GND
GND
PerR/W
C2
PerOE
F2
PerBLast
EOT0/TC0
PerWBE2
C3
GND
F3
PCIAD0
C4
PerCS1[GPIO10]
PerCS2[GPIO11]
F4
OV
PCIAD3
C5
GPIO1[TS1E]
F5
DD
OV
A19
A20
A21
A22
A23
A24
A25
Res – 27/GND – 35
PCIAD7
C6
C7
PerAddr6
PerAddr10
PerAddr13
PerAddr16
PerAddr18
DMAReq2
DMAAck3
D19
D20
D21
D22
D23
D24
D25
PCIC0[BE0]
Reserved
PCIAD10
SysReset
GND
F22
F23
F24
F25
F26
G1
DD
PCIGnt2
PCIC1[BE1]
PCIAD15
GND
GND
C8
GPIO3[TS1O]
PCIAD9
C9
C10
C11
C12
PCIReq3
TmrClk
PerData29
EOT1/TC1
AV
SysClk
G2
DD
Res – 27/OV – 35
A26
B1
GND
PerErr
GND
C13
C14
C15
D26
E1
TestEn
PerPar3
PerWBE1
G3
G4
G5
PerPar2
PerPar1
DD
PerAddr27
PerAddr30
OV
B2
E2
DD
OV
B3
B4
B5
B6
PerCS0
PerAddr2
PerAddr3
PerAddr5
C16
C17
C18
C19
DMAReq0
PCIAD2
E3
E4
E5
E6
PerReady
PerClk
GND
G22
G23
G24
G25
DD
PCIReq4
PCISErr
PCIPErr
PCIAD5
OV
PCIReq0[Gnt]
DD
OV
B7
B8
PerAddr9
PerAddr12
C20
C21
C22
C23
C24
C25
C26
GPIO2[TS2E]
PCIReq1
E7
E8
G26
H1
PCITRDY
Res – 27/GND – 35
PerData30
DD
OV
DD
B9
PerCS4[GPIO13]
PerCS5[GPIO14]
PerCS7[GPIO16]
PerAddr21
PCIAD13
PCIINT[PerWE]
GND
E9
GND
H2
V
B10
B11
B12
B13
E10
E11
E12
E13
H3
PerData28
DD
V
H4
PerData31
DD
V
OV
RcvrInh
H5
DD
DD
OV
PerAddr24
PCIAD14
GND
H22
DD
29
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed by Ball Assignment—456-Ball Package (Part 2 of 3)
Ball
H23
H24
H25
H26
J1
Signal Name
Ball
M1
M2
M3
M4
M5
Signal Name
PerData12
PerData17
PerData14
PerData15
Ball
P14
P15
P16
P22
P23
Signal Name
Ball
U1
U2
U3
U4
U5
Signal Name
PerData2
HoldAck
PCIStop
GND
EMCMDClk
PCIDevSel
PCIGnt3
GND
GND
PerData1
PerData0
GND
V
V
PerData23
PCIAD26
DD
DD
V
J2
J3
PerData26
PerData25
PerData27
GND
M11
M12
M13
M14
M15
M16
M22
GND
GND
GND
GND
GND
GND
P24
P25
P26
R1
PCIAD23
EMCTxD3
PCIIDSel
PerData8
PerData4
BusReq
U22
U23
U24
U25
U26
V1
DD
PCIGnt0[Req]
PHYRxErr
J4
Res – 27/OV – 35
J5
DD
J22
J23
J24
GND
R2
PCIAD29
HoldReq
PCIIRDY
PCIFrame
R3
V
R4
PerData6
V2
EOT2/TC2
DD
V
J25
J26
K1
K2
K3
K4
K5
PCIReq5
EMCTxD0
PerData20
M23
M24
M25
M26
N1
PCIAD19
PCIGnt5
R5
V3
V4
MemData31
MemData29
GND
DD
R11
R12
R13
R14
R15
R16
GND
GND
GND
GND
GND
GND
PCIAD18
PCIAD21
PerData11
PerData13
PerData10
V5
Res – 27/OV – 35
V22
V23
V24
V25
GND
DD
PerData22
PerData24
IRQ1[GPIO18]
PHYRxDV
IRQ0[GPIO17]
N2
V
N3
DD
V
V
K22
K23
K24
K25
K26
L1
N4
PerData16
GND
R22
R23
R24
R25
R26
T1
V26
W1
W2
W3
W4
W5
PCIAD31
DD
DD
EMCTxEn
PCIC2[BE2]
EMCTxErr
PCIAD16
GND
N5
PCIAD25
PCIAD24
PCIAD27
PCIC3[BE3]
GND
MemData30
MemData27
MemData28
MemData26
N11
N12
N13
N14
GND
GND
GND
OV
GND
DD
OV
L2
L3
L4
L5
PerData21
PerData18
PerData19
N15
N16
N22
N23
GND
GND
T2
T3
T4
T5
HoldPri
ExtReset
PerData3
W22
W23
W24
W25
DD
PHYCrS
GND
IRQ2[GPIO19]
IRQ3[GPIO20]
V
V
PCIGnt4
DD
DD
Res – 27/OV – 35
L11
L12
L13
L14
L15
L16
GND
GND
GND
GND
GND
GND
N24
N25
N26
P1
T11
T12
T13
T14
T15
T16
GND
GND
GND
GND
GND
GND
W26
Y1
Res – 27/GND – 35
EOT3/TC3
MemData25
ExtAck
DD
PCIAD20
PCIAD22
PerData9
PerData7
Y2
Y3
P2
Y4
ExtReq
Res – 27/OV – 35
OV
P3
Y5
DD
DD
V
V
OV
L22
L23
L24
L25
L26
P4
P5
PerData5
GND
T22
T23
T24
T25
T26
Y22
Y23
Y24
Y25
Y26
DD
DD
DD
PCIAD17
EMCTxD2
EMCTxD1
GND
PCIGnt1
PCIAD28
PCIAD30
GND
Reserved
IRQ4[GPIO21]
IRQ5[GPIO22]
Reserved
P11
P12
P13
GND
GND
GND
30
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed by Ball Assignment—456-Ball Package (Part 3 of 3)
Ball
AA1
AA2
AA3
Signal Name
Ball
AB26
AC1
AC2
Signal Name
Ball
Signal Name
MemData8
MemData6
MemData2
Ball
Signal Name
UART0_DCD
MemAddr7
GND
Halt
AD9
AE18
AE19
AE20
MemData23
DQM3
UART1_Rx
UART1_Tx
AD10
AD11
MemAddr5
UART1_DSR/
UART1_CTS
AA4
AA5
MemData22
AC3
AC4
AD12
AD13
ECC7
ECC3
AE21
AE22
MemAddr2
MemAddr0
OV
GND
DD
OV
Res – 27/OV – 35
AA22
AA23
AA24
AA25
AA26
AB1
AC5
AC6
MemData19
DQM2
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AE23
AE24
AE25
AE26
AF1
PHYRxD0
TDI
DD
DD
MemClkOut1
IRQ6[GPIO23]
PHYCol
UART0_RI
UART0_RTS
BankSel0
MemAddr11
MemAddr8
PHYRxD3
MemAddr3
TCK
AC7
GPIO8[TS6]
MemData12
GPIO5[TS3]
DQM1
GND
AC8
TRST
GND
AC9
GND
MemData24
MemData21
GPIO9[TrcClk]
UART0_CTS
GND
AC10
AC11
AC12
AC13
AC14
AC15
AF2
UART0_DTR
UART0_Tx
Reserved
GPIO7[TS5]
GND
AB2
MemData3
DQM0
AF3
AB3
AF4
AB4
MemData0
BankSel3
DQMCB
AF5
AB5
TDO
AF6
OV
AB6
GND
AF7
MemData11
DD
OV
AB7
AB8
AC16
AC17
WE
AD25
AD26
SysErr
AF8
AF9
Res – 27/GND – 35
MemData7
DD
EMCMDIO
[PHYMDIO]
OV
MemAddr12
DD
AB9
AB10
AB11
GND
AC18
AC19
AC20
MemAddr9
MemAddr6
PHYRxD2
AE1
AE2
AE3
GND
GND
AF10
AF11
AF12
MemData4
GND
V
DD
V
UART0_DSR
ECC5
DD
V
AB12
AB13
AB14
AB15
AC21
AC22
AC23
AC24
MemAddr1
TMS
AE4
AE5
AE6
AE7
MemData16
MemData15
MemData14
IICSDA
AF13
AF14
AF15
AF16
ECC4
ECC2
ECC1
GND
DD
GND
GND
GND
V
BA1
DD
V
AB16
AB17
AB18
AC25
AC26
AD1
ClkEn1
AE8
AE9
GPIO6[TS4]
MemData9
AF17
AF18
AF19
BankSel1
GPIO4[TS2O]
MemAddr10
DD
V
MemClkOut0
MemData20
DD
Res – 27/OV – 35
GND
AE10
DD
UART1_RTS/
UART1_DTR
OV
AB19
AB20
AD2
AD3
AE11
AE12
MemData5
MemData1
AF20
AF21
PHYRxClk
GND
DD
OV
GND
DD
OV
AB21
AB22
AB23
AB24
AB25
AD4
AD5
AD6
AD7
AD8
MemData18
MemData17
IICSCL
AE13
AE14
AE15
AE16
AE17
ECC6
ECC0
AF22
AF23
AF24
AF25
AF26
MemAddr4
PHYRxD1
RAS
DD
GND
CAS
BankSel2
UART0_Rx
UARTSerClk
BA0
MemData13
MemData10
GND
ClkEn0
GND
31
PowerPC 405GP Embedded Processor Data Sheet
Signal List
The table following table provides a summary of the number of package pins associated with each functional
interface group.
Pin Summary
No. of Pins
Group
413-Ball package
456-Ball Package
25 mm
60
35 mm
60
27mm
60
18
71
96
9
PCI
Ethernet
18
18
SDRAM
71
71
External peripheral
External master
Internal peripheral
Interrupts
96
96
9
9
15
15
15
7
7
7
JTAG
5
5
5
System
19
19
19
300
24
Total Signal Pins
300
38
300
32
OV
DD
V
22
26
24
60
36
4
24
56
DD
Gnd
Thermal (and Gnd)
Reserved
15
36
12
16
Total Pins
413
456
456
Multiplexed Pins
In the table “Signal Functional Description” on page 34, each external signal is listed along with a short
description of the signal function. Some signals are multiplexed on the same package pin (ball) so that the pin
can be used for different functions. Multiplexed signals are shown as a default signal with a secondary signal
in square brackets (for example, GPIO1[TS1E]). Active-low signals (for example, RAS) are marked with an
overline.
It is expected that in any single application a particular pin will always be programmed to serve the same
function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise
be possible.
In addition to multiplexing, many pins are also multi-purpose. For example, the EBC peripheral controller
address pins are used as outputs by the PPC405GP to broadcast an address to external slave devices when
the PPC405GP has control of the external bus. When, during the course of normal chip operation, an external
master gains ownership of the external bus, these same pins are used as inputs which are driven by the
external master and received by the EBC in the PPC405GP. In this example, the pins are also bidirectional,
serving as both inputs and outputs.
Intialization Strapping
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs
only during reset and are used for other functions during normal operation (see “Strapping” on page 55). Note
32
PowerPC 405GP Embedded Processor Data Sheet
that the use of these pins for strapping is not considered multiplexing since the strapping function is not
programmable.
Pull-Up and Pull-Down Resistors
Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in
an appropriate state. The recommended pull-up value of 3kΩ to +3.3V (10kΩ to +5V can be used on 5V
tolerant I/Os) and pull-down value of 1kΩ to GND, applies only to individually terminated signals. To prevent
possible damage to the device, I/Os capable of becoming outputs must never be tied together and terminated
through a common resistor.
If your system-level test methodology permits, input-only signals can be connected together and terminated
through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure
that the grouped I/Os reach a valid logic zero or logic one state when accounting for the total input current into
the PPC405GP.
Unused I/Os
Strapping of some pins may be necessary when they are unused. Although the PPC405GP requires only the
pull-up and pull-down terminations as specified in the “Signal Functional Description” on page 34, good
design practice is to terminate all unused inputs or to configure I/Os such that they always drive. If unused,
the peripheral, SDRAM, and PCI buses should be configured and terminated as follows:
• Peripheral interface—PerAddr0:31, PerData0:31, and all of the control signals are driven by default.
Terminate PerReady high and PerError low.
• SDRAM—Program SDRAM0_CFG[EMDULR]=1 and SDRAM0_CFG[DCE]=1. This causes the
PPC405GP to actively drive all of the SDRAM address, data, and control signals.
• PCI—The PCI pull-up requirements given in the Signal Functional Description apply only when the PCI
interface is being used. When the PCI bridge is unused, configure the PCI controller to park on the bus
and actively drive PCIAD31:0, PCIC3:0[BE3:0], and the remaining PCI control signals by doing the
following:
- Strap the PPC405GP to disable the internal PCI arbiter and to operate the PCI interface in
synchronous mode.
- Individually connect PCISErr, PCIPErr, PCITRDY, and PCIStop through 3.3kΩ resistors to +3.3V.
- Terminate PCIReq1:5 to +3.3V.
- Terminate PCIReq0[Gnt] to GND.
External Bus Control Signals
All peripheral bus control signals (PerCS0:7, PerR/W, PerWBE0:3, PerOE, PerWE, PerBLast, HoldAck,
ExtAck) are set to the high-impedance state when ExtReset=0. In addition, as detailed in the PowerPC
405GP Embedded Processor User’s Manual, the peripheral bus controller can be programmed via
EBC0_CFG to float some of these control signals between transactions and/or when an external master
owns the peripheral bus. As a result, a pull-up resistor should be added to those control signals where an
undriven state may affect any devices receiving that particular signal.
The following table lists all of the I/O signals provided by the PPC405GP. Please refer to “Signals Listed
Alphabetically” on page 16 for the pin number to which each signal is assigned.
33
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description (Part 1 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 33.
Signal Name
Description
I/O
Type
Notes
PCI Interface
5V tolerant
3.3V PCI
PCIAD31:0
PCI Address/Data Bus. Multiplexed address and data bus.
PCI bus command and byte enables.
I/O
I/O
5V tolerant
3.3V PCI
PCIC3:0[BE3:0]
PCI parity. Parity is even across PCIAD0:31 and PCIC0:3[BE0:3].
PCIParity is valid one cycle after either an address or data phase.
The PCI device that drove PCIAD0:31 is responsible for driving
PCIParity on the next PCI bus clock.
5V tolerant
3.3V PCI
PCIParity
I/O
PCIFrame is driven by the current PCI bus master to indicate the
beginning and duration of a PCI access.
5V tolerant
3.3V PCI
PCIFrame
PCIIRDY
I/O
I/O
2
2
PCIIRDY is driven by the current PCI bus master. Assertion of
PCIIRDY indicates that the PCI initiator is ready to transfer data.
5V tolerant
3.3V PCI
The target of the current PCI transaction drives PCITRDY.
Assertion of PCITRDY indicates that the PCI target is ready to
transfer data.
5V tolerant
3.3V PCI
PCITRDY
PCIStop
I/O
I/O
I/O
2
2
2
The target of the current PCI transaction can assert PCIStop to
indicate to the requesting PCI master that it wants to end the
current transaction.
5V tolerant
3.3V PCI
PCIDevSel is driven by the target of the current PCI transaction. A
PCI target asserts PCIDevSel when it has decoded an address
and command encoding and claims the transaction.
5V tolerant
3.3V PCI
PCIDevSel
PCIIDSel is used during configuration cycles to select the PCI
slave interface for configuration.
5V tolerant
3.3V PCI
PCIIDSel
PCISErr
I
PCISErr is used for reporting address parity errors or catastrophic
failures detected by a PCI target.
5V tolerant
3.3V PCI
I/O
2
2
PCIPErr is used for reporting data parity errors on PCI
transactions. PCIPErr is driven active by the device receiving
PCIAD0:31, PCIC0:3[BE0:3], and PCIParity, two PCI clocks
following the data in which bad parity is detected.
5V tolerant
3.3V PCI
PCIPErr
I/O
PCIClk is used as the asynchronous PCI clock when in asynch
mode. It is unused when the PCI interface is operated
synchronously with the PLB bus.
5V tolerant
3.3V PCI
PCIClk
I
5V tolerant
3.3V PCI
PCIReset
PCI specific reset.
O
PCI interrupt. Open-drain output (two states; 0 or open circuit)
or
5V tolerant
3.3V PCI
PCIINT[PerWE]
PCIReq0[Gnt]
O
I
Peripheral write enable. Low when any of the four PerWBE0:3
write byte enables are low.
Multipurpose signal, used as PCIReq0 when internal arbiter is
used, and as Gnt when external arbiter is used.
5V tolerant
3.3V PCI
34
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description (Part 2 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 33.
Signal Name
Description
I/O
Type
Notes
5V tolerant
3.3V PCI
PCIReq1:5
Used as PCIReq1:5 input when internal arbiter is used.
I
Gnt0 when internal arbiter is used
or
5V tolerant
3.3V PCI
PCIGnt0[Req]
O
O
Req when external arbiter is used.
5V tolerant
3.3V PCI
PCIGnt1:5
Ethernet Interface
PHYRxD3:0
Used as PCIGnt1:5 output when internal arbiter is used.
Received data. This is a nibble wide bus from the PHY. The data
is synchronous with the PHYRxClk.
5V tolerant
3.3V LVTTL
I
O
I
1
6
1
1
Transmit data. A nibble wide data bus towards the net. The data
is synchronous to the PHYTxClk.
5V tolerant
3.3V LVTTL
EMCTxD3:0
PHYRxErr
PHYRxClk
Receive Error. This signal comes from the PHY and is
synchronous to the PHYRxClk.
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
Receiver Medium clock. This signal is generated by the PHY.
I
Receive Data Valid. Data on the Data Bus is valid when this
signal is activated. Deassertion of this signal indicates end of the
frame reception.
5V tolerant
3.3V LVTTL
PHYRxDV
PHYCrS
I
I
1
1
6
Carrier Sense signal from the PHY. This is an asynchronous
signal.
5V tolerant
3.3V LVTTL
Transmit Error. This signal is generated by the Ethernet
controller, is connected to the PHY and is synchronous with the
PHYTxClk. It informs the PHY that an error was detected.
5V tolerant
3.3V LVTTL
EMCTxErr
O
Transmit Enable. This signal is driven by the EMAC to the PHY.
Data is valid during the active state of this signal. Deassertion of
this signal indicates end of frame transmission. This signal is
synchronous to the PHYTxClk.
5V tolerant
3.3V LVTTL
EMCTxEn
O
6
This clock comes from the PHY and is the Medium Transmit
clock.
5V tolerant
3.3V LVTTL
PHYTxClk
PHYCol
I
I
1
1
5V tolerant
3.3V LVTTL
Collision signal from the PHY. This is an asynchronous signal.
Management Data Clock. The MDClk is sourced to the PHY. This
clock has a period of 400ns, adjustable via
EMAC0_STACR[OPBC]. Management information is transferred
synchronously with respect to this clock.
5V tolerant
3.3V LVTTL
EMCMDClk
O
Management Data Input/Output is a bidirectional signal between
EMCMDIO[PHYMDIO] the Ethernet controller and the PHY. It is used to transfer control
and status information.
5V tolerant
3.3V LVTTL
I/O
1
35
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description (Part 3 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 33.
Signal Name
Description
I/O
I/O
O
Type
Notes
SDRAM Interface
Memory data bus.
Notes:
MemData0:31
MemAddr12:0
3.3V LVTTL
3.3V LVTTL
1. MemData0 is the most significant bit (msb).
2. MemData31 is the least significant bit (lsb).
Memory address bus.
Notes:
1. MemAddr12 is the most significant bit (msb).
2. MemAddr0 is the least significant bit (lsb).
BA1:0
RAS
Bank Address supporting up to 4 internal banks.
Row Address Strobe.
O
O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
CAS
Column Address Strobe.
DQM for byte lane: 0 (MemData0:7),
1 (MemData8:15),
DQM0:3
O
3.3V LVTTL
2 (MemData16:23), and
3 (MemData24:31)
DQMCB
ECC0:7
BankSel0:3
WE
DQM for ECC check bits.
ECC check bits 0:7.
O
I/O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Select up to four external SDRAM banks.
Write Enable.
O
ClkEn0:1
SDRAM Clock Enable.
O
Two copies of an SDRAM clock allows, in some cases, glueless
SDRAM attach without requiring this signal to be repowered by a
PLL or zero-delay buffer.
MemClkOut0:1
O
3.3V LVTTL
External Slave Peripheral Interface
Peripheral data bus used by PPC405GP when not in external
master mode, otherwise used by external master.
5V tolerant
3.3V LVTTL
PerData0:31
I/O
1
Note: PerData0 is the most significant bit (msb) on this bus.
Peripheral address bus used by PPC405GP when not in external
master mode, otherwise used by external master.
5V tolerant
3.3V LVTTL
PerAddr0:31
PerPar0:3
I/O
I/O
1
1
Note: PerAddr0 is the most significant bit (msb) on this bus.
5V tolerant
3.3V LVTTL
Peripheral byte parity signals.
As outputs, these pins can act as byte-enables which are valid for
an entire cycle or as write-byte-enables which are valid for each
byte on each data transfer, allowing partial word transactions. As
outputs, pins are used by either the pripheral controller or the
DMA controller depending upon the type of transfer involved.
Used as inputs when an external bus master owns the external
interface.
5V tolerant
3.3V LVTTL
PerWBE0:3
I/O
1, 7
36
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description (Part 4 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 33.
Signal Name
Description
I/O
Type
Notes
Peripheral write enable. Low when any of the four PerWBE0:3
write byte enables are low.
5V tolerant
3.3V PCI
[PerWE]PCIINT
O
or
PCI interrupt. Open-drain output (two states; 0 or open circuit)
5V tolerant
3.3V LVTTL
PerCS0
Peripheral chip select bank 0.
O
7
Seven additional peripheral chip selects
or
5V tolerant
3.3V LVTTL
PerCS1:7[GPIO10:16]
O[I/O]
1, 7
General Purpose I/O - To access this function, software must
toggle a DCR bit.
Used by either peripheral controller or DMA controller depending
upon the type of transfer involved. When the PPC405GP is the
bus master, it enables the selected device to drive the bus.
5V tolerant
3.3V LVTTL
PerOE
O
7
1
Used by the PPC405GP when not in external master mode, as
output by either the peripheral controller or DMA controller
depending upon the type of transfer involved. High indicates a
read from memory, low indicates a write to memory.
5V tolerant
3.3V LVTTL
PerR/W
I/O
Otherwise it used by the external master as an input to indicate
the direction of transfer.
5V tolerant
3.3V LVTTL
PerReady
PerBLast
Used by a peripheral slave to indicate it is ready to transfer data.
I
1
Used by the PPC405GP when not in external master mode,
otherwise used by external master. Indicates the last transfer of a
memory access.
5V tolerant
3.3V LVTTL
I/O
1, 7
DMAReq0:3 are used by slave peripherals to indicate they are
prepared to transfer data.
5V tolerant
3.3V LVTTL
DMAReq0:3
DMAAck0:3
I
1
6
1
DMAAck0:3 are used by the PPC405GP to cause the DMA
peripheral to transfer data.
5V tolerant
3.3V LVTTL
O
5V tolerant
3.3V LVTTL
EOT0:3/TC0:3
End Of Transfer/Terminal Count.
I/O
37
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description (Part 5 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 33.
Signal Name
Description
I/O
Type
Notes
External Master Peripheral Interface
Peripheral clock to be used by an external master and by
synchronous peripheral slaves.
5V tolerant
3.3V LVTTL
PerClk
ExtReset
HoldReq
HoldAck
ExtReq
ExtAck
O
O
I
Peripheral reset to be used by an external master and by
synchronous peripheral slaves.
5V tolerant
3.3V LVTTL
Hold Request, used by an external master to request ownership
of the peripheral bus.
5V tolerant
3.3V LVTTL
1, 5
6
Hold Acknowledge, used by the PPC405GP to transfer ownership
of peripheral bus to an external master.
5V tolerant
3.3V LVTTL
O
I
ExtReq is used by an external master to indicate it is prepared to
transfer data.
5V tolerant
3.3V LVTTL
1
ExtAck is used by the PPC405GP to indicate a data transfer
cycle.
5V tolerant
3.3V LVTTL
O
I
6
Used by an external master to indicate the priority of a given
external master tenure.
5V tolerant
3.3V LVTTL
HoldPri
BusReq
PerErr
1
Used when the PPC405GP needs to regain control of peripheral
interface from an external Master.
5V tolerant
3.3V LVTTL
O
I
An input used to indicate to the PPC405GP that an external slave
peripheral error occurred.
5V tolerant
3.3V LVTTL
1, 5
Internal Peripheral Interface
Serial Clock used to provide an alternate clock to the internally
generated serial clock. Used in cases where the allowable
internally generated baud rates are not satisfactory. This input
can be individually connected to either UART.
5V tolerant
3.3V LVTTL
UARTSerClk
I
1
5V tolerant
3.3V LVTTL
UART0_Rx
UART0_Tx
UART0 Serial Data In.
I
O
I
1
6
1
1
1
6
6
1
5V tolerant
3.3V LVTTL
UART0 Serial Data Out.
UART0 Data Carrier Detect.
UART0 Data Set Ready.
UART0 Clear To Send.
UART0 Data Terminal Ready.
UART0 Request To Send.
UART0 Ring Indicator.
5V tolerant
3.3V LVTTL
UART0_DCD
UART0_DSR
UART0_CTS
UART0_DTR
UART0_RTS
UART0_RI
5V tolerant
3.3V LVTTL
I
5V tolerant
3.3V LVTTL
I
5V tolerant
3.3V LVTTL
O
O
I
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
38
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description (Part 6 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 33.
Signal Name
Description
I/O
Type
Notes
5V tolerant
3.3V LVTTL
UART1_Rx
UART1 Serial Data In.
UART1 Serial Data Out.
I
1
5V tolerant
3.3V LVTTL
UART1_Tx
O
I
6
1
UART1 Data Set Ready
or
UART1_DSR/
UART1_CTS
5V tolerant
3.3V LVTTL
UART1 Clear To Send. To access this function, software must
toggle a DCR bit.
UART1 Request To Send
or
UART1_RTS/
UART1_DTR
5V tolerant
3.3V LVTTL
O
6
UART1 Data Terminal Ready. To access this function, software
must toggle a DCR bit.
5V tolerant
3.3V LVTTL
IICSCL
IIC Serial Clock.
IIC Serial Data.
I/O
I/O
1, 2
1, 2
5V tolerant
3.3V LVTTL
IICSDA
Interrupts Interface
Interrupt requests
or
5V tolerant
3.3V LVTTL
IRQ0:6[GPIO17:23]
I[I/O]
1
General Purpose I/O. To access this function, software must
toggle a DCR bit.
JTAG Interface
5V tolerant
3.3V LVTTL
TDI
Test data in.
I
I
1, 4
1, 4
5V tolerant
3.3V LVTTL
TMS
TDO
TCK
JTAG test mode select.
Test data out.
5V tolerant
3.3V LVTTL
O
I
JTAG test clock. The frequency of this input can range from DC to
25MHz.
5V tolerant
3.3V LVTTL
1, 4
5
JTAG reset. TRST must be low at power-on to initialize the JTAG
controller and for normal operation of the PPC405GP.
5V tolerant
3.3V LVTTL
TRST
System Interface
SysClk
I
5V tolerant
3.3V LVTTL
Main system clock input.
I
Main system reset. External logic can drive this bidirectional pin
low (minimum of 16 cycles) to initiate a system reset. A system
reset can also be initiated by software. Implemented as an open-
drain output (two states; 0 or open circuit).
5V tolerant
3.3V LVTTL
SysReset
I/O
I
1, 2
AV
Clean voltage input for the PLL.
DD
39
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description (Part 7 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 33.
Signal Name
Description
I/O
Type
Notes
5V tolerant
3.3V LVTTL
SysErr
Set to 1 when a Machine Check is generated.
O
5V tolerant
3.3V LVTTL
Halt
Halt from external debugger.
I
1, 2
1, 6
General Purpose I/O
or
GPIO1[TS1E]
GPIO2[TS2E]
5V tolerant
3.3V LVTTL
I/O[O]
Even Trace execution status. To access this function, software
must toggle a DCR bit.
General Purpose I/O
or
5V tolerant
3.3V LVTTL
GPIO3[TS1O]
GPIO4[TS2O]
GPIO5:8[TS3:6]
I/O[O]
I/O[O]
I/O[O]
1
1, 6
1
Odd Trace execution status. To access this function, software
must toggle a DCR bit.
General Purpose I/O
or
5V tolerant
3.3V LVTTL
Odd Trace execution status. To access this function, software
must toggle a DCR bit.
General Purpose I/O
or
5V tolerant
3.3V LVTTL
Trace status. To access this function, software must toggle a
DCR bit.
General Purpose I/O
or
5V tolerant
3.3V LVTTL
GPIO9[TrcClk]
I/O[O]
1
Trace interface clock. A toggling signal that is always half of the
CPU core frequency. To access this function, software must
toggle a DCR bit.
Test Enable. Used only for manufacturing tests. Pull down for
normal operation.
2.5V CMOS
w/pull-down
TestEn
RcvrInh
I
I
I
I
Receiver Inhibit. Used only for manufacturing tests. Pull up for
normal operation.
5V tolerant
3.3V LVTTL
2
2
1
Driver Inhibit 1 and 2. Used only for manufacturing tests. Pull up
for normal operation.
5V tolerant
3.3V LVTTL
DrvrInh1:2
An external clock input that can be used to clock the timers in the
CPU core.
5V tolerant
3.3V LVTTL
TmrClk
Trace Interface
Even Trace execution status. To access this function, software
must toggle a DCR bit
[TS1E]GPIO1
[TS2E]GPIO2
5V tolerant
3.3V LVTTL
O[I/O]
1, 6
or
General Purpose I/O.
40
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description (Part 8 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 33.
Signal Name
Description
I/O
Type
Notes
Odd Trace execution status. To access this function, software
must toggle a DCR bit
5V tolerant
3.3V LVTTL
[TS1O]GPIO3
O[I/O]
1
or
General Purpose I/O.
Odd Trace execution status. To access this function, software
must toggle a DCR bit
5V tolerant
3.3V LVTTL
[TS2O]GPIO4
O[I/O]
O[I/O]
1, 6
or
General Purpose I/O.
Trace status. To access this function, software must toggle a
DCR bit
5V tolerant
3.3V LVTTL
[TS3:6]GPIO5:8
1
or
General Purpose I/O.
Trace interface clock. A toggling signal that is always half of the
CPU core frequency. To access this function, software must
toggle a DCR bit
5V tolerant
3.3V LVTTL
[TrcClk]GPIO9
O[I/O]
1
or
General Purpose I/O.
Ground pins
Ground
Note: On the 456-ball packages, L11-L16, M11-M16, N11-N16,
P11-P16, R11-R16, and T11-T16 are also thermal balls.
GND
On the 413-ball package, J11, J13, K11-K13, L11-L13,
M11-N13, N11-N13, P11-P13, R11, and R13 are also
thermal balls.
OVDD pins
OV
Output driver voltage—3.3V.
Logic voltage—2.5V.
DD
VDD pins
V
DD
Other pins
Reserved—Except for Y5 (on the 413-ball package) or AF4, do
not connect signals, voltage, or ground to these pins. Y5 (on the
Reserved
413-ball package) and AF4 must be tied to OV or GND.
DD
41
PowerPC 405GP Embedded Processor Data Sheet
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to the device
Characteristic
Supply Voltage (Internal Logic)
Symbol
Value
Unit
V
V
0 to +2.7
0 to +3.6
0 to +2.7
DD
OV
Supply Voltage (I/O Interface)
V
DD
AV
PLL Supply Voltage
V
DD
V
-0.6 to V + 0.6
Input Voltage (2.5V CMOS receivers)
Input Voltage (3.3V LVTTL receivers)
Input Voltage (5.0V LVTTL receivers)
Storage Temperature Range
V
IN
DD
V
-0.6 to OV + 0.6
V
IN
DD
V
-0.6 to OV + 2.4
V
IN
DD
T
-55 to +150
-40 to +120
°C
°C
STG
T
Case temperature under bias
C
Note: All specified voltages are with respect to GND.
Package Thermal Specifications
The PPC405GP is designed to operate within a case temperature range of -40°C to +85°C. Thermal resistance values for
the E-PBGA packages in a convection environment are as follows:
Airflow
ft/min (m/sec)
Symbol
Package—Thermal Resistance
Unit
0 (0)
100 (0.51)
200 (1.02)
35mm, 456-balls—Junction-to-Case
θJC
θCA
θJC
θCA
θJC
θCA
2
2
2
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1
14
2
13
2
12
2
35mm, 456-balls—Case-to-Ambient
27mm, 456-balls—Junction-to-Case
1
18
1.5
17
16
1.5
15
15
1.5
13
27mm, 456-balls—Case-to-Ambient
25mm, 413-balls—Junction-to-Case
1
25mm, 413-balls—Case-to-Ambient
Note:
1. For a chip mounted on a JEDEC 2S2P card without a heat sink.
2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist:
a. Case temperature, T , is measured at top center of case surface with device soldered to circuit board.
C
b. T = T – P×θCA, where T is ambient temperature and P is power consumption.
A
C
A
c. TCMax = TJMax – P×θJC, where TJMax is maximum junction temperature and P is power consumption.
42
PowerPC 405GP Embedded Processor Data Sheet
Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Notes:
1. PCI drivers meet PCI specifications.
Parameter
Logic Supply Voltage
Symbol
Minimum
2.3
Typical
2.5
Maximum
2.7
Unit
V
Notes
V
DD
OV
I/O Supply Voltage
PLL Supply Voltage
3.0
3.3
3.6
V
DD
AV
2.3
2.5
2.7
V
DD
Input Logic High (2.5V CMOS
receivers)
V
1.7
2.0
2.0
0
V
V
V
V
V
V
IH
DD
Input Logic High (3.3V LVTTL
receivers)
V
OV
IH
DD
Input Logic High (5.0V LVTTL
receivers)
V
5.5
0.7
IH
Input Logic Low (2.5V CMOS
receivers)
V
IL
Input Logic Low (3.3/5.0V LVTTL
receivers)
V
0
0.8
IL
V
OV
Output Logic High
Output Logic Low
2.4
0
V
V
OH
DD
V
0.4
OL
3.3V I/O Input Current (no pull-up or
pull-down)
I
±10
µA
IL1
I
400 (@ V
)
Input Current (with internal pull-down)
±10 (@ 0V)
±10
µA
µA
IL2
DD
1
I
-650
5V Tolerant I/O Input Current
IL4
Input Max Allowable Overshoot (2.5V
CMOS receivers)
V
V
+ 0.6
DD
V
V
V
IMAO25
Input Max Allowable Overshoot (3.3V
LVTTL receivers)
V
OV + 0.6
IMAO3
DD
Input Max Allowable Overshoot (5.0V
LVTTL receivers)
V
5.5
IMAO5
V
Input Max Allowable Undershoot
Output Max Allowable Overshoot
Output Max Allowable Undershoot
Case Temperature
-0.6
V
V
IMAU
V
OV + 0.3
OMAO
DD
V
-0.6
-40
V
OMAU3
T
+85
°C
C
Note:
1. See “5V-Tolerant Input Current” on page 44
43
PowerPC 405GP Embedded Processor Data Sheet
5V-Tolerant Input Current
100
0
-100
-200
-300
-400
-500
-600
-700
0.0
1.0
2.0
3.0
4.0
5.0
Input Voltage (V)
Input Capacitance
Parameter
Symbol
Maximum
Unit
pF
Notes
C
C
C
C
3.3V LVTTL I/O
5V tolerant LVTTL I/O
PCI I/O
5.5
5
IN1
IN2
IN3
IN4
pF
7
pF
Rx only pins
4
pF
44
PowerPC 405GP Embedded Processor Data Sheet
DC Electrical Characteristics
Parameter
Symbol
Minimum
Typical
550
730
35
Maximum
Unit
mA
mA
mA
mA
mA
W
Active Operating Current (V )–200MHz
I
670
880
37
DD
DD
Active Operating Current (V )–266MHz
I
DD
DD
Active Operating Current (OV )–200MHz
I
DD
ODD
Active Operating Current (OV )–266MHz
I
37
40
DD
ODD
PLL V Input current
I
16
23
DD
PLL
1
P
Active Operating Power–200MHz
Active Operating Power–266MHz
Note:
1.5
2.0
DD
1
P
2.0
W
2.6
DD
1. Maximum power is characterized at V = 2.7V, OV = 3.6V, T = 85°C, across the silicon process (worse case to best case),
DD
DD
C
while running an application designed to maximize power consumption. The specification at 200MHz corresponds to
CPU = 200 MHz, PLB = 100MHz, OPB = EBC = 50MHz, PCI = 33.3MHz. The 266MHz maximum power was measured with
CPU = 266.6MHz, PLB =133.3MHz, OPB = EBC = 66.6MHz, PCI = 33.3MHz.
2. AV should be derived from V using the following circuit:
DD
DD
L1 – 2.2µH SMT inductor (equivalent to MuRata
LQH3C2R2M34) or SMT chip ferrite bead (equivalent
to MuRata BLM31A700S)
AV
V
DD
DD
L1
+
C1 – 3.3 µF SMT tantalum
C1
C2
C3
C2 – 0.1µF SMT monolithic ceramic capacitor with X7R
AGND
dielectric or equivalent
C3 – 0.01µF SMT monolithic ceramic capacitor with X7R
GND
dielectric or equivalent
Test Conditions
Clock timing and switching characteristics are specified in
accordance with operating conditions shown in the table
“Recommended DC Operating Conditions.” For all signals other than
PCI signals, AC specifications are characterized at OVDD = 3V and
Output
Pin
50pF
All signals other
than PCI
TC = 85°C with the 50pF test load shown in the figure at right.
For PCI signals there are two different test load circuits, one for the
rising edge and one the falling edge as shown in the figures at right.
Output
Pin
10pF
25Ω
PCI Rising edge
Output
Pin
OV
DD
25Ω
PCI Falling edge
10pF
45
PowerPC 405GP Embedded Processor Data Sheet
Clocking Specifications
Symbol
Parameter
Min
Max
Units
CPU
PF
Processor clock frequency
200 or 266.66
5 or 3.75
MHz
ns
C
PT
Processor clock period
C
SysClk Input
SCF
Clock input frequency
25
15
66.66
40
MHz
ns
C
SCT
Clock period
C
SCT
Clock edge stability (phase jitter, cycle to cycle)
Clock input high time
± 0.15
ns
CS
SCT
40% of nominal period 60% of nominal period
40% of nominal period 60% of nominal period
ns
CH
SCT
Clock input low time
ns
CL
Note: Input slew rate > 2V/ns
MemClkOut Output
MCOF
MCOT
MCOF
MCOT
MCOT
Clock output frequency @ PF = 200MHz
100
MHz
ns
C
C
C
C
C
Clock period @ PF = 200MHz
10
C
Clock output frequency @ PF = 266MHz
133.33
MHz
ns
C
Clock period @ PF = 266MHz
7.5
C
Clock edge stability (phase jitter, cycle to cycle)
Clock output high time
± 0.2
ns
CS
CH
MCOT
MCOT
45% of nominal period 55% of nominal period
45% of nominal period 55% of nominal period
ns
Clock output low time
ns
CL
Other Clocks
VCOF
VCO frequency @ PF = 200MHz
400
800
100
MHz
MHz
MHz
MHz
MHz
C
C
PLBF
PLB frequency @ PF = 200MHz
C
C
PLBF
PLB frequency @ PF = 266MHz
133.33
50
C
C
OPBF
OPB frequency @ PF = 200MHz
C
C
OPBF
OPB frequency @ PF = 266MHz
66.66
C
C
Clocking Waveform
2.0V
1.5V
0.8V
T
T
CL
CH
T
C
46
PowerPC 405GP Embedded Processor Data Sheet
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC405GP. This
controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG
is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew
there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When
using an SSCG with the PPC405GP the following conditions must be met:
• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
PPC405GP with one or more internal clocks at their maximum supported frequency, the SSCG can only
lower the frequency.
• The maximum frequency deviation cannot exceed −3%, and the modulation frequency cannot exceed
40kHz. In some cases, on-board PPC405GP peripherals impose more stringent requirements (see
Note 1).
• Use the peripheral bus clock (PerClk) for logic that is synchronous to the peripheral bus since this clock
tracks the modulation.
• Use the SDRAM MemClkOut since it also tracks the modulation.
Please refer to the application note Using a Spread Spectrum Clock Generator with the PowerPC 405GP for
additional details. This application note is available on the IBM Microelectronics web site at
http://www.chips.ibm.com.
Notes:
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of
approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that
the connected device is running at precise baud rates. If an external serial clock is used the baud rate is
unaffected by the modulation
2. Operation of the PPC405GP PCI Bridge is unaffected by the use of a SSCG.
For PCI frequencies of 33.33 MHz and below the PCI controller supports synchronous mode operation.
This is accomplished by strapping the PPC405GP for synchronous mode PCI and connecting the PCI bus
clock to the PPC405GP SysClk input. For 33.33 MHz signalling, the PCI specification has no limitation on
the amount of frequency deviation or modulation that may be applied to the PCI clock. Therefore, the
PPC405GP SSCG requirements stated above take precedence.
At PCI frequencies above 33.33 MHz, the PCI controller must be operated in asynchronous mode. When
in asynchronous mode, the PCI bus clock must be driven into the PPC405GP PCIClk input. In this
configuration the PCI controller supports the 66.66 MHz PCI clock specification which specifies a
maximum frequency deviation of -1% at a modulation of between 30 kHz and 33 kHz.
3. Ethernet operation is unaffected.
4. IIC operation is unaffected.
Caution: It is up to the system designer to ensure that any SSCG used with the PPC405GP meets the above
requirements and does not adversely affect other aspects of the system.
47
PowerPC 405GP Embedded Processor Data Sheet
Peripheral Interface Clock Timings
Parameter
PCIClk input frequency (asynchronous mode)
PCIClk period (asynchronous mode)
PCI Clock frequency (synchronous mode)
PCI Clock period (synchronous mode - Note 2)
PCIClk input high time
Min
Note 1
15
Max
66.66
Note 1
33.33
40
Units
MHz
ns
25
MHz
ns
30
40% of nominal period 60% of nominal period
40% of nominal period 60% of nominal period
ns
PCIClk input low time
ns
EMCMDClk output frequency
EMCMDClk period
–
2.5
–
MHz
ns
400
EMCMDClk output high time
EMCMDClk output low time
PHYTxClk input frequency
160
–
ns
160
–
ns
2.5
25
400
–
MHz
ns
PHYTxClk period
40
PHYTxClk input high time
35% of nominal period
ns
PHYTxClk input low time
35% of nominal period
–
ns
PHYRxClk input frequency
2.5
25
400
–
MHz
ns
PHYRxClk period
40
PHYRxClk input high time
35% of nominal period
ns
PHYRxClk input low time
35% of nominal period
–
ns
PerClk output frequency–200MHz
PerClk period–200MHz
–
20
–
50
–
MHz
ns
PerClk output frequency–266MHz
PerClk period–266MHz
66.66
–
MHz
ns
15
PerClk output high time
45% of nominal period 55% of nominal period
45% of nominal period 55% of nominal period
± 0.3
ns
PerClk output low time
ns
PerClk clock edge stability (phase jitter, cycle to cycle)
ns
1000/(2T
+2ns)
–
MHz
UARTSerClk input frequency (Note 3)
UARTSerClk period
OPB
2T
T
+2
–
ns
ns
OPB
+1
UARTSerClk input high time
–
OPB
T
+1
UARTSerClk input low time
TmrClk input frequency–200MHz
TmrClk period–200MHz
TmrClk input frequency–266MHz
TmrClk period–266MHz
TmrClk input high time
TmrClk input low time
–
50
ns
MHz
ns
OPB
–
20
–
–
66.66
–
MHz
ns
15
40% of nominal period 60% of nominal period
40% of nominal period 60% of nominal period
ns
ns
Note:
1. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the PowerPC 405GP Embedded Proces-
sor User’s Manual for more information.
2. In synchronous PCI mode the PCI clock is derived from SysClk and the PCIClk input pin is unused.
3. T
is the period in ns of the OPB clock. The maximum OPB clock frequency is 50 MHz for 200MHz parts and 66.66MHz for
OPB
266MHz parts.
48
PowerPC 405GP Embedded Processor Data Sheet
Input Setup and Hold Waveform
SysClk
1.5V
T
T
IS
IH
MIN
MIN
Inputs
1.5V
Valid
Output Delay and Float Timing Waveform
SysClk
1.5V
1.5V
T
T
OH
OV
MAX
MIN
Outputs
Valid
MAX
T
OF
MIN
Outputs
1.5V
49
PowerPC 405GP Embedded Processor Data Sheet
Notes: 1. In all of the following I/O Specifications tables a timing values of na means “not applicable” and dc
means “don’t care.”
2. See “Test Conditions” on page 45 for output capacitive loading.
I/O Specifications—All speeds (Part 1 of 3)
Notes:
1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz
and 2ns for 33.33MHz.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at
2.4 V and I/O L is specified at 0.4 V.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
I/O H
(min)
I/O L
(min)
(T min)
(T min)
(T max)
(T min)
IS
IH
OV
OH
PCI Interface
PCIAD31:0
PCIC3:0[BE3:0]
PCIClk
3
3
0
0
6
6
1
1
0.5
0.5
na
1.5
1.5
na
PCIClk
PCIClk
1
1
async
1
dc
3
dc
0
na
1
PCIDevSel
PCIFrame
6
6
0.5
0.5
1.5
1.5
PCIClk
PCIClk
3
0
1
1
PCIGnt0[Req]
PCIGnt1:5
na
na
6
1
0.5
1.5
PCIClk
1
PCIIDSel
3
na
3
0
na
0
6
dc
6
1
dc
1
na
0.5
0.5
0.5
0.5
na
1.5
1.5
1.5
1.5
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
1
PCIINT[PerWE]
PCIIRDY
async
1
1
1
PCIParity
PCIPErr
3
0
6
1
3
0
6
1
PCIReq0[Gnt]
PCIReq1:5
5
0
na
na
na
na
PCIClk
1
PCIReset
na
na
3
na
na
0
na
na
6
na
na
1
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
PCIClk
PCIClk
PCIClk
PCIClk
PCISErr
PCIStop
1
1
PCITRDY
3
0
6
1
Ethernet Interface
EMCMDClk
na
na
0
settable
2
9
9
6
6
2, async
2
1 OPB clock 1 OPB clock
period + 10ns
EMCMDIO[PHYMDIO]
100
EMCMDClk
period
EMCTxD3:0
EMCTxEn
EMCTxErr
PHYCol
na
na
na
na
na
na
20
20
20
2
2
2
9
9
6
6
PHYTX
PHYTX
PHYTX
2
2
9
6
2
2, async
2, async
2, async
2
9
6
PHYCrS
9
6
PHYRxClk
PHYRxD3:0
PHYRxDV
PHYRxErr
PHYTxClk
na
9
na
6
4
4
4
1
1
1
na
na
na
na
na
na
PHYRX
PHYRX
PHYRX
9
6
2
9
6
2
na
na
2, async
50
PowerPC 405GP Embedded Processor Data Sheet
I/O Specifications—All speeds (Part 2 of 3)
Notes:
1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz
and 2ns for 33.33MHz.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at
2.4 V and I/O L is specified at 0.4 V.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
I/O H
(min)
I/O L
(min)
(T min)
(T min)
(T max)
(T min)
IS
IH
OV
OH
Internal Peripheral Interface
IICSCL
na
na
na
na
na
na
na
na
na
na
na
na
na
na
19
19
12
12
12
12
12
12
12
12
12
12
8
IICSDA
UART0_CTS
UART0_DCD
UART0_DSR
UART0_DTR
UART0_RI
8
8
8
na
na
na
na
8
UART0_RTS
UART0_Rx
UART0_Tx
UART1_RTS/
UART1_DTR
UART1_DSR/
UART1_CTS
UART1_Rx
UART1_Tx
UARTSerClk
na
na
8
8
na
na
na
na
8
12
na
8
na
na
na
na
na
na
12
na
na
8
na
na
na
na
na
Interrupts Interface
IRQ0:6[GPIO17:23]
12
8
JTAG Interface
TCK
TDI
na
na
12
na
na
na
na
8
async
async
async
async
async
TDO
TMS
TRST
na
na
51
PowerPC 405GP Embedded Processor Data Sheet
I/O Specifications—All speeds (Part 3 of 3)
Notes:
1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz
and 2ns for 33.33MHz.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at
2.4 V and I/O L is specified at 0.4 V.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
I/O H
(min)
I/O L
(min)
(T min)
(T min)
(T max)
(T min)
IS
IH
OV
OH
System Interface
DrvrInh1:2
dc
dc
na
na
na
12
na
8
GPIO1[TS1E]
GPIO2[TS2E]
GPIO3[TS1O]
GPIO4[TS2O]
GPIO5[TS3]
GPIO6[TS4]
GPIO7[TS5]
GPIO8[TS6]
GPIO9[TrcClk]
Halt
dc
dc
dc
dc
na
na
na
na
10
na
na
na
na
na
na
1
na
na
na
12
12
na
na
na
na
na
8
async
RcvrInh
SysClk
SysErr
SysReset
TestEn
TmrClk
async
async
async
async
8
dc
dc
dc
dc
na
na
na
na
52
PowerPC 405GP Embedded Processor Data Sheet
I/O Specifications—200MHz
Notes:
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM.
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
3. SDRAM interface hold times are guaranteed at the PPC405GP package pin. System designers must use the
PPC405GP IBIS model (available from www.chips.ibm.com) to ensure their clock distribution topology minimizes
loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal
wiring.
4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
5. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns)
Output (ns)
Output Current (mA)
I/O H I/O L
(minimum) (minimum)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
(T min)
(T min)
(T max)
(T min)
IS
IH
OV
OH
SDRAM Interface
BA1:0
na
na
na
na
na
na
2
na
na
na
na
na
na
1
7.5
6.2
7.5
5.2
6.1
6.2
6.2
7.6
6.3
7.5
7.5
1
1
1
1
1
1
1
1
1
1
1
19
19
19
40
19
19
19
19
19
19
19
12
12
12
25
12
12
12
12
12
12
12
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
1, 2
2
BankSel3:0
CAS
1, 2
2
ClkEn0:1
DQM0:3
2
DQMCB
2
ECC0:7
2
MemAddr12:0
MemData0:31
RAS
na
2
na
1
1, 2
2
na
na
na
na
1, 2
1, 2
WE
External Slave Peripheral Interface
DMAAck0:3
DMAReq0:3
EOT0:3/TC0:3
PerAddr0:31
PerBLast
na
5
na
1
8
na
8
0
na
0
12
na
12
19
12
8
na
8
PerClk
PerClk
PerClk
PerClk
PerClk
dc
4
dc
1
10
8
0
12
8
4
1
0
PerCS0
na
na
8
0
12
8
PerClk
PerCS1:7[GPIO10:16]
PerData0:31
PerOE
6
na
4
1
na
1
10
8
0
0
19
12
19
12
na
12
12
8
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerPar0:3
10
8
0
12
8
PerR/W
4
1
0
PerReady
9
1
na
8
na
0
na
8
PerWBE0:3
3
1
External Master Peripheral Interface
BusReq
ExtAck
ExtReq
ExtReset
HoldAck
HoldPri
HoldReq
PerClk
na
na
5
na
na
1
8
7
0
0
12
12
na
19
12
na
na
19
na
8
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PLB Clk
PerClk
8
na
8
na
0
na
12
8
na
na
4
na
na
1
8
0
na
na
0.9
na
na
na
0.7
na
na
na
12
na
5
1
na
3
na
1
4
PerErr
53
PowerPC 405GP Embedded Processor Data Sheet
I/O Specifications—266MHz
Notes:
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM.
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
3. SDRAM interface hold times are guaranteed at the PPC405GP package pin. System designers must use the
PPC405GP IBIS model (available from www.chips.ibm.com) to ensure their clock distribution topology minimizes
loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal
wiring.
4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
5. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns)
Output (ns)
Output Current (mA)
I/O H I/O L
(maximum) (minimum)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
(T min)
(T min)
(T max)
(T min)
IS
IH
OV
OH
SDRAM Interface
BA1:0
na
na
na
na
na
na
1.5
na
1.5
na
na
na
na
na
na
na
na
1
5.7
4.8
5.7
4.2
4.8
4.8
4.8
5.7
4.9
5.7
5.7
1
1
1
1
1
1
1
1
1
1
1
19
19
19
40
19
19
19
19
19
19
19
12
12
12
25
12
12
12
12
12
12
12
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
1, 2
2
BankSel3:0
CAS
1, 2
2
ClkEn0:1
DQM0:3
2
DQMCB
2
ECC0:7
2
MemAddr12:0
MemData0:31
RAS
na
1
1, 2
2
na
na
1, 2
1, 2
WE
External Slave Peripheral Interface
DMAAck0:3
DMAReq0:3
EOT0:3/TC0:3
PerAddr0:31
PerBLast
na
4
na
1
6
na
6
0
na
0
12
na
12
19
12
8
na
8
PerClk
PerClk
PerClk
PerClk
PerClk
dc
3
dc
1
7.2
6
0
12
8
3
1
0
PerCS0
PerCS1:7[GPIO10:16]
na
na
6
0
12
8
PerClk
PerData0:31
PerOE
5
na
3
1
na
1
7.2
6
0
0
19
12
19
12
na
12
12
8
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerPar0:3
PerR/W
7.2
6
0
12
8
4
1
0
PerReady
PerWBE0:3
6.5
3
1
na
6
na
0
na
8
1
External Master Peripheral Interface
BusReq
ExtAck
ExtReq
ExtReset
HoldAck
HoldPri
HoldReq
PerClk
na
na
4
na
na
1
6
6
0
0
12
12
na
19
12
na
na
19
na
8
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PLB Clk
PerClk
8
na
6
na
0
na
12
8
na
na
3
na
na
1
6
0
na
na
0.9
na
na
na
0.7
na
na
na
12
na
4
1
na
3
na
1
4
PerErr
54
PowerPC 405GP Embedded Processor Data Sheet
Strapping
When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is
read to enable default initial conditions prior to PPC405GP start-up. The actual capture instant is the nearest
SysClk edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or
pull-down (logical 0) resistors to select the desired default conditions. The recommended pull-up is 3kΩ to
+3.3V or 10kΩ to 5V. The recommended pull-down is 1KΩ to GND. These pins are use for strap functions
only during reset. They are used for other signals during normal operation. The following table lists the
strapping pins along with their functions and strapping options. The pin for the 456-ball package is listed first
(for example, AF3), followed by the corresponding pin for the 413-ball package (for example, U8), which
appears as AF3/U8.
PPC405GP Strapping Pin Assignments (Part 1 of 2)
Function
Option
Ball Strapping
AF2/T8
1
AF3/U8
AD16/AB15
(UART0_Tx) (UART0_DTR) (UART0_RTS)
PLL Tuning
for 6 ≤ M ≤ 7 use choice 3
for 7 < M ≤ 12 use choice 5
for 12 < M ≤ 32 use choice 6
Choice 1; TUNE[5:0] = 010001
Choice 2; TUNE[5:0] = 111011
Choice 3; TUNE[5:0] = 010011
Choice 4; TUNE[5:0] = 111101
Choice 5; TUNE[5:0] = 010101
Choice 6; TUNE[5:0] = 010110
Choice 7; TUNE[5:0] = 111110
Choice 8; TUNE[5:0] = 100100
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
D16/A17
(DMAAck0)
B15/B14
(DMAAck1)
PLL Forward Divider
Bypass mode
Divide by 3
Divide by 4
Divide by 6
0
0
1
1
0
1
0
1
2
B14/A15
(DMAAck2)
C12/A8
(DMAAck3)
PLL Feedback Divider
Divide by 1
Divide by 2
Divide by 3
Divide by 4
0
0
1
1
0
1
0
1
2
P25/R23
(EMCTxD3)
L24/J22
(EMCTxD2)
PLB Divider from CPU
Divide by 1
Divide by 2
Divide by 3
Divide by 4
0
0
1
1
0
1
0
1
2
L25/K21
(EMCTxD1)
J26/F22
(EMCTxD0)
OPB Divider from PLB
Divide by 1
Divide by 2
Divide by 3
Divide by 4
0
0
1
1
0
1
0
1
55
PowerPC 405GP Embedded Processor Data Sheet
PPC405GP Strapping Pin Assignments (Part 2 of 2)
Function
Option
Ball Strapping
C20/C19
2, 3
D18/A20
PCI Divider from PLB
(GPIO1[TS1E]) (GPIO2[TS2E])
Divide by 1
Divide by 2
Divide by 3
Divide by 4
0
0
1
1
0
1
0
1
2
K25/K20
(EMCTxErr)
K23/J21
(EMCTxEn)
External Bus Divider from PLB
Divide by 2
Divide by 3
Divide by 4
Divide by 5
0
0
1
1
0
1
0
1
ROM Width
AD2/N7
(UART1_RTS/
UART1_DTR)
AC2/N3
(UART1_Tx)
8-bit ROM
16-bit ROM
32-bit ROM
Reserved
0
0
1
1
0
1
0
1
ROM Location
U2/P4
(HoldAck)
PPC405GP Peripheral Attach
PPC405GP PCI Attach
0
1
PCI Asynchronous Mode Enable
Y3/U4
(ExtAck)
Synchronous PCI Mode
Asynchronous Mode
0
1
3
AF18/AB18
(GPIO4[TS2O])
PCI Arbiter Enable
Internal Arbiter Disabled
Internal Arbiter Enabled
0
1
Note:
1. The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the
PPC405GP. These bits are shown for information only; and do not require modification except in special clocking circumstances
such as spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405GP,
visit the technical documents area of the IBM PowerPC web site.
2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in “Clocking
Specifications” on page 46. Further requirements are detailed in the Clocking chapter of the PowerPC 405GP Embedded
Processor User’s Manual.
3. Additional consideration must be given to pins that normally function as Trace signals. Improved design margin can be gained by
using tri-state buffers instead of strapping resistors, and minimizing trace lengths and stubs.
56
PowerPC 405GP Embedded Processor Data Sheet
Inside of back cover
57
PowerPC 405GP Embedded Processor Data Sheet
(c) Copyright International Business Machines Corporation 1999, 2002
All Rights Reserved
Printed in the United States of America, February 2002
The following are trademarks of International Business Machines Corporation in
the United States, or other countries, or both:
Blue Logic
CodePack
CoreConnect
IBM
IBM Logo
PowerPC
Other company, product, and service names may be trademarks or service marks
of others.
Preliminary Edition (2/20/02)
This document contains information on a new product under development by IBM.
IBM reserves the right to change or discontinue this product without notice.
This document is a preliminary edition of the PowerPC 405GP data sheet. Make
sure you are using the correct edition for the level of the product.
While the information contained herein is believed to be accurate, such
information is preliminary, and should not be relied upon for accuracy or
completeness, and no representations or warranties of accuracy or completeness
are made.
All information contained in this document is subject to change without notice. The
products described in this document are NOT intended for use in implantation or
other life support applications where malfunction may result in injury or death to
persons. The information contained in this document does not affect or change
IBM product specifications or warranties. Nothing in this document shall operate
as an express or implied license or indemnity under the intellectual property rights
of IBM or third parties. All information contained in this document was obtained in
specific environments, and is presented as an illustration. The results obtained in
other operating environments may vary.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN
"AS IS" BASIS. In no event will IBM be liable for damages arising directly or
indirectly from any use of the information contained in this document.
IBM Microelectronics Division
1580 Route 52
Hopewell Junction, NY 12533-6351
The IBM home page is www. ibm.com.
The IBM Microelectronics Division home is www.chips.ibm.com.
SA14-2521-11
58
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