ICS932S801AFLFT_技术文档

ICS932S801

Integrated

Circuit

Systems, Inc.

K8 Clock Chip for Serverworks GC-HT 2-Way Servers

Recommended Application:

Serverworks GC-HT systems using AMD K8 processors

Pin Configuration

X1 1

X2 2

VDD48 3

48 VDDREF

Output Features:

47 FS0/REF0

46 FS1/REF1

45 FS2

•

4 - Pairs of AMD K8 clocks

1 - Pair of SRC/PCI Express* clock

2 - 14.318 MHz REF clocks

2 - USB_48MHz clocks

4 - HyperTransport 66 MHz clocks

4 - PCI 33 MHz clocks

48MHz_0 4

48MHz_1 5

GND 6

SCLK 7

SDATA 8

44 GND

43 CPUCLK8T0

42 CPUCLK8C0

41 VDDCPU

VDDHTT 9

HTTCLK0 10

HTTCLK1 11

HTTCLK2 12

HTTCLK3 13

GNDHTT 14

VDDPCI 15

PCICLK0 16

PCICLK1 17

PCICLK2 18

PCICLK3 19

GNDPCI 20

PD# 21

40 GNDCPU

39 CPUCLK8T1

38 CPUCLK8C1

37 VDDCPU

36 GNDCPU

35 CPUCLK8T2

34 CPUCLK8C2

33 VDDCPU

32 GNDCPU

31 CPUCLK8T3

30 CPUCLK8C3

29 SPREAD_EN

28 GNDSRC

27 VDDSRC

Features:

•

Spread Spectrum for EMI reduction

Outputs may be disabled via SMBus

M/N programming via SMBus

VDDA 22

GNDA 23

IREF 24

26 SRCCLKT0

25 SRCCLKC0

48-SSOP, TSSOP

Functionality

Power Groups

CPU

MHz

Hi-Z

X

HTT

MHz

Hi-Z

X/3

PCI

MHz

Hi-Z

Pin Number

FS2

FS1

FS0

Description

VDD

GND

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

6

14

20

48MHz

X/6

9

15

66MHz HTT Clocks

33 MHz PCI Clocks

IREF, Analog Core

180.00 60.00

220.00 73.12

100.00 66.66

133.33 66.66

166.67 66.66

200.00 66.66

30.00

36.56

33.33

22

23

27

28

SRC PLL, SRCCLK

K8 CPU Clocks, CPU PLL

REF Clocks, Xtal Oscillator

33,37,41

48

32,36,40

44

0959C—03/13/06

*Other names and brands may be claimed as the property of others.

ICS932S801

Pin Descriptions

PIN # PIN NAME

PIN TYPE

IN

DESCRIPTION

Crystal input, Nominally 14.318MHz.

Crystal output, Nominally 14.318MHz

Power pin for the 48MHz output.3.3V

48MHz clock output.

Ground pin.

Clock pin of SMBus circuitry, 5V tolerant.

Data pin for SMBus circuitry, 5V tolerant.

Supply for HTT clocks, nominal 3.3V.

3.3V Hyper Transport output

Ground pin for the HTT outputs

Power supply for PCI clocks, nominal 3.3V

PCI clock output.

1

2

X1

X2

OUT

PWR

OUT

PWR

I/O

3

VDD48

4

5

6

48MHz_0

48MHz_1

GND

7

SCLK

8

9

SDATA

VDDHTT

HTTCLK0

HTTCLK1

HTTCLK2

HTTCLK3

GNDHTT

VDDPCI

PCICLK0

PCICLK1

PCICLK2

PCICLK3

GNDPCI

I/O

PWR

OUT

PWR

OUT

PWR

10

11

12

13

14

15

16

17

18

19

20

Ground pin for the PCI outputs

Asynchronous active low input pin used to power down the device. The internal

clocks are disabled and the VCO and the crystal are stopped.

3.3V power for the PLL core.

21

PD#

IN

22

23

VDDA

GNDA

PWR

OUT

Ground pin for the PLL core.

This pin establishes the reference current for the differential current-mode output

pairs. This pin requires a fixed precision resistor tied to ground in order to establish

the appropriate current. 475 ohms is the standard value.

Complement clock of differential SRC clock pair.

True clock of differential SRC clock pair.

Supply for SRC clocks, 3.3V nominal

Ground pin for the SRC outputs

Asynchronous, active high input to enable spread spectrum functionality.

Complementary clock of differential 3.3V push-pull K8 pair.

True clock of differential 3.3V push-pull K8 pair.

Ground pin for the CPU outputs

Supply for CPU clocks, 3.3V nominal

Complementary clock of differential 3.3V push-pull K8 pair.

True clock of differential 3.3V push-pull K8 pair.

Ground pin for the CPU outputs

Supply for CPU clocks, 3.3V nominal

Complementary clock of differential 3.3V push-pull K8 pair.

True clock of differential 3.3V push-pull K8 pair.

Ground pin for the CPU outputs

24

IREF

OUT

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

SRCCLKC0

SRCCLKT0

VDDSRC

OUT

PWR

IN

GNDSRC

SPREAD_EN

CPUCLK8C3

CPUCLK8T3

GNDCPU

OUT

PWR

OUT

PWR

OUT

PWR

OUT

PWR

IN

VDDCPU

CPUCLK8C2

CPUCLK8T2

GNDCPU

VDDCPU

CPUCLK8C1

CPUCLK8T1

GNDCPU

VDDCPU

Supply for CPU clocks, 3.3V nominal

Complementary clock of differential 3.3V push-pull K8 pair.

True clock of differential 3.3V push-pull K8 pair.

Ground pin.

CPUCLK8C0

CPUCLK8T0

GND

FS2

Frequency select pin.

FS1/REF1

FS0/REF0

VDDREF

I/O

PWR

Frequency select latch input pin / 14.318 MHz reference clock.

Ref, XTAL power supply, nominal 3.3V

0959C—03/13/06

2

ICS932S801

General Description

The ICS932S801 is a main clock synthesizer chip that, when paired with ICS9DB108, provides all clocks required by

Serverworks GC-HT-based servers.

An SMBus interface allows full control of the device.

Block Diagram

REF(1:0)

X1

XTAL

OSC.

48MHz(1:0)

PCICLK(3:0)

FIXED PLL

X2

PCI33

DIV

HTT66

DIV

HTTCLK(3:0)

CPU PLL

CPU

DIV

FS(2:0)

PD#

CPUCLK8(3:0)

SPREAD

CONTROL

LOGIC

SDATA

SCLK

SRC

DIV1

SRC PLL

SRCCLK(0)

Skew Characteristics

Skew

Window

Parameter

Description

Test Conditions

Unit

T

i

m

e

Measured at crossing points

of CPUCLKT rising edges

Tsk_CPU_CPU

CPU to CPU Skew

250

2000

500

ps

Meastured at crossing point

for CPUCLKT and 1.5V for

PCI clock

I

Tsk_CPU_PCI

CPU to PCI skew

ps

n

d

e

p

e

n

e

n

t

Measured between rising

edges at 1.5V

Tsk_PCI33-HT66 PCI33 to HT66 skew

Meastured at crossing point

Tsk_CPU_HT66 CPU to HT66 skew for CPUCLKT and 1.5V for

HT66 clock

2000

Measured at crossing points

of CPUCLKT rising edges

T

i

m

e

Tsk_CPU_CPU

Tsk_CPU_PCI

CPU to CPU Skew

CPU to PCI skew

200

ps

Meastured at crossing point

for CPUCLKT and 1.5V for

PCI clock

V

a

r

Measured between rising

edges at 1.5V

Tsk_PCI33-HT66 PCI33 to HT66 skew

i

a

n

t

Meastured at crossing point

Tsk_CPU_HT66 CPU to HT66 skew for CPUCLKT and 1.5V for

HT66 clock

0959C—03/13/06

3

ICS932S801

Table1: SRC Frequency Selection Table

SRCFS1

B5b3

SRCFS0

B5b2

SRCCLK

(MHz)

0

1

0

1

0

1

100.00

101.00

102.00

104.00

Table 2: CPU Divider Ratios

Divider (3:2)

01

0100

0101

0110

0111

10

1000

1001

1010

1011

11

1100

1101

1110

1111

MSB

16

24

40

120

Div

Bit

00

01

10

11

00

0000

0001

0010

0011

2

3

5

15

Div

4

6

10

30

Div

8

12

20

60

Div

LSB

Address

Table 3: HTT Divider Ratios

Divider (3:2)

01

0100

0101

0110

0111

10

1000

1001

1010

1011

11

1100

1101

1110

1111

MSB

32

24

40

120

Div

Bit

00

01

10

11

00

0000

0001

0010

0011

4

3

5

15

Div

8

6

10

30

Div

16

12

20

60

Div

LSB

Address

Table 4: SRC Divider Ratios

Divider (3:2)

01

0100

0101

0110

0111

10

1000

1001

1010

1011

11

1100

1101

1110

1111

MSB

16

24

40

56

Bit

00

01

10

11

00

0000

0001

0010

0011

2

3

5

7

Div

4

6

10

14

Div

8

12

20

28

Div

LSB

Address

Div

0959C—03/13/06

4

ICS932S801

Absolute Maximum Ratings

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 3.8V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD+3.8 V

Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . Input ESD protection usung human body model > 1KV

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These

ratings are stress specifications only and functional operation of the device at these or any other conditions above those

listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect product reliability.

Electrical Characteristics - Input/Supply/Common Output Parameters

T_A= 0 - 70°C; Supply Voltage V_DD= 3.3 V +/-5%

PARAMETER

SYMBOL

V_IH

CONDITIONS

3.3 V +/-5%

MIN

2

TYP

MAX UNITS NOTES

V

_DD+ 0.3

Input High Voltage

V

1

V_IL

I_IH

V

_SS- 0.3

-5

Input Low Voltage

Input High Current

0.8

5

V

1

V_IN= V_DD

V_IN= 0 V; Inputs with no pull-up

resistors

uA

I_IL1

-5

Input Low Current

I_IL2

V_IN= 0 V; Inputs with pull-up resistors

all outputs driven

-200

uA

1

I_DD3.3OP

I_DD3.3PD

F_i

L_pin

C_IN

Operating Current

Powerdown Current

Input Frequency³

Pin Inductance¹

325

100

mA

MHz

nH

pF

V_DD= 3.3 V

14.31818

3

1

7

5

6

5

Logic Inputs

Output pin capacitance

X1 & X2 pins

Input Capacitance¹

C_OUT

C_INX

pF

From V_DDPower-Up or de-assertion of

Clk Stabilization^1,2

T_STAB

3

ms

1,2

PD# to 1st clock

Modulation Frequency

SMBus Voltage

Low-level Output Voltage

Current sinking at V_OL= 0.4 V

SCLK/SDATA

Triangular Modulation

30

2.7

33

5.5

0.4

kHz

V

1

V_DD

V_OL

I_PULLUP

@ I_PULLUP

4

mA

T_RI2C

(Max VIL - 0.15) to (Min VIH + 0.15)

(Min VIH + 0.15) to (Max VIL - 0.15)

1000

300

ns

1

Clock/Data Rise Time³

SCLK/SDATA

Clock/Data Fall Time³

T_FI2C

¹Guaranteed by design and characterization, not 100% tested in production.

²See timing diagrams for timing requirements.

³Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet

ppm frequency accuracy on PLL outputs.

0959C—03/13/06

5

ICS932S801

Electrical Characteristics - K8 Push Pull Differential Pair

T_A= 0 - 70°C; V_DD= 3.3 V +/-5%; C_L=AMD64 Processor Test Load

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS NOTES

Measured at the AMD64 processor's

test load. 0 V +/- 400 mV (differential

measurement)

Rising Edge Rate

δV/δt

2

10

V/ns

1

Falling Edge Rate

δV/δt

V/ns

V

1

V_DIFF

Differential Voltage

Change in V_{DIFF_DC}

Magnitude

0.4 1.25 2.3

-150

∆V_DIFF

V_CM

150 mV

1

Measured at the AMD64 processor's

test load. (single-ended measurement)

Common Mode Voltage

1.05 1.25 1.45

V

Change in Common

Mode Voltage

∆V_CM

-200

0

200 mV

Measurement from differential

wavefrom. Maximum difference of cycle

time between 2 adjacent cycles.

t_jcyc-cyc

Jitter, Cycle to cycle

100 200

ps

1

Measured using the JIT2 software

package with a Tek 7404 scope.

TIE (Time Interval Error) measurement

technique:

t_ja

Jitter, Accumulated

-1000

45

1000

1,2,3

Sample resolution = 50 ps,

Sample Duration = 10 µs

Measurement from differential

d_t3

Duty Cycle

Output Impedance

Group Skew

53

35 55

250

%

Ω

1

wavefrom

Average value during switching

transition. Used for determining series 15

R_ON

termination value.

Measurement from differential

wavefrom

t_src-skew

ps

¹Guaranteed by design and characterization, not 100% tested in production.

²All accumulated jitter specifications are guaranteed assuming that REF is at 14.31818MHz

³Spread Spectrum is off

0959C—03/13/06

6

ICS932S801

Electrical Characteristics - SRC 0.7V Current Mode Differential Pair

T_A= 0 - 70°C; V_DD= 3.3 V +/-5%; C_L=2pF, R_S=33.2Ω, R_P=49.9Ω, Ι_REF= 475Ω

PARAMETER

SYMBOL

Zo

CONDITIONS

V_O= V_x

MIN

TYP

MAX UNITS NOTES

Current Source Output

Impedance

3000

1

Ω

Statistical measurement on

single ended signal using

oscilloscope math function.

Measurement on single ended

signal using absolute value.

Voltage High

Voltage Low

VHigh

VLow

660

850

1,3

mV

-150

150

Max Voltage

Min Voltage

Vovs

Vuds

1150

1

mV

-300

250

Crossing Voltage (abs) Vcross(abs)

350

12

550

1

Variation of crossing over all

edges

see Tperiod min-max values

100.00 MHz nominal

100.00 MHz spread

@100.00MHz nominal/spread

V_OL= 0.175V, V_OH= 0.525V

Crossing Voltage (var)

Long Accuracy

d-Vcross

ppm

140

300

-300

ppm

ns

ps

1,2

2

1,2

1

9.9970 10.0000 10.0030

Average period

Tperiod

9.9970

9.8720

175

10.0530

Absolute min period

Rise Time

Fall Time

Rise Time Variation

Fall Time Variation

Tabsmin

t_r

t_f

d-t_r

d-t_f

700

125

V_OH= 0.525V V_OL= 0.175V

175

30

Measurement from differential

wavefrom

Measurement from differential

d_t3

Duty Cycle

45

55

N/A

86

%

ps

1

t_src-skew

Group Skew

wavefrom

PCI Express Gen 1 phase jitter

CPU=200MHz, Spread off

PCI Express Gen 1 phase jitter

CPU=200MHz, Spread on

Measurement from differential

wavefrom

38

52

1, 4

1

t_jphase-pcie1

Jitter, Phase

86

t_jcyc-cyc

Jitter, Cycle to cycle

100

¹Guaranteed by design and characterization, not 100% tested in production.

²All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz

³I_REF= V_DD/(3xR_R). For R_R= 475Ω (1%), I_REF= 2.32mA. I_OH= 6 x I_REFand V_OH= 0.7V @ Z_O=50Ω.

⁴Per PCI SIG method for PCI Express Gen 1. Visit http://www.pcisig.com for details.

0959C—03/13/06

7

ICS932S801

Electrical Characteristics - PCICLK 33 MHz, HTTCLK 66 MHz Clocks

T_A= 0 - 70°C; VDD=3.3V +/-5%; C_L= 20 pF (unless otherwise specified)

PARAMETER

Long Accuracy

SYMBOL

ppm

CONDITIONS

MIN

TYP MAX UNITS Notes

see Tperiod min-max values

33.33MHz output nominal

33.33MHz output spread

66.67MHz output nominal

66.67MHz output spread

I_OH= -1 mA

-300

300

ppm

1,2

2

29.9910

14.9955

2.4

30.0090 ns

30.1598 ns

15.0045 ns

15.0799 ns

V

T_period

PCI33 Clock period

T_period

HTT66 Clock period

V_OH

V_OL

Output High Voltage

Output Low Voltage

1

I_OL= 1 mA

V _OH@MIN = 1.0 V

_OH@ MAX = 3.135 V

V_OL@ MIN = 1.95 V

V_OL@ MAX = 0.4 V

Rising edge rate

Falling edge rate

V_T= 1.5 V

0.55

-33

38

V

1

-33

30

mA

I_OH

I_OL

Output High Current

Output Low Current

V

Edge Rate

Duty Cycle

1

45

4

55

200

250

V/ns

%

1

δ /δ

V t

δ /δ

V t

d_t1

t_sk1

V_T= 1.5 V

Skew

ps

t_jcyc-cyc

V_T= 1.5 V

Jitter, Cycle to cycle

¹Guaranteed by design and characterization, not 100% tested in production.

ps

²All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is at 14.31818MHz

Electrical Characteristics - 48MHz

T_A= 0 - 70°C; V_DD= 3.3 V +/-5%; C_L= 20 pF (unless otherwise specified)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS Notes

Long Accuracy

Clock period

Output High Voltage

ppm

T_period

V_OH

see Tperiod min-max values

48.00MHz output nominal

I_OH= -1 mA

-100

20.8257

2.4

100

20.8340 ns

V

ppm

1,2

2

1

V_OL

I_OL= 1 mA

_OH@ MIN = 1.0 V

_OH@ MAX = 3.135 V

_OL@MIN = 1.95 V

_OL@ MAX = 0.4 V

Rising edge rate

Falling edge rate

V_T= 1.5 V

Output Low Voltage

0.55

V

mA

V/ns

%

1

V

-33

30

I_OH

Output High Current

-33

I_OL

Output Low Current

38

4

Edge Rate

δV/δt

d_t1

1

Duty Cycle

45

55

50

200

t_sk1

V_T= 1.5 V

Skew

ps

t_jcyc-cyc

V_T= 1.5 V

Jitter, Cycle to cycle

ps

¹Guaranteed by design and characterization, not 100% tested in production.

²All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is at

14.31818MHz

0959C—03/13/06

8

ICS932S801

Electrical Characteristics - REF-14.318MHz

T_A= 0 - 70°C; V_DD= 3.3 V +/-5%; C_L= 27 pF (unless otherwise specified)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP MAX UNITS Notes

Long Accuracy

Clock period

Output High Voltage

Output Low Voltage

ppm

T_period

V_OH

see Tperiod min-max values

14.318MHz output nominal

I_OH= -1 mA

-300

69.8270

2.4

300

69.8550

ppm

ns

V

1

2

1

V_OL

I_OL= 1 mA

V _OH@MIN = 1.0 V,

0.4

-23

V

I_OH

I_OL

Output High Current

Output Low Current

-29

29

mA

1

V

_OH@MAX = 3.135 V

V_OL@MIN = 1.95 V,

_OL@MAX = 0.4 V

27

V

Edge Rate

δV/δt

d_t1

Rising edge rate

Falling edge rate

V_T= 1.5 V

1

2

V/ns

%

1

Duty Cycle

45

55

t_sk1

V_T= 1.5 V

Skew

50

ps

t_jcyc-cyc

V_T= 1.5 V

Jitter, Cycle to cycle

¹Guaranteed by design and characterization, not 100% tested in production.

²All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is

at 14.31818MHz

1000

ps

0959C—03/13/06

9

ICS932S801

General SMBus serial interface information

How to Read:

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address D2_(H)

• ICS clock will acknowledge

• Controller (host) will send start bit.

• Controller (host) sends the write address D2_(H)

• ICS clock will acknowledge

• Controller (host) sends the begining byte location = N

• ICS clock will acknowledge

• Controller (host) sends the begining byte

location = N

• Controller (host) sends the data byte count = X

• ICS clock will acknowledge

• Controller (host) starts sending Byte N through

Byte N + X -1

• ICS clock will acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address D3_(H)

• ICS clock will acknowledge

(see Note 2)

• ICS clock will send the data byte count = X

• ICS clock sends Byte N + X -1

• ICS clock will acknowledge each byte one at a time

• ICS clock sends Byte 0 through byte X (if X_(H)

was written to byte 8).

• Controller (host) sends a Stop bit

• Controller (host) will need to acknowledge each byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

Index Block Read Operation

Index Block Write Operation

Controller (Host)

ICS (Slave/Receiver)

Controller (Host)

ICS (Slave/Receiver)

T

starT bit

T

Slave Address D2_(H)

WR

WRite

WR

WRite

ACK

Beginning Byte = N

Data Byte Count = X

Beginning Byte N

RT

Repeat starT

Slave Address D3_(H)

RD

ReaD

ACK

Data Byte Count = X

Beginning Byte N

ACK

Byte N + X - 1

ACK

P

stoP bit

Byte N + X - 1

N

P

Not acknowledge

stoP bit

0959C—03/13/06

10

ICS932S801

SMBus Table: Frequency Select and Spread Control Register

Byte 0

Pin #

Name

Control Function

Type

0

1

PWD

Latched Input or SMBus

Frequency Select

Latched

Inputs

-

FS Source

RW

SMBus

0

Bit 7

Spread Enable for CPU

-

CPU SS_EN

SRC SS_EN

RW

OFF

ON

0

Bit 6

Bit 5

and SRC PLLs.

Setting

SPREAD_EN to '1',

forces Spread ON for

both PLLs.

OFF

ON

-

Reserved

FS3

Reserved

RW

Reserved

0

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Freq Select Bit 3

Freq Select Bit 2

Freq Select Bit 1

Freq Select Bit 0

See Functionality Table on

Page 1

FS2

FS1

FS0

Latched

SMBus Table: Output Control Register

Byte 1

Bit 7

Pin #

Name

Control Function

Output Enable

Type

0

1

PWD

PCICLK3

PCICLK2

PCICLK1

PCICLK0

HTTCLK3

HTTCLK2

HTTCLK1

HTTCLK0

RW Disable (Low)

Enable

1

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: Output Control Register

Byte 2

Bit 7

Pin #

Name

48MHz_1

48MHz_0

REF1

Control Function

Output Enable

When Disabled

CPUCLKT = 0

CPUCLKC = 1

Type

0

1

PWD

RW Disable (Low)

RW

Enable

1

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

REF0

CPUCLK8(3)

CPUCLK8(2)

CPUCLK8(1)

CPUCLK8(0)

Disable

0959C—03/13/06

11

ICS932S801

SMBus Table: SRCCLK(0) Output Control Register

Byte 3

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Pin #

Name

Control Function

Reserved

Type

RW

0

1

PWD

-

Reserved

0

Reserved

SRCCLK Power Down

-

Bit 1

Bit 0

SRCCLK0 PD

SRCCLK0

RW

Driven

Hi-Z

0

1

Drive Mode

Output Enable

RW Disable (Hi-Z)

Enable

SMBus Table: 48MHz Drive Strength Control Register

Byte 4

Bit 7

Pin #

Name

Reserved

48MHz_1 DS

48MHz_0 DS

Control Function

Reserved

Type

RW

0

1

PWD

-

5

4

Reserved

1X

Reserved

2X

0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

Drive Strength Control

1X

2X

SMBus Table: SRC Frequency Select Register

Byte 5

Bit 7

Pin #

Name

Control Function

Reserved

Type

RW

0

1

PWD

-

Reserved

SRCFS1

SRCFS0

Reserved

See Table 1:

SRC Frequency Select

Reserved

0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

SRC FS bit 1

SRC FS bit 0

Reserved

SMBus Table: Device ID Register

Byte 6

Bit 7

Pin #

Name

Control Function

Device ID MSB

Device ID 6

Device ID 5

Device ID4

Device ID3

Device ID2

Device ID1

Device ID LSB

Type

R

0

-

1

-

PWD

-

DevID 7

DevID 6

DevID 5

DevID 4

DevID 3

DevID 2

DevID 1

DevID 0

1

0

1

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0959C—03/13/06

12

ICS932S801

SMBus Table: Vendor ID Register

Byte 7

Bit 7

Pin #

Name

RID3

RID2

RID1

RID0

VID3

VID2

VID1

VID0

Control Function

Type

R

0

-

1

-

PWD

-

X

0

1

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Revision ID

VENDOR ID

(0001 = ICS)

SMBus Table: Byte Count Register

Byte 8

Bit 7

Pin #

Name

BC7

BC6

BC5

BC4

BC3

BC2

BC1

BC0

Control Function

Type

RW

0

1

PWD

-

0

1

0

1

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Writing to this register will

configure how many bytes

will be read back, default is

9 bytes.

Byte Count Programming

b(7:0)

SMBus Table: Reserved Register

Byte 9

Bit 7

Pin #

Name

Control Function

Reserved

Type

RW

0

1

PWD

-

Reserved

0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: M/N Programming Enable

Byte 10

Pin #

Name

Control Function

CPU and SRC PLL M/N

Programming Enable

Reserved

Type

0

1

PWD

-

Bit 7

M/N_EN

RW

Disable

Enable

0

-

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

RW

-

0

Reserved

0959C—03/13/06

13

ICS932S801

SMBus Table: CPU Frequency Control Register

Byte 11

Bit 7

Pin #

Name

N Div8

N Div9

M Div5

M Div4

M Div3

M Div2

M Div1

Control Function

N Divider Prog bit 8

N Divider Prog bit 9

Type

0

1

PWD

X

-

RW The decimal representation

RW of M and N Divier in Byte

RW

RW the CPU VCO frequency.

RW Default at power up = latch-

RW

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

11 and 12 will configure

M Divider Programming

bit (5:0)

in or Byte 0 Rom table.

RW VCO Frequency = 14.318

x [NDiv(9:0)+8] /

-

M Div0

RW

X

Bit 0

[MDiv(5:0)+2]

SMBus Table: CPU Frequency Control Register

Byte 12

Bit 7

Pin #

Name

N Div7

N Div6

N Div5

N Div4

N Div3

N Div2

N Div1

Control Function

Type

RW

0

1

PWD

X

-

The decimal representation

of M and N Divier in Byte

11 and 12 will configure

the CPU VCO frequency.

Default at power up = latch-

in or Byte 0 Rom table.

VCO Frequency = 14.318

x [NDiv(9:0)+8] /

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

N Divider Programming

Byte12 bit(7:0) and

Byte11 bit(7:6)

-

N Div0

RW

X

Bit 0

[MDiv(5:0)+2]

SMBus Table: CPU Spread Spectrum Control Register

Byte 13

Bit 7

Pin #

Name

SSP7

SSP6

SSP5

SSP4

SSP3

SSP2

SSP1

SSP0

Control Function

Type

RW

0

1

PWD

X

-

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

These Spread Spectrum

bits in Byte 13 and 14 will

program the spread

Spread Spectrum

Programming bit(7:0)

pecentage of CPU

SMBus Table: CPU Spread Spectrum Control Register

Byte 14

Bit 7

Pin #

Name

Reserved

SSP14

SSP13

SSP12

SSP11

SSP10

SSP9

Control Function

Type

R

0

-

1

-

PWD

0

X

-

Reserved

RW

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

These Spread Spectrum

bits in Byte 13 and 14 will

program the spread

Spread Spectrum

Programming bit(14:8)

pecentage of CPU

SSP8

0959C—03/13/06

14

ICS932S801

SMBus Table: SRC Frequency Control Register

Byte 15

Bit 7

Pin #

Name

N Div8

N Div9

M Div5

M Div4

M Div3

M Div2

M Div1

Control Function

N Divider Prog bit 8

N Divider Prog bit 9

Type

RW

0

1

PWD

X

-

The decimal representation

of M and N Divier in Byte

15 and 16 will configure

the SRC VCO frequency.

Default at power up = latch-

in or Byte 0 Rom table.

VCO Frequency = 14.318

x [NDiv(9:0)+8] /

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

M Divider Programming

bits

-

M Div0

RW

X

Bit 0

[MDiv(5:0)+2]

SMBus Table: SRC Frequency Control Register

Byte 16

Bit 7

Pin #

Name

N Div7

N Div6

N Div5

N Div4

N Div3

N Div2

N Div1

Control Function

Type

0

1

PWD

X

-

RW The decimal representation

RW of M and N Divier in Byte

RW

RW the SRC VCO frequency.

RW Default at power up = latch-

RW

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

15 and 16 will configure

N Divider Programming

b(7:0)

in or Byte 0 Rom table.

RW VCO Frequency = 14.318

x [NDiv(9:0)+8] /

-

N Div0

RW

X

Bit 0

[MDiv(5:0)+2]

SMBus Table: SRC Spread Spectrum Control Register

Byte 17

Bit 7

Pin #

Name

SSP7

SSP6

SSP5

SSP4

SSP3

SSP2

SSP1

SSP0

Control Function

Type

RW

0

1

PWD

X

-

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

These Spread Spectrum

bits in Byte 17 and 18 will

program the spread

Spread Spectrum

Programming b(7:0)

pecentage of SRC

SMBus Table: SRC Spread Spectrum Control Register

Byte 18

Bit 7

Pin #

Name

Reserved

SSP14

SSP13

SSP12

SSP11

SSP10

SSP9

Control Function

Type

R

0

-

1

-

PWD

0

X

-

Reserved

RW

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

These Spread Spectrum

bits in Byte 17 and 18 will

program the spread

Spread Spectrum

Programming b(14:8)

pecentage of SRC

SSP8

0959C—03/13/06

15

ICS932S801

SMBus Table: Programmable Output Divider Register

Byte 19

Bit 7

Pin #

Name

Control Function

Type

RW

0

1

PWD

X

-

CPUDiv3

CPUDiv2

CPUDiv1

CPUDiv0

HTTDiv3

HTTDiv2

HTTDiv1

HTTDiv0

CPU Divider Ratio

Programming Bits

See Table 2:

CPU Divider Ratios

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

HTT Divider Ratio

Programming Bits (PCI

divider is always 2x the

HTT divider or 1/2 freq.)

See Table 3:

HTT Divider Ratios

SMBus Table: Programmable Output Divider Register

Byte 20

Bit 7

Pin #

Name

Control Function

Reserved

Type

R

RW

0

-

1

-

PWD

X

-

Reserved

SRC_Div3

SRC_Div2

SRC_Div1

SRC_Div0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

SRC_ Divider Ratio

Programming Bits

See Table 4:

SRC Divider Ratios

SMBusTable: Test Byte Register

Byte 21

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Test Function

Test Result

Reserved

Test

Type

RW

PWD

`

ICS ONLY TEST

0

0959C—03/13/06

16

ICS932S801

Shared Pin Operation -

Input/Output Pins

Figure 1 shows a means of implementing this function

when a switch or 2 pin header is used. With no jumper is

installed the pin will be pulled high. With the jumper in

place the pin will be pulled low. If programmability is not

necessary, than only a single resistor is necessary. The

programming resistors should be located close to the

series termination resistor to minimize the current loop

area. It is more important to locate the series termination

resistor close to the driver than the programming resistor.

The I/O pins designated by (input/output) on the

ICS932S801 serve as dual signal functions to the device.

During initial power-up, they act as input pins. The logic

level (voltage) that is present on these pins at this time

is read and stored into a 5-bit internal data latch. At the

end of Power-On reset, (see AC characteristics for timing

values), the device changes the mode of operations for

these pins to an output function. In this mode the pins

produce the specified buffered clocks to external loads.

To program (load) the internal configuration register for

these pins, a resistor is connected to either the VDD

(logic 1) power supply or the GND (logic 0) voltage

potential. A 10 Kilohm (10K) resistor is used to provide

both the solid CMOS programming voltage needed during

the power-up programming period and to provide an

insignificant load on the output clock during the subsequent

operating period.

Via to

VDD

Programming

Header

2K W

Via to Gnd

Device

Pad

8.2K W

Clock trace to load

Series Term. Res.

Fig. 1

0959C—03/13/06

17

ICS932S801

300 mil SSOP

In Millimeters

COMMON DIMENSIONS

c

N

In Inches

COMMON DIMENSIONS

SYMBOL

L

MIN

2.41

0.20

0.13

MAX

2.80

0.40

0.34

0.25

MIN

.095

.008

.005

MAX

.110

.016

.0135

.010

A

A1

b

E1

E

INDEX

AREA

c

D

E

E1

e

h

L

SEE VARIATIONS

10.03

7.40

10.68

7.60

.395

.291

.420

.299

1

22

0.635 BASIC

0.025 BASIC

α

hh xx 4455°°

0.38

0.50

0.64

1.02

.015

.020

.025

.040

D

N

a

SEE VARIATIONS

0°

8°

0°

8°

A

VARIATIONS

D mm.

D (inch)

N

A1

MIN

15.75

MAX

16.00

MIN

.620

MAX

.630

- CC --

48

e

SEATING

PLANE

Reference Doc.: JEDEC Publication 95, MO-118

10-0034

b

.10 (.004)

C

Ordering Information

ICS932S801yFLFT

Example:

ICS XXXX y F - LF T

Designation for tape and reel packaging

RoHS Compliant

Package Type

F = SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV = Standard Device

0959C—03/13/06

18

ICS932S801

c

(240 mil)

(20 mil)

N

In Millimeters

In Inches

SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS

L

MIN

--

0.05

0.80

0.17

0.09

MAX

1.20

0.15

1.05

0.27

0.20

MIN

--

.002

.032

.007

.0035

MAX

.047

.006

.041

.011

.008

A

A1

A2

b

E1

E

INDEX

AREA

c

1

22

D

E

SEE VARIATIONS

8.10 BASIC

SEE VARIATIONS

0.319 BASIC

a

D

E1

e

6.00

6.20

.236

.244

0.50 BASIC

0.020 BASIC

L

0.45

0.75

.018

.030

A

N

SEE VARIATIONS

A2

a

aaa

0°

--

8°

0.10

0°

--

8°

.004

A1

- CC --

VARIATIONS

e

SEATING

PLANE

b

D mm.

D (inch)

N

aaa

C

MIN

12.40

MAX

12.60

MIN

.488

MAX

.496

48

Reference Doc.: JEDEC Publication 95, MO-153

10-0039

Ordering Information

ICS932S801yGLFT

Example:

ICS XXXX y G - LF T

Designation for tape and reel packaging

RoHS Compliant

Package Type

G = TSSOP

Revision Designator (will not correlate with datasheet revision)

DeviceType (consists of 3 or 4 digit numbers)

Prefix

ICS, AV = Standard Device

0959C—03/13/06

19

ICS932S801

Revision History

Rev. Issue Date Description

Page #

1. Updated Electrical Characteristics Tables:

i) Changed SRC jitter from 125ps to 100ps;

ii) Changed PCI/HTT Skew from 500ps to 200ps;

iii) Added USB Skew, 50ps.

iv) Change REF Skew from 500ps to 50ps.

14-16

18-19

B

C

5/18/2005 2. Updated LF Ordering Information from "Lead Free" to "RoHS Compliant".

1. Correct pin description of PD# (Pin 21). It does not contain a pull up resistor.

3/13/2006 2. Added PCIe Gen 1 phase noise numbers to SRC output characterisitics

2, 7

0959C—03/13/06

20


型号：	ICS932S801AFLFT
厂家：	ETC
描述：	K8 Clock Chip for Serverworks GC-HT 2-Way Servers
文件：	总20页 (文件大小：194K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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