IDT74ALVC1G07DY [ETC]
LOGIC GATE|BUFFER|AVC/ALVC-CMOS|TSSOP|6PIN|PLASTIC ; 逻辑门| BUFFER | AVC / ALVC -CMOS | TSSOP | 6PIN |塑料\n
| 型号： | IDT74ALVC1G07DY |
| 厂家： | 
ETC |
| 描述： | LOGIC GATE|BUFFER|AVC/ALVC-CMOS|TSSOP|6PIN|PLASTIC
|
| 文件： | 总6页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS SINGLE
IDT74ALVC1G07
GATE BUFFER/DRIVER
WITH OPEN DRAIN OUTPUT
FEATURES:
DESCRIPTION:
–
–
0.5 MICRON CMOS Technology
This buffer/driveris builtusingadvanceddualmetalCMOStechnology.
TheoutputsoftheALVC1G07deviceareopen-drainandcanbeconnected
tootheropen-drainoutputstoimplementactive-lowwired-ORoractive-high
wired-ANDfunctions.The maximumsinkcurrentis 24mA.
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 1.65V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4µW typ. static)
Rail-to-Rail output swing for increased noise margin
Available in PSOP package
–
–
–
–
–
–
The ALVC1G07 has been designed with a 24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speedperformance.
Drive Features for ALVC1G07:
APPLICATIONS:
–
–
High Output Drivers: 24mA
Suitable for heavy loads
• 3.3V High Speed Systems
• 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
2
4
1
2
3
5
4
N C
A
V C C
A
Y
S O 5 -1
G N D
Y
PSOP
TOP VIEW
FUNCTION TABLE (1)
PIN DESCRIPTION
Input
Output
Pin Names
Description
A
H
L
Y
H
L
A
Y
Data Input
Data Output
NC
No Internal Connection
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
INDUSTRIAL TEMPERATURE RANGE
FEBRUARY 2000
1
c
1999 Integrated Device Technology, Inc.
DSC-5415/-
IDT74ALVC1G07
INDUSTRIALTEMPERATURERANGE
3.3V CMOS SINGLE GATE BUFFER/DRIVER
o
ABSOLUTE MAXIMUM RATINGS (1)
A
CAPACITANCE(T = +25 C, f = 1.0MHz)
Parameter(1)
Conditions
Typ.
Max.
Unit
Symbol
Description
Max.
Unit
Symbol
(2)
CIN
Input Capacitance
VIN = 0V
5
7
pF
VTERM
Terminal Voltage with Respect to GND
– 0.5 to + 4.6
V
(3)
COUT
CI/O
Output Capacitance
I/O Port Capacitance
VOUT = 0V
VIN = 0V
7
7
9
9
pF
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC + 0.5
V
TSTG
IOUT
Storage Temperature
DC Output Current
– 65 to + 150
– 50 to + 50
± 50
°C
pF
ALVC 1G Link
mA
mA
NOTE:
1. As applicable to the device type.
IIK
Continuous Clamp Current,
VI < 0 or VI > VCC
IOK
Continuous Clamp Current, VO < 0
– 50
mA
mA
ICC
ISS
Continuous Current through
each VCC or GND
±100
ALVC 1G Link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
CC
Operating Condition: TA = – 40°C to +85°C, V = 2.3V to 3.6V
(1)
Typ.
Symbol
Parameter
Test Conditions
VCC = 1.65V to 1.95V
Min.
Max.
Unit
VIH
Input HIGH Voltage Level
0.65 x VCC
—
—
—
—
—
V
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 1.65V to 1.95V
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V
1.7
2
—
VIL
Input LOW Voltage Level
—
—
—
—
—
—
—
—
—
—
—
0.35 x VCC
0.7
V
—
—
0.8
IIH
Input HIGH Current
VI = VCC
—
± 5
µA
IIL
Input LOW Current
VCC = 3.6V
VI = GND
VO = VCC
VO = GND
—
± 5
IOZH
IOZL
VIK
VH
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
VCC = 3.6V
—
± 10
± 10
– 1.2
—
µA
µA
V
—
VCC = 2.3V, IIN = – 18mA
VCC = 3.3V
– 0.7
100
0.1
mV
µA
ICCL
ICCH
ICCZ
∆ICC
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
10
Quiescent Power Supply
Current Variation
One input at VCC − 0.6V,
other inputs at VCC or GND
—
—
750
µA
ALVC 1G Link
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2
IDT74ALVC1G07
3.3V CMOS SINGLE GATE BUFFER/DRIVER
INDUSTRIALTEMPERATURERANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Max.
Unit
VOL
Output LOW Voltage
VCC = 1.65V to 3.6V
IOL = 0.1mA
IOL = 4mA
IOL = 6mA
IOL = 12mA
IOL = 12mA
IOL = 24mA
—
0.2
V
VCC = 1.65V
VCC = 2.3V
0.45
0.4
—
—
—
—
0.7
VCC = 2.7V
VCC = 3.0V
0.4
0.55
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to + 85°C.
o
OPERATING CHARACTERISTICS, T = 25 C
A
VCC = 1.8V ± 0.15V
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Symbol
Parameter
Test Conditions
Typical
Typical
Typical
Unit
CPD
Power Dissipation Capacitance
CL = 0pF, f = 10Mhz
4
5
6
pF
SWITCHING CHARACTERISTICS(1)
VCC = 1.8V ± 0.15V
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
tPLZ
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
A to Y
1
6
0.5
3
3.3
1
2.8
ns
tPZL
NOTE:
A
1. See test circuits and waveforms. T = – 40°C to + 85°C.
3
IDT74ALVC1G07
INDUSTRIALTEMPERATURERANGE
3.3V CMOS SINGLE GATE BUFFER/DRIVER
TEST CIRCUITS AND WAVEFORMS:
TEST CONDITIONS
Symbol
PROPAGATION DELAY
(1)
(1)
(2)
VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V
Unit
VLOAD
6
6
2 xVcc
Vcc
V
VIH
SAME PHASE
INPUT TRANSITION
T
V
VIH
VT
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
V
0V
tPHL
tPLH
Vcc / 2
150
VOH
OUTPUT
V
LZ
mV
mV
T
V
VOL
VHZ
CL
150
PLH
tPHL
t
VIH
VT
0V
30
pF
ALVC 1G Link
OPPOSITE PHASE
INPUT TRANSITION
ALVC 1G Link
ENABLE AND DISABLE TIMES
TEST CIRCUITS FOR ALL OUTPUTS
LOAD
V
DISABLE
ENABLE
CC
V
IH
V
Open
GND
CONTROL
INPUT
VT
0V
500Ω
tPZL
tPLZ
VIN
VOUT
Pulse(1, 2)
Generator
VLOAD/2
VT
VLOAD/2
OUTPUT
NORMALLY
LOW
D.U.T.
SWITCH
CLOSED
VLZ
VOL
tPHZ
500Ω
tPZH
T
R
CL
OUTPUT
NORMALLY
HIGH
OH
V
SWITCH
OPEN
VT
0V
VHZ
DEFINITIONS:
ALVC 1G Link
0V
CL= Load capacitance: includes jig and probe capacitance.
ALVC 1G Link
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
NOTES:
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
SWITCH POSITION
SET-UP, HOLD, AND RELEASE TIMES
Test
Switch
VIH
VT
0V
tPZL
VLOAD
DATA
INPUT
tPLZ
tSU
tH
tPHZ/tPZH
VLOAD
IH
V
TIMING
INPUT
VT
0V
tREM
VIH
VT
0V
ASYNCHRONOUS
CONTROL
VIH
VT
0V
SYNCHRONOUS
CONTROL
tSU
tH
ALVC 1G Link
PULSE WIDTH
LOW-HIGH-LOW
PULSE
VT
VT
tW
HIGH-LOW-HIGH
PULSE
ALVC 1G Link
4
IDT74ALVC1G07
3.3V CMOS SINGLE GATE BUFFER/DRIVER
INDUSTRIALTEMPERATURERANGE
1.8V ± 0.15V TEST CIRCUITS AND WAVEFORMS:
TESTCONDITIONS
PROPAGATIONDELAY
(1)
VCC = 1.8V ± 0.15V
Symbol
Unit
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
VLOAD
2 x VCC
VCC
V
VIH
VT
V
V
tPHL
tPHL
tPLH
VOH
VT
OUTPUT
VCC / 2
150
VOL
V
LZ
mV
mV
t
PLH
VHZ
CL
150
VIH
VT
OPPOSITE PHASE
INPUT TRANSITION
30
pF
ALVC 1G Link
0V
ALVC 1G Link
TEST CIRCUITS FOR ALL OUTPUTS
ENABLEANDDISABLETIMES
VLOAD
DISABLE
ENABLE
VCC
VIH
VT
Open
GND
CONTROL
INPUT
0V
1000Ω
tPZL
tPLZ
VIN
VOUT
Pulse(1)
Generator
VLOAD/2
VT
VLOAD/2
OUTPUT
NORMALLY
LOW
D.U.T.
SWITCH
CLOSED
VLZ
VOL
tPHZ
tPZH
1000Ω
RT
CL
OUTPUT
NORMALLY
HIGH
VOH
VHZ
SWITCH
OPEN
VT
0V
DEFINITIONS:
ALVC 1G Link
0V
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
NOTE:
ALVC 1G Link
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
Generator.
NOTE:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
SET-UP, HOLD, AND RELEASE TIMES
SWITCHPOSITION
Test
tPZL
Switch
VIH
VT
0V
DATA
VLOAD
INPUT
tSU
tH
tPLZ
VIH
VT
0V
TIMING
INPUT
tPHZ/tPZH
VLOAD
tREM
VIH
VT
0V
ASYNCHRONOUS
CONTROL
VIH
VT
0V
SYNCHRONOUS
CONTROL
tSU
tH
ALVC 1G Link
PULSEWIDTH
LOW-HIGH-LOW
VT
VT
PULSE
tW
HIGH-LOW-HIGH
PULSE
ALVC 1G Link
5
IDT74ALVC1G07
INDUSTRIALTEMPERATURERANGE
3.3V CMOS SINGLE GATE BUFFER/DRIVER
ORDERINGINFORMATION
IDT
XX
ALVC XXX
XX
Device Type Package
Temp. Range
DY
Plastic Small Outline Package (SO5-1)
1G07
74
Single Gate Buffer/Driver with open Drain Output,
+24mA
– 40°C to +85°C
PICOGATE-LOGIC (DY) PACKAGES
Due to their small size, PicoGate-Logic packages require more complex symbolization guidelines. IDT’s 5-pin PSOP (DY) packaged devices
utilize a three-symbol name rule. The first symbol denotes device technology, the second symbol denotes device function, and the third symbol
denotes a wafer fab/assembly site code for internal tracking.
EXAMPLES:
1. A PicoGate-Logic device with package code LR* is an IDT74LVC1G79A.
2. A PicoGate-Logic device with package code GC* is an IDT74ALVC1G04.
PICOGATE-LOGIC (DY) PACKAGE SYMBOLIZATION GUIDELINES
TECHNOLOGY
ALVC
CODE
G
J
FUNCTION
00
CODE
A
B
ALVCH
02
LVC
L
04
U04
06
C
D
T
(1)
LVCH
07
V
08
E
14
F
32
G
79
R
86
H
125
126
132
M
N
Y
NOTE:
1. Code to be determined.
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www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6
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