IDT77V1264L200PG_技术文档

Quad Port PHY (Physical Layer)

for 25.6, 51.2, and 204.8 Mbps

ATM Networks and Backplane

Applications

IDT77V1264L200

Description

Features List

Performs the PHY-Transmission Convergence (TC) and

The IDT77V1264L200 is a member of IDT's family of products

supporting Asynchronous Transfer Mode (ATM) data communications

and networking. The IDT77V1264L200 implements the physical layer for

25.6 Mbps ATM, connecting four serial copper links (UTP Category 3

and 5) to one ATM layer device such as a SAR or a switch ASIC. The

IDT77V1264L200 also operates at 51.2 Mbps and 204.8 Mbps, and is

well suited to backplane driving applications.

Physical Media Dependent (PMD) Sublayer functions for

four 204.8 Mbps ATM channels

Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5

specifications for 25.6 Mbps physical interface

Operates at 25.6, 51.2, 102.4, 204.8 Mbps data rates

Individual Selection of Port Data Rates

Backwards Compatible with 77V1254L25

UTOPIA Level 1, UTOPIA Level 2, or DPI-4 Interface

3-Cell Transmit and Receive FIFOs

The 77V1264L200-ATM layer interface is selectable as either: 16-bit

UTOPIA Level 2, 8-bit UTOPIA Level 1 Multi-PHY, or quadruple 4-bit

DPI (Data Path Interface).

The IDT77V1264L200 is fabricated using IDT's state-of-the-art

CMOS technology, providing the highest levels of integration, perfor-

mance and reliability, with the low-power consumption characteristics of

CMOS.

LED Interface for status signalling

Supports UTP Category 3 and 5 physical media

Low-Power CMOS

3.3V supply with 5V tolerant inputs

144-pin PQFP Package (28 x 28 mm)

Commercial and Industrial Temperature Ranges

Block Diagram

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IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

1 of 49

December 6, 2001

DSC 6029

2001 Integrated Device Technology, Inc.

IDT77V1264L200

Mbps, as shown in Table 3. For 204.8Mbps data rate applications,

ST6200T magnetics from Pulse Engineering can be used. These

magnetics have been tested to work over 10 meters of UTP 5 cable at

204.8Mbps. The rate is determined by the frequency of the OSC clock,

multiplied by the internal PLL clock multiplier factor (1x, 2x or 4x) as

determined in the Enhanced Control 2 Registers. Although the OSC

clock frequency is common to all ports of the PHY, the clock multiplier

factor can be set individually for each port. As an example, with a 64

MHz oscillator, this allows some ports to operate at 51.2 Mbps while

other ports are simultaneously operating at 204.8 Mbps.

When operating at clock multiples other than 1x, use of the RXREF

pin requires that the RXREF Pulse Width Select field in the LED Driver

and HEC Status/Control Registers be programmed to a value greater

than the default of 1 cycle.

Also, the PHY loopback mode without clock recovery (10) in the

Diagnostic Control Registers works only when the clock multiplier is 1x.

For higher multiples, the PHY loopback mode (01) with clock recovery

must be used.

Except as noted above, these higher speed configurations operate

exactly the same as the basic 25.6 Mbps configuration. The scrambling

and encoding are unchanged.

Applications

Up to 204.8Mbps backplane transmission

Rack-to-rack short links

ATM Switches

77V1264L200 Overview

The 77V1264L200 is a four port implementation of the physical layer

standard for 25.6Mbps ATM network communications as defined by

ATM Forum document af-phy-040.000 and ITU-T I.432.5. The physical

layer is divided into a Physical Media Dependent sub layer (PMD) and

Transmission Convergence (TC) sub layer. The PMD sub layer includes

the functions for the transmitter, receiver and clock recovery for opera-

tion across 100 meters of category 3 and 5 unshielded twisted pair

(UTP) cable. This is referred to as the Line Side Interface. The TC sub

layer defines the line coding, scrambling, data framing and synchroniza-

tion.

On the other side, the 77V1264L200 interfaces to an ATM layer

device (such as a switch core or SAR). This cell level interface is config-

urable as either an 8-bit Utopia Level 1 Multi-PHY, 16-bit Utopia Level 2,

or four 4-bit DPI interface, as determined by two MODE pins. This is

referred to as the PHY-ATM Interface. The pinout and front page block

diagram are based on the Utopia 2 configuration. Table 3 shows the

corresponding pin functions for the other two modes, and Figure 2 and

Figure 3 show functional block diagrams.

The 77V1264L200 is based on the 77105, and maintains significant

register compatibility with it. The 77V1264L200, however, has additional

register features, and also duplicates most of its registers to provide

significant independence between the four ports.

Table 1 shows some of the different data rates the PHY can operate

at with a 32MHz or 64MHz oscillator. Note that any oscillator frequency

between 32MHz and 64MHz can be used. For example, if a 48MHz

oscillator is used and the multiplier is set to 4x, the data rate would be

153.6Mbps.

Clock Multiplier

Line Bit

Rate

Data

Rate

Access to these status and control registers is through the utility bus.

This is an 8-bit muxed address and data bus, controlled by a conven-

tional asynchronous read/write handshake.

Reference

Control Bits

(Enhanced Control 2

Registers)

Clock (OSC)

(MHz)

(Mbps)

Additional pins permit insertion and extraction of an 8kHz timing

32 MHz

64 MHz

00 (1x)

01 (2x)

10 (4x)

00 (1x)

01 (2x)

10 (4x)

32

64

128

64

128

256

25.6

51.2

102.4

51.2

102.4

204.8

marker, and provide LED indication of receive and transmit status.

Auto-Synchronization and Good Signal Indica-

tion

The 77V1264L200 features a new receiver synchronization algorithm

that allow it to achieve 4b/5b symbol framing on any valid data stream.

This is an improvement on earlier products which could frame only on

the escape symbol, which occurs only in start-of-cell or 8kHz (X8) timing

marker symbol pairs.

Table 1 200 Speed Grade Option

ATM25 transceivers always transmit valid 4b/5b symbols, allowing

the 77V1264L200 receive section to achieve symbol framing and prop-

erly indicate receive signal status, even in the absence of ATM cells or

8kHz (X8) timing markers in the receive data stream. A state machine

monitors the received symbols and asserts the “Good Signal” status bit

when a valid signal is being received. “Good Signal” is deasserted and

the receive FIFO is disabled when the signal is lost. This is sometimes

referred to as Loss of Signal (LOS).

Operation at Speeds Above 25 Mbps

In addition to operation at the standard rate of 25.6 Mbps, the

77V1264L200 can be operated at a range of data rates, up to 204.8

2 of 49

December 6, 2001

IDT77V1264L200

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3 of 49

December 6, 2001

IDT77V1264L200

Signal Descriptions

Line Side Signals

Signal Description

Signal Name Pin Number

I/O

In

RX0+,-

RX1+,-

RX2+,-

RX3+,-

TX0+,-

TX1+,-

TX2+,-

TX3+,-

139, 138

133, 132

121, 120

115, 114

4, 3

Port 0 positive and negative receive differential input pair.

Port 1 positive and negative receive differential input pair.

Port 2 positive and negative receive differential input pair.

Port 3 positive and negative receive differential input pair.

Port 0 positive and negative transmit differential output pair.

Port 1 positive and negative transmit differential output pair.

Port 2 positive and negative transmit differential output pair.

Port 3 positive and negative transmit differential output pair.

In

Out

144, 143

110, 109

106, 105

Utility Bus Signals

Signal Name Pin Number

I/O

Signal Description

AD[7:0]

ALE

CS

101, 100, 99, 98, 96, 95, 94, In/Out Utility bus address/data bus. The address input is sampled on the falling edge of ALE. Data is output on this

bus when a read is performed. Input data is sampled at the completion of a write operation.

93

91

In

Utility bus address latch enable. Asynchronous input. An address on the AD bus is sampled on the falling

edge of ALE. ALE must be low when the AD bus is being used for data.

90

89

88

Utility bus asynchronous chip select. CS must be asserted to read or write an internal register. It may remain

asserted at all times if desired

RD

In

Utility bus read enable. Active low asynchronous input. After latching an address, a read is performed by

deasserting WR and asserting RD and CS.

WR

Utility bus write enable. Active low asynchronous input. After latching an address, a write is performed by

deasserting RD, placing data on the AD bus, and asserting WR and CS. Data is sampled when WR or CS is

deasserted.

Miscellaneous Signals

Signal Name Pin Number

I/O

In

Signal Description

DA

103

85

Reserved signal. This input must be connected to logic low.

INT

Out

Interrupt. INT is an open-drain output, driven low to indicate an interrupt. Once low, INT remains low until the

interrupt status in the appropriate interrupt Status Register is read. Interrupt sources are programmable via

the interrupt Mask Registers.

MM

6

In

Reserved signal. This input must be connected to logic low.

MODE[1:0]

7, 8

Mode Selects. They determine the configuration of the PHY/ATM interface. 00 = UTOPIA Level 2. 01 = UTO-

PIA Level 1. 10 = DPI. 11 is reserved.

OSC

RST

126

87

In

TTL line rate clock source, driven by a 100 ppm oscillator. 32 MHz or 64 MHz.

Reset. Active low asynchronous input resets all control logic, counters and FIFOs. A reset must be per-

formed after power up prior to normal operation of the part.

RXLED[3:0]

RXREF

82, 81, 80, 79

9

Out

Receive LED drivers. Driven low for 223 cycles of OSC, beginning with RXSOC when that port receives a

good (non-null and non-errored) cell. Drives 8 mA both high and low. One per port.

Receive Reference. Active low, synchronous to OSC. RXREF pulses low for a programmable number of

clock cycles when an x_8 command byte is received. Register 0x40 is programmed to indicate which port is

referenced. Note that when operating the 77V1264L200 at 2x or 4x multiple of OSC (See Enhanced Control

2 Registers) the RXREF pulse width (See LED Driver and HEC Status/Control Registers) must be pro-

grammed to any value greater than the default for proper operation of RXREF.

Table 2 Signal Descriptions (Part 1 of 3)

4 of 49

December 6, 2001

IDT77V1264L200

SE

102

In

Reserved signal. This input must be connected to logic low.

TXLED[3:0]

12, 13, 14, 15

Out

Ports 3 through 0 Transmit LED driver. Goes low for 223 cycles of OSC, beginning with TXSOC when this

port receives a cell for transmission. 8 mA drive current both high and low. One per port.

TXREF

10

In

Transmit Reference. Synchronous to OSC. On the falling edge, an X_8 command byte is inserted into the

transmit data stream. Logic for this signal is programmed in register 0x40. Typical application is WAN timing.

Power Supply Signals

Signal Name Pin Number

I/O

Signal Description

AGND

AVDD

GND

112, 117, 118, 123, 124,

____ Analog ground. AGND supply a ground reference to the analog portion of the ship, which sources a more

constant current than the digital portion.

127, 129, 130, 135, 136, 141

113, 116, 119, 122, 125,

128, 131, 134, 137, 140

____ Analog power supply 3.3 ± 0.3V AVDD supply power to the analog portion of the chip, which draws a more

constant current than the digital portion.

2, 11, 44, 50, 56, 67, 77, 83, ____ Digital Ground.

86, 97, 107, 111, 142

VDD

1, 5, 16, 38, 45, 57, 68, 78, ____ Digital power supply. 3.3 ± 0.3V.

84, 92, 104, 108

16-BIT UTOPIA 2 Signals (MODE[1:0] = 00)

Signal Description

Signal Name Pin Number

I/O

RXADDR[4:0] 53, 52, 51, 49, 48

In

Utopia 2 Receive Address Bus. This bus is used in polling and selecting the receive port. The port addresses

are defined in bits [4:0] of the Enhanced Control Registers.

RXCLAV

54

Out

Utopia 2 Receive Cell Available. Indicates the cell available status of the addressed port. It is asserted when

a full cell is available for retrieval from the receive FIFO. When non of the four ports is addressed. RXCLAV is

high impedance.

RXCLK

46

In

Utopia 2 Receive Clock. This is a free running clock input.

RXDATA[15:0] 59, 60, 61, 62, 63, 64, 65,

66, 69, 70, 71, 72, 73, 74,

75, 76

Out

Utopia 2 Receive Data. When one of the four ports is selected, the 77V1264L200 transfers received cells to

an ATM device across this bus. Also see RXPARITY.

RXEN

47

In

Utopia 2 Receive Enable. Driven by an ATM device to indicate its ability to receive data across the RXDATA

bus.

RXPARITY

RXSOC

58

55

Out

In

Utopia 2 Receive Data Parity. Odd parity over RXDATA[15:0].

Utopia 2 Receive Start of Cell. Asserted coincident with the first word of data for each cell on RXDATA.

TXADDR[4:0] 36, 37, 39, 40, 41

Utopia 2 Transmit Address Bus. This bus is used in polling and selecting the transmit port. The port

addresses are defined in bits [4:0] of the Enhanced Control Registers.

TXCLAV

TXCLK

42

43

Out

Utopia 2 Transmit Cell Available. Indicates the availability of room in the transmit FIFO of the addressed port

for a full cell. When none of the four ports is addressed, TXCLAV is high impedance.

In

Utopia Transmit Clock. This is a free running clock input.

TXDATA[15:0] 32, 31, 30, 29, 28, 27, 26,

25, 24, 23, 22, 21, 20, 19,

18, 17

Utopia 2 Transmit Data. An ATM device transfers cells across this bus to the 77V1264L200 for transmission.

Also see TXPARITY.

TXEN

34

In

Utopia 2 Transmit Enable. Driven by an ATM device to indicate it is transmitting data across the TXDATA

bus.

TXPARITY

33

Utopia 2 Transmit Data Parity. Odd parity across TXDATA[15:0]. Parity is checked and errors are indicated in

the Interrupt Status Registers, as enabled in the Master Control Registers. No other action is taken in the

event of an error. Tie high or low if unused.

TXSOC

35

In

Utopia 2 Transmit Start of Cell. Asserted coincident with the first word of data for each cell on TXDATA.

Table 2 Signal Descriptions (Part 2 of 3)

5 of 49

December 6, 2001

IDT77V1264L200

8-BIT UTOPIA Level 1 Signals (MODE[1:0] = 01)

Signal Name Pin Number

I/O

Signal Description

RXCLAV[3:0] 64, 65, 66, 54

Out

Utopia 1 Receive Cell Available. Indicates the cell available status of the respective port. It is asserted when

a full cell is available for retrieval from the receive FIFO.

RXCLK

46

In

Utopia 1 Receive Clock. This is a free running clock input.

RXDATA[7:0] 69, 70, 71, 72, 73, 74, 75, 76 Out

Utopia 1 Receive Data. When one of the four ports is selected, the 77V1264L200 transfers received cells to

an ATM device across this bus. Bit 5 in the Diagnostic Control Registers determines whether RXDATA tri-

states when RXEN[3:0] are high. Also see RXPARITY.

RXEN[3:0]

51, 49, 48, 47

In

Utopia 1 Receive Enable. Driven by an ATM device to indicate its ability to receive data across the RXDATA

bus. One for each port

RXPARITY

RXSOC

58

55

Out

Utopia 1 Receive Data Parity. Odd parity over RXDATA[7:0].

Utopia 1 Receive Start of Cell. Asserted coincident with the first word of data for each cell on RXDATA. Tri-

statable as determined by bit 5 in the Diagnostic Control Registers.

TXCLAV[3:0] 39, 40, 41, 42

TXCLK 43

Out

In

Utopia 1 Transmit cell Available. Indicates the availability of room in the transmit FIFO of the respective port

for a full cell.

Utopia 1 Transmit Clock. This is a free running clock input.

TXDATA[7:0] 24, 23, 22, 21, 20, 19, 18, 17 In

Utopia 1 Transmit Data. An ATM device transfers cells across the bus to the 77V1264L200 for transmission.

Also see TXPARITY.

TXEN[3:0]

TXPARITY

27, 26, 25, 34

33

In

Utopia 1 Transmit Enable. Driven by an ATM device to indicate it is transmitting data across the TXDATA

bus. One for each port.

Utopia 1 Transmit Data Parity. Odd parity across TXDATA[7:0]. Parity is checked and errors are indicated in

the Interrupt Status Registers, as enabled in the Master Control Registers. No other action is taken in the

event of an error. Tie high or low if unused.

TXSOC

35

In

Utopia 1 Transmit Start of Cell. Asserted coincident with the first word of data for each cell on TXDATA.

DPI Mode Signals (MODE[1:0] = 10)

Signal Name Pin Number

I/O

In

Signal Description

DPICLK

43

DPI Source Clock for Transmit. This is the free-running clock used as the source to generate Pn_TCLK.

Pn_RCLK

52, 51, 49, 48

In

DPI Port ’n’ Receive Clock. Pn_RCLK is cycled to indicate that the interfacing device is ready to receive a

nibble of data on Pn_RD[3:0] of port ’n’.

Pn_RD[3:0]

59, 60, 61, 62, 63, 64, 65,

66, 69, 70, 71, 72, 73, 74,

75, 76

Out

DPI Port ’n’ Receive Data. Cells received on port ’n’ are passed to the interfacing device across this bus.

Each port has its own dedicated bus.

Pn_RFRM

Pn_TCLK

Pn_TD[3:0]

53, 58, 54, 55

Out

In

DPI Port ’n’ Receive Frame. Pn_RFRM is asserted for one cycle immediately preceding the transfer of each

cell on Pn_RD[3:0].

37, 39, 40, 41

DPI Port ’n’ Transmit Clock. Pn_TCLK is derived from DPICLK and is cycled when the respective port is

ready to accept another 4 bits of data on Pn_TD[3:0].

32, 31, 30, 29, 28, 27, 26,

25, 24, 23, 22, 21, 20, 19,

18, 17

DPI Port ’n’ Transmit Data. Cells are passed across this bus to the PHY for transmission on port ’n’. Each

port has its own dedicated bus.

Pn_TFRM

36, 33, 34, 35

In

DPI Port ’n’ Transmit Frame. Start of cell signal which is asserted for one cycle immediately preceding the

first 4 bits of each cell on Pn_TD[3:0].

Table 2 Signal Descriptions (Part 3 of 3)

6 of 49

December 6, 2001

IDT77V1264L200

Signal Assignment as a Function of PHY/ATM Interface Mode

16-BIT UTOPIA 2

MODE[1,0] = 00

8-BIT UTOPIA 1

MODE[1,0] = 01

DPI

SIGNAL NAME

PIN NUMBER

MODE[1,0] = 10

VDD

1

GND

2

TX0-

3

TX0+

4

VDD

5

MM

6

MODE1

MODE0

RXREF

7

8

9

TXREF

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

GND

TXLED3

TXLED2

TXLED1

TXLED0

VDD

TXDATA0

TXDATA1

TXDATA2

TXDATA3

TXDATA4

TXDATA5

TXDATA6

TXDATA7

TXDATA8

TXDATA9

TXDATA10

TXDATA11

TXDATA12

TXDATA13

TXDATA14

TXDATA15

TXPARITY

TXEN

TXDATA0

TXDATA1

TXDATA2

TXDATA3

TXDATA4

TXDATA5

TXDATA6

TXDATA7

TXDATA8

TXDATA9

TXDATA10

TXDATA11

TXDATA12

TXDATA13

TXDATA14

TXDATA15

TXPARITY

TXEN

TXDATA0

TXDATA1

TXDATA2

TXDATA3

TXDATA4

TXDATA5

TXDATA6

TXDATA7

TXEN[1]

P0_TD[0]

P0_TD[1]

P0_TD[2]

P0_TD[3]

P1_TD[0]

P1_TD[1]

P1_TD[2]

P1_TD[3]

P2_TD[0]

P2_TD[1]

P2_TD[2]

P2_TD[3]

P3_TD[0]

P3_TD[1]

P3_TD[2]

P3_TD[3]

P2_TFRM

P1_TFRM

P0_TFRM

P3_TFRM

TXEN[2]

TXEN[3]

see note 2

TXPARITY

TXEN[0]

TXSOC

TXADDR4

see note 2

Table 3 Signal Assignment as a Function of PHY/ATM Interface Mode (Part 1 of 4)

7 of 49

December 6, 2001

IDT77V1264L200

SIGNAL NAME

16-BIT UTOPIA 2

MODE[1,0] = 00

8-BIT UTOPIA 1

MODE[1,0] = 01

DPI

PIN NUMBER

MODE[1,0] = 10

TXADDR3

VDD

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

TXADDR3

see note 2

P3_TCLK

TXADDR2

TXADDR1

TXADDR0

TXCLAV

TXCLK

TXADDR2

TXADDR1

TXADDR0

TXCLAV

TXCLK

TXCLAV[3]

TXCLAV[2]

TXCLAV[1]

TXCLAV[0]

TXCLK

P2_TCLK

P1_TCLK

P0_TCLK

see note 1

DPICLK

GND

VDD

RXCLK

see note 2

P0_RCLK

P1_RCLK

RXEN

RXEN[0]

RXEN[1]

RXEN[2]

RXADDR0

RXADDR1

GND

RXADDR0

RXADDR1

RXADDR2

RXADDR3

RXADDR4

RXCLAV

RXSOC

RXADDR2

RXADDR3

RXADDR4

RXCLAV

RXSOC

RXEN[3]

P2_RCLK

P3_RCLK

P3_RFRM

P1_RFRM

P0_FRM

see note 2

RXCLAV[0]

RXSOC

GND

VDD

RXPARITY

RXDATA15

RXDATA14

RXDATA13

RXDATA12

RXDATA11

RXDATA10

RXDATA9

RXDATA8

GND

RXPARITY

RXDATA15

RXDATA14

RXDATA13

RXDATA12

RXDATA11

RXDATA10

RXDATA9

RXDATA8

RXPARITY

see note 1

RXCLAV[3]

RXCLAV[2]

RXCLAV[1]

P2_RFRM

P3_RD[3]

P3_RD[2]

P3_RD[1]

P3_RD[0]

P2_RD[3]

P2_RD[2]

P2_RD[1]

P2_RD[0]

VDD

RXDATA7

RXDATA6

RXDATA5

RXDATA4

RXDATA3

RXDATA7

RXDATA6

RXDATA5

RXDATA4

RXDATA3

RXDATA7

RXDATA6

RXDATA5

RXDATA4

RXDATA3

P1_RD[3]

P1_RD[2]

P1_RD[1]

P1_RD[0]

P0_RD[3]

Table 3 Signal Assignment as a Function of PHY/ATM Interface Mode (Part 2 of 4)

8 of 49

December 6, 2001

IDT77V1264L200

SIGNAL NAME

16-BIT UTOPIA 2

MODE[1,0] = 00

8-BIT UTOPIA 1

MODE[1,0] = 01

DPI

PIN NUMBER

MODE[1,0] = 10

RXDATA2

RXDATA1

RXDATA0

GND

VDD

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

RXDATA2

RXDATA1

RXDATA0

RXDATA2

RXDATA1

RXDATA0

P0_RD[2]

P0_RD[1]

P0_RD[0]

RXLED0

RXLED1

RXLED2

RXLED3

GND

VDD

INT

GND

RST

WR

RD

CS

ALE

VDD

AD0

AD1

AD2

AD3

GND

AD4

AD5

AD6

100

101

102

103

104

105

106

107

108

109

110

AD7

SE

DA

VDD

TX3-

TX3+

GND

VDD

TX2-

TX2+

Table 3 Signal Assignment as a Function of PHY/ATM Interface Mode (Part 3 of 4)

9 of 49

December 6, 2001

IDT77V1264L200

SIGNAL NAME

16-BIT UTOPIA 2

MODE[1,0] = 00

8-BIT UTOPIA 1

MODE[1,0] = 01

DPI

PIN NUMBER

111

MODE[1,0] = 10

GND

AGND

AVDD

RX3-

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

RX3+

AVDD

AGND

AVDD

RX2-

RX2+

AVDD

AGND

AVDD

OSC

AGND

AVDD

AGND

AVDD

RX1-

RX1+

AVDD

AGND

AVDD

RX0-

RX0+

AVDD

AGND

GND

TX1-

TX1+

Table 3 Signal Assignment as a Function of PHY/ATM Interface Mode (Part 4 of 4)

Note: 1.This output signal is unused in this mode. It must be left unconnected.

2.This input signal is unused in this mode. It must be connected to either logic high or logic low.

10 of 49

December 6, 2001

IDT77V1264L200

(X _C) is NOT scrambled before it's encoded (see diagram for illustra-

tion). The PRNG is based upon the following polynomial:

Functional Description

10

7

Transmission Convergence (TC) Sub Layer

X + X + 1

Introduction

With this polynomial, the four output data bits (D3, D2, D1, D0) will be

generated from the following equations:

The TC sub layer defines the line coding, scrambling, data framing

and synchronization. Under control of a switch interface or Segmenta-

tion and Reassembly (SAR) unit, the 25.6Mbps ATM PHY accepts a 53-

byte ATM cell, scrambles the data, appends a command byte to the

beginning of the cell, and encodes the entire 53 bytes before transmis-

sion. These data transformations ensure that the signal is evenly distrib-

uted across the frequency spectrum. In addition, the serialized bit

stream is NRZI coded. An 8kHz timing sync pulse may be used for

isochronous communications.

D3 = d3 xor X(t-3)

D2 = d2 xor X(t-2)

D1 = d1 xor X(t-1)

D0 = d0 xor X(t)

The following nibble is scrambled with X(t+4), X(t+3), X(t+2), and

X(t+1).

A scrambler lock between the transmitter and receiver occurs each

time an X_X command is sent. An X_X command is initiated only at the

beginning of a cell transfer after the PRNG has cycled through all of its

Data Structure and Framing

Each 53-byte ATM cell is preceded with a command byte. This byte

is distinguished by an escape symbol followed by one of 17 encoded

symbols. Together, this byte forms one of seventeen possible command

bytes. Three command bytes are defined:

10

states (2 - 1 = 1023 states). The first valid ATM data cell transmitted

after power on will also be accompanied with an X_X command byte.

Each time an X_X command byte is sent, the first nibble after the last

escape (X) nibble is XOR'd with 1111b (PRNG = 3FFx).

1. X_X (read: 'escape' symbol followed by another 'escape'): Start-

of-cell with scrambler/descrambler reset.

Because a timing marker command (X_8) may occur at any time, the

possibility of a reset PRNG start-of-cell command and a timing marker

command occurring consecutively does exist (e.g. X_X_X_8). In this

case, the detection of the last two consecutive escape (X) nibbles will

cause the PRNG to reset to its initial 3FFx state. Therefore, the PRNG is

clocked only after the first nibble of the second consecutive escape pair.

Once the data nibbles have been scrambled using the PRNG, the

nibbles are further encoded using a 4b/5b process. The 4b/5b scheme

ensures that an appropriate number of signal transitions occur on the

line. A total of seventeen 5-bit symbols are used to represent the sixteen

4-bit data nibbles and the one escape (X) nibble. The table below lists

the 4-bit data with their corresponding 5-bit symbols:

2. X_4 ('escape' followed by '4'): Start-of-cell without scrambler/

descrambler reset.

3. X_8 ('escape' followed by '8'): 8kHz timing marker. This

command byte is generated when the 8kHz sync pulse is

detected, and has priority over all line activity (data or command

bytes). It is transmitted immediately when the sync pulse is

detected. When this occurs during a cell transmission, the data

transfer is temporarily interrupted on an octet boundary, and the

X_8 command byte is inserted. This condition is the only allowed

interrupt in an otherwise contiguous transfer.

Below is an illustration of the cell structure and command byte usage:

{X_X} {53-byte ATM cell} {X_4} {53-byte ATM {X_8} cell}...

In the above example, the first ATM cell is preceded by the X_X start-

of-cell command byte which resets both the transmitter-scrambler and

receiver-descrambler pseudo-random nibble generators (PRNG) to their

initial states. The following cell illustrates the insertion of a start-of-cell

command without scrambler/descrambler reset. During this cell's trans-

mission, an 8kHz timing sync pulse triggers insertion of the X_8 8kHz

timing marker command byte.

ꢖꢙ.ꢙ

&&&&

&(&&

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&&(((

(&&(&

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.

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Transmission Description

Refer to Figure 4. Cell transmission begins with the PHY-ATM Inter-

face. An ATM layer device transfers a cell into the 77V1264L200 across

the Utopia transmit bus or DPI transmit bus. This cell enters a 3-cell

deep transmit FIFO. Once a complete cell is in the FIFO, transmission

begins by passing the cell, four bits (MSB first) at a time to the 'Scram-

bler'.

The 'Scrambler' takes each nibble of data and exclusive-ORs them

against the 4 high order bits (X(t), X(t-1), X(t-2), X(t-3)) of a 10 bit

pseudo-random nibble generator (PRNG). Its function is to provide the

appropriate frequency distribution for the signal across the line.

*ꢍ&ꢍ ꢓꢋ9 &ꢍꢙ

.

ꢑꢘꢂ0ꢁ2 @ &&&(&

This encode/decode implementation has several very desirable prop-

erties. Among them is the fact that the output data bits can be repre-

sented by a set of relatively simple symbols;

Run length is limited to <= 5;

Disparity never exceeds +/- 1.

On the receiver, the decoder determines from the received symbols

whether a timing marker command (X_8) or a start-of-cell command was

sent (X_X or X_4). If a start-of-cell command is detected, the next 53

bytes received are decoded and forwarded to the descrambler. (See TC

Receive Block Diagram, Figure 5).

The PRNG is clocked every time a nibble is processed, regardless of

whether the processed nibble is part of a data or command byte. Note

however that only data nibbles are scrambled. The entire command byte

11 of 49

December 6, 2001

IDT77V1264L200

The output of the 4b/5b encoder provides serial data to the NRZI

encoder. The NRZI code transitions the wire voltage each time a '1' bit is

sent. This, together with the previous encoding schemes guarantees

that long run lengths of either '0' or '1's are prevented. Each symbol is

shifted out with its most significant bit sent first.

The IDT77V1264L200 monitors line conditions and can provide an

interrupt if the line is deemed 'bad'. The Interrupt Status Registers

(registers 0x01, 0x11, 0x21 and 0x31) contain a Good Signal Bit (bit 6,

set to 0 = Bad signal initially) which shows the status of the line per the

following algorithm:

When no cells are available to transmit, the 77V1264L200 keeps the

line active by continuing to transmit valid symbols. But it does not

transmit another start-of-cell command until it has another cell for trans-

mission. The 77V1264L200 never generates idle cells.

To declare 'Good Signal' (from "Bad" to "Good")

There is an up-down counter that counts from 7 to 0 and is initially

set to 7. When the clock ticks for 1,024 cycles (32MHz clock, 1,024

cycles = 204.8 symbols) and no "bad symbol" has been received, the

counter decreases by one. However, if at least one "bad symbol" is

detected during these 1,024 clocks, the counter is increased by one, to

a maximum of 7. The Good Signal Bit is set to 1 when this counter

reaches 0. The Good Signal Bit could be set to 1 as quickly as 1,433

symbols (204.8 x 7) if no bad symbols have been received.

Transmit HEC Byte Calculation/Insertion

Byte #5 of each ATM cell, the HEC (Header Error Control) is calcu-

lated automatically across the first 4 bytes of the cell header, depending

upon the setting of bit 5 of registers 0x03, 0x13, 0x23 and 0x33. This

byte is then either inserted as a replacement of the fifth byte transferred

to the PHY by the external system, or the cell is transmitted as received.

A third operating mode provides for insertion of "Bad" HEC codes which

may aid in communication diagnostics. These modes are controlled by

the LED Driver and HEC Status/Control Registers.

To declare 'Bad Signal' (from "Good" to "Bad")

The same up-down counter counts from 0 to 7 (being at 0 to provide

a "Good" status). When the clock ticks for 1,024 cycles (32MHz clock,

1,024 cycles = 204.8 symbols) and there is at least one "bad symbol",

the counter increases by one. If it detects all "good symbols" and no

"bad symbols" in the next time period, the counter decreases by one.

The "Bad Signal" is declared when the counter reaches 7. The Good

Signal Bit could be set to 0 as quickly as 1,433 symbols (204.8 x 7) if at

least one "bad symbol" is detected in each of seven consecutive groups

of 204.8 symbols.

Receiver Description

The receiver side of the TC sublayer operates like the transmitter, but

in reverse. The data is NRZI decoded before each symbol is reassem-

bled. The symbols are then sent to the 5b/4b decoder, followed by the

Command Byte Interpreter, De-Scrambler, and finally through a FIFO to

the UTOPIA or DPI interface to an ATM Layer device.

8kHz Timing Marker

ATM Cell Format

The 8kHz timing marker, described earlier, is a completely optional

feature which is essential for some applications requiring synchroniza-

tion for voice or video, and unnecessary for other applications. Figure 7

shows the options available for generating and receiving the 8kHz

timing marker.

ꢀꢁꢂꢃ

ꢀꢁꢂꢄ

+ꢉꢙꢓꢉꢋ ꢎꢌ.ꢉ (

+ꢉꢙꢓꢉꢋ ꢎꢌ.ꢉ )

+ꢉꢙꢓꢉꢋ ꢎꢌ.ꢉ *

+ꢉꢙꢓꢉꢋ ꢎꢌ.ꢉ ꢐ

The source of the marker is programmable in the RXREF and

TXREF Control Register (0x40). Each port is individually programmable

to either a local source or a looped remote source. The local source is

TXREF, which is an 8kHz clock of virtually any duty cycle. When

unused, TXREF should be tied high. Also note that it is not limited to

8kHz, should a different frequency be desired. When looped, a received

X_8 command byte causes one to be generated on the transmit side.

1ꢖ$

ꢗꢙꢌꢅꢆꢙꢓ ꢎꢌ.ꢉ (

•

ꢗꢙꢌꢅꢆꢙꢓ ꢎꢌ.ꢉ ꢐ=

*ꢍ&ꢍ ꢓꢋ9 ꢍ)

A received X_8 command byte causes the 77V1264L200 to issue a

negative pulse on RXREF. The source channel of the marker is

programmable. When the clock multiplier in the Enhanced Control 2

register(s) is set to 2x or 4x, it is also necessary to set the RXREF Pulse

Width Select in the LED Driver and HEC Status/Control register(s) to

any value greater than the default for proper operation of RXREF.

.

1ꢖ$ @ 1 ꢉꢋ ꢖꢉ/ꢔꢒꢉꢓ $ꢔꢉꢅꢓ 0ꢆꢋ +ꢑꢂ2

Note that although the IDT77V1264L200 can detect symbol and

HEC errors, it does not attempt to correct them.

Upon reset or the re-connect, each port's receiver is typically not

symbol-synchronized. When not symbol-synchronized, the receiver will

indicate a significant number of bad symbols, and will deassert the Good

Signal Bit as described below. Synchronization is established immedi-

ately once that port receives an Escape symbol, usually as part of the

start-of-cell command byte preceding the first received cell.

12 of 49

December 6, 2001

IDT77V1264L200

TXRef

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Figure 2 Block Diagram for Utopia Level 1 Configuration (MODE[1:0] = 01)

13 of 49

December 6, 2001

IDT77V1264L200

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ꢗ&Bꢀꢖ4*5&6

ꢗ(B!ꢂꢃꢄ

ꢗ(B!$ꢀ#

ꢗ(B!ꢖ4*5&6

7

-

!ꢁ ꢗꢆꢋ. (

ꢀꢁ ꢗꢆꢋ. (

ꢍꢎꢏꢐꢎ

!ꢁꢏꢀꢁ "!#

ꢂꢉꢅꢅ $ꢜ$%

ꢘꢇꢋꢙꢝꢞꢅꢉꢋꢏ

ꢗꢏꢘ ꢙꢒꢓ ꢘꢏꢗ

ꢚꢀꢛꢜ

ꢑꢒꢇꢆꢓꢔꢒꢕꢏ

ꢖꢉꢇꢆꢓꢔꢒꢕ

ꢖꢉ ꢇꢋꢙꢝꢞꢅꢉꢋ

7

-

ꢗ(Bꢀꢂꢃꢄ

ꢗ(Bꢀ$ꢀ#

ꢗ(Bꢀꢖ4*5&6

ꢖꢗꢜ

#Aꢅ.ꢔ-ꢗ+,

ꢜꢒ.ꢉꢋ/ꢙꢇꢉ

ꢗ)B!ꢂꢃꢄ

ꢗ)B!$ꢀ#

ꢗ)B!ꢖ4*5&6

7

-

!ꢁ ꢗꢆꢋ. )

ꢀꢁ ꢗꢆꢋ. )

ꢍꢎꢏꢐꢎ

!ꢁꢏꢀꢁ "!#

ꢂꢉꢅꢅ $ꢜ$%

ꢘꢇꢋꢙꢝꢞꢅꢉꢋꢏ

ꢗꢏꢘ ꢙꢒꢓ ꢘꢏꢗ

ꢚꢀꢛꢜ

ꢑꢒꢇꢆꢓꢔꢒꢕꢏ

ꢖꢉꢇꢆꢓꢔꢒꢕ

ꢖꢉ ꢇꢋꢙꢝꢞꢅꢉꢋ

7

-

ꢗ)Bꢀꢂꢃꢄ

ꢗ)Bꢀ$ꢀ#

ꢗ)Bꢀꢖ4*5&6

ꢗ*B!ꢂꢃꢄ

ꢗ*B!$ꢀ#

ꢗ*B!ꢖ4*5&6

7

-

!ꢁ ꢗꢆꢋ. *

ꢀꢁ ꢗꢆꢋ. *

ꢍꢎꢏꢐꢎ

!ꢁꢏꢀꢁ "!#

ꢂꢉꢅꢅ $ꢜ$%

ꢘꢇꢋꢙꢝꢞꢅꢉꢋꢏ

ꢗꢏꢘ ꢙꢒꢓ ꢘꢏꢗ

ꢚꢀꢛꢜ

ꢑꢒꢇꢆꢓꢔꢒꢕꢏ

ꢖꢉꢇꢆꢓꢔꢒꢕ

ꢗ*Bꢀꢂꢃꢄ

ꢗ*Bꢀ$ꢀ#

ꢗ*Bꢀꢖ4*5&6

ꢖꢉ ꢇꢋꢙꢝꢞꢅꢉꢋ

7

-

.

ꢐ

INT

RST

RD

#ꢔꢇꢋꢆ3ꢋꢆꢇꢉ ꢆꢋ

ꢜꢒ.ꢉꢋ/ꢙꢇꢉ

WR

CS

"ꢖ4:5&6

"ꢃꢑ

%ꢘꢂ

ꢀꢁꢃꢑꢖ4*5&6

!ꢁꢃꢑꢖ4*5&6

RXRef

*ꢍ&ꢍ ꢓꢋ9 &ꢐ

Figure 3 Block Diagram for DPI Configuration (MODE[1:0] = 10)

ꢘ.ꢙꢋ. ꢆ/ ꢂꢉꢅꢅ

TXRef 0=ꢈ+F2

* ꢂꢉꢅꢅ

ꢐ

ꢂꢆꢝꢝꢙꢒꢓ

ꢎꢌ.ꢉ

ꢘꢇꢋꢙꢝꢞꢅꢉꢋ

ꢜꢒ ꢉꢋ.ꢔꢆꢒ

ꢗ+,-"!#

Reset

ꢜꢒ.ꢉꢋ/ꢙꢇꢉ

ꢂꢆꢒ.ꢋꢆꢅC

1!%ꢗꢜ"

ꢆꢋ

ꢖꢗꢜ ꢜꢒ.ꢉꢋ/ꢙꢇꢉ

+ꢑꢂ ;ꢉꢒD E

ꢜꢒ ꢉꢋ.ꢔꢆꢒ

ꢐ

ꢘꢇꢋꢙꢝꢞꢅꢉ

ꢚꢔꢞꢞꢅꢉ

ꢚꢉ'.

ꢅꢆꢇꢈ

ꢐꢞꢏꢍꢞ

ꢑꢒꢇꢆꢓꢔꢒꢕ

(

%ꢘꢂ

ꢚꢀꢛꢜ

!ꢁ

7

ꢂꢅꢆꢇꢈ ꢜꢒ3A.

ꢑꢒꢇꢆꢓꢔꢒꢕ

!ꢁ -

*ꢍ&ꢍ ꢓꢋ9 &ꢍ

Figure 4 TC Transmit Block Diagram

14 of 49

December 6, 2001

IDT77V1264L200

PHY-ATM Interface

RXEN

ATM to PHY

PHY to ATM

ATM to PHY

The 77V1264L200 PHY offers three choices in interfacing to ATM

layer devices such as segmentation and reassembly (SAR) and

switching chips. MODE[1:0] are used to select the configuration of this

interface, as shown in the table below.

RXCLAV

RXCLK

To determine if any of them has room to accept a cell for transmis-

sion (TXCLAV), or has a receive cell available to pass on to the ATM

device (RXCLAV). To poll, the ATM device drives an address (TXADDR

or RXADDR) then observes TXCLAV or RXCLAV on the next cycle of

TXCLK or RXCLK. A port must tri-state TXCLAV and RXCLAV except

when it is addressed.

If TXCLAV or RXCLAV is asserted, the ATM device may select that

port, then transfer a cell to or from it. Selection of a port is performed by

driving the address of the desired port while TXEN or RXEN is high, then

driving TXEN or RXEN low. When TXEN is driven low, TXSOC (start of

cell) is driven high to indicate that the first 16 bits of the cell are being

driven on TXDATA. The ATM device may chose to temporarily suspend

transfer of the cell by deasserting TXEN. Otherwise, TXEN remains

asserted as the next 16 bits are driven onto TXDATA with each cycle of

TXCLK.

UTOPIA is a Physical Layer to ATM Layer interface standardized by

the ATM Forum. It has separate transmit and receive channels and

specific handshaking protocols. UTOPIA Level 2 has dedicated address

signals for both the transmit and receive directions that allow the ATM

layer device to specify with which of the four PHY channels it is commu-

nicating. UTOPIA Level 1 does not have address signals.

Instead, key handshaking signals are duplicated so that each

channel has its own signals. In both versions of UTOPIA, all channels

share a single transmit data bus and a single receive data bus for data

transfer.

DPI is a low-pin count Physical Layer to ATM Layer interface. The

low-pin count characteristic allows the 77V1264L200 to incorporate four

separate DPI 4-bit ports, one for each of the four serial ports. As with the

UTOPIA interfaces, the transmit and receive directions have their own

data paths and handshaking.

In the receive direction, the ATM device selects a port if it wished to

receive the cell that the port is holding. It does this by asserting RXEN.

The PHY then transfers the data 16 bits each clock cycle, as deter-

mined by RXEN. As in the transmit direction, the ATM device may

suspend transfer by deasserting RXEN at any time. Note that the PHY

asserts RXSOC coincident with the first 16 bits of each cell.

UTOPIA Level 2 Interface Option

The 16-bit Utopia Level 2 interface operates as defined in ATM

Forum document af-phy-0039. This PHY-ATM interface is selected by

setting the MODE[1:0] pins both low.

This mode is configured as a single 16-bit data bus in the transmit

(ATM-to-PHY) direction, and a single 16-bit data bus in the receive

(PHY-to-ATM) direction. In addition to the data bus, each direction also

includes a single optional parity bit, an address bus, and several hand-

shaking signals. The UTOPIA address of each channel is determined by

bits 4 to 0 in the Enhanced Control Registers. Please note that the

transmit bus and the receive bus operate completely independently. The

Utopia 2 signals are summarized below:

TXPARITY and RXPARITY are parity bits for the corresponding 16-

bit data fields. Odd parity is used.

Figures 9 through 14 may be referenced for Utopia 2 bus examples.

Because this interface transfers an even number of bytes, rather

than the ATM standard of 53 bytes, a filler byte is inserted between the

5-byte header and the 48-byte payload. This is shown in Figure 8.

TXDATA[15:0]

TXPARITY

TXSOC

ATM to PHY

PHY to ATM

ATM to PHY

TXADDR[4:0]

TXEN

TXCLAV

TXCLK

RXDATA[15:0]

RXPARITY

RXSOC

PHY to ATM

ATM to PHY

RXADDR[4:0]

15 of 49

December 6, 2001

IDT77V1264L200

ꢅꢆꢇꢈ

ꢘꢇꢋꢙꢝꢞꢅꢉ

ꢚꢔꢞꢞꢅꢉ

ꢀꢉ ꢉ.

RXRef

ꢐ

ꢚꢉ'.

ꢂꢆꢝꢝꢙꢒꢓ

ꢎꢌ.ꢉ

ꢍꢞꢏꢐꢞ

ꢖꢉꢇꢆꢓꢔꢒꢕ

ꢚꢀꢛꢜ

ꢖꢉꢇꢆꢓꢔꢒꢕ

ꢖꢉ-

ꢖꢉ.ꢉꢇ.ꢔꢆꢒC

ꢀꢉꢝꢆꢊꢙꢅC

E ꢖꢉꢇꢆꢓꢉ

ꢀꢁ 7

ꢍ

ꢐ

ꢘꢇꢋꢙꢝꢞꢅꢉꢋ

.

ꢀꢁ

ꢘ.ꢙꢋ. ꢆ/ ꢂꢉꢅꢅ

ꢐ

* ꢂꢉꢅꢅ

*)D&#+F

Clock

ꢂꢅꢆꢇꢈ

Recovery

E ꢗꢃꢃ

1!%ꢗꢜ"

ꢆꢋ

ꢖꢗꢜ ꢜꢒ.ꢉꢋ/ꢙꢇꢉ

ꢗ+,-"!#

ꢘꢌꢒ.Gꢉ ꢔFꢉꢋ

ꢜꢒ.ꢉꢋ/ꢙꢇꢉ

ꢂꢆꢒ.ꢋꢆꢅ -

ꢀꢑꢂ8

*ꢍ&ꢍ ꢓꢋ9 &<

%ꢘꢂ

Figure 5 TC Receive Block Diagram

UTOPIA Level 1 Multi-phy Interface Option

The UTOPIA Level 1 MULTI-PHY interface is based on ATM Forum document af-phy-0017. Utopia Level 1 is essentially the same as Utopia Level

2, but without the addressing, polling and selection features.

ꢎꢔ. (ꢍ

ꢎꢔ. &

$ꢔꢋ . +ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ (

+ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ *

+ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ ꢍ

ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ (

ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ *

ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ ꢍ

+ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ )

+ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ ꢐ

.A// ꢞꢌ.ꢉ

ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ )

ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ ꢐ

ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ <

ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ ꢐꢍ ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ ꢐ<

ꢃꢙ . ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ ꢐ: ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ ꢐ=

Figure 6 Utopia Level 2 Data Format and Sequence

Instead of addressing, this mode utilizes separate TXCLAV, TXEN, RXCLAV and RXEN signals for each channel of the 77V1264L200. There are

just one each of the TXSOC and RXSOC signals, which are shared across all four channels.

In addition to Utopia Level 2's cell mode transfer protocol, Utopia Level 1 also offers the option of a byte mode protocol. Bit 1 of the Master Control

Registers is used to program whether the UTOPIA Level 1 bus is in cell mode or byte mode. In byte mode, the PHY is allowed to control data transfer

on a byte-by-byte basis via the TXCLAV and RXCLAV signals. In cell mode, TXCLAV and RXCLAV are ignored once the transfer of a cell has begun.

In every other way the two modes are identical. Cell mode is the default configuration and is the one described later.

16 of 49

December 6, 2001

IDT77V1264L200

TXRef ^ꢜꢒ3A.

0 ꢀꢉꢕ ꢐ&C ꢎꢔ. &2

ꢃ!ꢘꢉꢅH&

ꢀꢁꢀꢉ/H&

#A'

!ꢁꢀꢉ/H&

0ꢁB= ꢕꢉꢒꢉꢋꢙ.ꢆꢋ2

0ꢁB= ꢋꢉꢇꢉꢔꢊꢉꢓ2

0 ꢀꢉꢕ ꢐ&C ꢎꢔ. (2

ꢃ!ꢘꢉꢅH(

ꢀꢁꢀꢉ/H(

#A'

!ꢁꢀꢉ/H(

0ꢁB= ꢕꢉꢒꢉꢋꢙ.ꢆꢋ2

0ꢁB= ꢋꢉꢇꢉꢔꢊꢉꢓ2

0 ꢀꢉꢕ ꢐ&C ꢎꢔ. )2

ꢃ!ꢘꢉꢅH)

ꢀꢁꢀꢉ/H)

#A'

0ꢁB= ꢋꢉꢇꢉꢔꢊꢉꢓ2

!ꢁꢀꢉ/H)

0ꢁB= ꢕꢉꢒꢉꢋꢙ.ꢆꢋ2

0 ꢀꢉꢕ ꢐ&C ꢎꢔ. *2

ꢃ!ꢘꢉꢅH*

ꢀꢁꢀꢉ/H*

#A'

0ꢁB= ꢋꢉꢇꢉꢔꢊꢉꢓ2

!ꢁꢀꢉ/H*

0ꢁB= ꢕꢉꢒꢉꢋꢙ.ꢆꢋ2

.

ꢀꢁꢀꢉ/

ꢘꢉꢅꢉꢇ.

ꢀꢁꢀꢉ/ꢘꢉꢅ4(5&6

IDT77V1264L200

ꢜꢖ!::8()ꢍꢐ

ꢖꢉꢇꢆꢓꢉꢋ

RXRef ^%A.3A.

*ꢍ&ꢍ ꢓꢋ9 &

Figure 7 RXREF and TXREF Block Diagram

The Utopia 1 signals are summarized below:

TXDATA[7:0]

TXPARITY

TXSOC

TXEN[3:0]

TXCLAV[3:0]

TXCLK

ATM to PHY

PHY to ATM

ATM to PHY

RXDATA[7:0]

RXPARITY

RXSOC

PHY to ATM

ATM to PHY

PHY to ATM

ATM to PHY

RXEN[3:0]

RXCLAV[3:0]

RXCLK

17 of 49

December 6, 2001

IDT77V1264L200

Transmit and receive both utilize free running clocks, which are inputs to the 77V1264L200. All Utopia signals are timed to these clocks.

In the transmit direction, the PHY first asserts TXCLAV (transmit cell available) to indicate that it has room in its transmit FIFO to accept at least

one 53-byte ATM cell. When the ATM layer device is ready to begin passing the cell, it asserts TXEN (transmit enable) and TXSOC (start of cell), coin-

cident with the first byte of the cell on TXDATA. TXEN remains asserted for the duration of the cell transfer, but the ATM device may deassert TXEN at

any time once the cell transfer has begun, but data is transferred only when TXEN is asserted.

In the receive direction, RXEN indicates when the ATM device is prepared to receive data. As with transmit, it may be asserted or deasserted at

any time. Note, however, that not more than one RXEN should be asserted at a time. Also, once a given RX port is selected, that port's FIFO must be

emptied of cells (as indicated by RXCLAV) before a different RX port may be enabled.

In both transmit and receive, TXSOC and RXSOC (start of cell) is asserted for one clock, coincident with the first byte of each cell. Odd parity is

utilized across each 8-bit data field.

Figure 8 shows the data sequence for an ATM cell over Utopia Level 1, and Figures 15 through 21 are examples of the Utopia Level 1 handshake.

ꢎꢔ. :

ꢎꢔ. &

$ꢔꢋ . +ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ (

+ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ )

+ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ *

+ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ ꢐ

+ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ ꢍ

ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ (

ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ )

ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ *

ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ ꢐ<

ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ ꢐ:

ꢃꢙ . ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ ꢐ=

*ꢍ&ꢍ ꢓꢋ9 (ꢍ

Figure 8 Utopia 1 Data Format and Sequence

18 of 49

December 6, 2001

IDT77V1264L200

ꢉꢅꢉꢇ.ꢔꢆꢒ

3ꢆꢅꢅꢔꢒꢕ

3ꢆꢅꢅꢔꢒꢕ5

!ꢁꢂꢃꢄ

!ꢁ"ꢖꢖꢀ4ꢐ5&6

($

ꢚ7*

($

ꢚ7)

($

ꢚ7*

($

ꢚ

($

+ꢔꢕG-ꢛ

!ꢁꢂꢃ"8

ꢚ7(

ꢚ7*

ꢚ7)

ꢚ7*

ꢚ

TXEN

!ꢁꢖꢙ.ꢙ4(ꢍ5&6C

!ꢁꢗ"ꢀꢜ!,

+ꢍC Aꢒꢓꢉ/ꢔꢒꢉꢓ

ꢗ*>C ꢐ&

ꢗꢐ(C ꢐ)

ꢗꢐ*C ꢐꢐ

ꢗꢐꢍC ꢐ<

ꢗꢐ:C ꢐ=

+(C )

+*C ꢐ

ꢗ(C )

.

!ꢁꢘ%ꢂ

ꢗ+, ꢚ7*

ꢗ+, ꢚ

ꢇꢉꢅꢅ .ꢋꢙꢒ ꢝꢔ ꢔꢆꢒ .ꢆ5

*ꢍ&ꢍ ꢓꢋ9 &>

Figure 9 Utopia 2 Transmit Handshake - Back to Back Cells

ꢉꢅꢉꢇ.ꢔꢆꢒ

3ꢆꢅꢅꢔꢒꢕ

3ꢆꢅꢅꢔꢒꢕ5

!ꢁꢂꢃꢄ

!ꢁ"ꢖꢖꢀ4ꢐ5&6

!ꢁꢂꢃ"8

TXEN

($

ꢚ7*

($

ꢚ7)

($

ꢚ7*

($

ꢚ

($

+ꢔꢕG-ꢛ

ꢚ7(

ꢚ7*

ꢚ7)

ꢚ7*

ꢚ

!ꢁꢖꢙ.ꢙ4(ꢍ5&6C

!ꢁꢗ"ꢀꢜ!,

+ꢍC Aꢒꢓꢉ/ꢔꢒꢉꢓ

ꢗꢐ*C ꢐꢐ

ꢗꢐꢍC ꢐ<

ꢗꢐ:C ꢐ=

+(C )

+*C ꢐ

ꢗ(C )

.

!ꢁꢘ%ꢂ

ꢗ+, ꢚ7*

ꢗ+, ꢚ

ꢇꢉꢅꢅ .ꢋꢙꢒ ꢝꢔ ꢔꢆꢒ .ꢆ5

*ꢍ&ꢍ ꢓꢋ9 (&

Figure 10 Utopia 2 Transmit Handshake - Delay Between Cells

19 of 49

December 6, 2001

IDT77V1264L200

ꢉꢅꢉꢇ.ꢔꢆꢒ

3ꢆꢅꢅꢔꢒꢕ

3ꢆꢅꢅꢔꢒꢕ5

!ꢁꢂꢃꢄ

!ꢁ"ꢖꢖꢀ4ꢐ5&6

($

ꢚ7*

($

ꢚ7)

($

#

($

ꢚ

($

+ꢔꢕG-ꢛ

!ꢁꢂꢃ"8

ꢚ7(

ꢚ7*

ꢚ7)

#

ꢚ

TXEN

+ꢔꢕG-ꢛ

!ꢁꢖꢙ.ꢙ4(ꢍ5&6C

!ꢁꢗ"ꢀꢜ!,

ꢗ)ꢍC )<

ꢗ):C )=

ꢗ)>C *&

ꢗ*(C *)

ꢗ**C *ꢐ

ꢗ*ꢍC *<

.

+ꢔꢕG-ꢛ

!ꢁꢘ%ꢂ

ꢗ+, #

ꢇꢉꢅꢅ .ꢋꢙꢒ ꢝꢔ ꢔꢆꢒ .ꢆ5

*ꢍ&ꢍ ꢓꢋ9 ((

Figure 11 Utopia 2 Transmit Handshake - Transmission Suspended

ꢉꢅꢉꢇ.ꢔꢆꢒ

3ꢆꢅꢅꢔꢒꢕ

3ꢆꢅꢅꢔꢒꢕ5

ꢀꢁꢂꢃꢄ

ꢀꢁ"ꢖꢖꢀ4ꢐ5&6

ꢀꢁꢂꢃ"8

RXEN

ꢚ7*

($

ꢚ7)

($

ꢚ7*

($

ꢚ

($

ꢚ7(

($

+ꢔꢕG-ꢛ

ꢚ7*

ꢚ7)

ꢚ7*

ꢚ

+ꢔꢕG-ꢛ

ꢀꢁꢖꢙ.ꢙ4(ꢍ5&6C

ꢀꢁꢗ"ꢀꢜ!,

+ꢍC Aꢒꢓꢉ/ꢔꢒꢉꢓ

ꢗ*>C ꢐ&

ꢗꢐ(C ꢐ)

ꢗꢐ*C ꢐꢐ

ꢗꢐꢍC ꢐ<

ꢗꢐ:C ꢐ=

+(C )

+*C ꢐ

ꢗ(C )

.

+ꢔꢕG-ꢛ

ꢀꢁꢘ%ꢂ

ꢗ+, ꢚ7*

ꢗ+, ꢚ

ꢇꢉꢅꢅ .ꢋꢙꢒ ꢝꢔ ꢔꢆꢒ .ꢆ5

*ꢍ&ꢍ ꢓꢋ9 ()

Figure 12 Utopia 2 Receive Handshake - Back to Back Cells

20 of 49

December 6, 2001

IDT77V1264L200

ꢉꢅꢉꢇ.ꢔꢆꢒ

3ꢆꢅꢅꢔꢒꢕ

3ꢆꢅꢅꢔꢒꢕ5

ꢀꢁꢂꢃꢄ

ꢀꢁ"ꢖꢖꢀ4ꢐ5&6

ꢚ7*

($

ꢚ7)

($

ꢚ7(

($

ꢚ7(

($

ꢚ

($

+ꢔꢕG-ꢛ

ꢀꢁꢂꢃ"8

ꢚ7*

ꢚ7)

ꢚ7(

RXEN

+ꢔꢕG-ꢛ

ꢀꢁꢖꢙ.ꢙ4(ꢍ5&6C

ꢀꢁꢗ"ꢀꢜ!,

ꢗꢐꢍC ꢐ<

ꢗꢐ:C ꢐ=

+(C )

+*C ꢐ

Aꢒꢓꢉ/ꢔꢒꢉꢓ

.

+ꢔꢕG-ꢛ

ꢀꢁꢘ%ꢂ

ꢗ+, ꢚ7(

ꢗ+, ꢚ7*

ꢇꢉꢅꢅ .ꢋꢙꢒ ꢝꢔ ꢔꢆꢒ .ꢆ5

*ꢍ&ꢍ ꢓꢋ9 (*

Figure 13 Utopia 2 Receive Handshake - Delay Between Cells

ꢋꢉ- ꢉꢅꢉꢇ.ꢔꢆꢒ

3ꢆꢅꢅꢔꢒꢕ

3ꢆꢅꢅꢔꢒꢕ5

ꢀꢁꢂꢃꢄ

ꢀꢁ"ꢖꢖꢀ4ꢐ5&6

ꢀꢁꢂꢃ"8

RXEN

ꢚ7*

($

ꢚ7)

($

#

($

ꢚ7(

($

ꢚ7)

+ꢔꢕG-ꢛ

ꢚ7*

ꢚ7)

#

ꢚ7(

+ꢔꢕG-ꢛ

ꢀꢁꢖꢙ.ꢙ4(ꢍ5&6C

ꢀꢁꢗ"ꢀꢜ!,

ꢗ)ꢍC )<

ꢗ):C )=

ꢗ)>C *&

ꢗ*(C *)

ꢗ**C *ꢐ

ꢗ*ꢍC *<

+ꢔꢕG-ꢛ

ꢀꢁꢘ%ꢂ

ꢗ+, #

ꢇꢉꢅꢅ .ꢋꢙꢒ ꢝꢔ ꢔꢆꢒ /ꢋꢆꢝ5

*ꢍ&ꢍ ꢓꢋ9 (ꢐ

Figure 14 Utopia 2 Receive Handshake - Suspended Transfer of Data

!ꢁꢂꢃꢄ

!ꢁꢂꢃ"84*5&6

TXEN4*5&6

!ꢁꢖ"!"4:5&6C

!ꢁꢗ"ꢀꢜ!,

ꢁ

+(

+)

ꢗꢐꢐ

ꢗꢐꢍ

ꢗꢐ<

ꢗꢐ:

ꢗꢐ=

ꢁ

!ꢁꢘ%ꢂ

.

*ꢍ&ꢍ ꢓꢋ9 (<

Figure 15 Utopia 1 Transmit Handshake - Single Cell

21 of 49

December 6, 2001

IDT77V1264L200

!ꢁꢂꢃꢄ

!ꢁꢂꢃ"84*5&6

TXEN4*5&6

!ꢁꢖ"!"4:5&6C

!ꢁꢗ"ꢀꢜ!,

ꢗꢐ<

ꢗꢐ:

ꢗꢐ=

+(

+)

+*

+ꢐ

ꢁ

+ꢍ

!ꢁꢘ%ꢂ

*ꢍ&ꢍ ꢓꢋ9

*ꢍ&ꢍ ꢓꢋ9 (:

Figure 16 Utopia 1 Transmit Handshake - Back-to-Back Cells, and TXEN Suspended Transmission

!ꢁꢂꢃꢄ

!ꢁꢂꢃ"84*5&6

TXEN4*5&6

!ꢁꢖ"!"4:5&6C

!ꢁꢗ"ꢀꢜ!,

ꢗꢐ)

ꢗꢐ*

ꢗꢐꢐ

ꢗꢐꢍ

ꢗꢐ<

ꢁ

ꢗꢐ:

ꢗꢐ=

+(

!ꢁꢘ%ꢂ

.

*ꢍ&ꢍ ꢓꢋ9 (=

Figure 17 Utopia 1 Transmit Handshake - TXEN Suspended Transmission and Back-to-Back Cells (Byte Mode Only)

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ"84*5&6

RXEN4*5&6

+ꢔꢕG-ꢛ

ꢀꢁꢖ"!"4:5&6C

ꢀꢁꢗ"ꢀꢜ!,

ꢗꢐ:

ꢗꢐ=

+(

+)

+*

+ꢔꢕG-ꢛ

ꢀꢁꢘ%ꢂ

*ꢍ&ꢍ ꢓꢋ9 (>

.

Figure 18 Utopia 1 Receive Handshake - Delay Between Cells

22 of 49

December 6, 2001

IDT77V1264L200

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ"84*5&6

RXEN4*5&6

+ꢔꢕG-ꢛ

ꢀꢁꢖ"!"4:5&6C

ꢀꢁꢗ"ꢀꢜ!,

ꢗꢐ:

ꢗꢐ=

+(

ꢗꢐ:

ꢗꢐ=

ꢁ

+(

+)

+ꢔꢕG-ꢛ

ꢀꢁꢘ%ꢂ

.

*ꢍ&ꢍ ꢓꢋ9 )&

Figure 19 Utopia 1 Receive Handshake - RXEN and RXCLAV Control

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ"84*5&6

ꢑꢙꢋꢅꢌ ꢀ'ꢂꢃ"8 ꢆ3.ꢔꢆꢒ 0ꢞꢔ. <@(C ꢋꢉꢕꢔ .ꢉꢋ &'&)C &'()C &'))C &'*)2

RXEN4*5&6

+ꢔꢕG-ꢛ

ꢀꢁꢖ"!"4:5&6C

ꢀꢁꢗ"ꢀꢜ!,

ꢗꢐ)

ꢗꢐ*

ꢗꢐꢐ

ꢗꢐꢍ

ꢗꢐ<

ꢗꢐ:

ꢗꢐ=

ꢁ

+ꢔꢕG-ꢛ

ꢀꢁꢘ%ꢂ

.

*ꢍ&ꢍ ꢓꢋ9 )(

Figure 20 Utopia 1 Receive Handshake - RXCLAV Deassertion

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ"84*5&6

RXEN4*5&6

+ꢔꢕG-ꢛ

ꢀꢁꢖ"!"4:5&6C

ꢀꢁꢗ"ꢀꢜ!,

+(

+)

ꢁ

+*

+ꢐ

+ꢍ

ꢗ(

+ꢔꢕG-ꢛ

ꢀꢁꢘ%ꢂ

*ꢍ&ꢍ ꢓꢋ9 ))

.

Figure 21 Utopia 1 Receive Handshake - RXCLAV Suspended Transfer (Byte Mode Only)

23 of 49

December 6, 2001

IDT77V1264L200

DPI Interface Option

ꢎꢔ. *

ꢎꢔ. &

The DPI interface is relatively new and worth additional description.

The biggest difference between the DPI configurations and the UTOPIA

configurations is that each channel has its own DPI interface. Each

interface has a 4-bit data path, a clock and a start-of-cell signal, for both

the transmit direction and the receive direction. Therefore, each signal is

point-to-point, and none of these signals has high-Z capability. Addition-

ally, there is one master DPI clock input (DPICLK) into the 77V1254L25

which is used as a source for the DPI transmit clock outputs. DPI is a

cell-based transfer scheme like Utopia Level 2, whereas UTOPIA Level

1 transfers can be either byte- or cell-based.

$ꢔꢋ .

+ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ (C 0=5ꢍ2

+ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ (C 0ꢐ5(2

+ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ )C 0=5ꢍ2

+ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ )C 0ꢐ5(2

+ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ *C 0=5ꢍ2

+ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ *C 0ꢐ5(2

+ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ ꢐC 0=5ꢍ2

+ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ ꢐC 0ꢐ5(2

+ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ ꢍC 0=5ꢍ2

+ꢉꢙꢓꢉꢋ ꢞꢌ.ꢉ ꢍC 0ꢐ5(2

ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ (C 0=5ꢍ2

ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ (C 0ꢐ5(2

Another unique aspect of DPI is that it is a symmetrical interface. It is

as easy to connect two PHYs back-to-back as it is to connect a PHY to a

switch fabric chip. In contrast, Utopia is asymmetrical. Note that for the

77V1254L25 the nomenclature "transmit" and "receive" is used in the

naming of the DPI signals, whereas other devices may use more

generic "in" and "out" nomenclature for their DPI signals.

ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ ꢐ:C 0=5ꢍ2

ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ ꢐ:C 0ꢐ5(2

ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ ꢐ=C 0=5ꢍ2

ꢗꢙꢌꢅꢆꢙꢓ ꢞꢌ.ꢉ ꢐ=C 0ꢐ5(2

ꢃꢙ .

Figure 22 DPI Data Format and Sequence

The DPI signals are summarized below, where "Pn_" refers to the

signals for channel number "n":

DPICLK

input to PHY

PHY to ATM

ATM to PHY

Pn_TCLK

Pn_TD[3:0]

Pn_TFRM

Pn_RCLK

Pn_RD[3:0]

Pn_RFRM

ATM to PHY

PHY to ATM

In the transmit direction (ATM to PHY), the ATM layer device asserts

start-of-cell signal (Pn_TFRM) for one clock cycle, one clock prior to

driving the first nibble of the cell on Pn_TD[3:0]. Once the ATM side has

begun sending a cell, it is prepared to send the entire cell without inter-

ruption. The 77V1254L25 drives the transmit DPI clocks (Pn_TCLK)

back to the ATM device, and can modulate (gap) it to control the flow of

data. Specifically, if it cannot accept another nibble, the 77V1254L25

disables Pn_TCLK and does not generate another rising edge until it

has room for the nibble. Pn_TCLK are derived from the DPICLK free

running clock source.

The DPI protocol is exactly symmetrical in the receive direction, with

the 77V1254L25 driving the data and start-of-cell signals while receiving

Pn_RCLK as an input.

The DPI data interface is four bits, so the 53 bytes of an ATM cell are

transferred in 106 cycles. Figure 22 shows the sequence of that data

transfer. igures 23 through 31 show how the handshake operates.

24 of 49

December 6, 2001

IDT77V1264L200

ꢗBꢀꢂꢃꢄ 0ꢔꢒ2

ꢗBꢀ$ꢀ# 0ꢆA.2

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ (&ꢐ

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ (&ꢍ

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ &

ꢗBꢀꢖ0*5&2 0ꢆA.2

ꢁ

*ꢍ&ꢍ ꢓꢋ9 )ꢐ

*ꢍ&ꢍ ꢓꢋ9 )ꢍ

*ꢍ&ꢍ ꢓꢋ9 )<

Figure 23 DPI Receive Handshake - One Cell Received

ꢗBꢀꢂꢃꢄ 0ꢔꢒ2

ꢗBꢀ$ꢀ# 0ꢆA.2

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ (&ꢐ

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ &

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ (

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ (&ꢍ

ꢂꢉꢅꢅ )

ꢗBꢀꢖ0*5&2 0ꢆA.2

ꢁ

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ &

ꢚꢔꢞꢞꢅꢉ (

.

Figure 24 DPI Receive Handshake - Back-to-Back Cells

ꢗBꢀꢂꢃꢄ 0ꢔꢒ2

ꢗBꢀ$ꢀ# 0ꢆA.2

ꢂꢉꢅꢅ )

ꢚꢔꢞꢞꢅꢉ (

ꢂꢉꢅꢅ (

ꢂꢉꢅꢅ )

ꢚꢔꢞꢞꢅꢉ &

ꢂꢉꢅꢅ )

ꢚꢔꢞꢞꢅꢉ )

ꢂꢉꢅꢅ )

ꢗBꢀꢖ0*5&2 0ꢆA.2

ꢚꢔꢞꢞꢅꢉ (&ꢐ

ꢚꢔꢞꢞꢅꢉ (&ꢍ

ꢚꢔꢞꢞꢅꢉ *

ꢚꢔꢞꢞꢅꢉ ꢐ

Figure 25 DPI Receive Handshake - ATM Layer Device Suspends Transfer

"!# ꢃꢙꢌꢉꢋ ꢖꢉꢊꢔꢇꢉ ꢚꢆ. ꢀꢉꢙꢓꢌ

::8()ꢍꢐ ꢚꢆ. ꢀꢉꢙꢓꢌ

ꢗBꢀꢂꢃꢄ 0ꢔꢒ2

ꢗBꢀ$ꢀ# 0ꢆA.2

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ (&ꢐ

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ (&ꢍ

ꢂꢉꢅꢅ )

ꢚꢔꢞꢞꢅꢉ &

ꢂꢉꢅꢅ )

ꢚꢔꢞꢞꢅꢉ (

ꢂꢉꢅꢅ )

ꢗBꢀꢖ0*5&2 0ꢆA.2

ꢁ

ꢚꢔꢞꢞꢅꢉ )

*ꢍ&ꢍ ꢓꢋ9 ):

.

Figure 26 DPI Receive Handshake - Neither Device Ready

25 of 49

December 6, 2001

IDT77V1264L200

ꢗB!ꢂꢃꢄ 0ꢆA.2

ꢗB!$ꢀ# 0ꢔꢒ2

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ &

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ (

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ (&ꢐ

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ (&ꢍ

ꢗB!ꢖ0*5&2 0ꢔꢒ2

ꢁ

Figure 27 DPI Transmit Handshake - One Cell for Transmission

ꢗB!ꢂꢃꢄ 0ꢆA.2

ꢗB!$ꢀ# 0ꢔꢒ2

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ (&ꢐ

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ &

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ (

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ (&ꢍ

ꢂꢉꢅꢅ )

ꢗB!ꢖ0*5&2 0ꢔꢒ2

ꢁ

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ &

ꢚꢔꢞꢞꢅꢉ (

Figure 28 DPI Transmit Handshake - Back-to-Back Cells for Transmission

ꢗB!ꢂꢃꢄ 0ꢆA.2

ꢗB!$ꢀ# 0ꢔꢒ2

ꢗB!ꢖ0*5&2 0ꢔꢒ2

ꢂꢉꢅꢅ )

ꢚꢔꢞꢞꢅꢉ (

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ (&ꢍ

ꢂꢉꢅꢅ )

ꢚꢔꢞꢞꢅꢉ &

ꢂꢉꢅꢅ )

ꢚꢔꢞꢞꢅꢉ )

ꢂꢉꢅꢅ )

ꢚꢔꢞꢞꢅꢉ (&ꢐ

ꢚꢔꢞꢞꢅꢉ *

ꢚꢔꢞꢞꢅꢉ ꢐ

Figure 29 DPI Transmit Handshake - 77V1254L25 Transmit FIFO Full

::8()ꢍꢐ ꢚꢆ. ꢀꢉꢙꢓꢌ

"!# ꢃꢙꢌꢉꢋ ꢖꢉꢊꢔꢇꢉ ꢚꢆ. ꢀꢉꢙꢓꢌ

ꢗB!ꢂꢃꢄ 0ꢆA.2

ꢗB!$ꢀ# 0ꢔꢒ2

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ (&ꢐ

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ (&ꢍ

ꢂꢉꢅꢅ )

ꢚꢔꢞꢞꢅꢉ (

ꢂꢉꢅꢅ )

ꢚꢔꢞꢞꢅꢉ )

ꢗB!ꢖ0*5&2 0ꢔꢒ2

ꢁ

ꢚꢔꢞꢞꢅꢉ &

*ꢍ&ꢍ ꢓꢋ9 *(

.

Figure 30 DPI Transmit Handshake - Neither Device Ready

26 of 49

December 6, 2001

IDT77V1264L200

signal control is provided by bit 5 of the Master Control Registers. When

this bit is set (=1), receive cell errors will be flagged via interrupt signal-

ling and all other interrupt conditions are masked. These errors include:

Control and Status Interface

Utility Bus

The Utility Bus is a byte-wide interface that provides access to the

registers within the IDT77V1264L200. These registers are used to select

desired operating characteristics and functions, and to communicate

status to external systems.

Bad receive HEC

Short (fewer than 53 bytes) cells

Received cell symbol error

Normal interrupt operations are performed by setting bit 0 and

clearing bit 5 in the Master Control Registers. INT (pin 85) will go to a

low state when an interrupt condition is detected. The external system

should then interrogate the 77V1264L200 to determine which one (or

more) conditions caused this flag, and reset the interrupt for further

occurrences. This is accomplished by reading the Interrupt Status

Registers. Decoding the bits in these bytes will tell which error condition

caused the interrupt. Reading these registers also:

The Utility Bus is implemented using a multiplexed address and data

bus (AD[7:0]) where the register address is latched via the Address

Latch Enable (ALE) signal.

The Utility Bus interface is comprised of the following pins:

AD[7:0], ALE, CS, RD, WR

Read Operation

Refer to the Utility Bus timing waveforms in Figures 43 - 44. A

register read is performed as follows:

clears the (sticky) interrupt status bits in the registers that are read

resets INT

1. Initial condition:

This leaves the interrupt system ready to signal an alarm for further

problems.

LED Control and Signalling

The LED outputs provide bi-directional LED drive capability of 8 mA.

As an example, the RXLED outputs are described in the truth table:

–

RD, WR, CS not asserted (logic 1)

ALE not asserted (logic 0)

2. Set up register address:

–

place desired register address on AD[7:0]

set ALE to logic 1;

latch this address by setting ALE to logic 0.

3. Read register data:

State

Pin Voltage

–

Remove register address data from AD[7:0]

Cells being received

Low

assert CS by setting to logic 0;

assert RD by setting to logic 0

Cells not being received High

wait minimum pulse width time (see AC specifications)

As illustrated in the following drawing, this could be connected to

provide for a two-LED condition indicator. These could also be different

colors to provide simple status indication at a glance. (The minimum

value for R should be 330Ω).

Write Operation

A register write is performed as described below:

1. Initial condition:

–

RD, WR, CS not asserted (logic 1)

ALE not asserted (logic 0)

LED Indicator

2. Set up register address:

*D*8

–

place desired register address on AD[7:0]

set ALE to logic 1;

ꢀ

0ꢜꢒꢓꢔꢇꢙ.ꢉ 5 ꢂꢉꢅꢅ

latch this address by setting ALE to logic 0.

ꢞꢉꢔꢒꢕ ꢋꢉꢇꢉꢔꢊꢉꢓ ꢆꢋ

3. Write data:

.ꢋꢙꢒ ꢝꢔ..ꢉꢓ2

–

place data on AD[7:0]

ꢀ'ꢃꢑꢖ0*5&2

assert CS by setting to logic 0;

!'ꢃꢑꢖ0*5&2

assert WR (logic 0) for minimum time (according to timing

specification); reset WR to logic 1 to complete register write

cycle.

0ꢜꢒꢓꢔꢇꢙ.ꢉ 5 ꢂꢉꢅꢅ ꢙꢋꢉ

ꢒꢆ. ꢞꢉꢔꢒꢕ ꢋꢉꢇꢉꢔꢊꢉꢓ ꢆꢋ

ꢀ

.ꢋꢙꢒ ꢝꢔ..ꢉꢓ2

Interrupt Operations

*ꢍ&ꢍ ꢓꢋ9 *)

The IDT77V1264L200 provides a variety of selectable interrupt and

signalling conditions which are useful both during ‘normal’ operation,

and as diagnostic aids. Refer to the Status and Control Register List

section.

Overall interrupt control is provided via bit 0 of the Master Control

Registers. When this bit is cleared (set to 0), interrupt signalling is

prevented on the respective port. The Interrupt Mask Registers allow

individual masking of different interrupt sources. Additional interrupt

TXLED Truth Table

State

Pin Voltage

Cells being transmitted

Low

Cells not being transmitted High

27 of 49

December 6, 2001

IDT77V1264L200

::8()ꢍꢐ ꢚꢆ. ꢀꢉꢙꢓꢌ

"!# ꢃꢙꢌꢉꢋ ꢖꢉꢊꢔꢇꢉ ꢚꢆ. ꢀꢉꢙꢓꢌ

ꢗB!ꢂꢃꢄ 0ꢆA.2

ꢗB!$ꢀ# 0ꢔꢒ2

ꢂꢉꢅꢅ (

ꢚꢔꢞꢞꢅꢉ (&ꢍ

ꢂꢉꢅꢅ )

ꢚꢔꢞꢞꢅꢉ &

ꢂꢉꢅꢅ )

ꢚꢔꢞꢞꢅꢉ (

ꢂꢉꢅꢅ )

ꢚꢔꢞꢞꢅꢉ )

ꢗB!ꢖ0*5&2 0ꢔꢒ2

ꢁ

ꢚꢔꢞꢞꢅꢉ (&ꢐ

*ꢍ&ꢍ ꢓꢋ9 *(

.

Figure 31 DPI Transmit Handshake - Neither Device Ready

Diagnostic Functions

Loopback

There are two loopback modes supported by the 77V1264L200. The loopback mode is controlled via bits 1 and 0 of the Diagnostic Control Regis-

ters:

Bit 1

Bit 0

Mode

Normal operating mode

0

1

0

1

PHY Loopback

Line Loopback

Normal Mode

This mode, Figure 32, supports normal operating conditions: data to be transmitted is transferred to the TC, where it is queued and formatted for

transmission by the PMD. Receive data from the PMD is decoded along with its clock for transfer to the receiving "upstream system".

PHY Loopback

As Figure 33 illustrates below, this loopback mode provides a connection within the PHY from the transmit PHY-ATM interface to the PHY-ATM

receive interface. Note that while this mode is operating, no data is forwarded to or received from the line interface. When Bits [1:0] in the Diagnostic

Control Registers are set to 10, the PHY loopback mode works only if clock multiplier is 1x. For higher multiplies, these bits must be set to 01.

Line Loopback

Figure 34 might also be called “remote loopback” since it provides for a means to test the overall system, including the line. Since this mode will

probably be entered under direction from another system (at a remote location), receive data is also decoded and transferred to the upstream system

to allow it to listen for commands. A common example would be a command asking the upstream system to direct the TC to leave this loopback state,

and resume normal operations.

28 of 49

December 6, 2001

IDT77V1264L200

ꢜꢖ!::8()ꢍꢐ

"!# ꢃꢙꢌꢉꢋ ꢖꢉꢊꢔꢇꢉ

ꢃꢔꢒꢉ

!ꢂ Aꢞꢅꢙꢌꢉꢋ

ꢗ#ꢖ Aꢞꢅꢙꢌꢉꢋ

ꢜꢒ.ꢉꢋ/ꢙꢇꢉ

*ꢍ&ꢍ ꢓꢋ9 **

Figure 32 Normal Mode

ꢜꢖ!::8()ꢍꢐ

IDT77V1264L200

"!# ꢃꢙꢌꢉꢋ ꢖꢉꢊꢔꢇꢉ

ꢃꢔꢒꢉ

ꢗ#ꢖ Aꢞꢅꢙꢌꢉꢋ

!ꢂ Aꢞꢅꢙꢌꢉꢋ

ꢜꢒ.ꢉꢋ/ꢙꢇꢉ

*ꢍ&ꢍ ꢓꢋ9 *ꢐ

Figure 33 PHY Loopback

ꢜꢖ!::8()ꢍꢐ

IDT77V1264L200

"!# ꢃꢙꢌꢉꢋ ꢖꢉꢊꢔꢇꢉ

ꢗ#ꢖ

Aꢞꢅꢙꢌꢉꢋ

ꢃꢔꢒꢉ

!ꢂ Aꢞꢅꢙꢌꢉꢋ

ꢜꢒ.ꢉꢋ/ꢙꢇꢉ

*ꢍ&ꢍ ꢓꢋ9 *ꢍ

Figure 34 Line Loopback

29 of 49

December 6, 2001

IDT77V1264L200

Counters

Jitter in Loop Timing Mode

Several condition counters are provided to assist external systems

(e.g. software drivers) in evaluating communications conditions. It is

anticipated that these counters will be polled from time to time (user

selectable) to evaluate performance. A separate set of registers exists

for each channel of the PHY.

One of the primary concerns when using loop timing mode is the

amount of jitter that gets added each time data is transmitted. Table 4

shows the jitter measured at various data rates. The set-up shown in

Figure 35 was used to perform these tests. The maximum jitter seen

was at TX point 5 and the minimum jitter was at point 2. The loop timing

jitter is defined as the amount of jitter generated by each TX node. In

other words, the loop timing jitter or the jitter added by a loop-timed port

in the set-up below is the difference between the Total Output Jitter and

the Total Input Jitter.

Symbol Error Counters

–

8 bits

counts all invalid 5-bit symbols received

Transmit Cell Counters

–

16 bits

–

counts all transmitted cells

Receive Cell Counters

–

16 bits

–

counts all received cells, excluding idle cells and HEC errored

cells

Receive HEC Error Counters

–

5 bits

–

counts all HEC errors received

The TXCell and RXCell counters are sized (16 bits) to provide a full

cell count (without roll over) if the counter is read once/second. The

Symbol Error counter and HEC Error counter were given sufficient size

to indicate exact counts for low error-rate conditions. If these counters

overflow, a gross condition is occurring, where additional counter resolu-

tion does not provide additional diagnostic benefit.

Reading Counters

1. Decide which counter value is desired. Write to the Counter

Select Register(s) (0x06, 0x16, 0x26 and 0x36) to the bit location

corresponding to the desired counter. This loads the High and

Low Byte Counter Registers with the selected counter’s value,

and resets this counter to zero.

Note: Only one counter may be enabled at any time in each

of the Counter Select Registers.

2. Read the Counter Registers (0x04, 0x14, 0x24 or 0x34 (low

byte)) and (0x05, 0x15, 0x25 or 0x35 (high byte)) to get the value.

Further reads may be accomplished in the same manner by writing

to the Counter Select Registers.

Note: The PHY takes some time to set up the low and high

byte counters after a specific counter has been selected in the

Counter Selector register. This time delay (in µS) varies with

the line rate and can be calculated as follows:

Time delay (µS) =

12.5___

line rate (Mbps)

Loop Timing Feature

The 77V1264L200 also offers a loop timing feature for specific appli-

cations where data needs to be repeated / transmitted using the recov-

ered clock. If the loop timing mode is enabled in the Enhanced Control

Register 1 bit 6, the recovered receive clock is used as to clock out data

on transmit side. This mode is port specific, i.e., the user can select one

or more ports to be in loop timing mode. In normal mode, the transmitter

transmits data using the multiplied oscillator clock.

30 of 49

December 6, 2001

IDT77V1264L200

OSC

1

2

RX

TX

Data

CLK

TX

RX

P1

Loop Timing Mode

P0

Normal Mode

3

4

RX

TX

Data

CLK

P2

Loop Timing Mode

Data

RX

TX

CLK

P3

5

SWITCH

Loop Timing Mode

Figure 35 Test Setup for Loop Timing Jitter Measurements

Loop Timing Jitter Specification

Line Rate

Mbps

Data Rate

Mbps

Min.

Typ.

Max.

Note

32

64

25.6

51.2

--

100 ps

80 ps

--

Using 32Mhz OSC, multiplier at 1x

Using 64Mhz OSC, multiplier at 1x

Using 32Mhz OSC, multiplier at 4x

Using 64Mhz OSC, multiplier at 4x

128

256

102.4

204.8

20 ps

Table 4 Loop Timing Jitter

The waveforms below show some of the measurements taken with the set-up in Figure 35. Using the formula above, the jitter specification was

derived. For example, at data rate of 25.6Mbps, jitter added going through Line Card 3 is 1.5ns -1.4ns (as shown in the waveforms below).

31 of 49

December 6, 2001

IDT77V1264L200

Jitter at 25.6Mbps at point 5 with respect to point 1

Jitter at 25.6Mbps at point 4 with respect to point 1

Jitter at 51.2Mbps at point 4 with respect to point 1

Jitter at 51.2Mbps at point 5 with respect to point 1

32 of 49

December 6, 2001

IDT77V1264L200

Jitter at 102.4Mbps at point 5 with respect to point 1

Jitter at 102.4Mbps at point 4 with respect to point 1

Jitter at 256Mbps at point 5 with respect to point 1

Jitter at 256Mbps at point 4 with respect to point 1

From the above measurements taken, the amount of jitter being added at each TX point is not significant. These tests were also run at line rates of

256Mbps for extended periods of time (64 hours) and no bit errors were seen.

VPI/VCI Swapping

For compatibility with IDT's SwitchStar products (77V400 and 77V500), the 77V1254L25 has the ability to swap parts of the VPI/VCI address

space in the header of receive cells. This function is controlled by the VPI/VCI Swap bits, which are bit 5 of the Enhanced Control Registers (0x08,

0x18, 0x28 and 0x38). The portions of the VPI/VCI that are swapped are shown below. Bits X(7:0) are swapped with Y(7:0) when the VPI/VCI Swap

bit is set and the chip is in DPI mode.

:

&

:

&

8ꢗꢜ

8ꢂꢜ

ꢎꢌ.ꢉ &

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ꢎꢌ.ꢉ ꢐ

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,: ,< ,ꢍ ,ꢐ ꢎꢌ.ꢉ (

;$ꢂꢏ8ꢗꢜ

8ꢗꢜ

8ꢂꢜ

,* ,) ,( ,&

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ꢎꢌ.ꢉ ꢐ

8ꢂꢜ

ꢗ!ꢜ

ꢂꢃꢗ

+ꢑꢂ

33 of 49

December 6, 2001

IDT77V1264L200

Line Side (Serial) Interface

Each of the four ports has two pins for differential serial transmission, and two pins for differential serial receiving.

PHY to Magnetics Interface

A standard connection to 100Ω and 120Ω unshielded twisted pair cabling is shown in Figure 36. Note that the transmit signal is somewhat attenu-

ated in order to meet the launch amplitude specified by the standards. The external receive circuitry is designed to attenuate low frequencies in order

to compensate for the high frequency attenuation of the cable.

Also, the receive circuitry biases the positive and negative RX inputs to slightly different voltages. This is done so that the receiver does not receive

false signals in the absence of a real signal. This can be important because the 77V1264L200 does not disable error detection or interrupts when an

input signal is not present.

When connecting to UTP at 51.2Mbps and 204.8Mbps, it is necessary to use magnetics with sufficient bandwidth. Refer to Table 6 for the recom-

mended magnetics.

ꢚꢛꢜꢃꢃꢝꢊꢞꢎꢌ

IDT77V1264L200

ꢈꢇꢛ

ꢚꢛꢜꢃꢃꢝꢊꢞꢎꢍ

ꢆꢊ

ꢍ

ꢌ

ꢎ

ꢜ"ꢛ#

ꢜ"ꢛ$

ꢊ

ꢞ

ꢌ

ꢍ

ꢎ

!

ꢃ

ꢉ

ꢃ

ꢉ

ꢆꢌ

ꢞ

ꢆꢞ

ꢝꢛꢛ

ꢆꢎ

ꢏꢐꢑꢒꢓꢂꢁꢔꢕ

ꢗꢊ

ꢆꢉ

ꢆ"ꢛ#

ꢊ!

ꢆꢃ

%ꢊ

ꢆꢍ

ꢊꢄ

ꢋ

ꢆꢋ

ꢗꢞ

ꢊꢎ

ꢆ"ꢛ$

ꢊꢍ

ꢊꢌ

ꢊꢞ

ꢆ!

ꢈꢇꢛ

.

*ꢍ&ꢍ ꢓꢋ9 *<

ꢈꢇꢛ

Figure 36 Recommended Connection to Magnetics

Component

R1

Value

47Ω

Tolerance

±5%

R2

R3

R4

R5

R6

R7

R8

R9

47Ω

±5%

620Ω

110Ω

2700Ω

82Ω

33Ω

Table 5 Analog Component Values

34 of 49

December 6, 2001

IDT77V1264L200

Component

C1

Value

470pF

Tolerance

±20%

C2

L1

470pF

±20%

3.3µH

Table 5 Analog Component Values

Magnetics Modules for 25.6 Mbps

Pulse PE-67583 or R4005

TDK TLA-6M103

www.pulseeng.com

www.component.tdk.com

Magnetics Module for 51.2 Mbps

Pulse R4005

www.pulseeng.com

Magnetics Module for 204.8 Mbps

Pulse ST6200T

www.pulseeng.com

Table 6 Magnetics Modules

Status and Control Register List

The 77V1264L200 has 41 registers that are accessible through the utility bus. Each of the four ports has 9 registers dedicated to that port. There is

only one register (0x40) which is not port specific.

For those register bits which control operation of the Utopia interface, the operation of the Utopia interface is determined by the registers corre-

sponding to the port which is selected at that particular time. For consistent operation, the Utopia control bits should be programmed the same for all

four ports, except for the Utopia 2 port addresses in the Enhanced Control Registers.

Register Address

Register Name

Port 0

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

Port 1

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

Port 2

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

Port 3

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

All Ports

Master Control Registers

Interrupt Status Registers

Diagnostic Control Registers

LED Driver and HEC Status/control

Low Byte Counter Register [7:0]

High Byte Counter Register [15:8]

Counter Registers Read Select

Interrupt Mask Registers

Enhanced Control 1 Registers

Enhanced Control 2 Registers

RXREF and TXREF Control Register

0x40

Nomenclature

"Reserved" register bits, if written, should always be written "0"

R-only or W-only = register is read-only or write-only

“0” = ‘cleared’ or ‘not set’

R/W = register may be read and written via the utility bus

sticky = register bit is cleared after the register containing it is read; all sticky bits are read-only

“1” = ‘set’

35 of 49

December 6, 2001

IDT77V1264L200

Master Control Registers

Addresses: 0x00, 0x10, 0x20, 0x30

Bit

Type

R/W

Initial State

Function

7

6

0

Reserved

R/W

1 = discard errored cells Discard Receive Error Cells - On receipt of any cell with an error (e.g. short cell, invalid command mnemonic, receive

HEC error (if enabled), this cell will be discarded and will not enter the receive FIFO.

5

R/W

0 = all interrupts

Enable Cell Error Interrupts Only - If Bit 0 in this register is set (Interrupts Enabled), setting of this bit enables only

"Received Cell Error" (as defined in bit 6) to trigger interrupt line.

4

3

R/W

0 = disabled

Transmit Data Parity Check - Directs TC to check parity of TXDATA against parity bit located in TXPARITY.

1 = discard idle cells

Discard Received Idle Cells - Directs TC to discard received idle (VPI/VCI = 0) cells from PMD without signalling

external systems.

2

1

0

R/W

0 = not halted

Halt Transmit - Halts transmission of data from TC to PMD and forces the TXD outputs to the "0" state

UTOPIA Level 1 mode select: - 0 = cell mode, 1 = byte mode. Not applicable for Utopia 2 or DPI modes.

0 = cell mode

1 = enable interrupts

Enable Interrupt Pin (Interrupt Mask Bit) - Enables interrupt output pin (pin 85). If cleared, pin is always high and

interrupt is masked. If set, an interrupt will be signaled by setting the interrupt pin to "0". It doesn’t affect the Interrupt

Status Registers.

Interrupt Status Registers

Addresses: 0x01, 0x11, 0x21, 0x31

Bit

Type

Initial State

Reserved

Function

7

6

R

0 = Bad Signal

Good Signal Bit - See definition on page 14.

1 - Good Signal 0 - Bad Signal

5

4

sticky

0

HEC error cell received - Set when a HEC error is detected on received cell.

"Short Cell" Received - Interrupt signal which flags received cells with fewer than 53 bytes. This condition is detected

when receiving Start-of-Cell command bytes with fewer than 53 bytes between them.

3

2

sticky

0

Transmit Parity Error - If Bit 4 of Register 0x00 / 0x10 / 0x20 / 0x30 is set (Transmit Data Parity Check), this interrupt

flags a transmit data parity error condition. Odd parity is used.

Receive Signal Condition change - This interrupt is set when the received ’signal’ changes either from ’bad to good’

or from ’good to bad’.

1

0

sticky

0

Received Symbol Error - Set when an undefined 5-bit symbol is received.

Receive FIFO Overflow - Interrupt which indicates when the receive FIFO has filled and cannot accept additional data.

Diagnostic Control Registers

Addresses: 0x02, 0x12, 0x22, 0x32

Bit

Type

R/W

Initial State

0 = normal

Function

7

Force TXCLAV deassert - (applicable only in Utopia 1 and 2 modes) Used during line loopback mode to prevent

upstream system from continuing to send data to the 77V1264L200. Not applicable in DPI mode.

36 of 49

December 6, 2001

IDT77V1264L200

Addresses: 0x02, 0x12, 0x22, 0x32

Bit

Type

R/W

Initial State

0 = UTOPIA

Function

6

RXCLAV Operation Select - (for Utopia 1 mode) The UTOPIA standard dictates that during cell mode operation, if the

receive FIFO no longer has a complete cell available for transfer from PHY, RXCLAV is deasserted following transfer of

the last byte out of the PHY to the upstream system. With this bit set, early deassertion of this signal will occur coinci-

dent with the end of Payload byte 44 (as in octet mode for TXCLAV). This provides early indication to the upstream

system of this impending condition.

0 = "Standard UTOPIA RXCLAV’

1 = "Cell mode = Byte mode"

5

R/W

1 = tri-state

Single/Multi-PHY configuration select - (applicable and writable only in Utopia 1 mode)

0 = single:

Never tri-state RXDATA, RXPARITY and RXSOC

1 = Multi-PHY mode: Tri-state RXDATA, RXPARITY and RXSOC when RXEN = 1

4

3

R/W

0 = normal

RFLUSH = Clear Receive FIFO - This signal is used to tell the TC to flush (clear) all data in the receive FIFO. The TC

signals this completion by clearing this bit.

Insert Transmit Payload Error - Tells TC to insert cell payload errors in transmitted cells. This can be used to test

error detection and recovery systems at destination station, or, under loopback control, at the local receiving station.

This payload error is accomplished by flipping bit 0 of the last cell payload byte.

2

R/W

0 = normal

Insert Transmit HEC Error - Tells TC to insert HEC error in Byte 5 of cell. This can be used to test error detection and

recovery systems in downstream switches, or, under loopback control, the local receiving station. The HEC error is

accomplished by flipping bit 0 of the HEC byte.

1,0

00 = normal

Loopback Control

bit # 1

0

0 Normal mode (receive from network)

1

0

0 PHY Loopback (with clock recovery)¹

1 Line Loopback

1 PHY Loopback (with clock recovery)¹

^1.When Bits [1:0] in the Diagnostic Control Registers are set to 10, the PHY loopback mode works only if clock multiplier is 1x. For higher multiplies, these bits must be set to 01.

LED Driver and HEC Status/Control Registers

Addresses: 0x03, 0x13, 0x23, 0x33

Bit

Type

Initial State

Function

7

6

0

Reserved

R/W

0 = enable checking

Disable Receive HEC Checking (HEC Enable) - When not set, the HEC is calculated on first 4 bytes of received cell,

and compared against the 5th byte. When set (= 1), the HEC byte is not checked.

5

R/W

0 = enable calculate & Disable Transmit HEC Calculate & Replace - When set, the 5th header byte of cells queued for transmit is not

replace

replaced with the HEC calculated across the first four bytes of that cell.

4, 3

00 = 1 cycle

RXREF Pulse Width Select - See notes about 8KHz Timing Marker in the Functional Description Section.

bit #

4

3 .

0

0 RXREF active for 1 OSC cycle

1 RXREF active for 2 OSC cycles

0 RXREF active for 4 OSC cycles

1 RXREF active for 8 OSC cycles

0

1

2

1

0

R

1 = empty

FIFO Status

1 = TxFIFO empty

0 = Cell Transmitted

0 = Cell Received

0 = TxFIFO not empty

1

TXLED Status

RXLED Status

1 = Cell Not Transmitted

1 = Cell Not Received

37 of 49

December 6, 2001

IDT77V1264L200

Low Byte Counter Registers [7:0]

Addresses: 0x04, 0x14, 0x24, 0x34

Bit

[7:0]

Type

Initial State

0x00

Function

R

Provides low byte of counter value selected via registers 0x06, 0x16, 0x26, and 0x36

High Byte Counter Registers [15:8]

Addresses: 0x05, 0x15, 0x25, 0x35

Bit

[7:0]

Type

Initial State

0x00

Function

R

Provides high-byte of counter value selected via registers 0x06, 0x16, 0x26, and 0x36

Counter Select Registers

Addresses: 0x06, 0x16, 0x26, 0x36

Bit

Type

Initial State

Function

7

6

5

4

3

2

1

0

—

0

Reserved.

—

W

Reserved.

Symbol Error Counter.

TXCell Counter.

0

RXCell Counter. Cells with HEC errors are never counted.

Receive HEC Error Counter.

0

Note: For proper operation, only one bit may be set in a Counter Select Register at any time.

Interrupt Mask Registers

Addresses: 0x07, 0x17, 0x27, 0x37

Bit

Type

Initial State

Function

7

6

5

4

3

2

1

0

Reserved.

R/W

0 = interrupt enabled

HEC Error Cell.

R/W

Short Cell Error.

Transmit Parity Error.

Receive Signal Condition Change.

Receive Cell Symbol Error.

Receive FIFO Overflow.

Note: When set to "1", these bits mask the corresponding interrupts going to the interrupt pin (INT). When set to "0", the interrupts are

unmasked. These interrupts correspond to the interrupt status bits in the Interrupt Status Registers.

38 of 49

December 6, 2001

IDT77V1264L200

Enhanced Control 1 Registers

Addresses: 0x08, 0x18, 0x28, 0x38

Bit

Type

Initial State

0 = not reset

Function

7

6

W

Individual Port Software Reset 1= Reset. This bit is self-cleaning; It isn’t necessary to write “0” to exit reset.

R/W

0 = OSC

Transmit Line Clock (or Loop Timing Mode). When set to 0, the OSC input is used as the transmit line clock.

When set to 1, the recovered receive clock is used as the transmit line clock.

5

R/W

0 = no swap

VPI/VCI Swap DPI mode only. Receive direction only. See description earlier.

4-0

Port 0 (Reg 0x08) 00000 Utopia 2 Port Address When operating in Utopia 2 Mode, these register bits determine the Utopia 2 port address

Port 1 (Reg 0x18) 00001

Port 2 (Reg 0x28) 00010

Port 3 (Reg 0x38) 00011

Enhanced Control 2 Registers

Addresses: 0x09, 0x19, 0x29, 0x39

Bit

7-6

Type

Initial State

Function

R/W

00

Line Rate Control These bits determine the line bit rate relative to the reference clock, as well as the pre-driver

strength for the TXD+/- outputs.

00 Clock multiplier = 1x, pre-driver strength is “standard”

01 Clock multiplier = 2x, pre-driver strength is “standard”

10 Clock multiplier = 4x, pre-driver strength is “strong”

11 Reserved

5

4

3

2

1

0

R/W

0

Reserved

RXREF and TXREF Control Register

Addresses: 0x40

Bit

7-6

Type

Initial State

Function

R/W

W

0 = RXREF0 (Port 0) RXREF Source Select Selects which of the four ports (0-3) is the source of RXREF.

5

0 = not reset

0

Master Software Reset 1 = Reset. This bit is self-cleaning; it isn’t necessary to write “0” to exit reset.

4

Reserved

3-0

R/W

0000 = not looped

RXREF to TXREF Loop Select When set to 0, TXREF is used to generate X_8 timing marker commands.

When set to 1, TXREF input is ignored, and received X_8 timing commands are looped back and added to the transmit

stream of that same port. It is recommended that the RXREF pulse width be set to 2x, 4x, and 8x or greater when the

clock multiplier is set to 1x, 2x, or 4x respectively and bits 3-0 are set to 1. Refer to Figure 7.

bit 3: port 3

bit 2: port 2

bit 1: port 1

bit 0: port 0

39 of 49

December 6, 2001

IDT77V1264L200

Absolute Maximum Ratings

Symbol

Rating

Value

Unit

VTERM

TBIAS

TSTG

IOUT

Terminal Voltage with Respect to GND

Temperature Under Bias

Storage Temperature

-0.5 to +5.5

V

-55 to +125 °C

-55 to +120 °C

DC Output Current

50

mA

Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Recommended DC Operating Conditions

Symbol

Parameter

Min.

Typ. Max. Unit

VDD

Digital Supply Voltage

Digital Ground Voltage

Input High Voltage

Input Low Voltage

3.13

0

3.3

0

3.47

0

V

GND

VIH

2.0

-0.3

3.13

0

____

3.3

0

5.25

0.8

3.47

0

VIL

AVDD

AGND

VDIF

Analog Supply Voltage

Analog Ground Voltage

VDD - AVDD

-0.5

0

0.5

Capacitance (TA = +25°C, F = 1MHz)

Symbol

Parameter

Conditions Max.

Unit

1

CIN

Input Capacitance

I/O Capacitance

VIN = 0V

10

pF

1

CIO

VOUT = 0V

^1.Characterized values, not tested.

DC Electrical Characteristics (All Pins except TX+/- and RX+/-)

Symbol

Parameter

Test Conditions

Min.

Max. Unit

ILI

Input Leakage Current

Gnd ≤ VIN ≤ VDD

-5

5

µA

V

ILO

/O (as input) Leakage Current

Output Logic "1" Voltage

Gnd ≤ VIN ≤ VDD

-10

2.4

—

10

—

1

2

VOH1

VOH2

IOH = -2mA, VDD = min.

Output Logic "1" Voltage

IOH = -8mA, VDD = min.

—

V

3

VOL

Output Logic "0" Voltage

IOL = -8mA, VDD = min.

0.4

91

V

4, 5

IDD1

Digital Power Supply Current - VDD

OSC = 32 MHz, all outputs unloaded

OSC = 64 MHz, all outputs unloaded

OSC = 256 MHz, all outputs unloaded

—

mA

—

169

197

44

—

5

IDD2

Analog Power Supply Current - AVDD OSC = 32 MHz, all outputs unloaded

OSC = 64 MHz, all outputs unloaded

—

54

OSC = 256 MHz, all outputs unloaded

—

61

^1.For AD[7:0] pins only.

^2.For all output pins except AD[7:0], INT and TX+/-.

^3.For all output pins except TX+/-.

^4.Add 15mA for each TX+/- pair that is driving a load.

^5.Total supply current is the sum of IDD1 and IDD2

40 of 49

December 6, 2001

IDT77V1264L200

DC Electrical Characteristics (TX+/- Output Pins Only)

Symbol

Parameter

Test Conditions

IOH = -20mA

IOL = -20mA

Min.

Max.

Unit

VOH1

VOL

Output Logic High Voltage

Output Logic Low Voltage

VDD - 0.5V

—

V

0.5

V

DC Electrical Characteristics (RXD+/- Input Pins Only)

Symbol

Parameter

RXD+/- input voltage range

Min.

Typ

Max.

Unit

VIR

0

—

VDD

V

VIP

RXD+/- input peak-to-peak differential voltage

RXD+/- input common mode voltage

0.6

1.0

2*VDD

VDD-0.5

VICM

VDD/2

UTOPIA Level 2 Bus Timing Parameters

Symbol

Parameter

Min.

Max.

Unit

t1

t2

t3

t4

t5

t6

t7

t8

t9

TXCLK Frequency

0.2

40

4

50

60

—

10

50

60

—

10

MHz

%

TXCLK Duty Cycle (% of t1)

TXDATA[15:0], TXPARITY Setup Time to TXCLK

TXDATA[15:0], TXPARITY Hold Time to TXCLK

TXADDR[4:0], Setup Time to TXCLK

TXADDR[4:0], Hold Time to TXCLK

TXSOC, TXEN Setup Time to TXCLK

TXSOC, TXEN Hold Time to TXCLK

TXCLK to TXCLAV High-Z

ns

MHz

%

1.5

4

1.5

4

1.5

2

t10

t12

t13

t14

t15

t16

t17

t18

t19

t20

t21

t22

t23

TXCLK to TXCLAV Low-Z (min) and Valid (max)

RXCLK Frequency

2

0.2

40

4

RXCLK Duty Cycle (% of t12)

RXEN Setup Time to RXCLK

ns

RXCLK Hold Time to RXCLK

1.5

4

RXADDR[4:0] Setup Time to RXCLK

RXADDR[4:0] Hold Time to RXCLK

RXCLK to RXCLAV High-Z

1.5

2

RXCLK to RXCLAV Low-Z (min) and Valid (max)

RXCLK to RXSOC High-Z

2

RXCLK to RXSOC Low-Z (min) and Valid (max)

RXCLK to RXDATA, RXPARITY High-Z

2

RXCLK to RXDATA, RXPARITY Low-Z (min) and Valid (max)

2

41 of 49

December 6, 2001

IDT77V1264L200

.*

.ꢐ

.)

.(

!ꢁꢂꢃꢄ

!ꢁꢖ"!"4(ꢍ5&6C

!ꢁꢗ"ꢀꢜ!,

%ꢇ.ꢉ. (

.<

%ꢇ.ꢉ. )

.ꢍ

!ꢁ"ꢖꢖꢀ4ꢐ5&6

.:

.=

.(&

.>

.(&

!ꢁꢘ%ꢂ

TXEN

+ꢔꢕG-ꢛ

!ꢁꢂꢃ"8

*ꢍ&ꢍ ꢓꢋ9 *:

Figure 37 UTOPIA Level 2 Transmit

.()

.(*

ꢀꢁꢂꢃꢄ

.(ꢐ

.(<

.(ꢍ

.(:

RXEN

ꢀꢁ"ꢖꢖꢀ4ꢐ5&6

.(=

.(>

+ꢔꢕG-ꢛ

ꢀꢁꢂꢃ"8

ꢀꢁꢘ%ꢂ

.)(

.)*

.)&

+ꢔꢕG-ꢛ

.)*

.))

+ꢔꢕG-ꢛ

ꢀꢁꢖ"!"4(ꢍ5&6C

ꢀꢁꢗ"ꢀꢜ!,

*ꢍ&ꢍ ꢓꢋ9 *=

.

Figure 38 UTOPIA Level 2 Receive

42 of 49

December 6, 2001

IDT77V1264L200

UTOPIA Level 1 Bus Timing Parameters

Symbol

Parameter

Min.

Max.

50

Unit

t31

TXCLK Frequency

0.2

40

4

MHz

%

t32

t33

t34

t35

t36

t37

t39

t40

t41

t42

t43

t44

t45

t46

t47

TXCLK Duty Cycle (% of t31)

60

—

10

50

60

—

10

TXDATA[7:0], TXPARITY Setup Time to TXCLK

TXDATA[7:0], TXPARITY Hold Time to TXCLK

TXSOC, TXEN[3:0] Setup Time to TXCLK

TXSOC, TXEN[3:0] Hold Time to TXCLK

TXCLK to TXCLAV[3:0] Invalid (min) and Valid (max)

RXCLK Frequency

ns

1.5

4

ns

1.5

2

ns

MHz

%

0.2

40

4

RXCLK Duty Cycle (% of t39)

RXEN[3:0] Setup Time to RXCLK

ns

RXEN[3:0] Hold Time to RXCLK

1.5

2

RXCLK to RXCLAV[3:0] Invalid (min) and Valid (max)

RXCLK to RXSOC High-Z

ns

2

RXCLK to RXSOC Low-Z (min) and Valid (max)

RXCLK to RXDATA, RXPARITY High-Z

RXCLK to RXDATA, RXPARITY Low-Z (min) and Valid (max)

2

ns

2

.*(

.*)

.**

.*ꢐ

!ꢁꢂꢃꢄ

!ꢁꢖ"!"4:5&6C

!ꢁꢗ"ꢀꢜ!,

%ꢇ.ꢉ. (

.*<

%ꢇ.ꢉ. )

.*ꢍ

.*:

!ꢁꢘ%ꢂ

TXEN[3:0]

!ꢁꢂꢃ"84*5&6

*ꢍ&ꢍ ꢓꢋ9 *>

Figure 39 UTOPIA Level 1 Transmit

.*>

.ꢐ&

ꢀꢁꢂꢃꢄ

.ꢐ(

.ꢐ)

RXEN[3:0]

.ꢐ*

ꢀꢁꢂꢃ"84*5&6

ꢀꢁꢘ%ꢂ

.ꢐꢍ

.ꢐ:

.ꢐꢐ

.ꢐ<

+ꢔꢕG-ꢛ

.ꢐ:

ꢀꢁꢖ"!"4:5&6C

ꢀꢁꢗ"ꢀꢜ!,

*ꢍ&ꢍ ꢓꢋ9 ꢐ&

Figure 40 UTOPIA Level 1 Receive

43 of 49

December 6, 2001

IDT77V1264L200

DPI Bus Timing Parameters

Symbol

Parameter

Min.

Max.

50

Unit

t51

t52

t53

t54

t55

t56

t57

t61

t62

t63

t64

t65

DPICLK Frequency

0.2

40

2

MHz

%

DPICLK Duty Cycle (% of t51)

60

14

—

12

DPICLK to Pn_TCLK Propagation Delay

Pn_TFRM Setup Time to Pn_TCLK

Pn_TFRM Hold Time to Pn_TCLK

Pn_TD[3:0] Setup Time to Pn_TCLK

Pn_TD[3:0] Hold Time to Pn_TCLK

Pn_RCLK Period

ns

11

1

11

1

25

10

2

Pn_RCLK High Time

Pn_RCLK Low Time

Pn_RCLK to Pn_TFRM Invalid (min) and Valid (max)

Pn_RCLK to Pn_RD Invalid (min) and Valid (max)

2

.ꢍ(

.ꢍ)

ꢖꢗꢜꢂꢃꢄ

ꢗꢒB!ꢂꢃꢄ

ꢗꢒB!$ꢀ#

ꢗꢒB!ꢖ4*5&6

.ꢍ*

.ꢍꢐ

.ꢍꢍ

.ꢍ<

.ꢍ:

*ꢍ&ꢍ ꢓꢋ9 ꢐ(

.

Figure 41 DPI Transmit

.<(

.<)

.<*

ꢗꢒBꢀꢂꢃꢄ

ꢗꢒBꢀ$ꢀ#

ꢗꢒBꢀꢖ4*5&6

.<ꢐ

.<ꢍ

*ꢍ&ꢍ ꢓꢋ9 ꢐ)

Figure 42 DPI Receive

44 of 49

December 6, 2001

IDT77V1264L200

Utility Bus Read Cycle

Name Min. Max. Unit

Description

Tas

10

0

—

10

18

—

MHz

%

Address setup to ALE

Chip select to read enable

Address hold to ALE

Tcsrd

Tah

5

ns

Tapw

Ttria

Trdpw

Tdh

10

0

ALE min pulse width

Address tri-state to RD assert

Min. RD pulse width

20

0

Data Valid hold time

Tch

0

RD deassert to CS deassert

RD deassert to data tri-state

Read Data access

Ttrid

Trd

—

5

Tar

ALE low to start of read

Start of read to Data low-Z

Trdd

0

Utility Bus Write Cycle

Name Min. Max. Unit

Description

Tapw

Tas

10

5

—

ns

ALE min pulse width

Address set up to ALE

Address hold time to ALE

CS Assert to WR

Tah

Tcswr

Twrpw

Tdws

Tdwh

Tch

0

20

10

0

Min. WR pulse width

Write Data set up

Write Data hold time

WR deassert to CS deassert

ALE low to end of write

Taw

20

!ꢙG

!ꢙ

"ꢖ4:5&6

0ꢔꢒ3A.2

"ꢓꢓꢋꢉ

!ꢙ39

"ꢃꢑ

!ꢇG

!ꢇ ꢋꢓ

CS

!ꢙꢋ

!ꢋꢓ39

!.ꢋꢔꢓ

RD

!ꢓG

!ꢋꢓ

!ꢋꢓꢓ

"ꢖ4:5&6

0ꢆA.3A.2

ꢖꢙ.ꢙ

*ꢍ&ꢍ ꢓꢋ9 ꢐ*

Figure 43 Utility Bus Read Cycle

45 of 49

December 6, 2001

IDT77V1264L200

!ꢙ

!ꢙG

!ꢓ9

!ꢓ9G

"ꢖ4:5&6

ꢖꢙ.ꢙ 0ꢔꢒ3A.2

"ꢓꢓꢋꢉ

!ꢙ39

"ꢃꢑ

!ꢇG

!ꢙ9

CS

!ꢇ 9ꢋ

!9ꢋ39

WR

*ꢍ&ꢍ ꢓꢋ9 ꢐꢐ

Figure 44 Utility Bus Write Cycle

OSC, RXREF, TXREF and Reset Timing

Symbol

Tcyc

Parameter

Min.

Typ.

Max.

33

Unit

OSC cycle period

30

15

31.25

ns

15.625

—

16.5

60

1

Tch

OSC high tim

OSC low time

40

—

1

%

Tcl

—

Tcc

OSC cycle to cycle period variation

OSC to RXREF Propagation Delay

TXREF High Time

—

%

Trrpd¹

Ttrh

Ttrl

—

30

—

ns

—

35

—

TXREF Low Time

—

Trspw

Minimum RST Pulse Width

two OSC cycles

—

^1.The width of the RXREF pulse is programmable in the LED Driver and HEC Status/Control Registers.

!ꢇG

!ꢇꢅ

!ꢇꢌꢇ

%ꢘꢂ

!ꢋꢋ3ꢓ

RXREF

!.ꢋꢅ

!.ꢋG

TXREF

!ꢋ 39

RST

.

*ꢍ&ꢍ ꢓꢋ9 ꢐꢍ

Figure 45 OSC, RXREF, TXREF and Reset Timing

46 of 49

December 6, 2001

IDT77V1264L200

AC Test Conditions

Input Pulse Levels

GND to 3.0V

3ns

Input Rise/Fall Times

Input Timing Reference Levels 1.5V

Output Reference Levels

Output Load

1.5V

See Figure 46

3.3V

1.2KΩ

D.U.T.

30pF*

900Ω

* Includes jig and scope capacitances.

Figure 46 Output Load

A note about Figures 47 and 48: The ATM Forum and ITU-T standards for 25 Mbps ATM define "Network" and "User" interfaces. They are identical

except that transmit and receive are switched between the two. A Network device can be connected directly to a User device with a straight-through

cable. User-to-User or Network-to-Network connections require a cable with 1-to-7 and 2-to-8 crossovers.

ꢚꢆ.ꢉ *

(&ꢍ

(&<

(((

(()

!ꢁ*7 !ꢁ*-

ꢚꢆ.ꢉ (

ꢚꢆ.ꢉ )

";ꢚꢖ

ꢀ'

(

ꢀ'

)

((ꢐ ꢀꢁ*-

((ꢍ ꢀꢁ*7

$ꢔꢅ.ꢉꢋ

=

:

<

ꢍ ꢐ * ) (

ꢆꢖꢍꢎ

ꢗꢘꢒꢒꢓꢔꢂꢘꢙ

ꢏꢐꢑꢒꢓꢂꢁꢔꢕ

IDT77V1264L200

ꢚꢛꢜ

:

> (& (( () (* (ꢐ (ꢍ (<

";ꢚꢖ

!'

=

$ꢔꢅ.ꢉꢋ

ꢃꢃꢝꢊꢞꢎꢍ

ꢆꢖꢍꢎ

ꢏꢐꢑꢒꢓꢂꢁꢔꢕ

ꢚꢆ.ꢉ ꢍ

(ꢐ(

(ꢐ)

*ꢍ&ꢍ ꢓꢋ9 ꢐ:

.

Figure 47 PC Board Layout for ATM Network

Note: 1.No power or ground plane inside this area.

2.Analog power plane inside this area.

3.Digital power plane inside this area.

4.A single ground plane should extend over the area covered by the analog and digital power planes, without breaks.

5.All analog signal traces should avoid 90° corners.

47 of 49

December 6, 2001

IDT77V1264L200

(&ꢍ

(&<

ꢚꢆ.ꢉ *

(((

(()

!ꢁ*7 !ꢁ*-

ꢚꢆ.ꢉ (

";ꢚꢖ

ꢚꢆ.ꢉ )

!'

(

)

$ꢔꢅ.ꢉꢋ

!'

=

:

<

ꢍ ꢐ * ) (

ꢆꢖꢍꢎ

ꢗꢘꢒꢒꢓꢔꢂꢘꢙ

ꢏꢐꢑꢒꢓꢂꢁꢔꢕ

IDT77V1264L200

ꢚꢛꢜ

:

=

((ꢐ ꢀꢁ*-

((ꢍ ꢀꢁ*7

> (& (( () (* (ꢐ (ꢍ (<

";ꢚꢖ

ꢀ'

$ꢔꢅ.ꢉꢋ

ꢃꢃꢝꢊꢞꢎꢍ

ꢆꢖꢍꢎ

ꢏꢐꢑꢒꢓꢂꢁꢔꢕ

ꢚꢆ.ꢉ ꢍ

(ꢐ(

(ꢐ)

.

*ꢍ&ꢍ ꢓꢋ9 ꢐ=

Figure 48 PC Board Layout for ATM User

Note: 1.No power or ground plane inside this area.

2.Analog power plane inside this area.

3.Digital power plane inside this area.

4.A single ground plane should extend over the area covered by the analog and digital power planes, without breaks.

5.All analog signal traces should avoid 90° corners.

Package Dimensions

(ꢐꢐ

(&>

")

(

"(

(&=

.

ꢉ

(ꢐꢐ-ꢗꢔꢒ

ꢗ?$ꢗ

4.3514 '

^5.ꢑ^{4035 '}

ꢑ(

:*

*<

2.4792 '

"

*:

:)

⁴ꢖ^.43(^{19 '}

5.5125 '

ꢖ

ꢃ

ꢞ

ꢘ,#ꢎ%ꢃ

#ꢜꢚD

ꢚ%#D

#"ꢁD

"

"(

")

ꢖ

*D:&

&D**

*D*:

*(D)&

)=D&&

*(D)&

)=D&&

&D==

&D<ꢍ

-

ꢐD&:

&D)ꢍ

-

*D)&

*D<&

-

ꢖ(

ꢑ

-

ꢑ(

ꢃ

&D:*

-

(D&*

-

ꢉ

ꢞ

&D))

&D*=

ꢖꢔꢝꢉꢒ ꢔꢆꢒ ꢙꢋꢉ ꢔꢒ ꢝꢔꢅꢅꢔꢝꢉ.ꢉꢋ

*ꢍ&ꢍ ꢓꢋ9 ꢐ>

PSC-4053 is a more comprehensive package outline drawing which is available from the packaging section of the IDT web site.

48 of 49

December 6, 2001

IDT77V1264L200

Ordering Information

ꢜꢖ!

ꢚꢚꢚꢚꢚ

"

ꢚꢚꢚ

"

ꢗꢋꢆꢇꢉ ꢏ

ꢖꢉꢊꢔꢇꢉ !ꢌ3ꢉ

ꢘ3ꢉꢉꢓ

ꢗꢙꢇꢈꢙꢕꢉ

ꢗꢆ9ꢉꢋ

!ꢉꢝ3D ꢀꢙꢒꢕꢉ

ꢎꢅꢙꢒꢈ

ꢜ

ꢂꢆꢝꢝꢉꢋꢇꢔꢙꢅ 0&ꢟꢂ .ꢆ 7:&ꢟꢂ2

ꢜꢒꢓA .ꢋꢔꢙꢅ 0-ꢐ&ꢟꢂ .ꢆ 7=ꢍꢟꢂ2

ꢗ;

(ꢐꢐ-ꢗꢔꢒ ꢗ?$ꢗ 0ꢗ1-(ꢐꢐ2

)&&

)ꢍD< - )&ꢐD= #ꢞꢏ

ꢃ

77V1264L200

?Aꢙꢓ )ꢍ#ꢞꢏ "!# ꢗ+,

!ꢋꢙꢒ ꢝꢔ ꢔꢆꢒ ꢂꢆꢒꢊꢉꢋꢕꢉꢒꢇꢉ 0!ꢂ2

ꢙꢒꢓ ꢗ#ꢖ ꢘAꢞꢅꢙꢌꢉꢋ

::8()ꢍꢐ

*ꢍ&ꢍ ꢓꢋ9 ꢍ& )&&

.

Revision History

September 20, 2001: Initial publication.

December 6, 2001: Added DPI information.

CORPORATE HEADQUARTERS

2975 Stender Way

for SALES:

for Tech Support:

800-345-7015 or 408-727-6116

fax: 408-330-1748

email: phyhelp@idt.com

phone: 408-330-1752

Santa Clara, CA 95054

www.idt.com

49 of 49

December 6, 2001


型号：	IDT77V1264L200PG
厂家：	ETC
描述：	Telecommunication IC 电信IC\n 电信
文件：	总49页 (文件大小：822K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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