IP1001-DS-R05_技术文档

IP1001 LF

Data Sheet

Integrated 10/100/1000 Gigabit Ethernet Transceiver

Features

General Description

ꢀ

IEEE 802.3 compliant 1000BASE-T,

100BASE-TX, and 10BASE-T

Support auto-negotiation

Support timing programmable MII/ GMII/

RGMII (delay clock, and driving current etc.)

Support 3 power saving modes

Support software based Smart Cable Analyzer

(SCA)

Support auto MDI/MDIX (auto negotiation or

force mode)

Support auto polarity correction

Supports programmable LED modes and LED

driving current

IP1001 is an integrated physical layer device for

1000BASE-T, 100BASE-TX, and 10BASE-T

applications. IP1001 supports MII, GMII and

RGMII for different types of 10/100/1000Mb Media

Access Controller (MAC). It supports Auto

MDI/MDIX function to simplify the network

installation and reduce the system maintenance

cost. IP1001 supports speed down shift feature for

a poor link quality to guarantee data transmission.

Cable analysis function “SCA” is supported by

programming MII registers of IP1001 through

MDC/MDIO.

ꢀ

Supports speed down shift feature

Built in synchronization FIFO to support jumbo

frame size up to 10KB in giga mode (4KB in

10M/100M mode)

IP1001 supports 2 types of power saving modes;

i.e., power down mode defined in IEEE802.3, and

APS (auto power saving).

ꢀ

Supports 2.1v and 1.2v built-in regulator

control

ꢀ

Provide a 125MHz free running clock

Operating voltage 3.3v/ (2.5v option for

RGMII)/ 1.8v/ 1.2v

ꢀ

64-pin QFN lead-free package

Supports Lead Free package (Please refer to

the Order Information)

MAC Device

Physical Layer Device

Network Medium

10BASE-T

100BASE-TX

1000BASE-T

NIC/

RJ45

TP-MDI

Magnetic

RGMII/ GMII/ MII

IP1001

NIC/

Switch

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IP1001-DS-R06

IP1001 LF

Data Sheet

Table of Contents

Features ................................................................................................................................................................1

General Description ..............................................................................................................................................1

Table of Contents ..................................................................................................................................................2

Revision History ....................................................................................................................................................3

1

2

3

Pin diagram ...................................................................................................................................................4

Pin description...............................................................................................................................................5

Functional Description.................................................................................................................................16

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Medium Dependent Interface (MDI) for Twisted Pair Cable................................................ 16

MAC Interface (RGMII/ GMII/ MII) ....................................................................................... 17

Serial Management Interface............................................................................................... 20

LED ...................................................................................................................................... 20

Auto MDI/MDIX Crossover................................................................................................... 22

Polarity Correction ............................................................................................................... 22

Auto-Negotiation .................................................................................................................. 23

Smart speed......................................................................................................................... 24

Power supply........................................................................................................................ 24

3.10 Digital Internal Function ....................................................................................................... 25

3.11 IEEE802.3 1000BASE_T Test mode ................................................................................... 25

Register Descriptions..................................................................................................................................26

4

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

Control Register (Reg0)....................................................................................................... 27

Status Register (Reg1)......................................................................................................... 28

PHY Identifier Register (Reg2) ............................................................................................ 29

PHY Identifier Register (Reg3) ............................................................................................ 29

Advertisement Register (Reg4)............................................................................................ 30

Link Partner’s Ability Register (Base Page) (Reg5)............................................................. 31

Auto-Negotiation Expansion Register (Reg6)...................................................................... 33

Auto-Negotiation Next Page Transmit Register (Reg7)....................................................... 34

Auto-Negotiation Link Partner Next Page Register (Reg8) ................................................. 34

4.10 1000BASE-T Control Register (Reg9)................................................................................. 35

4.11 1000BASE-T Status Register (Reg10)................................................................................. 36

4.12 Extended Status Register (Reg15) ...................................................................................... 37

4.13 PHY Specific Control & Status Register (Reg16)................................................................. 38

4.14 PHY Link Status Register (Reg17)....................................................................................... 40

4.15 PHY Specific Control Register2 (Reg20)............................................................................. 41

Electrical Characteristics.............................................................................................................................42

5

5.1

5.2

5.3

5.4

Absolute Maximum Rating................................................................................................... 42

DC. Characteristic................................................................................................................ 42

AC Timing............................................................................................................................. 43

Thermal Data ....................................................................................................................... 47

6

7

Order Information ........................................................................................................................................47

Package Detail ............................................................................................................................................48

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IP1001 LF

Data Sheet

Revision History

Revision #

Change Description

Initial release.

IP1001-DS-R01

IP1001-DS-R02

Assign pin number to power pins. Modify CAP pin description. Modify package

dimension.

IP1001-DS-R03

IP1001-DS-R04

Modify features description. Modify the pin desecration for X1. Change the part

number to “IP1001 LF”. Modify the LED pins description. Modify the RGMII/GMII

driving current. Modify the operating temperature range. Modify RGMII/GMII timing.

Modify LED mode description of pin 55. Modify DC characteristics. Add thermal

parameters.

IP1001-DS-R05

IP1001-DS-R06

Correct an editing error found on Page 4.

Modify Maximum voltage of AVDD to 2.2V on Page 42 DC. Characteristic.

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IP1001 LF

Data Sheet

1

Pin diagram

RXD5/ TXPHASE_SEL

RXD6/ PHY_ADDR[4]

RXD7/ PHY_ADDR[3]

VDDO

CTRL12D

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

AVDD

MDI3M

MDI3P

AVDD

MDI2M

MDI2P

CAP

RX_ER/ PHY_ADDR[2]

DVDD

TX_CLK/ LED_MODE0

VDDO

IP1001

GTX_CLK/ TXC

TX_EN/ TX_CTL

TXD0

AVDDH

(64-QFN)

AVDD

MDI1M

MDI1P

AVDD

MDI0M

MDI0P

R_SET

TXD1

TXD2

TXD3

DVDD

VDDO

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Data Sheet

2

Pin description

Abbreviation

Description

PWR

I

Power and Ground Pin

Schmitt trigger input

LI

The input is latched at the end of reset and used as a default value

O

Output

I/O

Schmitt trigger input/ Output

Open drain output

OD

IPH

IPL

IPECL

OPECL

Schmitt trigger input with 60 kohm internal pull high

Schmitt trigger input with 60 kohm internal pull low

PECL input

PECL output

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Data Sheet

Pin description (continued)

Pin no.

Label

Type

Description

Configuration

50,51,53,7,8 PHY_ADDR[4:0] LI/O,

IPH

PHY Address Configuration

These pins are latched upon power-on reset to define the

PHY address of IP1001.

PHY_ADDR[1:0] are internally pulled high.

PHY_ADDR[4:0] share the same pins with RXD6, RXD7,

RX_ER, CRS and COL.

36

48

RGMII_N/GMII IPL

RXPHASE_SEL LI/O

GMII (MII)/ RGMII MAC Interface Mode Selection

This pin is latched upon power-on reset to define the

RGMII/GMII interface mode.

0: RGMII mode (default)

1: GMII/MII mode

RX_CLK Phase Selection

This pin is latched upon power-on reset, and acts as the initial

value of register16 [0] to adjust timing of RX_CLK.

0: No output delay is added on RX_CLK

1: An output delay is added on RX_CLK (with respect to RXD,

about 2ns delay in 1000BASE-T, and about 4ns delay in

100BASE-TX and 10BASE-T).

RXPHASE_SEL shares the same pin with RXD4.

49

TXPHASE_SEL LI/O

GTX_CLK/TXC Phase Selection

This pin is latched upon power-on reset, and acts as the initial

value of register16 [1] to adjust timing of GTX_CLK/TXC.

0: No input delay is added on GTX_CLK/TXC

1: An input delay is added on GTX_CLK/TXC (with respect to

TXD, about 2ns delay in 1000BASE-T, and about 4ns

delay in 100BASE-TX and 10BASE-T).

TXPHASE_SEL shares the same pin with RXD5.

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Data Sheet

Pin description (continued)

Pin no.

Label

Type

I

Description

MAC Interface

GMII

RGMII

MII

--

57

GTX_CLK TXC

GMII/RGMII Transmit Clock

I/F

MDI Description

speed

Gigabit 125Mhz input.

GMII

IP1001 utilizes this clock to

Mode

sample TXD[7:0], TX_ER and

TX_EN at the rising edge.

10/100M Not used.

bps

Gigabit 125Mhz input.

RGMII

Mode

IP1001 utilizes this clock to

sample TXD[3:0] and

TX_CTL at both the rising

edge and falling edge of

GTX_CLK.

100Mbps 25Mhz input.

IP1001 utilizes this clock to

sample TXD[3:0] and

TX_CTL at both the rising

edge and falling edge.

10Mbps 2.5Mhz input.

IP1001 utilizes this clock to

sample TXD[3:0] and

TX_CTL at both the rising

edge and falling edge.

55

--

TX_CLK

O

MII Transmit Clock

I/F

MDI Description

speed

Gigabit Not used.

GMII

100Mbps 25Mhz output.

Mode

IP1001 uses the clock to

sample TX_EN, TX_ER, and

TXD[3:0].

10Mbps 2.5Mhz output.

IP1001 uses the clock to

sample TX_EN, TX_ER, and

TXD[3:0].

Gigabit Not used.

RGMII

Mode

This pin should be left open

for normal operation.

100Mbps

10Mbps

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Data Sheet

Pin no.

58

Label

Type

I

Description

MAC Interface

GMII

RGMII

MII

TX_EN

TX_CTL TX_EN

GMII and MII Transmit Enable/ RGMII Transmit

Control

I/F

MDI Description

speed

Gigabit, Indicates the valid data is

GMII 100Mbps, present on the data bus of

Mode 10Mbps TXD. Synchronous to the

rising edge of GTX_CLK

(Gigabit) or TXC_CLK

(10/100M).

Gigabit, The TX_CTL indicates a

RGMII 100Mbps, signal like TX_EN at the

Mode 10Mbps rising edge of TXC. A signal

like TX_ER is derived by the

logical operation of latched

“TX_EN” and the value at the

falling edge of TXC.

5,4,2,1

TXD[7:4] --

--

I

GMII Transmit Data (high nibble)

Please see the pin description of pin 57.

62,61,60,59 TXD[3:0] TXD[3:0] TXD[3:0] I

TX_ER -- TX_ER

GMII/RGMII/MII Transmit Data

Please see the pin description of pin 57.

6

I

GMII and MII Transmit Error

I/F

MDI Description

speed

Gigabit A “high” state present on this

pin indicates transmit data

error or carrier extension. It is

synchronous to GTX_CLK

100Mbps A “high” state present on this

, 10Mbps pin indicates transmit data

error. It is synchronous to

TX_CLK

GMII

Mode

Gigabit, Not used.

RGMII 100Mbps,

Mode 10Mbps

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Data Sheet

Pin no.

39

Label

Type

Description

MAC Interface

GMII

RGMII

MII

RX_CLK O

RX_CLK RXC

GMII/ RGMII Receive Clock.

I/F

MDI Description

speed

Gigabit 125Mhz output.

GMII

IP1001 sends out RXD[7:0],

Mode

RXDV and RX_ER at the

rising edge of RX_CLK.

100Mbps 25Mhz output.

IP1001 sends out RXD[3:0],

RXDV and RX_ER at the

rising edge of RX_CLK.

10Mbps 2.5Mhz output.

IP1001 sends out RXD[3:0],

RXDV and RX_ER at the

rising edge of RX_CLK.

Gigabit 125Mhz output.

RGMII

Mode

IP1001 sends out RXD[3:0]

and RX_CTL at both the

rising edge and falling edge

of RXC.

100Mbps 25Mhz output.

IP1001 sends out RXD[3:0]

and RX_CTL at both the

rising edge and falling edge

of RXC.

10Mbps 2.5Mhz output.

IP1001 sends out RXD[3:0]

and RX_CTL at both the

rising edge and falling edge

of RXC.

40

RX_DV RX_CTL RX_DV

O

GMII and MII Receive Enable/ RGMII Receive

Control

I/F

MDI Description

speed

Gigabit RX_DV indicates the valid

GMII 100Mbps data is present on the data

Mode 10Mbps bus of RXD. Synchronous to

the rising edge of RX_CLK.

Gigabit RX_CTL indicates a signal

RGMII

Mode

like RX_DV at the rising edge

of TXC. A signal like RX_ER

is derived by the logical

operation of latched RX_DV

and the value at the falling

edge of RX_CLK

100Mbps

10Mbps

51,50,49,48 RXD[7:4] --

--

O

GMII Receive Data (high nibble)

Please see the pin description of pin 39.

RXD[7:4] share the same pins with

PHY_ADDR[3:4], TXPHASE_SEL, and

RXPHASE_SEL.

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Data Sheet

Pin no.

Label

Type

Description

MAC Interface

GMII

RGMII

MII

45,44,42,41 RXD[3:0] RXD[3:0] RXD[3:0] O

GMII/RGMII/MII Receive Data

Please see the pin description of pin 39.

53

RX_ER --

RX_ER

O

GMII and MII Receive Error

RX_ER shares the same pin with PHY_ADDR2.

I/F

MDI Description

speed

Gigabit A “high” state present on this

pin indicates received data

error or carrier extension. It is

synchronous to RX_CLK

100Mbps A “high” state present on this

, 10Mbps pin indicates received data

error. It is synchronous to

RX_CLK

GMII

Mode

Gigabit, Not used.

RGMII 100Mbps,

Mode 10Mbps

7

8

CRS

COL

--

CRS

COL

IPH/O GMII/MII Carrier Sense

It asserts during either the transmission or the

reception.

CRS shares the same pin with PHY_ADDR1.

IPH/O GMII/MII Collision

If IP1001 operates in half mode, it asserts when both

transmission and reception are running. If IP1001

works in full duplex mode, COL is always idle (logic

low).

COL shares the same pin with PHY_ADDR0.

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Data Sheet

Pin description (continued)

Pin no.

LED Display

55

Label

Type

LI/O

Description

LED_MODE0

LED Mode Selection (MODE0~MODE3).

LED_MODE[1:0] can provide 4 LED display modes, Mode0~

Mode3.

LED_MODE1 is set by register16[15]. LED_MODE0 is

defined by pin or by register16[14]. The pin state of

LED_MODE0 is latched upon reset and set to register 16[14].

After power up, the designer can configure LED_MODE[1:0]

register during the operation.

Since LED_MODE1 is set to “0” upon reset, the designer can

set pin 55 to select “00” or “01” display mode if the register

16[15:14] is unchanged.

15,14,13

LED2, LED1,

LED0

IPH/O, LED output pins 0,1,2

LI/O

Mode0

00

Mode1

01

Mode2

Mode3

11

LED_Mode1,

LED_Mode0

10

LED0

LED1

LED2

10/100M Link/Act

0: link off

1: 10/100M link on

Flash: TX or RX

Bi-color mode

{LED0, LED1}=

1G Link/Act

0: link off

1: Giga link on

Flash: TX or RX

Bi-triple-color mode

{LED0, LED1}=

10= 1G Link;

01=10/100M Link;

00= link off

10= 1G Link;

01= 100M Link

00= 10M Link;

11= link off

100M Link/Act

0: link off

1: 100M link on

Flash: TX or RX

100M Link/Act

0: link off

1: 100M link on

Flash: TX or RX

11= link off

1G Link/Act

0: link off

1: Giga link on

Flash: TX or RX

Act

10M Link/Act

0: link off

1: 10M link on

Flash: TX or RX

Link/ Act

0: link off

1: 10/100M/giga link

on

0: link off or idle

1: TX or RX

Flash: TX or RX

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Data Sheet

Pin description (continued)

Pin no.

Label

Type

I

Description

Serial Management Interface

11

MDC

Management Data Clock.

MDC is the management data clock reference. A continuous

clock is not expected. The maximum frequency supported is

12.5 MHz.

12

MDIO

I/O

Management Data Input Output.

MDIO transfers management data in and out of the device

synchronous to MDC. This pin should be connected to VDDO

through a 5.1-kΩ pull up resistor.

Pin no.

Label

Type

I/O

Description

Medium Interface

29,26,21,18, MDI[3:0]P,

30,27,22,19 MDI[3:0]M

Twisted- Pair Media Dependent Interface

In 1000BASE-T mode, all 4 pairs are both input and output at

the same time. In 100BASE-TX and 10BASE-T mode,

MDI[0]P/M are used for transmit pair under MDI configuration,

and is used for receive pair under MDIX configuration.

MDI[1]P/M are used for receive pair under MDI configuration,

and is used for transmit pair under MDIX configuration.

MDI[2]P/M and MDI[3]P/M are unused in 100BASE-TX and

10BASE-T mode.

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Data Sheet

Pin description (continued)

Pin no.

Label

Type

O

Description

Miscellaneous

16

CTRL21

Regulator Control.

The internal linear regulator uses this pin to control an

external PNP transistor to generate a 2.1v voltage source.

IP1001 uses the AVDDH as a reference voltage, which can be

3.3v or 2.5v as shown in the following figure. The 2.1v power

source is used for center tap of transformer and AVDD. The

built in regulator works only if AVDD pins are connected to the

collector of the external PNP as shown in the following figure.

If AVDD pins are connected to an external power source

instead of the collector of PNP, the function of CTRL21

doesn’t work.

AVDDH (3.3v/ 2.5v)

CTRL21

AVDD (2.1v)

This pin can be left open if it is not used.

Regulator Control.

32

CTRL12D

O

The internal linear regulator uses this pin to control an

external PNP transistor to generate a 1.2v voltage source.

IP1001 uses the VDDO as a reference voltage, which can be

3.3v or 2.5v as shown in the following figure. The 1.2v power

source is used for DVDD.

The built in regulator works only if DVDD pins are connected

to the collector of the external PNP as shown in the following

figure. If DVDD pins are connected an external power source

instead of the collector of PNP, the function of CTRL12D

doesn’t work.

VDDO (3.3v/ 2.5v)

CTRL12D

DVDD (1.2v)

This pin can be left open if it is not used.

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Data Sheet

Pin description (continued)

Pin no.

Label

Type

I

Description

Miscellaneous

33

X1

Reference Clock.

25 MHz crystal reference or oscillator input.

Connects to crystal to provide the 25MHz crystal input. If a

25MHz oscillator is used, connect X1 to the oscillator’s output.

The input voltage of this pin should not exceed 1.8V. A voltage

divider formed by 2 resistors is recommended if the output

voltage of oscillator is over 1.8V. Please refer to the Crystal

Specifications in detail.

34

35

X2

O

I

Reference Clock.

25 MHz crystal reference.

Hardware reset

Active low.

RESET#

IP1001 enters reset state when this pin is pulled low.

37

10

IPL

O

It is used for scan test only. It should be left open for normal

operation.

NC_TEST

CLK_OUT

125M clock output

It is used by external MAC device. This signal is always active

after reset.

25

17

CAP

Capacitor pin

It should be connected to GND through an external 10uF

capacitor. It is used to stabilize the internal analog power.

R_SET

I

Band gap Reference

Add an external 6.19kΩ±1% resistor between this pin and

GND. IP1001 utilizes this resistor to set the current source.

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IP1001 LF

Data Sheet

Pin description (continued)

Pin no.

Label

Type

Description

Power pins

3, 38, 46,

54, 63

DVDD

AVDD

1.2v digital power

20, 23,

28,31,

1.8v or 2.1v analog power

AVDD can be fed with external 1.8v or 2.1v power.

If there is no external 1.8v power source, AVDD can be

connected the 2.1v power source generated by CTRL21. If an

external 1.8v power is available, AVDD can be connected to

1.8v to reduce the power consumption.

If there is no external 2.5v power source, the center tap of

transformer can be connected the 2.1v power source

generated by CTRL21. If an external 2.5v power is available,

the center tap of transformer can be connected to it,

consuming the extra power consumption.

9, 43, 47,

52, 56, 64

VDDO

3.3v/ 2.5v digial I/O power

VDDO is connected to 3.3v if IP1001 works in MII or GMII

mode. VDDO is connected to 2.5v if IP1001 works at RGMII

mode.

24

AVDDH

3.3v/ 2.5v analog power

AVDDH can be fed with 3.3v or 2.5v, using the same power

source of VDDO. Although VDDO and AVDDH use the same

power source, user has to place a bead between VDDO and

AVDDH to prevent the noise of AVDDH noise.

--

GND

Exposed PAD (E-PAD) (Thermal PAD) is Analog and Digital

ground.

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Data Sheet

3

Functional Description

The IP1001 is an Ethernet transceiver for 1000BASE-T, 100BASE-TX, and 10BASE-T. It uses one pair of

UTP wires to transmit data and uses another pair to receive data when working in 100BASE-TX or 10BASE-T.

It uses four pairs of UTP wires to transmit and to receive data when working in 1000BASE-T.

It supports auto-negotiation, including next page exchanging, speed (1000M, 100M, 10M), duplex (full/ half)

mode and master/slave resolution. This device also supports RGMII/ GMII/ MII to interface a MAC device.

Registers in the IP1001 can be accessed via the SMI (MDC/MDIO). Three LEDs shows the various statuses

of the device. Pair skews in the cables are automatically adjusted. Wiring errors are automatically corrected

via pair swapping (automatic MDI/MDIX) and polarity correction.

3.1

Medium Dependent Interface (MDI) for Twisted Pair Cable

The interface between IP1001 and CAT5 cable consists of four signal pairs, channel A, B, C and D, that are

used for 1000BASE-T transmission/receiving. Each signal pair consists of two bi-directional pins that transmit

and receive data stream at the same time.

When the IP1001 operates in 100BASE-TX or 10BASE-T mode, only channel A and B are used, one for

transmission and the other for reception. IP1001 will handle the MDIX/MDI crossover issue of the twisted-pair

wire automatically. Please refer to section 3.5 Auto MDI/MDIX Crossover for detail.

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Data Sheet

3.2

MAC Interface (RGMII/ GMII/ MII)

IP1001 supports RGMII and GMII/ MII interfaces. User can select the one of the interfaces by configure pin 36

and IP1001 will latch the setting at the end of hardware reset. If pin 36 is connected to GND through a resistor

R44, RGMII is selected. If pin 36 is connected to VDDO through a resistor R24, GMII/ MII is selected.

GMII/MII interface

RGMII interface

VDDO

RGMII_N/GMII

R24 5.1K

R44 5.1K RGMII_N/GMII

If GMII mode is selected and IP1001 links in 1000BASE-T mode, GTX_CLK, TX_EN, TXD[7:0] and TX_ER

are input signals and should be driven by an external MAC device, TX_CLK is driven low. RX_CLK, CRS,

RX_DV, RXD[7:0], RX_ER and COL are output signals to an external MAC device.

In the 100BASE-TX (10BASE-T) modes, both TX_CLK and RX_CLK source 25 MHz (2.5 MHz) clock

respectively. TX_EN, TXD[3:0] and TX_ER are input signal and should be driven by an external MAC device.

RX_CLK, CRS, RX_DV, RXD[3:0], RX_ER and COL are output signals to an external MAC device. GTX_CLK

and TXD[7:4] signals are ignored and RXD[7:4] drives low.

If RGMII mode is selected, TXC, TX_CTL and TXD[3:0] are input signals and should be driven by an external

MAC device, TX_CLK is driven low. RXC, RX_CTL and RXD[3:0] are output signals to an external MAC

device. RXC provides a 125 Mhz, 25 Mhz or 2.5 Mhz reference clock depending on the link speed is 1000M,

100M or 10M.

A timing adjustment on MAC interface is implemented in IP1001 by adding delay to the clock pins and

changing driving capability on RX pins. User can add input delay to the GTX_CLK(TXC) by programming pin

49 TXPHASE_SEL or register 16.1 or add output delay to the RX_CLK(RXC) by programming pin 48

RXPHASE_SEL or register 16.0. The driving capability of RX signals can be configured by programming MII

register 16[8:5]

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Data Sheet

MII/GMII/RGMII selection and signal direction

RGMII is active if pin 36 RGMII_N/GMII is pulled low.

TD[3:0]

TXD[3:0]

TX_ER

TXCTL

TXC

TXEN/ TXCTL

GTX_CLK/ TXC

RXD[3:0]

RX_ER

IP1001

MAC

MDI[3:0]P/M

transformer

RXCTL

RXC

RXDV/ RXCTL

CRS

COL

RX_CLK/ RXC

TX_CLK

GMII is active if pin 15 RGMII_N/GMII is pulled high and IP1001is linked at giga mode.

TXD[7:0]

TXER

TXD[7:0]

TX_ER

TXEN

TXEN/ TXCTL

GTX_CLK/ TXC

GTX_CLK

RXD[7:0]

RXER

RXD[7:0]

IP1001

RX_ER

RXDV/ RXCTL

CRS

MDI[3:0]P/M

transformer

RXDV

CRS

COL

RX_CLK/ RXC

TX_CLK

RXCLK

MII is active if pin 15 RGMII_N/GMII is pulled high and IP1001 islinked at 100M, or 10M.

TXD[3:0]

TXER

TXD[3:0]

TX_ER

TXEN

TXEN/ TXCTL

GTX_CLK/ TXC

RXD[3:0]

RXER

RXDV

CRS

RXD[3:0]

IP1001

RX_ER

RXDV/ RXCTL

CRS

MDI[3:0]P/M

transformer

COL

RX_CLK/ RXC

TX_CLK

RXCLK

TXCLK

18/48

Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

Waveform of RGMII and GMII (MII)

R G M II

TXC

G M II's

TX_C TL

TXD [3:0]

TX_E N

TXER R

TXD [3:0]

TXD [7:4]

TXE R R = G M II's TX _E N (X O R ) G M II's TX_E R

R XC

G M II's

R X_C TL

R XD [3:0]

R X_D V

R XER R

R XD [3:0]

R XD [7:4]

R X E R R = G M II's R X _D V (X O R ) G M II's R X _ER

G M II (M II)

G TX_C LK

(TX_C LK )

TX_E N , TX_ER

(TX_E N , TX_E R )

TXD [7:0]

(TXD [3:0])

R X_C LK

(R X_C LK )

R X_D V , R X_ER

(R X_D V, R X_E R )

R XD [7:0]

(R XD [3:0])

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IP1001-DS-R06

IP1001 LF

Data Sheet

3.3

Serial Management Interface

The serial management interface consisting of two pins, MDC and MDIO, provides access to the MII registers

of IP1001. MDC is a clock input and runs at a maximum rate of 12.5 MHz. MDIO is a bi-directional data pin

that runs synchronously to MDC. The MDIO pin requires a 5.1-kΩ pull up resistor. To access MII register in

IP1001, MDC should be at least one more cycle than MDIO. That is, a complete command consists of 32 bits

MDIO data and at least 33 MDC clocks.

Frame

format

Read

Operation

Write

Operation

MDC

z

MDIO

1..1

0 0 0 0

0 0

0

0 0 1

0

0 1 1 0 0

0 1

1

0

0 1 0 0 0

0

0 1 1 0

op

code

A A A A A R R R R R

4 3 2 1 0 4 3 2 1 0

b b b b b b b b b b b b b b b b

1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0

idle

start

TA

write

PHY address =

01h

Reg address =

00h

5 4 3 2 1 0

Register data

MDC

z

MDIO

1..1

0 0 0 0

0 0

1

0

0 0 Z

0

0 0 1 0 0

0 1

0

0 1 0 0 0

0

0 1 1 0

op

code

A A A A A R R R R R

4 3 2 1 0 4 3 2 1 0

b b b b b b b b b b b b b b b b

1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0

idle

start

TA

read

PHY address =

01h

Reg address =

00h

5 4 3 2 1 0

Register data

3.4

LED

IP1001 provides 3 LED pins, LED0~2, and four LED display modes, mode0~3. User can select one of four

LED modes by configuring LED_MODE1 and LED_MODE0. LED_MODE1 and LED_MODE0 are defined in

register 16[15:14]. Pin 55 LED_MODE0 defines the default value of register 16[14].

The functionality of the LED pins is shown in the table below. The driving capability of LED pins can be

programmed by writing MII register 16[13].

LED mode setting

LED mode 1

LED mode 0

VDDO

R24 5.1K TX_CLK/LED_MODE0

R44 5.1K TX_CLK/LED_MODE0

20/48

Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

LED application circuit

Mode 0 & mode 2

LED

R2

220 ohm

LED 0,1,2

Mode 1

LED0

LED1

R51 220

1

2

LED

R2

LED 2

Bi-color

220 ohm

Bi-color LED

configuration

Mode 3

VDDO

R51

220

LED4

Bi-tripple color

LED

R2

LED 2

LED0

LED1

220 ohm

Bi-tripple color LED

configuration

Mode0

0,0

Mode1

0,1

Mode2

Mode3

LED_MODE1,

LED_MODE0

1,0

1,1

Pin 13 LED0

Pin 14 LED1

10/100M Link/Act Bi-color mode

1G Link/ Act

Bi-triple-color mode

{LED0, LED1}=

10= 1G Link;

01= 100M Link

00= 10M Link;

11= link off

{LED0, LED1}=

100M Link/Act

100M Link/ Act

10M Link/ Act

10= 1G Link;

01=10/100M Link;

00= link off

11= link off

Pin 15 LED2

1G Link/Act

Act

Link/ Act

Note:

Link: LED on

Act (activity): LED blinking (frequency is about 10Hz)

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IP1001-DS-R06

IP1001 LF

Data Sheet

3.5

Auto MDI/MDIX Crossover

The IP1001 implements auto-crossover function, that is, users don’t have to care using a crossover or

non-crossover cable. Its pin mapping in MDI and MDIX modes is shown in the following table. If IP1001

interoperates with a device that does not implement auto MDI/MDIX crossover, the IP1001 makes the

necessary adjustment prior to performing auto-negotiation. If the IP1001 interoperates with a device that

implements auto MDI/MDIX crossover, a random algorithm as described in IEEE 802.3 section 40.4.4

determines which device performs the crossover.

When the IP1001 interoperates with a 10BASE_T PHY or a PHY that implements auto-negotiation, IP1001

decides the MDI/MDIX by the presence of link pulses. However, when interoperating with a 100BASE_TX

PHY that does not implement auto-negotiation (i.e. link pulses are not present), IP1001 uses signal energy of

receiving MLT3 signals to determine whether or not to crossover.

The auto MDI/MDIX function is turned on automatically after hardware reset and users can disable it by

programming MII register 20.2. User can check if IP1001 is in MDI or MDIX type by reading MII register 17.11.

Auto MDI/MDIX function is not affected by disabling auto-negotiation function.

MDI

MDIX

1000BASE-T 100BASE-TX 10BASE-T

MDI[0]P/M

MDI[1]P/M

MDI[2]P/M

MDI[3]P/M

BI_DA+/-

BI_DB+/-

BI_DC+/-

BI_DD+/-

TX+/-

RX+/-

Unused

TX+/-

RX+/-

Unused

BI_DB+/-

BI_DA+/-

BI_DD+/-

BI_DC+/-

RX+/-

TX+/-

Unused

RX+/-

TX+/-

Unused

3.6

Polarity Correction

The IP1001 performs polarity correction without any manual setting. It corrects polarity errors on the receive

pairs in 1000BASE-T and 10BASE-T modes automatically.

In 1000BASE-T mode, polarity correction is based on the sequence of idle symbols. In 10BASE-T mode,

polarity correction is based on the detection the polarity of valid normal link pulse and idle pulse. In

100BASE-TX mode, the polarity does not matter.

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IP1001-DS-R06

IP1001 LF

Data Sheet

3.7

Auto-Negotiation

IP1001 will performs Auto-Negotiation automatically if one of the following conditions happened:

1) Power up reset, hardware reset, or software reset (by programming MII register 0.15).

2) Restart Auto-Negotiation (by programming MII register 0.9).

3) Transition from power down to power up (by programming MII register 0.11).

4) Link is down.

Once Auto-Negotiation is initiated, IP1001 sends out the appropriate base pages/ next pages to advertise its

capability and negotiate with the link partner to determine speed, duplex, and master/slave. Note that IP1001

handles the base page/ next page exchanges automatically without user intervention. To link at giga mode,

the link partner of IP1001 has to support Auto-Negotiation, too. Once IP1001 completes Auto-Negotiation it

updates the statuses in registers 1, 5, 6, 10 and 17. The advertised abilities can be changed by writing

registers 4 and 9. It is noted that a write access to register 4 or 9 has no effect once the IP1001 begins

transmitting Fast Link Pulses (FLPs). This guarantees that the transmitted FLPs are consistent. Register 7 is

treated in a similar way as registers 4 and 9 during additional next page exchanges.

If the link partner doesn’t support Auto-Negotiation, IP1001 determines the link speed using parallel detection

and the link result is either 10M half duplex or 100M half duplex. Please refer to IEEE 802.3 clause 28 and 40

for more detailed description of Auto-Negotiation.

Auto-Negotiation can be disabled by programming register 0.12. When Auto-Negotiation is disabled, the

speed and duplex of IP1001 can be changed by programming registers 0.13, 0.6 and 0.8, respectively.

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IP1001-DS-R06

IP1001 LF

Data Sheet

3.8

Smart speed

IP1001 supports smart speed function. If IP1001 can’t link at Gigabit speed due to cable quality, the link

speed is down shift to 100M automatically if smart speed option is turned on. If the function is turned off,

IP1001 will link down if it can’t link at giga mode due to cable quality. The function is default on and it can be

enabled/disabled by programming MII register 16.11.

3.9

Power supply

IP1001 has 4 sets of power pins, DVDD, AVDD, VDDO and AVDDH. VDDO is connected to 3.3v or 2.5v

depending on MAC interface is GMII or RGMII. AVDDH can use the same power source of VDDO, that is 3.3v

or 2.5v, but it needs a bead to prevent VDDO noise. AVDD can be connected to 1.8v or 2.1v. If there is no

external 1.8v power source, user can use the 2.1v power generated by the built in regulator (CTRL21). DVDD

is connected to 1.2v. The center tap of transformer can be connected to 2.1v or 2.5v. If there is no external

2.5v power source, user can use the 2.1v power generated by the built in regulator control(CTRL21). The

current limit of bead should be large enough to prevent the IR drop in power supply input.

2.5v or 2.1v (from regulator)

bead

C T

1.2v (from regulator)

D V D D

1.8v or

2.1v (from regulator)

AV D D

Transform er

IP 1001

bead

VD D O

3.3v (G M II) or

2.5v (R G M II)

AV D D H

C TR L12D C TR L21

PN P

1.2v

2.1v

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IP1001-DS-R06

IP1001 LF

Data Sheet

3.10 Digital Internal Function

The IP1001 integrates all necessary function blocks to achieve the communication ability over CAT5

unshielded twisted pair cables. These function blocks include analog blocks and digital blocks.

Analog function blocks includes analog to digital converter (ADC), digital to analog converter (DAC), active

hybrid, and high-speed 1.25GHz transmitter/receiver. Digital function blocks include digital adaptive

feed-forward equalizer (FFE), decision-feedback equalizer (DFE), echo canceller (EC), near-end-cross-talk

canceller, baseline wander canceller, and digital phase lock-loop (DPLL). Some other encoding/decoding

blocks are also necessary in the transmission/receiving data path.

3.11 IEEE802.3 1000BASE_T Test mode

IP1001 supports four test modes for 1000BASE_T defined in IEEE802.3 clause 40.6. User can force IP1001

to be in test mode to characterize its waveform, jitter, and distortion by programming MII register 9[15:13].

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Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

4

Register Descriptions

Abbreviation description

Abbreviation

SC

Description

Self-Clear

LH

Latched High

LL

Latched Low

RO

Read Only

R/W

Read and Write

Not Affected

NA

HW Reset

SW Reset

Reset by RESET# pin

Reset by MII register 0 bit 15

PHY registers

The IP1001 supports a full set of PHY registers, which can be accessed through the MDC/MDIO interface.

Register

Reg0

Description

Control Register

Reg1

Status Register

Reg2

PHY Identifier Register

Reg3

PHY Identifier Register

Reg4

Auto-Negotiation advertise register

Link Partner Ability Register

Auto-Negotiation Expansion Register

Auto-Negotiation Next Page Transmit Register

Auto-Negotiation Link Partner Next Page Register

1000BASE-T Control Register

1000BASE-T Status Register

Reserved. Do not access to these registers.

Extended Status Register

Reg5

Reg6

Reg7

Reg8

Reg9

Reg10

Reg11~14

Reg15

Reg16

Reg17

Reg18~19

Reg20

Reg21~31

PHY Specific Control Register1

PHY Link Status Register

Reserved. Do not access to these registers.

PHY Specific Control Register2

Reserved

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Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

4.1

Bit

Control Register (Reg0)

HW

Reset Reset

SW

Name

Description

Type

0.5:0

0.6

Reserved

RO

Always 0

Speed Selection

(MSB)

0.6

1

0.13

R/W

1

NA

1

0

1

0

Reserved

1000Mb/s

100Mb/s

10Mb/s

1

0

0.7

0.8

0.9

0.10

Collision Test

Duplex Mode

1: Enable COL signal test

0: Disable COL signal test

R/W

0

1

0

1: Full duplex

0: Half duplex

NA

SC

0

Restart Auto-NEG 1: Restart Auto-Negotiation Process

0: Normal operation

R/W

SC

Isolate

1: Isolate PHY from MII, GMII, or RGMII

electrically

R/W

0: normal operation

0.11

0.12

0.13

0.14

0.15

Power Down

1: Power down

0: Normal operation

R/W

0

1

0

Auto-Negotiation

Enable

1: Enable Auto-Negotiation Process

0: Disable Auto-Negotiation Process

NA

0

Speed Selection

(LSB)

Please refer to bit 0.6 for detail information

Loopback

1: Enable loop back mode

0: Disable loop back mode

Software Reset

1: PHY software reset

0: normal operation

R/W

SC

0 (SC)

27/48

Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

4.2

Bit

Status Register (Reg1)

HW

Reset Reset

SW

Name

Description

Type

RO

1.0

1.1

1.2

1.3

1.4

1.5

1.6

Extended

Capability

1: Support extended register capabilities

0: Support basic register set capabilities only

1

0

1

0

1

0

1

0

Jabber Detect

1: Jabber condition detected

RO

LH

0: No jabber condition detected

Link Status

1: Link is up

RO

LL

0: Link is down

Auto-Negotiation

Ability

1: PHY is able to perform Auto-Negotiation

0: PHY is not able to perform Auto-Negotiation

RO

Remote Fault

1: Remote fault condition detected

0: No remote fault condition detected

RO

LH

Auto-Negotiation

Complete

1: Auto-Negotiation process completed

0: Auto-Negotiation process not completed

RO

MF Preamble

Suppression

1: PHY accepts management frames with

preamble suppressed.

RO

Reserved 1

0: PHY does not accept management frames

with preamble suppressed.

1.7

1.8

Reserved

Ignore when read

RO

Reserved 0

Reserved 1

Extended Status

1: There is extended status information in

Register 15

0: No extended status information in Register

15

1.9

100BASE-T2 Half 1: PHY able to perform half duplex 100BASE-T2 RO

Reserved 0

Duplex

0: PHY not able to perform half duplex

100BASE-T2

1.10

1.11

100BASE-T2 Full

Duplex

1: PHY able to perform full duplex 100BASE-T2 RO

0: PHY not able to perform full duplex

100BASE-T2

10Mb/s Half Duplex 1: PHY able to operate at 10 Mb/s in half

duplex mode

RO

1

0: PHY not able to operate at 10 Mb/s in half

duplex mode

1.12

10 Mb/s Full

Duplex

1: PHY able to operate at 10Mb/s in full duplex RO

mode

0: PHY not able to operate at 10Mb/s in full

duplex mode

1.13

1.14

1.15

100BASE-X Half

Duplex

1: PHY able to perform half duplex 100BASE-X RO

0: PHY not able to perform half duplex 100BASE-X

1

100BASE-X Full

Duplex

1: PHY able to perform full duplex 100BASE-X RO

0: PHY not able to perform full duplex 100BASE-X

100BASE-T4

1: PHY able to perform 100BASE-T4

RO

Reserved 0

0: PHY not able to perform 100BASE-T4

28/48

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IP1001-DS-R06

IP1001 LF

Data Sheet

4.3

Bit

PHY Identifier Register (Reg2)

HW

Reset Reset

SW

Name

Description

Type

RO

2[15:0] Organizationally

Unique Identifier

Bit [3:18]

0000_0010_0100_0011

Note: ICplus’s OUI is 0x0090C3

Always 0x0243

4.4

Bit

PHY Identifier Register (Reg3)

HW

Reset Reset

SW

Name

Description

Type

3[3:0]

3[9:4]

Revision Number

0000

RO

Always 0000

Manufacturer’s

Model Number

011001

Always 011001

3[15:10] Organizationally

Unique Identifier

Bit [19:24]

000011

RO

Always 000011

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Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

4.5

Bit

Advertisement Register (Reg4)

HW

Reset Reset

SW

Name

Description

Type

RO

4[4:0]

Selector Filed

00001 00001

Only CSMA/CD <00001> is specified. No

other protocols are supported.

4.5

4.6

4.7

4.8

10BASE-T Half

Duplex

R/W

1

1 = 10Base-T full duplex is supported

0 = 10Base-T full duplex not supported

10BASE-T Full

Duplex

1 = 10Base-T half duplex is supported

0 = 10Base-T half duplex not supported

100BASE-TX Half

Duplex

1 = 100Base-TX half duplex is supported

0 = 100Base-TX half duplex not supported

100BASE-TX Full

Duplex

1 = 100Base-TX full duplex is supported

0 = 100Base-TX full duplex not supported

4.9

100BASE-T4

PAUSE

RO

Reserved 0

1 = 100Base-T4 is supported

0 = 100Base-T4 not supported

4.10

4.11

R/W

0

1 = flow control is supported

0 = flow control is not supported

Asymmetric Pause

1 = asymmetric flow control is supported

0 = asymmetric flow control is not supported

Ignore when read

4.12

4.13

Reserved

R/W

0

Remote Fault

1 = Advertise remote fault detection capability

0 = Not advertise remote fault detection

capability

4.14

4.15

Reserved

RO

Reserved 0

1

R/W

1 = Next pages are supported

0 = Next pages are not supported

30/48

Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

4.6

Bit

Link Partner’s Ability Register (Base Page) (Reg5)

HW

Reset Reset

SW

Name

Description

Type

5[4:0]

5.5

Selector Field

RO

0

10BASE-T Half

Duplex

1 = 10Base-T is supported by link partner

0 = 10Base-T not supported by link partner

5.6

10BASE-T Full

Duplex

RO

0

1 = 10Base-T full duplex is supported by link

partner

0 = 10Base-T full duplex not supported by link

partner

5.7

5.8

100BASE-TX Half

Duplex

RO

0

1 = 100Base-TX is supported by link partner

0 = 100Base-TX not supported by link partner

100BASE-TX Full

Duplex

1 = 100Base-TX full duplex is supported by

link partner

0 = 100Base-TX full duplex not supported by

link partner

5.9

100BASE-T4

PAUSE

RO

0

1 = 100Base-T4 is supported by link partner

0 = 100Base-T4 not supported by link partner

5.10

1 = flow control is supported by Link partner

0 = flow control is not supported by Link

partner

5.11

5.12

Asymmetric Pause

RO

0

1 = asymmetric flow control is supported by

Link partner

0 = asymmetric flow control is NOT supported

by Link partner

Reserved

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IP1001-DS-R06

IP1001 LF

Data Sheet

HW

Reset Reset

SW

Bit

Name

Description

Type

RO

5.13

Remote Fault

0

1 = link partner is indicating a remote fault

0 = link partner does not indicate a remote

fault.

It is Received Code Word Bit 13.

5.14

5.15

Acknowledge

RO

1 = link partner acknowledges reception of

local node’s capability

0 = no acknowledgement

It is Received Code Word Bit 14.

1 = Next pages are supported by link partner

0 = Next pages are not supported by link

partner. It is Received Code Word Bit 15.

32/48

Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

4.7

Bit

Auto-Negotiation Expansion Register (Reg6)

HW

Reset Reset

SW

Name

Description

Type

RO

6.0

Link Partner

1: Link partner supports Auto-Negotiation

0

Auto-Negotiation Able 0: Link partner does not support

Auto-Negotiation

6.1

6.2

6.3

6.4

Page Received

1: A new page has been received

0: A new page has not been received

RO

LH

0

1

0

Local Next Page

Able

1: Local device supports Next Page

0: Local device does not support Next Page

RO

Link Partner Next

Page Able

1: Link Partner supports Next Page

0: Link Partner does not support Next Page

Parallel Detection 1: A fault has been detected via Parallel

Fault

Detection function

0: A fault has not been detected via Parallel

Detection function

6.15:5 Reserved

Ignore when read

RO

Reserve 0

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Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

4.8

Bit

Auto-Negotiation Next Page Transmit Register (Reg7)

Name Description

HW

Reset Reset

SW

Type

R/W

7[10:0] Message/Unformatted Transmit Code Word Bit 10:0

Field

0x001 0x001

7.11

7.12

7.13

7.14

7.15

Toggle

Transmit Code Word Bit 11

Transmit Code Word Bit 12

Transmit Code Word Bit 13

Transmit Code Word Bit 14

Transmit Code Word Bit 15

RO

0

1

0

1

Acknowledge 2

Message Page

Reserved

R/W

RO

Reserved 0

0

4.9

Bit

Auto-Negotiation Link Partner Next Page Register (Reg8)

HW

Reset Reset

SW

Name

Description

Type

RO

8[10:0] Message/Unformatted

Field

Received Code Word Bit 10:0

0x000 0x000

8.11

8.12

8.13

8.14

8.15

Toggle

Received Code Word Bit 11

Received Code Word Bit 12

Received Code Word Bit 13

Received Code Word Bit 14

Received Code Word Bit 15

RO

0

Acknowledge 2

Message Page

Acknowledge

Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

4.10 1000BASE-T Control Register (Reg9)

HW

Reset Reset

SW

Bit

Name

Description

Type

R/W

9[7:0]

Reserved

Ignore when read

Reserved to

0x00

9.8

1000BASE-T Half 1: Advertise 1000BASE-T half duplex capable R/W

Duplex 0: Not advertise

1000BASE-T Full 1: Advertise 1000BASE-T full duplex capable R/W

1

0

9.9

Duplex

0: Not advertise

9.10

9.11

Port Type

1: Prefer multi-port device (MASTER)

0: Prefer single-port device (SLAVE)

R/W

Configuration

Value

1: Manual configure as MASTER

0: Manual configure as SLAVE

It is valid only if bit 9.12 is set to 1.

9.12

Manual

Configuration

Enable

1: Manual Configuration Enabled

0: Manual Configuration Disabled

R/W

0

9[15:13] Test mode

1000BASE_T test mode defined in IEEE802.3 R/W

clause 40.6.

000

9[15:13] Mode

000

001

Normal Mode

Test Mode 1

- Transmit waveform test

010

Test Mode 2 - Transmit Jitter test in

MASTER mode

011

Test Mode 3 - Transmit Jitter test in

SLAVE mode

100

Test Mode 4 - Transmit distortion

test

Others

Reserved

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Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

4.11 1000BASE-T Status Register (Reg10)

HW

Reset Reset

0x00 0x00

SW

Bit

Name

Description

Type

10[7:0] Idle Error Count

RO

10.8

10.9

Reserved

Ignore when read

Reserved to 0

10.10 Link Partner’s

1000BASE-T Half

Duplex Capability

1: Link Partner is capable of 1000BASE-T half RO

0

duplex

0: Link Partner is not capable of 1000BASE-T

half duplex

10.11 Link Partner’s

1000BASE-T Full

1: Link Partner is capable of 1000BASE-T full RO

0

duplex

Duplex Capability

0: Link Partner is not capable of 1000BASE-T

full duplex

10.12 Remote Receiver

Status

1: Remote Receiver OK

0: Remote Receiver Not OK

RO

0

10.13 Local Receiver

Status

1: Local Receiver OK

0: Local Receiver Not OK

10.14 MASTER/SLAVE

Configuration

1: Local PHY configuration resolved to

MASTER

Resolution

0: Local PHY configuration resolved to SLAVE

10.15 MASTER/SLAVE

1: MASTER/SLAVE configuration fault detected RO

0

Configuration Fault 0: No MASTER/SLAVE configuration fault

detected

LH

SC

36/48

Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

4.12 Extended Status Register (Reg15)

HW

Reset Reset

SW

Bit

Name

Description

Type

RO

15[11:0]

15.12

Reserved

Ignore when read

0x000 0x000

1000BASE-T

Half Duplex

1: be able to perform half duplex 1000BASE-T RO

0: not able to perform half duplex 1000BASE-T

1

0

1

0

15.13

15.14

15.15

1000BASE-T

Full Duplex

1: be able to perform full duplex 1000BASE-T RO

0: not able to perform full duplex 1000BASE-T

1000BASE-X

Half Duplex

1: be able to perform half duplex 1000BASE-X RO

0: not able to perform half duplex 1000BASE-X

1000BASE-X

Full Duplex

1: be able to perform full duplex 1000BASE-X RO

0: not able to perform full duplex 1000BASE-X

37/48

Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

4.13 PHY Specific Control & Status Register (Reg16)

HW

Reset Reset

SW

Bit

Name

Description

Type

16.0

RXPHASE_SEL This bit is used to adjust RX clock phase at RW

GMII/ RGMII interface

Pin 48 NA

0: No intentional delay is added on RX_CLK

1: An intentional delay is added on RX_CLK

(about 2ns delay in 1000BASE-T, and about

4ns delay in 100BASE-TX and 10BASE-T).

(Pin 48 sets the default value of this bit)

16.1

TXPHASE_SEL This bit is used to adjust TX clock phase at

GMII/ RGMII interface

RW

Pin 49 NA

0: No intentional delay is added on

GTX_CLK/ TXC

1: An intentional delay is added on

GTX_CLK/ TXC

(about 2ns delay in 1000BASE-T, and about

4ns delay in 100BASE-TX and 10BASE-T)

Pin 49 sets the default value of this bit.

16.2

Repeater Mode 1 = Enable repeater mode

0 = Disable repeater mode

RW

0

NA

16[4:3]

16[6:5]

Reserved

01

10

NA

RXCLK_DRIVE[1:0]

These 2 bits are used to adjust driving

current of RX_CLK.

I/F

2’b00

2’b01

2’b10

2’b11

MII

2mA

4mA

8mA

2mA

GMII/

RGMII

(10/100)

GMII/

RGMII

(1000)

2mA

4mA

8mA

2mA

12mA

16[8:7]

RXD_DRIVE[1:0] These 2 bits are used to adjust driving

current of RXD[7:0], RX_ER, and RX_DV.

RW

10

NA

The driving current of RXD[3:0] and RX_DV

I/F

2’b00

2’b01

2’b10

2’b11

MII

2mA

4mA

8mA

2mA

GMII/

RGMII

(10/100)

GMII/

RGMII

(1000)

2mA

4mA

8mA

2mA

12mA

The driving current of RXD[7:4] and RX_ER

I/F

MII

GMII

2’b00

2mA

2’b01

4mA

2’b10

8mA

2’b11

2mA

(10/100)

GMII

4mA

2mA

4mA

8mA

2mA

12mA

2mA

(1000)

RGMII

(10/100)

RGMII

(1000)

12mA

16.9

Jabber

1 = Enable Jabber

RW

1

NA

38/48

Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

HW

Reset Reset

SW

Bit

Name

Description

Type

0 = Disable Jabber

16.10

16.11

Heart beat

1 = Enable Heart beat

0 = Disable Heart beat

RW

0

1

NA

Smart Speed

1 = Downshift to 100Mbps when 1000Mbps

link fails

0 = No Downshift

Reserved

16.12

16.13

1

0

NA

The default value (1) should be adopted for

normal operation.

LED_DRIVE

This bit is used to adjust LED driving current RW

1’b0

4mA

1’b1

8mA

16[15:14] LED_MODE[1:0] These 2 bits are used to select LED

displaying mode

RW

0

NA

Pin55

(Pin 55 sets the default value of bit14)

39/48

Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

4.14 PHY Link Status Register (Reg17)

HW

Reset

SW

Reset

Bit

Name

Description

Type

17[8:0]

17.9

Reserved

RO

0

Jabber Detected 0: 10Base Jabber not detected

1: 10Base Jabber detected

17.10

17.11

APS_Sleep

0: Normal Operation

1: APS sleep mode is entered

RO

0

MDI/MDIX

0: MDI

1: MDIX

MDI

1G

MDIX

100M 10M 1G

100M 10M

MDI0 A

TX

RX

--

TX

RX

--

B

A

D

C

RX

TX

--

RX

TX

--

MDI1 B

MDI2 C

MDI3 D

--

17.12

Link_Duplex

0: link at half duplex

1: link at full duplex

It is valid only if bit 15 is 1.

RO

0

17[14:13] Link_Speed[1:0] 2’b00: link at 10Base-T

2’b01: link at 100Base-TX

2’b10: link at 1000Base-T

2’b11: Reserved

It is valid only if bit 15 is 1.

17.15

Link_Status

1: link up

RO

0

0: link down

Register 18~19 are reserved registers. User is inhibited to access to these registers. It may introduce

abnormal function to write these registers.

40/48

Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

4.15 PHY Specific Control Register2 (Reg20)

HW

Reset

SW

Reset

Bit

Name

Description

Type

20[1:0]

20.2

SR_V/ SR_FAST Sew rate control parameters

RW

11

NA

Auto-crossover

Enable

1: Enable auto MDI/MDIX

0: Disable auto MDI/MDIX

1

20[5:3]

20.6

Reserved

The default value should be adopted for

normal operation.

R/W 101

NA

Speed10to100en Detect the link partner’s speed change from RW

1

able

10BASE-T to 100BASE-TX by detecting

MLT3 signals

1: Enable

0: Disable

20[8: 7]

20.9

FIFO_Depth

FIFO depth latency

00: latency = 2

01: latency = 3

10: latency = 4

11: latency = 5

RW

10

0

NA

0

MDIX Enable

When disable auto-crossover

RW

0: MDI

1: MDIX

20.10

20.11

Reserved

APS_ON

The default value should be adopted for

normal operation.

R/W

1

NA

This bit is used to activate auto power saving RW

(APS) mode

0: Disable APS

1: Enable APS

20[15:12] Reserved

The default value should be adopted for

normal operation.

R/W 0000

NA

Register 21~31 are reserved registers. User is inhibited to access to these registers. It may introduce

abnormal function to write these registers.

41/48

Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

5

Electrical Characteristics

Absolute Maximum Rating

5.1

Stresses exceed those values listed under Absolute Maximum Ratings may cause permanent damage to the

device. Functional performance and device reliability are not guaranteed under these conditions. All voltages

are specified with respect to GND.

Supply Voltage

Input Voltage

Output Voltage

Storage Temperature

Ambient Operating Temperature (Ta)

–0.3V to 4.0V

–0.3V to 5.0V

-65°C to 150°C

-10°C to 70°C

5.2

Symbol

DVDD

DC. Characteristic

Conditions

Minimum

Typical

1.2V

1.8V

3.3V

2.5V

3.3V

2.5V

Maximum

Note

Digital core supply voltage

Analog core supply voltage

I/O pad supply voltage

Analog supply voltage

AVDD

VDDO

AVDDH

VCT

1.7V

3.0V

1.88V

3.0V

2.4V

2.2V

3.6V

GMII/MII

RGMII

2.75V

3.6V

GMII/MII

RGMII

2.75V

70°C

Transformer center tap voltage

Operating Temperature

2.1V

TA

-10°C

Input Clock

Parameter

Sym.

Min.

-50

Typ.

25

Max. Unit

Conditions

Frequency

MHz

PPM

Frequency Tolerance

+50

I/O Electrical Characteristics

Symbol

V_IH

Specific Name

Input High Vol.

Input Low Vol.

Output High Vol.

Output Low Vol.

Tri-state Leakage

Input Current

Condition

Min

Max

0.5*Vcc

-0.5V

Vcc+0.5V

0.3*Vcc

Vcc

V_IL

V_OH

V_OL

I_OZ

0.9*Vcc

0.1*Vcc

Vout=Vcc or GND

Vin=Vcc or GND

I_IN

Icc

Average Operating Supply Current Iout=0mA

42/48

Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

5.3

AC Timing

5.3.1

Reset Timing

Description

Min.

Typ.

Max.

Unit

X1 valid period before reset released

Reset period

MII/GMII/RGMII clock out after reset released

CLK_OUT clock out after reset released

10

-

1

-

20

ms

µs

0

ns

Power on

VCC

OSCI

(X1)

X1 valid period before reset released

Reset released

resetb

Reset period

MII clock

MII clock comes out period after reset released

CLK_OUT

CLK_OUT comes out period after reset released

43/48

Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

5.3.2

MII Timing

a. Transmit Timing Requirements

Symbol

T_Tclk1

T_s1

Description

Min.

Typ.

Max.

Unit

Period of transmit clock in 100M mode

Period of transmit clock in 10M mode

TXEN, TXD to TX_CLK setup time

(TXPHASE_SEL=0, no clock delay added)

TXEN, TXD to TX_CLK setup time

(TXPHASE_SEL=1, clock delay added)

TXEN, TXD to TX_CLK hold time

-

40

400

-

ns

-0.65

3.35

0.2

ns

T_h1

(TXPHASE_SEL=0, no clock delay added)

TXEN, TXD to TX_CLK hold time

4.2

(TXPHASE_SEL=1, clock delay added)

TTclk1

MII_TXCLK

Th1

TXEN, TXD[3:0]

T^s1

b. Receive Timing

Symbol

Description

Min.

Typ.

Max.

Unit

T_Rclk1

T_d1

Period of receive clock in 100M mode

Period of receive clock in 10M mode

MII_RXCLK rising edge to RXDV, RXD

(RXPHASE_SEL=0, no clock delay added)

MII_RXCLK rising edge to RXDV, RXD

(RXPHASE_SEL=1, clock delay added)

-

40

400

0

-

ns

-0.4

0.4

3.6

4

4.4

ns

T^Rclk1

RX_CLK

Td1

RXDV, RXD[3:0]

44/48

Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

5.3.3

GMII Timing

c. Transmit Timing Requirements

Symbol

T_TXCLK

T_s2

Description

Min.

Typ.

8

Max.

-

Unit

Period of transmit clock

-

ns

TXEN, TXD to GTX_CLK setup time

(TXPHASE_SEL=0, no clock delay added)

TXEN, TXD to GTX_CLK setup time

(TXPHASE_SEL=1, clock delay added)

TXEN, TXD to GTX_CLK hold time

(TXPHASE_SEL=0, no clock delay added)

TXEN, TXD to GTX_CLK hold time

(TXPHASE_SEL=1, clock delay added)

-0.65

3.35

0.2

ns

T_h2

4.2

TTclk2

GTX_CLK

Th2

TXEN, TXD[7:0]

T^s2

d. Receive Timing

Symbol

Description

Min.

-

Typ.

8

Max.

Unit

T_Rclk2

T_d2

Period of receive clock

-

ns

RX_CLK rising edge to RXDV, RXD

(RXPHASE_SEL=0, no clock delay added)

RX_CLK rising edge to RXDV, RXD

(RXPHASE_SEL=1, clock delay added)

0.4

4.4

ns

T^Rclk2

RX_CLK

Td2

RXDV, RXD[7:0]

45/48

Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

5.3.4

RGMII Timing

e. Transmit Timing Requirements

Symbol

T_Tclk3

T_s3

Description

Min.

Typ.

Max.

Unit

Period of transmit clock in giga mode

Period of transmit clock in 100M mode

Period of transmit clock in 10M mode

TXEN, TXD to TXC setup time

-

8

40

400

-

ns

-0.65

(TXPHASE_SEL=0, no clock delay added)

TXEN, TXD to TXC setup time

(TXPHASE_SEL=1, clock delay added)

TXEN, TXD to TXC hold time

(TXPHASE_SEL=0, no clock delay added)

TXEN, TXD to TXC hold time

1.35

0.2

ns

T_h3

2.2

(TXPHASE_SEL=1, clock delay added)

TTclk3

TXC

Th3

TXCTL, TXD[3:0]

T^s3

Ts3

f. Receive Timing

Symbol

Description

Min.

Typ.

Max.

Unit

T_Rclk3

T_d3

Period of receive clock in giga mode

Period of receive clock in 100M mode

Period of receive clock in 10M mode

RXC edge to RXCTL, RXD

-

8

40

400

-

ns

0.4

(RXPHASE_SEL=0, no clock delay added)

RXC edge to RXCTL, RXD

2.4

ns

(RXPHASE_SEL=1, clock delay added)

TRclk3

RXC

T^d3

Td3

RXCTL, RXD[3:0]

46/48

Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

5.3.5

SMI Timing

a. MDC/MDIO Timing Requirements

Symbol

T_ch

T_cl

T_cm

T_md

T_mh

T_ms

Description

Min.

Typ.

Max.

Unit

MDC0 High Time

MDC0 Low Time

MDC0 period

MDIO0 output delay

MDIO0 setup time

MDIO0 hold time

40

80

-

10

-

5

-

ns

-

M D C

Tm s

Tm h

M D IO

W rite C ycle

M D C

Tcl

Tch

Tm d

Tcm

M D IO

R ead C ycle

5.4

Thermal Data

Theta Ja

24.5

Theta Jc

Conditions

Units

11.1

4 Layer PCB; air

flow@ 0m/sec

^oC/ W

68.6

14.2

2 Layer PCB; air

flow@ 0m/sec

^oC/ W

6

Order Information

Part No.

Package

Notice

IP1001 LF

64-PIN QFN

Lead free

47/48

Dec. 18, 2007

IP1001-DS-R06

IP1001 LF

Data Sheet

7

Package Detail

64 QFN Outline Dimensions

aaa

C

K

D

A

M

A B

bbb

ddd

C

D1

B

64

b

1

R

ccc

//

C

0.6max

A2

A3

A

E

E1

Optional

A1

L

b

Exposed support bar

(See list “*＂)

C

DETAIL :“A＂

DETAIL :“B＂

aaa

Dimension in mm

Dimension in inch

C

Symbol

Min

0.80

0.00

0.60

Nom

0.85

0.02

0.65

0.20REF

0.25

9.00BSC

8.75BSC

0.50BSC

0.40

---

Max

1.00

0.05

0.80

Min

Nom

Max

A

A1

A2

A3

b

0.031 0.033 0.039

0.000 0.001 0.002

0.024 0.026 0.031

0.008REF

A

eee

C

0.18

0.30

0.007 0.010 0.012

0.354BSC

Seating Plane

D/E

D1/E1

e

0.344BSC

“B＂

0.020BSC

L

0.30

0°

0.50

14°

0.012 0.016 0.020

0°

0.004

0.008

---

14°

---

D2

Θ

M

A B

C

fff

---

R

0.09

0.20

---

K

aaa

M

---

A B

fff

C

0.15

0.10

0.05

0.08

0.10

0.006

0.004

0.002

0.003

0.004

---

bbb

ccc

---

ddd

eee

---

fff

E2

NOTE:

CONTROLLING DIMENSION : MILLIMETER

Exposed Pad Size

“A＂

D2/E2 (mm)

Nom

D2/E2 (inch)

Nom Max

＊

N

Min

5.49

Max

5.79

Min

5.64

0.216 0.222 0.228

e

IC Plus Corp.

Headquarters

Sales Office

10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2,

Hsin-Chu City, Taiwan 300, R.O.C.

4F, No. 106, Hsin-Tai-Wu Road, Sec.1,

Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C.

TEL : 886-3-575-0275

FAX : 886-3-575-0475

TEL : 886-2-2696-1669

FAX : 886-2-2696-2220

Website: www.icplus.com.tw

48/48

Dec. 18, 2007

IP1001-DS-R06


型号：	IP1001-DS-R05
厂家：	ETC
描述：	Integrated 10/100/1000 Gigabit Ethernet Transceiver 集成10/100/1000千兆以太网收发器以太网局域网（LAN）标准
文件：	总48页 (文件大小：625K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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