IS45S16400J-7CTLA1 [ETC]
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM;
| 型号： | IS45S16400J-7CTLA1 |
| 厂家： | 
ETC |
| 描述： | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 文件： | 总60页 (文件大小：1221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS42S16400J
IS45S16400J
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
JANUARY 2014
FEATURES
OVERVIEW
ISSI'sꢀ64MbꢀSynchronousꢀDRAMꢀisꢀorganizedꢀasꢀ1,048,576ꢀ
bitsꢀ xꢀ 16-bitꢀ xꢀ 4-bankꢀ forꢀ improvedꢀ performance.ꢀ Theꢀ
synchronousꢀ DRAMsꢀ achieveꢀ high-speedꢀ dataꢀ transferꢀ
using pipeline architecture. All inputs and outputs signals
refer to the rising edge of the clock input.
•ꢀ Clock frequency: 200, 166, 143, 133 MHz
•ꢀ Fullyꢀsynchronous;ꢀallꢀsignalsꢀreferencedꢀtoꢀaꢀ
positive clock edge
•ꢀ Internalꢀbankꢀforꢀhidingꢀrowꢀaccess/precharge
•ꢀ Singleꢀ3.3Vꢀpowerꢀsupply
•ꢀ LVTTLꢀinterface
•ꢀ Programmableꢀburstꢀlengthꢀ
KEY TIMING PARAMETERS
– (1, 2, 4, 8, full page)
•ꢀ Programmableꢀburstꢀsequence:ꢀ
Parameter
-5
-6
-7
Unit
Sequential/Interleave
ClkꢀCycleꢀTimeꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀꢀ
5ꢀ
7.5ꢀ
ꢀ
6ꢀ
7.5ꢀ
ꢀ
7ꢀ
7.5ꢀ
ꢀ
nsꢀ
ns
•ꢀ Selfꢀrefreshꢀmodes
•ꢀ Autoꢀrefreshꢀ(CBR)
ClkꢀFrequencyꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀꢀ
200ꢀ
133ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ 4096ꢀrefreshꢀcyclesꢀeveryꢀ64ꢀmsꢀ(Com,ꢀInd,ꢀA1ꢀ
166ꢀ
133ꢀ
143ꢀ
133ꢀ
Mhzꢀ
Mhz
grade) or 16ms (A2 grade)
•ꢀ Randomꢀcolumnꢀaddressꢀeveryꢀclockꢀcycle
AccessꢀTimeꢀꢀfromꢀClockꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
4.8ꢀ
5.4ꢀ
5.4ꢀ
5.4ꢀ
5.4ꢀ
5.4ꢀ
nsꢀ
ns
•ꢀ ProgrammableꢀCAS latency (2, 3 clocks)
•ꢀ Burstꢀread/writeꢀandꢀburstꢀread/singleꢀwriteꢀ
operations capability
•ꢀ Burstꢀterminationꢀbyꢀburstꢀstopꢀandꢀprechargeꢀ
command
ADDRESS TABLE
OPTIONS
Parameter
4M x 16
•ꢀ Package:
Configuration
1M x 16 x 4
54-pinꢀTSOPꢀII
banks
54-ballꢀTF-BGAꢀ(8mmꢀxꢀ8mm)
60-ballꢀTF-BGAꢀ(10.1mmꢀxꢀ6.4mm)
Refresh Count
Com./Ind. 4K/64ms
A1 4K/64ms
•ꢀ OperatingꢀTemperatureꢀRange
Commercial (0oC to +70oC)
A2 4K/16ms
Industrial (-40oC to +85oC)
Row Addresses
A0-A11
AutomotiveꢀGradeꢀA1ꢀ(-40oC to +85oC)
AutomotiveꢀGradeꢀA2ꢀ(-40oC to +105oC)
Column Addresses
Bank Address Pins
Auto Precharge Pins
A0-A7
BA0, BA1
A10/AP
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
GENERAL DESCRIPTION
Theꢀ 64Mbꢀ SDRAMꢀ isꢀ aꢀ highꢀ speedꢀ CMOS,ꢀ dynamicꢀ
random-accessꢀ memoryꢀ designedꢀ toꢀ operateꢀ inꢀ 3.3Vꢀ
memory systems containing 67,108,864 bits. Internally
configuredꢀasꢀaꢀquad-bankꢀDRAMꢀwithꢀaꢀsynchronousꢀ
interface.ꢀꢀEachꢀ16,777,216-bitꢀbankꢀisꢀorganizedꢀasꢀ4,096ꢀ
rows by 256 columns by 16 bits.
otherthreebankswillhidetheprechargecyclesandprovide
seamless, high-speed, random-access operation.
SDRAM readandwriteaccessesareburstorientedstarting
at a selected location and continuing for a programmed
numberꢀ ofꢀ locationsꢀ inꢀ aꢀ programmedꢀ sequence.ꢀ ꢀTheꢀ
registrationꢀ ofꢀ anꢀ ACTIVEꢀ commandꢀ beginsꢀ accesses,ꢀ
followedꢀbyꢀaꢀREADꢀorꢀWRITEꢀcommand.ꢀTheꢀACTIVEꢀ
command in conjunction with address bits registered are
usedꢀtoꢀselectꢀtheꢀbankꢀandꢀrowꢀtoꢀbeꢀaccessedꢀ(BA0,ꢀ
BA1ꢀselectꢀtheꢀbank;ꢀA0-A11ꢀselectꢀtheꢀrow).ꢀꢀTheꢀREADꢀ
orꢀWRITEꢀ commandsꢀ inꢀ conjunctionꢀ withꢀ addressꢀ bitsꢀ
registered are used to select the starting column location
for the burst access.
Theꢀ64MbꢀSDRAMꢀincludesꢀanꢀAUTOꢀREFRESHꢀMODE,ꢀ
and a power-saving, power-down mode. All signals are
registeredꢀonꢀtheꢀpositiveꢀedgeꢀofꢀtheꢀclockꢀsignal,ꢀCLK.ꢀ
AllꢀinputsꢀandꢀoutputsꢀareꢀLVTTLꢀcompatible.
Theꢀ64MbꢀSDRAMꢀhasꢀtheꢀabilityꢀtoꢀsynchronouslyꢀburstꢀ
data at a high data rate with automatic column-address
generation, theabilitytointerleavebetweeninternalbanks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
ProgrammableꢀREADꢀorꢀWRITEꢀburstꢀlengthsꢀconsistꢀofꢀ
1, 2, 4 and 8 locations, or full page, with a burst terminate
option.
A self-timed row precharge initiated at the end of the burst
sequenceꢀisꢀavailableꢀwithꢀtheꢀAUTOꢀPRECHARGEꢀfunctionꢀ
enabled. Precharge one bank while accessing one of the
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
DQM
DATA IN
BUFFER
COMMAND
DECODER
&
CLOCK
GENERATOR
16
16
REFRESH
CONTROLLER
MODE
REGISTER
DQ 0-15
A10
12
V
DD/VDDQ
SELF
DATA OUT
BUFFER
REFRESH
GND/GNDQ
A11
CONTROLLER
16
16
A9
A8
A7
A6
REFRESH
COUNTER
A5
A4
4096
A3
A2
A1
A0
BA0
BA1
4096
MEMORY CELL
ARRAY
4096
4096
12
BANK 0
ROW
ADDRESS
LATCH
ROW
ADDRESS
BUFFER
12
12
SENSE AMP I/O GATE
256K
(x 16)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
8
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
8
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
PIN CONFIGURATION
PACKAꢀꢁ Cꢂꢃꢁ: B 54 BALL Tꢄ-BꢀA (Top View) (8 mm x 8 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9
A
GND DQ15 GNDQ
DQ14 DQ13 VDDQ
DQ12 DQ11 GNDQ
DQ10 DQ9 VDDQ
VDDQ DQ0 VDD
GNDQ DQ2 DQ1
VDDQ DQ4 DQ3
GNDQ DQ6 DQ5
VDD DQML DQ7
CAS RAS WE
B
C
D
E
F
DQ8
NC GND
DQMH CLK CKE
G
H
J
NC
A8
A11
A7
A9
A6
A4
BA0 BA1
CS
A10
VDD
A0
A3
A1
A2
GND
A5
PIN DESCRIPTIONS
A0-A11
A0-A7
BA0, BA1
ꢃQ0 to ꢃQ15
CLK
Row Address Input
Column Address Input
Bank Select Addresses
ꢃata I/ꢂ
WE
Write ꢁnable
LꢃQM, UꢃQM
Vdd
x16 Input/ꢂutput Mask
Power
ꢀNꢃ
ꢀround
System Clock Input
Clock ꢁnable
Vddq
Power Supply for I/ꢂ Pin
ꢀround for I/ꢂ Pin
No Connection
CKꢁ
ꢀNꢃQ
NC
CS
Chip Select
RAS
Row Address Strobe Command
CAS
Column Address Strobe Command
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3
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
PIN CONFIGURATION
PACKAGEꢀCODE:ꢀB2ꢀꢀ60ꢀBALLꢀTF-BGAꢀ(TopꢀView)ꢀ(10.1ꢀmmꢀxꢀ6.4ꢀmmꢀBody,ꢀ0.65ꢀmmꢀBallꢀPitch)
1 2 3 4 5 6 7
A
GND DQ15
DQ14 GNDQ
DQ13 VDDQ
DQ12 DQ11
DQ10 GNDQ
DQ9 VDDQ
DQ8 NC
DQ0 VDD
VDDQ DQ1
GNDQ DQ2
DQ4 DQ3
VDDQ DQ5
GNDQ DQ6
B
C
D
E
F
G
H
J
NC
DQ7
NC
NC
NC UDQM
NC CLK
CKE NC
NC
VDD
LDQM WE
K
L
CAS
CS
RAS
NC
BA1
A0
M
N
P
R
A11
A8
A9
A7
A5
BA0
A10
A1
A6
A2
GND A4
VDD
A3
PIN DESCRIPTIONS
A0-A11ꢀ ꢀ
A0-A7
RowꢀAddressꢀInput
Column Address Input
BankꢀSelectꢀAddresses
DataꢀI/O
WEꢀ
ꢀ
WriteꢀEnable
LDQM,ꢀUDQMꢀ x16ꢀInput/OutputꢀMask
BA0,ꢀBA1ꢀ
DQ0ꢀtoꢀDQ15ꢀ
Vdd
Power
GNDꢀ
Vddqꢀ
GNDqꢀ
NCꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Ground
CLKꢀ
CKEꢀ
CS
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
PowerꢀSupplyꢀforꢀI/OꢀPin
GroundꢀforꢀI/OꢀPin
NoꢀConnection
Chip Select
RASꢀ
CAS
ꢀ
RowꢀAddressꢀStrobeꢀCommand
Column Address Strobe Command
4
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Rev. F
12/17/2013
IS42S16400J
IS45S16400J
PIN CONFIGURATIONS
54 pin TSOP - Type II
V
DD
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
GND
DQ0
2
DQ15
GNDQ
DQ14
DQ13
V
DD
Q
3
DQ1
DQ2
4
5
GNDQ
DQ3
6
VDDQ
7
DQ12
DQ11
GNDQ
DQ10
DQ9
DQ4
8
V
DD
Q
9
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
GNDQ
DQ7
VDDQ
DQ8
GND
NC
VDD
LDQM
WE
CAS
RAS
CS
UDQM
CLK
CKE
NC
BA0
BA1
A10
A0
A11
A9
A8
A7
A1
A6
A2
A5
A3
A4
V
DD
GND
PIN DESCRIPTIONS
A0-A11ꢀ ꢀ
RowꢀAddressꢀInput
WEꢀ
WriteꢀEnable
A0-A7
Column Address Input
BankꢀSelectꢀAddress
DataꢀI/O
LDQMꢀ x16ꢀLowerꢀByte,ꢀInput/OutputꢀMask
UDQMꢀ x16ꢀUpperꢀByte,ꢀInput/OutputꢀMask
BA0,ꢀBA1ꢀ
DQ0ꢀtoꢀDQ15ꢀ
Vdd
Power
CLKꢀ
CKEꢀ
CS
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
GNDꢀ
Vddqꢀ
Ground
PowerꢀSupplyꢀforꢀI/OꢀPin
Chip Select
GNDqꢀ GroundꢀforꢀI/OꢀPin
NCꢀ NoꢀConnection
RASꢀ
CAS
ꢀ
RowꢀAddressꢀStrobeꢀCommand
Column Address Strobe Command
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5
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
PIN FUNCTIONS
Symbol
TSOP Pin No.
Type
Input Pin
ꢀ
Function
A0-A11
23 to 26
29ꢀtoꢀ34
22, 35
ꢀ
AddressꢀInputs:ꢀA0-A11ꢀareꢀsampledꢀduringꢀtheꢀACTIVE
commandꢀ(row-addressꢀA0-A11)ꢀandꢀREAD/WRITEꢀcommandꢀ(A0-A7
ꢀ
with A10 defining auto precharge) to select one location out of the memory array
inꢀtheꢀrespectiveꢀbank.ꢀA10ꢀisꢀsampledꢀduringꢀaꢀPRECHARGEꢀcommandꢀtoꢀdeter-
mineꢀifꢀallꢀbanksꢀareꢀtoꢀbeꢀprechargedꢀ(A10ꢀHIGH)ꢀorꢀbankꢀselectedꢀby
BA0,ꢀBA1ꢀ(LOW).ꢀTheꢀaddressꢀinputsꢀalsoꢀprovideꢀtheꢀop-codeꢀduringꢀaꢀLOADꢀ
MODEꢀREGISTERꢀcommand.
BA0,ꢀBA1
CAS
20, 21
17
Input Pin
Input Pin
Input Pin
ꢀ
BankꢀSelectꢀAddress:ꢀBA0ꢀandꢀBA1ꢀdefinesꢀwhichꢀbankꢀtheꢀACTIVE,ꢀREAD,ꢀWRITEꢀ
orꢀPRECHARGEꢀcommandꢀisꢀbeingꢀapplied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"CommandꢀTruthꢀTable"ꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
ꢀ
ꢀ
CKEꢀ
37
ꢀ
TheꢀCKEꢀinputꢀdeterminesꢀwhetherꢀtheꢀCLKꢀinputꢀisꢀenabled.ꢀTheꢀnextꢀrisingꢀedgeꢀ
ofꢀtheꢀCLKꢀsignalꢀwillꢀbeꢀvalidꢀwhenꢀisꢀCKEꢀHIGHꢀandꢀinvalidꢀwhenꢀLOW.ꢀWhenꢀCKEꢀ
isꢀLOW,ꢀtheꢀdeviceꢀwillꢀbeꢀinꢀeitherꢀpower-downꢀmode,ꢀclockꢀsuspendꢀmode,ꢀorꢀselfꢀ
refresh mode. CKEꢀisꢀan asynchronous input.
CLKꢀ
38
Input Pin
ꢀ
CLKꢀisꢀtheꢀmasterꢀclockꢀinputꢀforꢀthisꢀdevice.ꢀExceptꢀforꢀCKE,ꢀallꢀinputsꢀtoꢀthisꢀdeviceꢀ
are acquired in synchronization with the rising edge of this pin.
CS
19ꢀ
InputꢀPin
ꢀ
TheꢀCS input determines whether command input is enabled within the device.
Command input is enabled when CSꢀisꢀLOW,ꢀandꢀdisabledꢀwithꢀCSꢀisꢀHIGH.ꢀTheꢀ
device remains in the previous state when CSꢀisꢀHIGH.
DQ0 to
DQ15
2, 4, 5, 7, 8, 10,
11,13, 42, 44, 45,
47, 48, 50, 51, 53
15,ꢀ39ꢀ
DQ Pin
ꢀ
DQ0ꢀtoꢀDQ15ꢀareꢀI/Oꢀpins.ꢀI/Oꢀthroughꢀtheseꢀpinsꢀcanꢀbeꢀcontrolledꢀinꢀbyteꢀunits
usingꢀtheꢀLDQMꢀandꢀUDQMꢀpins.
ꢀ
ꢀ
ꢀ
ꢀ
LDQM,ꢀ
UDQMꢀ
InputꢀPin
ꢀ
LDQMꢀandꢀUDQMꢀcontrolꢀtheꢀlowerꢀandꢀupperꢀbytesꢀofꢀtheꢀI/Oꢀbuffers.ꢀInꢀread
ꢀ
ꢀ
mode,ꢀLDQMꢀandꢀUDQMꢀcontrolꢀtheꢀoutputꢀbuffer.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀLOW,ꢀ
theꢀcorrespondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀwhenꢀHIGH,ꢀdisabled.ꢀTheꢀoutputsꢀ
goꢀtoꢀtheꢀHIGHꢀimpedanceꢀstateꢀwhenꢀLDQM/UDQMꢀisꢀHIGH.ꢀThisꢀfunctionꢀcor-
responds to OEꢀinꢀconventionalꢀDRAMs.ꢀInꢀwriteꢀmode,ꢀLDQMꢀandꢀUDQMꢀcontrolꢀ
theꢀinputꢀbuffer.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀLOW,ꢀtheꢀcorrespondingꢀbufferꢀbyteꢀisꢀen-
abled,ꢀandꢀdataꢀcanꢀbeꢀwrittenꢀtoꢀtheꢀdevice.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀHIGH,ꢀinputꢀ
data is masked and cannot be written to the device.
RAS
WE
18
16
Input Pin
RAS, in conjunction with CAS and WE, forms the device command. See the "Com-
mandꢀTruthꢀTable"ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.
Input Pin
WE, in conjunction with RAS and CAS, forms the device command. See the "Com-
mandꢀTruthꢀTable"ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Vddq
Vdd
3,ꢀ9,ꢀ43,ꢀ49ꢀ
1, 14, 27
PowerꢀSupplyꢀPin
Power Supply Pin
Power Supply Pin
Power Supply Pin
ꢀ
ꢀ
ꢀ
ꢀ
Vddq is the output buffer power supply.
Vdd is the device internal power supply.
GNdq is the output buffer ground.
GNd is the device internal ground.
GNdq
GNd
6, 12, 46, 52
28, 41, 54
6
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Rev. F
12/17/2013
IS42S16400J
IS45S16400J
applyꢀexceptꢀinꢀfull-pageꢀburstꢀmode.ꢀUponꢀcompletionꢀofꢀ
theꢀREADꢀorꢀWRITEꢀburst,ꢀaꢀprechargeꢀofꢀtheꢀbank/rowꢀ
that is addressed is automatically performed.
READ
TheꢀREADꢀcommandꢀselectsꢀtheꢀbankꢀfromꢀBA0,ꢀBA1ꢀinputsꢀ
and starts a burst read access to an active row. Inputs
A0-A7ꢀprovidesꢀtheꢀstartingꢀcolumnꢀlocation.ꢀꢀWhenꢀA10ꢀisꢀ
HIGH,ꢀthisꢀcommandꢀfunctionsꢀasꢀanꢀAUTOꢀPRECHARGEꢀ
command.ꢀꢀWhenꢀtheꢀautoꢀprechargeꢀisꢀselected,ꢀtheꢀrowꢀ
beingꢀaccessedꢀwillꢀbeꢀprechargedꢀatꢀtheꢀendꢀofꢀtheꢀREADꢀ
burst.ꢀTheꢀrowꢀwillꢀremainꢀopenꢀforꢀsubsequentꢀaccessesꢀ
whenꢀAUTOꢀPRECHARGEꢀisꢀnotꢀselected.ꢀꢀDQ’sꢀreadꢀ
data is subject to the logic level on the DQM inputs two
clocksꢀearlier.ꢀWhenꢀaꢀgivenꢀDQMꢀsignalꢀwasꢀregisteredꢀ
HIGH,ꢀtheꢀcorrespondingꢀDQ’sꢀwillꢀbeꢀHigh-Zꢀtwoꢀclocksꢀ
later.ꢀDQ’sꢀwillꢀprovideꢀvalidꢀdataꢀwhenꢀtheꢀDQMꢀsignalꢀ
wasꢀregisteredꢀLOW.
AUTO REFRESH COMMAND
ThisꢀcommandꢀexecutesꢀtheꢀAUTOꢀREFRESHꢀoperation.ꢀ
Theꢀrowꢀaddressꢀandꢀbankꢀtoꢀbeꢀrefreshedꢀareꢀautomaticallyꢀ
generatedꢀduringꢀthisꢀoperation.ꢀ Theꢀstipulatedꢀperiodꢀ(trc)is
required for a single refresh operation, and no other com-
mandsꢀcanꢀbeꢀexecutedꢀduringꢀthisꢀperiod.ꢀ Thisꢀcommandꢀ
isꢀexecutedꢀatꢀleastꢀ4096ꢀtimesꢀeveryꢀTref.ꢀDuringꢀanꢀAUTOꢀ
REFRESHꢀcommand,ꢀaddressꢀbitsꢀareꢀ“Don’tꢀCare”.ꢀꢀThisꢀ
commandꢀcorrespondsꢀtoꢀCBRꢀAuto-refresh.
SELF REFRESH
DuringꢀtheꢀSELFꢀREFRESHꢀoperation,ꢀtheꢀrowꢀaddressꢀtoꢀ
be refreshed, the bank, and the refresh interval are gen-
eratedꢀautomaticallyꢀinternally.ꢀꢀSELFꢀREFRESHꢀcanꢀbeꢀ
usedꢀtoꢀretainꢀdataꢀinꢀtheꢀSDRAMꢀwithoutꢀexternalꢀclocking,ꢀ
evenꢀifꢀtheꢀrestꢀofꢀtheꢀsystemꢀisꢀpoweredꢀdown.ꢀTheꢀSELFꢀ
REFRESHꢀoperationꢀisꢀstartedꢀbyꢀdroppingꢀtheꢀCKEꢀpinꢀ
fromꢀHIGHꢀtoꢀLOW.ꢀDuringꢀtheꢀSELFꢀREFRESHꢀoperationꢀ
allꢀotherꢀinputsꢀtoꢀtheꢀSDRAMꢀbecomeꢀ“Don’tꢀCare”.ꢀTheꢀ
device must remain in self refresh mode for a minimum
period equal to tras or may remain in self refresh mode
forꢀanꢀindefiniteꢀperiodꢀbeyondꢀthat.ꢀTheꢀSELF-REFRESHꢀ
operationꢀcontinuesꢀasꢀlongꢀasꢀtheꢀCKEꢀpinꢀremainsꢀLOWꢀ
and there is no need for external control of any other pins.
Theꢀnextꢀcommandꢀcannotꢀbeꢀexecutedꢀuntilꢀtheꢀdeviceꢀ
internal recovery period (trc)ꢀ hasꢀ elapsed.ꢀ Onceꢀ CKEꢀ
goesꢀHIGH,ꢀtheꢀNOPꢀcommandꢀmustꢀbeꢀissuedꢀ(minimum
of two clocks) to provide time for the completion of any
internal refresh in progress. After the self-refresh, since it
is impossible to determine the address of the last row to
beꢀrefreshed,ꢀanꢀAUTO-REFRESHꢀshouldꢀimmediatelyꢀbeꢀ
performed for all addresses.
WRITE
A burst write access to an active row is initiated with the
WRITEꢀcommand.ꢀꢀBA0,ꢀBA1ꢀinputsꢀselectsꢀtheꢀbank,ꢀ
and the starting column location is provided by inputs
A0-A7.ꢀWhetherꢀorꢀnotꢀAUTO-PRECHARGEꢀisꢀusedꢀisꢀ
determined by A10.
Theꢀrowꢀbeingꢀaccessedꢀwillꢀbeꢀprechargedꢀatꢀtheꢀendꢀofꢀ
theꢀWRITEꢀburst,ꢀifꢀAUTOꢀPRECHARGEꢀisꢀselected.ꢀIfꢀ
AUTOꢀPRECHARGEꢀisꢀnotꢀselected,ꢀtheꢀrowꢀwillꢀremainꢀ
open for subsequent accesses.
A memory array is written with corresponding input data
onꢀDQ’sꢀandꢀDQMꢀinputꢀlogicꢀlevelꢀappearingꢀatꢀtheꢀsameꢀ
time. Data will be written to memory when DQM signal is
LOW.ꢀꢀWhenꢀDQMꢀisꢀHIGH,ꢀtheꢀcorrespondingꢀdataꢀinputsꢀ
willꢀbeꢀignored,ꢀandꢀaꢀWRITEꢀwillꢀnotꢀbeꢀexecutedꢀtoꢀthatꢀ
byte/column location.
PRECHARGE
TheꢀPRECHARGEꢀcommandꢀisꢀusedꢀtoꢀdeactivateꢀtheꢀopenꢀ
rowꢀinꢀaꢀparticularꢀbankꢀorꢀtheꢀopenꢀrowꢀinꢀallꢀbanks.ꢀꢀBA0,ꢀ
BA1ꢀcanꢀbeꢀusedꢀtoꢀselectꢀwhichꢀbankꢀisꢀprechargedꢀorꢀtheyꢀ
areꢀtreatedꢀasꢀ“Don’tꢀCare”.ꢀA10ꢀdeterminesꢀwhetherꢀoneꢀ
orallbanksareprecharged.Afterexecutingthiscommand,
thenextcommandfortheselectedbank(s)isexecutedafter
passage of the period tRP, which is the period required for
bankꢀprecharging.ꢀꢀꢀOnceꢀaꢀbankꢀhasꢀbeenꢀprecharged,ꢀitꢀ
isꢀinꢀtheꢀidleꢀstateꢀandꢀmustꢀbeꢀactivatedꢀpriorꢀtoꢀanyꢀREADꢀ
orꢀWRITEꢀcommandsꢀbeingꢀissuedꢀtoꢀthatꢀbank.
BURST TERMINATE
TheꢀBURSTꢀTERMINATEꢀcommandꢀforciblyꢀterminatesꢀ
the burst read and write operations by truncating either
fixed-length or full-page bursts and the most recently
registeredꢀREADꢀorꢀWRITEꢀcommandꢀpriorꢀtoꢀtheꢀBURSTꢀ
TERMINATE.
COMMAND INHIBIT
COMMANDꢀINHIBITꢀpreventsꢀnewꢀcommandsꢀfromꢀbeingꢀ
executed.ꢀOperationsꢀinꢀprogressꢀareꢀnotꢀaffected,ꢀapartꢀ
fromꢀwhetherꢀtheꢀCLKꢀsignalꢀisꢀenabled
AUTO PRECHARGE
Theꢀ AUTOꢀ PRECHARGEꢀ functionꢀ ensuresꢀ thatꢀ theꢀ
precharge is initiated at the earliest valid stage within a
burst.ꢀꢀThisꢀfunctionꢀallowsꢀforꢀindividual-bankꢀprechargeꢀ
without requiring an explicit command. A10 can be used
toꢀenableꢀtheꢀAUTOꢀPRECHARGEꢀfunctionꢀinꢀconjunc-
tionꢀwithꢀaꢀspecificꢀREADꢀorꢀWRITEꢀcommand.ꢀꢀForꢀeachꢀ
individualꢀREADꢀorꢀWRITEꢀcommand,ꢀautoꢀprechargeꢀisꢀ
eitherꢀenabledꢀorꢀdisabled.ꢀAUTOꢀPRECHARGEꢀdoesꢀnotꢀ
NO OPERATION
WhenꢀCSꢀisꢀlow,ꢀtheꢀNOPꢀcommandꢀpreventsꢀunwantedꢀ
commands from being registered during idle or wait
states.
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LOAD MODE REGISTER
DuringꢀtheꢀLOADꢀMODEꢀREGISTERꢀcommandꢀtheꢀmodeꢀ
registerꢀisꢀloadedꢀfromꢀA0-A11.ꢀꢀThisꢀcommandꢀcanꢀonlyꢀ
be issued when all banks are idle.
ACTIVE COMMAND
Whenꢀ theꢀ ACTIVEꢀ COMMANDꢀ isꢀ activated,ꢀ BA0,ꢀ BA1ꢀ
inputs selects a bank to be accessed, and the address
inputsꢀonꢀA0-A11ꢀselectsꢀtheꢀrow.ꢀꢀꢀUntilꢀaꢀPRECHARGEꢀ
command is issued to the bank, the row remains open
for accesses.
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Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
Active
High-Z
Hꢀ
—ꢀ
IS42S16400J
IS45S16400J
TRUTH TABLE – COMMANDS AND DQM OPERATION(1)
FUNCTION
CS
Hꢀ
Lꢀ
RAS CAS
WE DQM
ADDR
Xꢀ
DQs
COMMANDꢀINHIBITꢀ(NOP)ꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
X
X
NOꢀOPERATIONꢀ(NOP)ꢀ
Xꢀ
ACTIVEꢀ(Selectꢀbankꢀandꢀactivateꢀrow)(3)ꢀ
READꢀ(Selectꢀbank/column,ꢀstartꢀREADꢀburst)(4)
WRITEꢀ(Selectꢀbank/column,ꢀstartꢀWRITEꢀburst)(4)ꢀ Lꢀ
BURSTꢀTERMINATEꢀ Lꢀ
PRECHARGEꢀ(Deactivateꢀrowꢀinꢀbankꢀorꢀbanks)(5)ꢀ Lꢀ
Lꢀ
Xꢀ
Bank/Rowꢀ
Bank/Colꢀ
Bank/Colꢀ
Xꢀ
X
ꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
L/H(8)
L/H(8)
Xꢀ
X
Lꢀ
Valid
Active
X
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Codeꢀ
Xꢀ
AUTOꢀREFRESHꢀorꢀSELFꢀREFRESH(6,7)
ꢀ
Lꢀ
Lꢀ
Hꢀ
Xꢀ
X
(Enter self refresh mode)
LOADꢀMODEꢀREGISTER(2)ꢀ
WriteꢀEnable/OutputꢀEnable(8)ꢀ
WriteꢀInhibit/OutputꢀHigh-Z(8)ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Lꢀ
Op-Codeꢀ
—ꢀ
X
NOTES:
1.ꢀ CKEꢀisꢀHIGHꢀforꢀallꢀcommandsꢀexceptꢀSELFꢀREFRESH.
2. A0-A11 define the op-code written to the mode register.
3.ꢀ A0-A11ꢀprovideꢀrowꢀaddress,ꢀandꢀBA0,ꢀBA1ꢀdetermineꢀwhichꢀbankꢀisꢀmadeꢀactive.
4.ꢀ A0-A7ꢀ(x16)ꢀprovideꢀcolumnꢀaddress;ꢀA10ꢀHIGHꢀenablesꢀtheꢀautoꢀprechargeꢀfeatureꢀ(nonpersistent),ꢀwhileꢀA10ꢀLOWꢀdisablesꢀ
autoꢀprecharge;ꢀBA0,ꢀBA1ꢀdetermineꢀwhichꢀbankꢀisꢀbeingꢀreadꢀfromꢀorꢀwrittenꢀto.
5.ꢀ A10ꢀLOW:ꢀBA0,ꢀBA1ꢀdetermineꢀtheꢀbankꢀbeingꢀprecharged.ꢀA10ꢀHIGH:ꢀAllꢀbanksꢀprechargedꢀandꢀBA0,ꢀBA1ꢀareꢀ“Don’tꢀCare.”
6.ꢀ AUTOꢀREFRESHꢀifꢀCKEꢀisꢀHIGH,ꢀSELFꢀREFRESHꢀifꢀCKEꢀisꢀLOW.
7.ꢀ Internalꢀrefreshꢀcounterꢀcontrolsꢀrowꢀaddressing;ꢀallꢀinputsꢀandꢀI/Osꢀareꢀ“Don’tꢀCare”ꢀexceptꢀforꢀCKE.
8.ꢀ ActivatesꢀorꢀdeactivatesꢀtheꢀDQsꢀduringꢀWRITEsꢀ(zero-clockꢀdelay)ꢀandꢀREADsꢀ(two-clockꢀdelay).
Integrated Silicon Solution, Inc. — www.issi.comꢀ
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TRUTH TABLE – CKE (1-4)
CURRENT STATE
COMMANDn
ACTIONn
CKEn-1
CKEn
Power-Downꢀ
Xꢀ
MaintainꢀPower-Downꢀ
MaintainꢀSelfꢀRefreshꢀ
MaintainꢀClockꢀSuspendꢀ
ExitꢀPower-Downꢀ
ExitꢀSelfꢀRefreshꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
L
L
SelfꢀRefreshꢀ
Xꢀ
ClockꢀSuspendꢀ
Power-Down(5)
SelfꢀRefresh(6)ꢀ
Clock Suspend(7)ꢀ
AllꢀBanksꢀIdleꢀ
AllꢀBanksꢀIdleꢀ
ReadingꢀorꢀWritingꢀ
Xꢀ
L
COMMANDꢀINHIBITꢀorꢀNOPꢀ
COMMANDꢀINHIBITꢀorꢀNOPꢀ
Xꢀ
H
H
H
L
ExitꢀClockꢀSuspendꢀ
Power-DownꢀEntryꢀ
SelfꢀRefreshꢀEntryꢀ
ClockꢀSuspendꢀEntryꢀ
COMMANDꢀINHIBITꢀorꢀNOPꢀ
AUTOꢀREFRESHꢀ
VALIDꢀ
L
L
See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n
H
H
NOTES:
1.ꢀ CKEnꢀisꢀtheꢀlogicꢀstateꢀofꢀCKEꢀatꢀclockꢀedgeꢀn;ꢀCKEn-1 wasꢀtheꢀstateꢀofꢀCKEꢀatꢀtheꢀpreviousꢀclockꢀedge.ꢀ
2.ꢀ CurrentꢀstateꢀisꢀtheꢀstateꢀofꢀtheꢀSDRAMꢀimmediatelyꢀpriorꢀtoꢀclockꢀedgeꢀn.
3.ꢀ COMMANDnꢀisꢀtheꢀcommandꢀregisteredꢀatꢀclockꢀedgeꢀn,ꢀandꢀACTONnꢀisꢀaꢀresultꢀofꢀCOMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n+1 (provided that tcks is
met)
.
6. Exiting self refresh at clock edge n will put the device in all banks idle state once txsrꢀisꢀmet.ꢀCOMMANDꢀINHIBITꢀorꢀNOPꢀ
commands should be issued on clock edges occurring during the txsrꢀperiod.ꢀAꢀminimumꢀofꢀtwoꢀNOPꢀcommandsꢀmustꢀbeꢀsentꢀ
during txsr period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge
n+1.
TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n (1-6)
CURRENTꢀSTATE
ꢀ
COMMANDꢀ(ACTION)
CS RAS CAS WE
Anyꢀ
COMMANDꢀINHIBITꢀ(NOP/Continueꢀpreviousꢀoperation)
ꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
X
H
H
H
L
ꢀ
NOꢀOPERATIONꢀ(NOP/Continueꢀpreviousꢀoperation)
ACTIVEꢀ(Selectꢀandꢀactivateꢀrow)ꢀ
ꢀAUTOꢀREFRESH(7)ꢀ
ꢀ
Idleꢀ
ꢀ
Lꢀ
ꢀ
LOADꢀMODEꢀREGISTER(7)
PRECHARGE(11)
Lꢀ
Lꢀ
ꢀ
Lꢀ
Hꢀ
Lꢀ
L
RowꢀActiveꢀ
ꢀ
READꢀ(SelectꢀcolumnꢀandꢀstartꢀREADꢀburst)(10)
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀWRITEꢀburst)(10)
PRECHARGEꢀ(Deactivateꢀrowꢀinꢀbankꢀorꢀbanks)(8)
READꢀ(SelectꢀcolumnꢀandꢀstartꢀnewꢀREADꢀburst)(10)
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀWRITEꢀburst)(10)
PRECHARGEꢀ(TruncateꢀREADꢀburst,ꢀstartꢀPRECHARGE)(8)
BURSTꢀTERMINATE(9)ꢀ
READꢀ(SelectꢀcolumnꢀandꢀstartꢀREADꢀburst)(10)
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀnewꢀWRITEꢀburst)(10)
PRECHARGEꢀ(TruncateꢀWRITEꢀburst,ꢀstartꢀPRECHARGE)(8)
BURSTꢀTERMINATE(9)ꢀ
Hꢀ
Hꢀ
Lꢀ
H
L
Lꢀ
ꢀ
Hꢀ
Lꢀ
L
Readꢀ
Hꢀ
Hꢀ
Lꢀ
H
L
(Autoꢀ
Lꢀ
Prechargeꢀ
Disabled)ꢀ
Writeꢀ
Hꢀ
Hꢀ
Lꢀ
L
Hꢀ
Hꢀ
Hꢀ
Lꢀ
L
H
L
(Autoꢀ
Lꢀ
Prechargeꢀ
Hꢀ
Hꢀ
L
Disabled)ꢀ
Hꢀ
L
NOTE:
ꢀ 1.ꢀThisꢀtableꢀappliesꢀwhenꢀCKEꢀn-1ꢀwasꢀHIGHꢀandꢀCKEꢀnꢀisꢀHIGHꢀ(seeꢀTruthꢀTableꢀ-ꢀCKE)ꢀandꢀafterꢀtxsr has been met (if the
previous state was SELFꢀREFRESH).
ꢀ 2.ꢀThisꢀtableꢀisꢀbank-specific,ꢀexceptꢀwhereꢀnoted;ꢀi.e.,ꢀtheꢀcurrentꢀstateꢀisꢀforꢀaꢀspecificꢀbankꢀandꢀtheꢀcommandsꢀshownꢀareꢀthoseꢀ
allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
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Rev. F
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IS42S16400J
IS45S16400J
3. Current state definitions:
ꢀ
ꢀ
Idle:ꢀTheꢀbankꢀhasꢀbeenꢀprecharged,ꢀandꢀtrp has been met.
RowꢀActive:ꢀAꢀrowꢀinꢀtheꢀbankꢀhasꢀbeenꢀactivated,ꢀandꢀtrcdꢀhasꢀbeenꢀmet.ꢀNoꢀdataꢀbursts/accessesꢀandꢀnoꢀregisterꢀ
accesses are in progress.
ꢀ
ꢀ
Read:ꢀAꢀREADꢀburstꢀhasꢀbeenꢀinitiated,ꢀwithꢀautoꢀprechargeꢀdisabled,ꢀandꢀhasꢀnotꢀyetꢀterminatedꢀorꢀbeenꢀtermi-
nated.
Write:ꢀAꢀWRITEꢀburstꢀhasꢀbeenꢀinitiated,ꢀwithꢀautoꢀprechargeꢀdisabled,ꢀandꢀhasꢀnotꢀyetꢀterminatedꢀorꢀbeenꢀtermi-
nated.
ꢀ 4.ꢀTheꢀfollowingꢀstatesꢀmustꢀnotꢀbeꢀinterruptedꢀbyꢀaꢀcommandꢀissuedꢀtoꢀtheꢀsameꢀbank.ꢀCOMMANDꢀINHIBITꢀorꢀNOPꢀcommands,ꢀ
or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable com-
mandsꢀtoꢀtheꢀotherꢀbankꢀareꢀdeterminedꢀbyꢀitsꢀcurrentꢀstateꢀandꢀCURRENTꢀSTATEꢀBANKꢀnꢀtruthꢀtables.
ꢀ
ꢀ
ꢀ
Precharging:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀPRECHARGEꢀcommandꢀandꢀendsꢀwhenꢀtrpꢀisꢀmet.ꢀOnceꢀtrp is met, the bank
will be in the idle state.
RowꢀActivating:ꢀStartsꢀwithꢀregistrationꢀofꢀanꢀACTIVEꢀcommandꢀandꢀendsꢀwhenꢀtrcdꢀisꢀmet.ꢀOnceꢀtrcd is met, the bank will
be in the row active state.
Readꢀw/Auto
Precharge Enabled:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀREADꢀcommandꢀwithꢀautoꢀprechargeꢀenabledꢀandꢀendsꢀwhenꢀtrp has been
met.ꢀOnceꢀtrp is met, the bank will be in the idle state.
ꢀ
Writeꢀw/Auto
Precharge Enabled:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀWRITEꢀcommandꢀwithꢀautoꢀprechargeꢀenabledꢀandꢀendsꢀwhenꢀtrp has been
met.ꢀOnceꢀtrp is met, the bank will be in the idle state.
ꢀ 5.ꢀTheꢀfollowingꢀstatesꢀmustꢀnotꢀbeꢀinterruptedꢀbyꢀanyꢀexecutableꢀcommand;ꢀCOMMANDꢀINHIBITꢀorꢀNOPꢀcommandsꢀmustꢀbeꢀ
applied on each positive clock edge during these states.
ꢀ
Refreshing:ꢀStartsꢀwithꢀregistrationꢀofꢀanꢀAUTOꢀREFRESHꢀcommandꢀandꢀendsꢀwhenꢀtrcꢀisꢀmet.ꢀOnceꢀtrc is met, the
SDRAMꢀwillꢀbeꢀinꢀtheꢀallꢀbanksꢀidleꢀstate.
Accessing Mode
ꢀ
Register:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀLOADꢀMODEꢀREGISTERꢀcommandꢀandꢀendsꢀwhenꢀtmrdꢀhasꢀbeenꢀmet.ꢀOnceꢀ
tmrdꢀisꢀmet,ꢀtheꢀSDRAMꢀwillꢀbeꢀinꢀtheꢀallꢀbanksꢀidleꢀstate.
Precharging All:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀPRECHARGEꢀALLꢀcommandꢀandꢀendsꢀwhenꢀtrpꢀisꢀmet.ꢀOnceꢀtrp is met, all
banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
ꢀ 7.ꢀNotꢀbank-specific;ꢀrequiresꢀthatꢀallꢀbanksꢀareꢀidle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
ꢀ 9.ꢀNotꢀbank-specific;ꢀBURSTꢀTERMINATEꢀaffectsꢀtheꢀmostꢀrecentꢀREADꢀorꢀWRITEꢀburst,ꢀregardlessꢀofꢀbank.
ꢀ10.ꢀREADsꢀorꢀWRITEsꢀlistedꢀinꢀtheꢀCommandꢀ(Action)ꢀcolumnꢀincludeꢀREADsꢀorꢀWRITEsꢀwithꢀautoꢀprechargeꢀenabledꢀandꢀ
READsꢀorꢀWRITEsꢀwithꢀautoꢀprechargeꢀdisabled.
ꢀ11.ꢀDoesꢀnotꢀaffectꢀtheꢀstateꢀofꢀtheꢀbankꢀandꢀactsꢀasꢀaꢀNOPꢀtoꢀthatꢀbank.
Integrated Silicon Solution, Inc. — www.issi.com
11
Rev. F
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IS42S16400J
IS45S16400J
(1-6)
TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK m
CURRENTꢀSTATE
ꢀ
COMMANDꢀ(ACTION)
CS RAS CAS WE
Anyꢀ
COMMANDꢀINHIBITꢀ(NOP/Continueꢀpreviousꢀoperation)ꢀ
NOꢀOPERATIONꢀ(NOP/Continueꢀpreviousꢀoperation)ꢀ
AnyꢀCommandꢀOtherwiseꢀAllowedꢀtoꢀBankꢀm
ACTIVEꢀ(Selectꢀandꢀactivateꢀrow)ꢀ
READꢀ(SelectꢀcolumnꢀandꢀstartꢀREADꢀburst)(7)ꢀ
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀWRITEꢀburst)(7)ꢀ
PRECHARGEꢀ
Hꢀ
Lꢀ
Xꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Lꢀ
X
H
X
H
H
L
ꢀ
Idleꢀ
Rowꢀ
Activating,ꢀ
Active,ꢀorꢀ
Prechargingꢀ
Readꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
L
ACTIVEꢀ(Selectꢀandꢀactivateꢀrow)ꢀ
Lꢀ
H
H
L
(Autoꢀ
READꢀ(SelectꢀcolumnꢀandꢀstartꢀnewꢀREADꢀburst)(7,10)
ꢀ
Hꢀ
Hꢀ
Lꢀ
Prechargeꢀ
Disabled)ꢀ
Writeꢀ
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀWRITEꢀburst)(7,11)
PRECHARGE(9)ꢀ
ꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
L
ACTIVEꢀ(Selectꢀandꢀactivateꢀrow)ꢀ
Lꢀ
H
H
L
(Autoꢀ
READꢀ(SelectꢀcolumnꢀandꢀstartꢀREADꢀburst)(7,12)
ꢀ
Hꢀ
Hꢀ
Lꢀ
Prechargeꢀ
Disabled)ꢀ
Readꢀ
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀnewꢀWRITEꢀburst)(7,13)
PRECHARGE(9)ꢀ
ꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
L
ACTIVEꢀ(Selectꢀandꢀactivateꢀrow)ꢀ
Lꢀ
H
H
L
(WithꢀAutoꢀ
Precharge)ꢀ
ꢀ
READꢀ(SelectꢀcolumnꢀandꢀstartꢀnewꢀREADꢀburst)(7,8,14)
ꢀ
Hꢀ
Hꢀ
Lꢀ
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀWRITEꢀburst)(7,8,15)
PRECHARGE(9)ꢀ
ꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
L
Writeꢀ
ACTIVEꢀ(Selectꢀandꢀactivateꢀrow)ꢀ
Lꢀ
H
H
L
(WithꢀAutoꢀ
Precharge)ꢀ
ꢀ
READꢀ(SelectꢀcolumnꢀandꢀstartꢀREADꢀburst)(7,8,16)
ꢀ
Hꢀ
Hꢀ
Lꢀ
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀnewꢀWRITEꢀburst)(7,8,17)
PRECHARGE(9)ꢀ
ꢀ
Lꢀ
Hꢀ
L
NOTE:ꢀ
ꢀ 1.ꢀThisꢀtableꢀappliesꢀwhenꢀCKEꢀn-1ꢀwasꢀHIGHꢀandꢀCKEꢀnꢀisꢀHIGHꢀ(TruthꢀTableꢀ-ꢀCKE)ꢀandꢀafterꢀtxsr has been met (if the previ-
ous state was self refresh).
ꢀ 2.ꢀThisꢀtableꢀdescribesꢀalternateꢀbankꢀoperation,ꢀexceptꢀwhereꢀnoted;ꢀi.e.,ꢀtheꢀcurrentꢀstateꢀisꢀforꢀbankꢀn and the commands
shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Excep-
tions are covered in the notes below.
3. Current state definitions:
ꢀ
ꢀ
Idle:ꢀTheꢀbankꢀhasꢀbeenꢀprecharged,ꢀandꢀtrp has been met.
RowꢀActive:ꢀAꢀrowꢀinꢀtheꢀbankꢀhasꢀbeenꢀactivated,ꢀandꢀtrcdꢀhasꢀbeenꢀmet.ꢀNoꢀdataꢀbursts/accessesꢀandꢀnoꢀregisterꢀ
accesses are in progress.
ꢀ
ꢀ
ꢀ
Read:ꢀAꢀREADꢀburstꢀhasꢀbeenꢀinitiated,ꢀwithꢀautoꢀprechargeꢀdisabled,ꢀandꢀhasꢀnotꢀyetꢀterminatedꢀorꢀbeenꢀtermi-
nated.
Write:ꢀAꢀWRITEꢀburstꢀhasꢀbeenꢀinitiated,ꢀwithꢀautoꢀprechargeꢀdisabled,ꢀandꢀhasꢀnotꢀyetꢀterminatedꢀorꢀbeenꢀtermi-
nated.
Readꢀw/Auto
Precharge Enabled:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀREADꢀcommandꢀwithꢀautoꢀprechargeꢀenabled,ꢀandꢀendsꢀwhenꢀtrp has been
met.ꢀOnceꢀtrp is met, the bank will be in the idle state.
ꢀ
Writeꢀw/Auto
Precharge Enabled:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀWRITEꢀcommandꢀwithꢀautoꢀprechargeꢀenabled,ꢀandꢀendsꢀwhenꢀtrp has been
met.ꢀOnceꢀtrp is met, the bank will be in the idle state.
ꢀ 4.ꢀAUTOꢀREFRESH,ꢀSELFꢀREFRESHꢀandꢀLOADꢀMODEꢀREGISTERꢀcommandsꢀmayꢀonlyꢀbeꢀissuedꢀwhenꢀallꢀbanksꢀareꢀidle.
ꢀ 5.ꢀAꢀBURSTꢀTERMINATEꢀcommandꢀcannotꢀbeꢀissuedꢀtoꢀanotherꢀbank;ꢀitꢀappliesꢀtoꢀtheꢀbankꢀrepresentedꢀbyꢀtheꢀcurrentꢀstateꢀ
only.
6. All states and sequences not shown are illegal or reserved.
ꢀ 7.ꢀREADsꢀorꢀWRITEsꢀtoꢀbankꢀmꢀlistedꢀinꢀtheꢀCommandꢀ(Action)ꢀcolumnꢀincludeꢀREADsꢀorꢀWRITEsꢀwithꢀautoꢀprechargeꢀenabledꢀ
andꢀREADsꢀorꢀWRITEsꢀwithꢀautoꢀprechargeꢀdisabled.
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
ꢀ 8.ꢀCONCURRENTꢀAUTOꢀPRECHARGE:ꢀBankꢀnꢀwillꢀinitiateꢀtheꢀAUTOꢀPRECHARGEꢀcommandꢀwhenꢀitsꢀburstꢀhasꢀbeenꢀinter-
ruptedꢀbyꢀbankꢀm’sꢀburst.
ꢀ 9.ꢀBurstꢀinꢀbankꢀnꢀcontinuesꢀasꢀinitiated.
ꢀ10.ꢀForꢀaꢀREADꢀwithoutꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ
theꢀREADꢀonꢀbankꢀn,ꢀCASꢀlatencyꢀlaterꢀ(ConsecutiveꢀREADꢀBursts).
ꢀ11.ꢀForꢀaꢀREADꢀwithoutꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinter-
ruptꢀtheꢀREADꢀonꢀbankꢀnꢀwhenꢀregisteredꢀ(READꢀtoꢀWRITE).ꢀDQMꢀshouldꢀbeꢀusedꢀoneꢀclockꢀpriorꢀtoꢀtheꢀWRITEꢀcommandꢀtoꢀ
prevent bus contention.
ꢀ12.ꢀForꢀaꢀWRITEꢀwithoutꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ
theꢀWRITEꢀonꢀbankꢀnꢀwhenꢀregisteredꢀ(WRITEꢀtoꢀREAD),ꢀwithꢀtheꢀdata-outꢀappearingꢀCASꢀlatencyꢀlater.ꢀTheꢀlastꢀvalidꢀWRITEꢀ
toꢀbankꢀnꢀwillꢀbeꢀdata-inꢀregisteredꢀoneꢀclockꢀpriorꢀtoꢀtheꢀREADꢀtoꢀbankꢀm.
ꢀ13.ꢀForꢀaꢀWRITEꢀwithoutꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinter-
ruptꢀtheꢀWRITEꢀonꢀbankꢀnꢀwhenꢀregisteredꢀ(WRITEꢀtoꢀWRITE).ꢀTheꢀlastꢀvalidꢀWRITEꢀtoꢀbankꢀnꢀwillꢀbeꢀdata-inꢀregisteredꢀoneꢀ
clockꢀpriorꢀtoꢀtheꢀREADꢀtoꢀbankꢀm.
ꢀ14.ꢀForꢀaꢀREADꢀwithꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀtheꢀ
READꢀonꢀbankꢀn,ꢀCASꢀlatencyꢀlater.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀregisteredꢀ(FigꢀCAPꢀ
1).
ꢀ15.ꢀForꢀaꢀREADꢀwithꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ
theꢀREADꢀonꢀbankꢀnꢀwhenꢀregistered.ꢀDQMꢀshouldꢀbeꢀusedꢀtwoꢀclocksꢀpriorꢀtoꢀtheꢀWRITEꢀcommandꢀtoꢀpreventꢀbusꢀcontention.ꢀ
TheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀwhenꢀtheꢀWRITEꢀtoꢀbankꢀmꢀisꢀregisteredꢀ(FigꢀCAPꢀ2).
ꢀ16.ꢀForꢀaꢀWRITEꢀwithꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ
theꢀWRITEꢀonꢀbankꢀnꢀwhenꢀregistered,ꢀwithꢀtheꢀdata-outꢀappearingꢀCASꢀlatencyꢀlater.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀ
after tWR is met, where twrꢀbeginsꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀregistered.ꢀTheꢀlastꢀvalidꢀWRITEꢀtoꢀbankꢀnꢀwillꢀbeꢀdata-inꢀregis-
teredꢀoneꢀclockꢀpriorꢀtoꢀtheꢀREADꢀtoꢀbankꢀmꢀ(FigꢀCAPꢀ3).
ꢀ17.ꢀForꢀaꢀWRITEꢀwithꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ
theꢀWRITEꢀonꢀbankꢀnꢀwhenꢀregistered.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀafterꢀtwrꢀisꢀmet,ꢀwhereꢀtꢀWRꢀbeginsꢀwhenꢀtheꢀ
WRITEꢀtoꢀbankꢀmꢀisꢀregistered.ꢀTheꢀlastꢀvalidꢀWRITEꢀtoꢀbankꢀnꢀwillꢀbeꢀdataꢀregisteredꢀoneꢀclockꢀpriorꢀtoꢀtheꢀWRITEꢀtoꢀbankꢀmꢀ
(FigꢀCAPꢀ4).
Integrated Silicon Solution, Inc. — www.issi.com
13
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vdd maxꢀ
Vddq max
ViNꢀ
Parameters
Rating
–1.0ꢀtoꢀ+4.6ꢀ
–1.0ꢀtoꢀ+4.6ꢀ
–1.0ꢀtoꢀVddq +ꢀ0.5ꢀ
–1.0ꢀtoꢀVddq +ꢀ0.5ꢀ
1ꢀ
Unit
V
V
V
V
ꢀ
ꢀ
ꢀ
ꢀ
MaximumꢀSupplyꢀVoltageꢀ
MaximumꢀSupplyꢀVoltageꢀforꢀOutputꢀBufferꢀ
InputꢀVoltageꢀ
OutputꢀVoltageꢀ
AllowableꢀPowerꢀDissipationꢀ
output Shorted Current
Voutꢀ
Pd max
Ics
W
mA
50
ꢀ
ꢀ
Topr
operatingꢀTemperatureꢀ
Com.
Ind.
A1
0 to +70
-40 to +85
-40 to +85
-40 to +105
°C
°C
°C
°C
A2
Tstgꢀ
StorageꢀTemperatureꢀ
ꢀ
–65ꢀtoꢀ+150ꢀ
°C
DC RECOMMENDED OPERATING CONDITIONS(2)
(AtꢀTaꢀ=ꢀ0ꢀtoꢀ+70°Cꢀforꢀcommercialꢀgrade.ꢀTaꢀ=ꢀ-40ꢀtoꢀ+85°CꢀforꢀindustrialꢀandꢀA1ꢀgrade.ꢀꢀTaꢀ=ꢀ-40ꢀtoꢀ+105°CꢀforꢀA2ꢀgrade)
Symbol
Vdd, Vddqꢀ
Vihꢀ
Parameter
Min.
3.0ꢀ
2.0ꢀ
-0.3ꢀ
Typ.
3.3ꢀ
—ꢀ
Max.
3.6ꢀ
Vdd +ꢀ0.3ꢀ
+0.8ꢀ
Unit
V
V
ꢀ
ꢀ
ꢀ
SupplyꢀVoltageꢀ
InputꢀHighꢀVoltage(3)ꢀ
InputꢀLowꢀVoltage(4)ꢀ
Vilꢀ
—ꢀ
V
CAPACITANCE CHARACTERISTICS(1,2) (AtꢀTaꢀ=ꢀ0ꢀtoꢀ+25°C,ꢀVddꢀ=ꢀVddqꢀ=ꢀ3.3ꢀ±ꢀ0.3V,ꢀfꢀ=ꢀ1ꢀMHz)
Symbol
CiNꢀ
Parameter
Typ.
—ꢀ
—ꢀ
Max.
3.8ꢀ
3.5ꢀ
6.5ꢀ
Unit
pF
pF
InputꢀCapacitance:ꢀAddressꢀandꢀControlꢀ
InputꢀCapacitance:ꢀ(CLK)ꢀ
DataꢀInput/OutputꢀCapacitance:ꢀI/O0-I/O15ꢀ
Cclkꢀ
CI/Oꢀ
ꢀ
—ꢀ
pF
Notes:
1.ꢀ StressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.ꢀThisꢀisꢀaꢀ
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2.ꢀ AllꢀvoltagesꢀareꢀreferencedꢀtoꢀGND.
3.ꢀꢀVih(max)ꢀ=ꢀVddqꢀ+ꢀ1.2Vꢀwithꢀaꢀpulseꢀwidthꢀ<ꢀ3ns.
4.ꢀꢀVil(min)ꢀ=ꢀGNDꢀ-ꢀ1.2Vꢀwithꢀaꢀpulseꢀwidthꢀ<ꢀ3ns.
THERMAL RESISTANCE
Package
Substrate
Theta-ja
Theta-ja
Theta-ja
Theta-jc
Units
(Airflow = 0m/s) (Airflow = 1m/s) (Airflow = 2m/s)
Alloy42 TSꢂP2(54)
Copper TSꢂP2(54)
BꢀA(54)
4-layer
4-layer
4-layer
4-layer
88.0
51.7
50.5
48.3
81
77.4
47.7
41.7
41
16.1
11.9
11.3
7.5
C/W
C/W
C/W
C/W
49.0
44.6
42.3
BꢀA(60)
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
DC ELECTRICAL CHARACTERISTICS 1 (RecommendedꢀOperationꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
Symbol Parameter
Test Condition
-5
-6
-7
Unit
i
dd1 (1)
ꢀ
OperatingꢀCurrentꢀ
Oneꢀbankꢀactive,ꢀCLꢀ=ꢀ3,ꢀBLꢀ=ꢀ1,ꢀꢀꢀꢀꢀꢀꢀꢀꢀ
90ꢀ ꢀ 80ꢀ
70ꢀ
ꢀ
ꢀ
mA
tclkꢀ=ꢀtclk (min), trcꢀ=ꢀtrc (min)
i
i
dd2p
ꢀ
PrechargeꢀStandbyꢀCurrentꢀ CKEꢀ≤ Vil
(In Power-Down Mode) CS ≥ Vddꢀ-ꢀ0.2V
PrechargeꢀStandbyꢀCurrentꢀ CKEꢀ≤ Vil max),ꢀCLKꢀ≤ Vil
CS ≥ Vddꢀ-ꢀ0.2V
(max), tckꢀ=ꢀ15nsꢀ
ꢀ
2ꢀ
ꢀ
2ꢀ
2ꢀ
mA
dd2ps
ꢀ
(
(
max
)
2
2
2
mA
with clock stop
(In Power-Down Mode)
(2)
i
dd2N
Precharge Standby Current
CS ≥ Vddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vih
ckꢀ=ꢀ15ns
CS ≥ Vddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vih
(
miN
)
)
20
10
20
10
20
10
mA
mA
(InꢀNonꢀPower-DownꢀMode)
t
I
dd2Ns
Precharge Standby Current
with clock stop
(miN
(InꢀNonꢀPower-DownꢀMode) All inputs stable
(2)
i
i
dd3p
ꢀ
ActiveꢀStandbyꢀCurrentꢀ
CKEꢀ≤ Vil
ckꢀ=ꢀ15ns
CKEꢀ≤ Vil
(
max), CS ≥ Vddꢀ-ꢀ0.2Vꢀ
6ꢀ
ꢀ
6ꢀ
6ꢀ
ꢀ
mA
(In Power-Down Mode)
t
dd3ps
ꢀ
ActiveꢀStandbyꢀCurrentꢀ
with clock stop
(max),ꢀCLKꢀ≤ Vil
(max),
6
6
6
mA
CS ≥ Vddꢀ-ꢀ0.2V
(In Power-Down Mode)
(2)
i
dd3N
Active Standby Current
CS ≥ Vddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vih
ckꢀ=ꢀ15ns
(
(
miN
)
)
25
20
25
20
25
20
mA
mA
(InꢀNonꢀPower-DownꢀMode)
t
I
dd3Ns
Active Standby Current
with clock stop
CS ≥ Vddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vih
All inputs stable
miN
(InꢀNonꢀPower-DownꢀMode)ꢀꢀꢀꢀꢀ
OperatingꢀCurrentꢀ
i
dd4
ꢀ
Allꢀꢀbanksꢀactive,ꢀBLꢀ=ꢀ4,ꢀCLꢀ=ꢀ3,ꢀꢀꢀꢀꢀꢀꢀꢀꢀ
110ꢀ ꢀ 100ꢀ
110ꢀ ꢀ 100ꢀ
90ꢀ
ꢀ
ꢀ
mA
t
ckꢀ=ꢀtck (min)
i
i
dd5
dd6
ꢀ
ꢀ
Auto-RefreshꢀCurrentꢀ
Self-RefreshꢀCurrentꢀ
t
rcꢀ=ꢀtrc (min), tclkꢀ=ꢀtclkꢀ(min)ꢀꢀꢀꢀꢀꢀꢀꢀ
90ꢀ
mA
CKEꢀ≤ 0.2V
2
2
2
mA
Notes:
1. Idd (max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
DC ELECTRICAL CHARACTERISTICS 2 (RecommendedꢀOperationꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
Symbol Parameter
Test Condition
Min
Max
Unit
i
ꢀꢀ
i
il
ꢀ
InputꢀLeakageꢀCurrentꢀ
ꢀ
0Vꢀꢀ≤ꢀVinꢀ≤ꢀVdd, with pins other than
-5
5
µA
theꢀtestedꢀpinꢀatꢀ0Vꢀ
ꢀ
ol
oh
ol
ꢀ
OutputꢀLeakageꢀCurrentꢀ
OutputꢀHighꢀVoltageꢀLevelꢀ
OutputꢀLowꢀVoltageꢀLevelꢀ
Outputꢀisꢀdisabled,ꢀ0Vꢀꢀ≤ꢀVoutꢀ≤ꢀVdd
,
-5
2.4ꢀ
—
5
µA
V
V
ꢀ
I
ohꢀꢀ=ꢀꢀ-2mAꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
olꢀꢀ=ꢀꢀ2mAꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—
V
ꢀ
I
0.4
V
Integrated Silicon Solution, Inc. — www.issi.com
15
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
AC ELECTRICAL CHARACTERISTICS (1,2,3)
-5
-6
-7
Symbol Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Units
tck3ꢀ
tck2
ClockꢀCycleꢀTimeꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
5ꢀ
7.5ꢀ
—ꢀ
—ꢀ
6ꢀ
7.5ꢀ
—ꢀ
—ꢀ
7ꢀ
7.5ꢀ
—ꢀ
—ꢀ
ns
ns
tac3ꢀ
tac2
AccessꢀTimeꢀFromꢀCLK(4,6)
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
—ꢀ
—ꢀ
4.8ꢀ
5.4ꢀ
—ꢀ
—ꢀ
5.4ꢀ
5.4ꢀ
—ꢀ
—ꢀ
5.4ꢀ
5.4ꢀ
ns
ns
tchꢀ
tclꢀ
CLKꢀHIGHꢀLevelꢀWidthꢀ
CLKꢀLOWꢀLevelꢀWidthꢀ
OutputꢀDataꢀHoldꢀTime(6)
ꢀ
ꢀ
2ꢀ
2ꢀ
—ꢀ
—ꢀ
2ꢀ
2ꢀ
—ꢀ
—ꢀ
2.5ꢀ
2.5ꢀ
—ꢀ
—ꢀ
ns
ns
toh3ꢀ
toh2
CASꢀLatencyꢀ=ꢀ3ꢀ
CAS Latencyꢀ=ꢀ2ꢀ
2.5ꢀ
2.5ꢀ
—ꢀ
—ꢀ
2.5ꢀ
2.5ꢀ
—ꢀ
—ꢀ
2.7ꢀ
2.7ꢀ
—ꢀ
—ꢀ
ns
ns
tlzꢀ
OutputꢀLOWꢀImpedanceꢀTimeꢀ
OutputꢀHIGHꢀImpedanceꢀTime(5)
ꢀ
0ꢀ
—ꢀ
0ꢀ
—ꢀ
0ꢀ
—ꢀ
ns
thz3ꢀ
thz2
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
—ꢀ
—ꢀ
4.8ꢀ
5.4ꢀ
—ꢀ
—ꢀ
5.4ꢀ
5.4ꢀ
—ꢀ
—ꢀ
5.4ꢀ
5.4ꢀ
ns
ns
tdsꢀ
InputꢀDataꢀSetupꢀTimeꢀ
InputꢀDataꢀHoldꢀTimeꢀ
AddressꢀSetupꢀTimeꢀ
AddressꢀHoldꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
—ꢀ
—ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
—ꢀ
—ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
—ꢀ
—ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tdhꢀ
tasꢀ
—ꢀ
—ꢀ
—ꢀ
tahꢀ
—ꢀ
—ꢀ
—ꢀ
tcksꢀ
tckhꢀ
tckaꢀ
tcmsꢀ
tcmhꢀ
trcꢀ
CKEꢀSetupꢀTimeꢀ
—ꢀ
—ꢀ
—ꢀ
CKEꢀHoldꢀTimeꢀ
—ꢀ
—ꢀ
—ꢀ
CKEꢀtoꢀCLKꢀRecoveryꢀDelayꢀTimeꢀ
1CLK+3
1.5
—
1CLK+3
1.5
—
1CLK+3ꢀ
1.5
—
CommandꢀSetupꢀTimeꢀ(CS, RAS, CAS, WE, DQM)
CommandꢀHoldꢀTimeꢀ(CS, RAS, CAS, WE, DQM)
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ/ꢀACTꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACTꢀtoꢀPRE)ꢀ
—
—
—
0.8
—
0.8
—
0.8
—
ꢀ
ꢀ
ꢀ
55ꢀ
—ꢀ
60ꢀ
—ꢀ
63ꢀ
—ꢀ
trasꢀ
trpꢀ
40ꢀ
100,000
—ꢀ
42
100,000
—ꢀ
42
100,000
—ꢀ
CommandꢀPeriodꢀ(PREꢀtoꢀACT)ꢀ
15ꢀ
15ꢀ
15ꢀ
trcdꢀ
trrdꢀ
ActiveꢀCommandꢀToꢀReadꢀ/ꢀWriteꢀCommandꢀDelayꢀTimeꢀ
CommandꢀPeriodꢀ(ACTꢀ[0]ꢀtoꢀACT[1])ꢀ
15ꢀ
—ꢀ
15ꢀ
—ꢀ
15ꢀ
—ꢀ
ꢀ
10ꢀ
—ꢀ
12ꢀ
—ꢀ
14ꢀ
—ꢀ
tdpl orꢀ
twr
InputꢀDataꢀToꢀPrechargeꢀ
Command Delay time
CASꢀLatencyꢀ=ꢀ3ꢀ
2CLKꢀ
—ꢀ
2CLKꢀ
—ꢀ
2CLKꢀ
—ꢀ
CAS Latencyꢀ=ꢀ2ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
2CLKꢀ
—ꢀ
2CLKꢀ
—ꢀ
2CLKꢀ
—ꢀ
ns
tdalꢀ
InputꢀDataꢀToꢀActiveꢀ/ꢀRefreshꢀ
Command Delay time
2CLK+trp
—
2CLK+trp
—
2CLK+trp
—
ns
(During Auto-Precharge)
CAS Latencyꢀ=ꢀ2ꢀ
2CLK+trp
0.3ꢀ
—
2CLK+trp
0.3ꢀ
—
2CLK+trp
0.3ꢀ
—
ns
ns
ns
ttꢀ
TransitionꢀTimeꢀ
ꢀ
ꢀ
ꢀ
1.2ꢀ
—ꢀ
1.2ꢀ
—ꢀ
1.2ꢀ
—ꢀ
txsrꢀ
ExitꢀSelf-RefreshꢀtoꢀActiveꢀTimeꢀ
RefreshꢀCycleꢀTimeꢀ(4096)ꢀ
60ꢀ
66ꢀ
70ꢀ
trefꢀ
ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Ta ≤ 70oC Com., Ind., A1, A2
Ta ≤ 85oC Ind., A1, A2
Ta > 85oC A2
—
—
—
64
—
—
—
—
—
64
64
—
—
—
—
64
64
16
ms
ms
ms
Notes:
1.ꢀ Whenꢀpowerꢀisꢀfirstꢀapplied,ꢀmemoryꢀoperationꢀshouldꢀbeꢀstartedꢀ200ꢀµsꢀafterꢀVddꢀandꢀVddq reach their stipulated voltages. Also
note that the power-on sequence must be executed before starting memory operation.
2. measured with tt =ꢀ1ꢀns.
3.ꢀ Theꢀreferenceꢀlevelꢀisꢀ1.4ꢀVꢀwhenꢀmeasuringꢀinputꢀsignalꢀtiming.ꢀRiseꢀandꢀfallꢀtimesꢀareꢀmeasuredꢀbetweenꢀVih (min.)ꢀandꢀVil
(max.).
4.ꢀ Accessꢀtimeꢀisꢀmeasuredꢀatꢀ1.4Vꢀwithꢀtheꢀloadꢀshownꢀinꢀtheꢀfigureꢀbelow.
5.ꢀ Theꢀtimeꢀthz (max.)ꢀisꢀdefinedꢀasꢀtheꢀtimeꢀrequiredꢀforꢀtheꢀoutputꢀvoltageꢀtoꢀtransitionꢀbyꢀ±ꢀ200ꢀmVꢀfromꢀVoh (min.)ꢀorꢀVol (max.)
when the output is in the high impedance state.
6. If clock rising time is longer than 1ns, tt/2 - 0.5ns should be added to the parameter.
16
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER
-5
-6
-7
UNITS
tckꢀ
ꢀ
ClockꢀCycleꢀTimeꢀ
ꢀ
CL=3ꢀ
CL=2ꢀ
5ꢀ
7.5ꢀ
6ꢀ
7.5ꢀ
7ꢀ
7.5ꢀ
nsꢀꢀ
ns
ꢀ
ꢀ
ꢀ
Freq.ꢀ
ꢀ
OperatingꢀFrequencyꢀ
ꢀ
CL=3ꢀ
CL=2ꢀ
200ꢀ
133ꢀ
166ꢀ
133ꢀ
143ꢀ
133ꢀ
MHzꢀ
MHz
tccdꢀ
tckedꢀ
tpedꢀ
tdqd
READ/WRITEꢀcommandꢀtoꢀREAD/WRITEꢀcommandꢀ
CKEꢀtoꢀclockꢀdisableꢀorꢀpower-downꢀentryꢀmodeꢀ
CKEꢀtoꢀclockꢀenableꢀorꢀpower-downꢀexitꢀsetupꢀmodeꢀ
DQM to input data delay
1ꢀ
1ꢀ
1ꢀ
0
1ꢀ
1ꢀ
1ꢀ
0
1ꢀ
1ꢀ
1ꢀ
0
cycle
cycle
cycle
cycle
cycle
cycle
cycle
tdqmꢀ
tdqzꢀ
tdwdꢀ
DQMꢀtoꢀdataꢀmaskꢀduringꢀWRITEsꢀ
ꢀ
ꢀ
ꢀ
0ꢀ
2ꢀ
0ꢀ
0ꢀ
2ꢀ
0ꢀ
0ꢀ
2ꢀ
0ꢀ
DQMꢀtoꢀdataꢀhigh-impedanceꢀduringꢀREADsꢀ
WRITEꢀcommandꢀtoꢀinputꢀdataꢀdelayꢀ
tdalꢀ
ꢀ
Data-inꢀtoꢀACTIVEꢀcommandꢀ
ꢀ
CL=3ꢀ
CL=2ꢀ
5ꢀ
4ꢀ
5ꢀ
4ꢀ
5ꢀ
4ꢀ
cycleꢀ
cycle
ꢀ
tdplꢀ
tbdlꢀ
tcdlꢀ
trdlꢀ
Data-inꢀtoꢀPRECHARGEꢀcommandꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
2ꢀ
1ꢀ
1ꢀ
2ꢀ
2ꢀ
2ꢀ
1ꢀ
1ꢀ
2ꢀ
2ꢀ
2ꢀ
1ꢀ
1ꢀ
2ꢀ
2ꢀ
cycle
cycle
cycle
cycle
cycle
Lastꢀdata-inꢀtoꢀburstꢀSTOPꢀcommandꢀ
Lastꢀdata-inꢀtoꢀnewꢀREAD/WRITEꢀcommandꢀ
Lastꢀdata-inꢀtoꢀPRECHARGEꢀcommandꢀ
tmrdꢀ
ꢀ
LOADꢀMODEꢀREGISTERꢀcommandꢀ
toꢀACTIVEꢀorꢀREFRESHꢀcommand
ꢀ
ꢀ
trohꢀ
ꢀ
Data-outꢀtoꢀhigh-impedanceꢀfromꢀ
PRECHARGEꢀcommandꢀ
CL=3ꢀ
CL=2ꢀ
3ꢀ
2ꢀ
3ꢀ
2ꢀ
3ꢀ
2ꢀ
cycle
cycle
AC TEST CONDITIONS (Input/OutputꢀReferenceꢀLevel:ꢀ1.4V)
Input Load
Output Load
tCK
t
CH
t
CL
3.0V
50 Ω
1.4V
0V
CLK
I/O
+1.4V
t
CMS
tCMH
50 pF
3.0V
1.4V
INPUT
0V
tAC
t
OH
OUTPUT
1.4V
1.4V
Integrated Silicon Solution, Inc. — www.issi.com
17
Rev. F
12/17/2013
TIVEꢀcommandꢀwhichꢀisꢀthenꢀfollowedꢀbyꢀaꢀREADꢀorWRITEꢀ
IS42S16400J
IS45S16400J
FUNCTIONAL DESCRIPTION
Initialization
Theꢀ64MbꢀSDRAMsꢀ(1ꢀMegꢀxꢀ16ꢀxꢀ4ꢀbanks)ꢀareꢀquad-bankꢀ
DRAMsꢀwhichꢀoperateꢀatꢀ3.3Vꢀandꢀincludeꢀaꢀsynchronousꢀ
interface (all signals are registered on the positive edge of
theꢀclockꢀsignal,ꢀCLK).ꢀEachꢀofꢀtheꢀ16,777,216-bitꢀbanksꢀisꢀ
organizedꢀasꢀ4,096ꢀrowsꢀbyꢀ256ꢀcolumnsꢀbyꢀ16ꢀbits.
SDRAMsꢀ mustꢀ beꢀ poweredꢀ upꢀ andꢀ initializedꢀ inꢀ aꢀ
predefined manner.
Theꢀ64MbꢀSDRAMꢀisꢀinitializedꢀafterꢀtheꢀpowerꢀisꢀappliedꢀ
toꢀVddꢀandꢀVddq (simultaneously), and the clock is stable
withꢀDQMꢀHighꢀandꢀCKEꢀHigh.ꢀ
ReadꢀandꢀwriteꢀaccessesꢀtoꢀtheꢀSDRAMꢀareꢀburstꢀoriented;ꢀ
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
Aꢀ100µsꢀdelayꢀisꢀrequiredꢀpriorꢀtoꢀissuingꢀanyꢀcommandꢀ
other than a COMMANDꢀINHIBIT or a NOP.ꢀTheꢀCOMMANDꢀ
INHIBITꢀorꢀNOPꢀmayꢀbeꢀappliedꢀduringꢀtheꢀ100µsꢀperiodꢀandꢀ
continue should at least through the end of the period.
WithꢀatꢀleastꢀoneꢀCOMMANDꢀINHIBITꢀorꢀNOPꢀcommandꢀ
havingꢀbeenꢀapplied,ꢀaꢀPRECHARGEꢀcommandꢀshouldꢀ
beꢀappliedꢀonceꢀtheꢀ100µsꢀdelayꢀhasꢀbeenꢀsatisfied.ꢀꢀAllꢀ
banksꢀmustꢀbeꢀprecharged.ꢀꢀThisꢀwillꢀleaveꢀallꢀbanksꢀinꢀ
an idle state, afterꢀwhichꢀatꢀleastꢀtwoꢀAUTOꢀREFRESH cycles
must be performed. After the AUTOꢀREFRESH cycles are
complete,ꢀ theꢀ SDRAMꢀ isꢀ thenꢀ readyꢀ forꢀ modeꢀ registerꢀ
programming.
command.ꢀTheꢀaddressꢀbitsꢀregisteredꢀcoincidentꢀwithꢀtheꢀ
ACTIVEꢀcommandꢀareꢀusedꢀtoꢀselectꢀtheꢀbankꢀandꢀrowꢀtoꢀ
be accessed (BA0ꢀandꢀBA1ꢀselectꢀtheꢀbank,ꢀA0-A11ꢀselectꢀtheꢀ
row).Theꢀaddressꢀbitsꢀ(A0-A7)registeredcoincidentwiththe
READꢀorꢀWRITEꢀcommandꢀareꢀusedꢀtoꢀselectꢀtheꢀstartingꢀ
column location for the burst access.
Priorꢀ toꢀ normalꢀ operation,ꢀ theꢀ SDRAMꢀ mustꢀ beꢀ initial-
ized.ꢀTheꢀfollowingꢀsectionsꢀprovideꢀdetailedꢀinformationꢀ
covering device initialization, register definition, command
descriptions and device operation.
Theꢀ modeꢀ registerꢀ shouldꢀ beꢀ loadedꢀ priorꢀ toꢀ applyingꢀ
any operational command because it will power up in an
unknownꢀstate.ꢀAfterꢀtheꢀLoadꢀModeꢀRegisterꢀcommand,ꢀ
atꢀleastꢀoneꢀNOPꢀcommandꢀmustꢀbeꢀassertedꢀpriorꢀtoꢀ
any command.
18
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
initiatingꢀtheꢀsubsequentꢀoperation.
Violatingꢀeitherꢀofꢀtheseꢀ
IS42S16400J
IS45S16400J
REGISTER DEFINITION
Mode Register
Theꢀmodeꢀregisterꢀisꢀusedꢀtoꢀdefineꢀtheꢀspecificꢀmodeꢀ
ofꢀoperationꢀofꢀtheꢀSDRAM.ꢀThisꢀdefinitionꢀincludesꢀtheꢀ
selection of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
MODEꢀREGISTERꢀDEFINITION.ꢀ
Mode register bits M0-M2 specify the burst length, M3
specifiesthetypeofburst(sequentialorinterleaved), M4-M6
specify the CAS latency, M7 and M8 specify the operating
mode,ꢀM9ꢀspecifiesꢀtheꢀWRITEꢀburstꢀmode,ꢀandꢀM10ꢀandꢀ
M11 are reserved for future use.
Theꢀmodeꢀregisterꢀmustꢀbeꢀloadedꢀwhenꢀallꢀbanksꢀareꢀ
idle, and the controller must wait the specified time before
TheꢀmodeꢀregisterꢀisꢀprogrammedꢀviaꢀtheꢀLOADꢀMODEꢀ
REGISTERꢀcommandꢀandꢀwillꢀretainꢀtheꢀstoredꢀinformationꢀ
until it is programmed again or the device loses power.
requirements will result in unspecified operation.
MODE REGISTER DEFINITION
Address Bus
A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register (Mx)
Reserved(1)
Burst Length
M2 M1 M0
M3=0
M3=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Burst Type
M3
Type
0
1
Sequential
Interleaved
Latency Mode
M6 M5 M4
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Operating Mode
M8 M7 M6-M0 Mode
0
—
0
—
Defined Standard Operation
All Other States Reserved
—
Write Burst Mode
M9
0
Mode
Programmed Burst Length
Single Location Access
1. To ensure compatibility with future devices,
should program M11, M10 = "0, 0"
1
Integrated Silicon Solution, Inc. — www.issi.comꢀ
19
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
Burst Length
ing that the burst will wrap within the block if a boundary
isꢀreached.ꢀTheꢀblockꢀisꢀuniquelyꢀselectedꢀbyꢀA1-A7ꢀ(x16)ꢀ
when the burst length is set to two; by A2-A7 (x16) when
the burst length is set to four;and by A3-A7 (x16) when the
burstꢀlengthꢀisꢀsetꢀtoꢀeight.ꢀTheꢀremainingꢀ(leastꢀsignificant)ꢀ
address bit(s) is (are) used to select the starting location
withinꢀtheꢀblock.ꢀFull-pageꢀburstsꢀwrapꢀwithinꢀtheꢀpageꢀifꢀ
the boundary is reached.
ReadꢀandꢀwriteꢀaccessesꢀtoꢀtheꢀSDRAMꢀareꢀburstꢀoriented,ꢀ
with the burst length being programmable, as shown in
MODEꢀREGISTERꢀDEFINITION.ꢀTheꢀburstꢀlengthꢀdeter-
mines the maximum number of column locations that can
beꢀaccessedꢀforꢀaꢀgivenꢀREADꢀorꢀWRITEꢀcommand.ꢀBurstꢀ
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page
burstꢀisꢀavailableꢀforꢀtheꢀsequentialꢀtype.ꢀTheꢀfull-pageꢀ
burstꢀisꢀusedꢀinꢀconjunctionꢀwithꢀtheꢀBURSTꢀTERMINATEꢀ
command to generate arbitrary burst lengths.
Burst Type
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
Reservedꢀstatesꢀshouldꢀnotꢀbeꢀused,ꢀasꢀunknownꢀoperationꢀ
or incompatibility with future versions may result.
WhenꢀaꢀREADꢀorꢀWRITEꢀcommandꢀisꢀissued,ꢀaꢀblockꢀofꢀ
columnsequaltotheburstlengthiseffectivelyselected.All
accesses for that burst take place within this block, mean-
Theꢀorderingꢀofꢀaccessesꢀwithinꢀaꢀburstꢀisꢀdeterminedꢀbyꢀ
the burst length, the burst type and the starting column
address,ꢀasꢀshownꢀinꢀBURSTꢀDEFINITIONꢀtable.
BURST DEFINITION
Burst
Starting Column
Address
Order of Accesses Within a Burst
Length
Type = Sequential
Type = Interleaved
A0
2
4
0
1
0-1
1-0
0-1
1-0
A1
0
A0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0
1
1
0
1
1
A2
A1
0
A0
0
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
NotꢀSupportedꢀ
0
0
1
0
1
0
8
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
ꢀ
Fullꢀ
Page
(y)
nꢀ=ꢀA0-A7ꢀ
ꢀ
ꢀ
ꢀ
Cn,ꢀCnꢀ+ꢀ1,ꢀCnꢀ+ꢀ2ꢀ
Cn + 3, Cn + 4...
…Cn - 1,
ꢀ
(location 0-y)
Cn…
20
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
CAS Latency
Operating Mode
TheꢀCASꢀlatencyꢀisꢀtheꢀdelay,ꢀinꢀclockꢀcycles,ꢀbetweenꢀ
the registrationꢀofꢀaꢀREADꢀcommandꢀandꢀtheꢀavailabilityꢀofꢀ
theꢀfirstꢀpieceꢀofꢀoutputꢀdata.ꢀTheꢀlatencyꢀcanꢀbeꢀsetꢀtoꢀtwoꢀorꢀ
three clocks.
TheꢀnormalꢀoperatingꢀmodeꢀisꢀselectedꢀbyꢀsettingꢀM7ꢀandꢀM8ꢀ
to zero; the other combinations of values for M7 and M8 are
reservedꢀforꢀfutureꢀuseꢀand/orꢀtestꢀmodes.ꢀTheꢀprogrammedꢀ
burstꢀlengthꢀappliesꢀtoꢀbothꢀREADꢀandꢀWRITEꢀbursts.
IfꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀclockꢀedgeꢀn,ꢀandꢀ
the latency is m clocks, the data will be available by clock
edge n + m.ꢀTheꢀDQsꢀwillꢀstartꢀdrivingꢀasꢀaꢀresultꢀofꢀtheꢀ
clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid by
clock edge n + m.ꢀForꢀexample,ꢀassumingꢀthatꢀtheꢀclockꢀ
cycle time is such that all relevant access times are met,
ifꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀT0ꢀandꢀtheꢀlatencyꢀ
is programmed to two clocks, the DQs will start driving
afterꢀT1ꢀandꢀtheꢀdataꢀwillꢀbeꢀvalidꢀbyꢀT2,ꢀasꢀshownꢀinꢀCASꢀ
Latencyꢀdiagrams.ꢀTheꢀAllowable Operating Frequency
table indicates the operating frequencies at which each
CAS latency setting can be used.
Testꢀmodesꢀandꢀreservedꢀstatesꢀshouldꢀnotꢀbeꢀusedꢀbe-
cause unknown operation or incompatibility with future
versions may result.
Write Burst Mode
WhenꢀM9ꢀ=ꢀ0,ꢀtheꢀburstꢀlengthꢀprogrammedꢀviaꢀM0-M2ꢀ
appliesꢀtoꢀbothꢀREADꢀandꢀWRITEꢀbursts;ꢀwhenꢀM9ꢀ=ꢀ1,ꢀ
theꢀprogrammedꢀburstꢀlengthꢀappliesꢀtoꢀREADꢀbursts,ꢀbutꢀ
write accesses are single-location (nonburst) accesses.
CAS Latency
Allowable Operating Frequency (MHz)
Speed
CAS Latency = 2
CAS Latency = 3
Reservedꢀstatesꢀshouldꢀnotꢀbeꢀusedꢀasꢀunknownꢀoperationꢀ
or incompatibility with future versions may result.
-5
133
133
133
200
166
143
-6
-7
CAS Latency
T0
T1
T2
T3
CLK
READ
NOP
NOP
COMMAND
DQ
t
AC
D
OUT
OH
t
LZ
t
CAS Latency - 2
T0
T1
T2
T3
T4
CLK
READ
NOP
NOP
NOP
COMMAND
DQ
t
AC
D
OUT
OH
t
LZ
t
CAS Latency - 3
DON'T CARE
UNDEFINED
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OPERATION
Activating Specific Row Within Specific Bank
BANK/ROW ACTIVATION
BeforeꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀcanꢀbeꢀissuedꢀ
toꢀaꢀbankꢀwithinꢀtheꢀSDRAM,ꢀaꢀrowꢀinꢀthatꢀbankꢀmustꢀbeꢀ
“opened.”ꢀThisꢀisꢀaccomplishedꢀviaꢀtheꢀACTIVEꢀcommand,ꢀ
which selects both the bank and the row to be activated
(see ActivatingꢀSpecificꢀRowꢀWithinꢀSpecificꢀBank).
CLK
HIGH - Z
CKE
CS
RAS
CAS
WE
After opening a row (issuingꢀanꢀACTIVEꢀcommand),ꢀaꢀREADꢀ
orꢀWRITEꢀcommandꢀmayꢀbeꢀissuedꢀtoꢀthatꢀrow,ꢀsubjectꢀtoꢀ
the trcd specification. Minimum trcd should be divided by
the clock period and rounded up to the next whole number
toꢀ determineꢀ theꢀ earliestꢀ clockꢀ edgeꢀ afterꢀ theꢀ ACTIVEꢀ
commandꢀonꢀwhichꢀaꢀREADꢀorꢀWRITEꢀcommandꢀcanꢀbeꢀ
entered.ꢀForꢀexample,ꢀaꢀtrcd specification of 20ns with a
125 MHz clock (8ns period) results in 2.5 clocks, rounded
toꢀ3.ꢀThisꢀisꢀreflectedꢀinꢀtheꢀfollowingꢀexample,ꢀwhichꢀcov-
ersꢀanyꢀcaseꢀwhereꢀ2ꢀ<ꢀ[trcdꢀ(MIN)/tck] ≤ꢀ3.ꢀ(Theꢀsameꢀ
procedure is used to convert other specification limits from
time units to clock cycles).
A0-A11
BA0, BA1
ROW ADDRESS
BANK ADDRESS
AꢀsubsequentꢀACTIVEꢀcommandꢀtoꢀaꢀdifferentꢀrowꢀinꢀtheꢀ
same bank can only be issued after the previous active
rowꢀhasꢀbeenꢀ“closed”ꢀ(precharged).ꢀTheꢀminimumꢀtimeꢀ
intervalꢀbetweenꢀsuccessiveꢀACTIVEꢀcommandsꢀtoꢀtheꢀ
same bank is defined by trc.
AꢀsubsequentꢀACTIVEꢀcommandꢀtoꢀanotherꢀbankꢀcanꢀbeꢀ
issuedwhilethefirstbankisbeingaccessed, whichresults
inꢀaꢀreductionꢀofꢀtotalꢀrow-accessꢀoverhead.ꢀTheꢀminimumꢀ
timeꢀintervalꢀbetweenꢀsuccessiveꢀACTIVEꢀcommandsꢀtoꢀ
different banks is defined by trrd.
Example: Meeting tRCD (MIN) when 2 < [tRCD (min)/tCK] ≤ 3
T0
T1
T2
T3
T4
CLK
READ or
WRITE
ACTIVE
NOP
NOP
COMMAND
t
RCD
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Rev. F
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sameꢀbank.TheꢀPRECHARGEꢀcommandꢀshouldꢀbeꢀissuedꢀ
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READS
READ COMMAND
READꢀ burstsꢀ areꢀ initiatedꢀ withꢀ aꢀ READꢀ command,ꢀ asꢀ
shownꢀinꢀtheꢀREADꢀCOMMANDꢀdiagram.
CLK
Theꢀstartingꢀcolumnꢀandꢀbankꢀaddressesꢀareꢀprovidedꢀwithꢀ
theꢀREADꢀcommand,ꢀandꢀautoꢀprechargeꢀisꢀeitherꢀenabledꢀorꢀ
disabled for that burst access. If auto precharge is enabled,
the row being accessed is precharged at the completion of
theꢀburst.ꢀForꢀtheꢀgenericꢀREADꢀcommandsꢀusedꢀinꢀtheꢀfol-
lowing illustrations, auto precharge is disabled.
HIGH-Z
CKE
CS
RAS
DuringꢀREADꢀbursts,ꢀtheꢀvalidꢀdata-outꢀelementꢀfromꢀtheꢀ
starting column address will be available following the
CASꢀlatencyꢀafterꢀtheꢀREADꢀcommand.ꢀEachꢀsubsequentꢀ
data-out element will be valid by the next positive clock
edge.ꢀTheꢀCASꢀLatencyꢀdiagramꢀshowsꢀgeneralꢀtiming
for each possible CAS latency setting.
CAS
WE
COLUMN ADDRESS
AUTO PRECHARGE
Uponꢀcompletionꢀofꢀaꢀburst,ꢀassumingꢀnoꢀotherꢀcommandsꢀ
haveꢀbeenꢀinitiated,ꢀtheꢀDQsꢀwillꢀgoꢀHigh-Z.ꢀAꢀfull-pageꢀburstꢀ
will continue until terminated. (At the end of the page, it will
wrap to column 0 and continue.)
A0-A7
A8, A9, A11
A10
DataꢀfromꢀanyꢀREADꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsub-
sequentꢀREADꢀcommand,ꢀandꢀdataꢀfromꢀaꢀfixed-lengthꢀ
READꢀburstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀdataꢀfromꢀaꢀ
READꢀcommand.ꢀInꢀeitherꢀcase,ꢀaꢀcontinuousꢀflowꢀofꢀdataꢀ
canꢀbeꢀmaintained.ꢀTheꢀfirstꢀdataꢀelementꢀfromꢀtheꢀnewꢀ
burst follows either the last element of a completed burst
or the last desired data element of a longer burst which
is being truncated.
NO PRECHARGE
BANK ADDRESS
BA0, BA1
TheꢀDQMꢀinputꢀisꢀusedꢀtoꢀavoidꢀI/Oꢀcontention,ꢀasꢀshownꢀ
inꢀFiguresꢀRW1ꢀandꢀRW2.ꢀTheꢀDQMꢀsignalꢀmustꢀbeꢀas-
sertedꢀ(HIGH)ꢀatꢀleastꢀthreeꢀclocksꢀpriorꢀtoꢀtheꢀWRITEꢀ
command (DQM latency is two clocks for output buffers)
toꢀsuppressꢀdata-outꢀfromꢀtheꢀREAD.ꢀOnceꢀtheꢀWRITEꢀ
commandꢀisꢀregistered,ꢀtheꢀDQsꢀwillꢀgoꢀHigh-Zꢀ(orꢀremainꢀ
High-Z),ꢀregardlessꢀofꢀtheꢀstateꢀofꢀtheꢀDQMꢀsignal,ꢀprovidedꢀ
theꢀDQMꢀwasꢀactiveꢀonꢀtheꢀclockꢀjustꢀpriorꢀtoꢀtheꢀWRITEꢀ
commandꢀthatꢀtruncatedꢀtheꢀREADꢀcommand.ꢀIfꢀnot,ꢀtheꢀ
secondꢀWRITEꢀwillꢀbeꢀanꢀinvalidꢀWRITE.ꢀForꢀexample,ꢀifꢀ
DQMꢀwasꢀLOWꢀduringꢀT4ꢀinꢀFigureꢀRW2,ꢀthenꢀtheꢀWRITEsꢀ
atꢀT5ꢀandꢀT7ꢀwouldꢀbeꢀvalid,ꢀwhileꢀtheꢀWRITEꢀatꢀT6ꢀwouldꢀ
be invalid.
TheꢀnewꢀREADꢀcommandꢀshouldꢀbeꢀissuedꢀxcyclesbefore
the clock edge at which the last desired data element is
valid, where x equalsꢀtheꢀCASꢀlatencyꢀminusꢀone.ꢀThisꢀisꢀ
shownꢀinꢀConsecutiveꢀREADꢀBurstsꢀforꢀCASꢀlatenciesꢀofꢀ
two and three; data element n + 3 is either the last of a
burstꢀofꢀfourꢀorꢀtheꢀlastꢀdesiredꢀofꢀaꢀlongerꢀburst.ꢀTheꢀ64Mbꢀ
SDRAMꢀusesꢀaꢀpipelinedꢀarchitectureꢀandꢀthereforeꢀdoesꢀ
not require the 2n rule associated with a prefetch architec-
ture.ꢀAꢀREADꢀcommandꢀcanꢀbeꢀinitiatedꢀonꢀanyꢀclockꢀcycleꢀ
followingꢀaꢀpreviousꢀREADꢀcommand.ꢀFull-speedꢀrandomꢀ
read accesses can be performed to the same bank, as
shownꢀinꢀRandomꢀREADꢀAccesses,ꢀorꢀeachꢀsubsequentꢀ
READꢀmayꢀbeꢀperformedꢀtoꢀaꢀdifferentꢀbank.
TheꢀDQMꢀsignalꢀmustꢀbeꢀde-assertedꢀpriorꢀtoꢀtheꢀWRITEꢀ
command (DQM latency is zero clocks for input buffers)
to ensure that the written data is not masked.
DataꢀfromꢀanyꢀREADꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsub-
sequentꢀ WRITEꢀ command,ꢀ andꢀ dataꢀ fromꢀ aꢀ fixed-lengthꢀ
READꢀburstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀdataꢀfromꢀaꢀ
WRITEꢀcommandꢀ(subjectꢀtoꢀbusꢀturnaroundꢀlimitations).ꢀ
TheꢀWRITEꢀburstꢀmayꢀbeꢀinitiatedꢀonꢀtheꢀclockꢀedgeꢀim-
mediately following the last (or last desired) data element
fromꢀtheꢀREADꢀburst,ꢀprovidedꢀthatꢀI/Oꢀcontentionꢀcanꢀbeꢀ
avoided. In a given system design, there may be a pos-
sibilityꢀthatꢀtheꢀdeviceꢀdrivingꢀtheꢀinputꢀdataꢀwillꢀgoꢀLow-Zꢀ
beforeꢀtheꢀSDRAMꢀDQsꢀgoꢀHigh-Z.ꢀInꢀthisꢀcase,ꢀatꢀleastꢀ
a single-cycle delay should occur between the last read
dataꢀandꢀtheꢀWRITEꢀcommand.
Aꢀfixed-lengthꢀREADꢀburstꢀmayꢀbeꢀfollowedꢀby,ꢀorꢀtruncatedꢀ
with, aPRECHARGE commandtothesamebank(provided
that auto precharge was not activated), and a full-page burst
mayꢀbeꢀtruncatedꢀwithꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀ
x cycles before the clock edge at which the last desired
data element is valid, where x equals the CAS latency
minusꢀone.ꢀThisꢀisꢀshownꢀinꢀtheꢀREADꢀtoꢀPRECHARGEꢀ
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providedꢀthatꢀautoꢀprechargeꢀwasꢀnotꢀactivated.TheꢀBURSTꢀ
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diagram for each possible CAS latency; data element n +
3 is either the last of a burst of four or the last desired of
aꢀlongerꢀburst.ꢀFollowingꢀtheꢀPRECHARGEꢀcommand,ꢀaꢀ
subsequent command to the same bank cannot be issued
until trpꢀisꢀmet.ꢀNoteꢀthatꢀpartꢀofꢀtheꢀrowꢀprechargeꢀtimeꢀisꢀ
hidden during the access of the last data element(s).
Full-pageꢀREADꢀburstsꢀcanꢀbeꢀtruncatedꢀwithꢀtheꢀBURSTꢀ
TERMINATEꢀ command,ꢀ andꢀ fixed-lengthꢀ READꢀ burstsꢀ
mayꢀbeꢀtruncatedꢀwithꢀaꢀBURSTꢀTERMINATEꢀcommand,ꢀ
TERMINATEꢀcommandꢀshouldꢀbeꢀissuedꢀx cycles before
the clock edge at which the last desired data element is
valid, where x equalsꢀtheꢀCASꢀlatencyꢀminusꢀone.ꢀThisꢀisꢀ
shownꢀinꢀtheꢀREADꢀBurstꢀTerminationꢀdiagramꢀforꢀeachꢀ
possibleCASlatency;dataelementn+3isthelastdesired
data element of a longer burst.
In the case of a fixed-length burst being executed to
completion,ꢀ aꢀ PRECHARGEꢀ commandꢀ issuedꢀ atꢀ theꢀ
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burstꢀwithꢀautoꢀprecharge.ꢀTheꢀdisadvantageꢀofꢀtheꢀPRE-
CHARGEꢀcommandꢀisꢀthatꢀitꢀrequiresꢀthatꢀtheꢀcommandꢀ
and address buses be available at the appropriate time to
issueꢀtheꢀcommand;ꢀtheꢀadvantageꢀofꢀtheꢀPRECHARGEꢀ
command is that it can be used to truncate fixed-length
or full-page bursts.
CAS Latency
T0
T1
T2
T3
CLK
READ
NOP
NOP
COMMAND
DQ
t
AC
D
OUT
OH
t
LZ
t
CAS Latency - 2
T0
T1
T2
T3
T4
CLK
READ
NOP
NOP
NOP
COMMAND
DQ
tAC
D
OUT
OH
t
LZ
t
CAS Latency - 3
DON'T CARE
UNDEFINED
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Rev. F
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Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
READ
NOP
NOP
x=1 cycle
BANK,
COL n
BANK,
COL b
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
D
OUT
b
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
NOP
NOP
NOP
READ
NOP
x = 2 cycles
NOP
NOP
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
D
OUT
b
CAS Latency - 3
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Rev. F
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Random READ Accesses
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
D
OUT
n
DOUT
b
DOUT
m
DOUT
x
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DOUT
n
DOUT
b
DOUT
m
DOUT
x
CAS Latency - 3
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Rev. F
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RW1 - READ to WRITE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
WRITE
BANK,
COL n
BANK,
COL b
t
HZ
DOUT n+1
DOUT n+2
D
OUT
n
DIN b
CAS Latency - 2
t
DS
DON'T CARE
RW2 - READ to WRITE
T0
T1
T2
T3
T4
T5
CLK
DQM
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
WRITE
BANK,
COL n
BANK,
COL b
t
HZ
DOUT
n
DIN
b
CAS Latency - 3
t
DS
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READ to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t
RP
PRECHARGE
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
x = 1 cycle
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
t
RP
PRECHARGE
READ
NOP
NOP
NOP
NOP
x = 2 cycles
NOP
ACTIVE
BANK,
COL n
BANK,
COL b
BANK a,
ROW
DOUT
n
DOUT n+1
D
OUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
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READ Burst Termination
T0
T1
T2
T3
T4
T5
T6
CLK
BURST
TERMINATE
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
x = 1 cycle
BANK a,
COL n
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
x = 2 cycles
NOP
NOP
BANK,
COL n
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
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precharge.TheꢀdisadvantageꢀofꢀtheꢀPRECHARGEcommand
IS42S16400J
IS45S16400J
AnꢀexampleꢀisꢀshownꢀinꢀWRITEꢀtoꢀWRITEꢀdiagram.ꢀDataꢀ
n + 1 is either the last of a burst of two or the last desired
ofꢀaꢀlongerꢀburst.ꢀTheꢀ64MbꢀSDRAMꢀ usesꢀaꢀpipelinedꢀ
architecture and therefore does not require the 2n rule as-
sociatedꢀwithꢀaꢀprefetchꢀarchitecture.ꢀAꢀWRITEꢀcommandꢀ
can be initiated on any clock cycle following a previous
WRITEꢀcommand.ꢀFull-speedꢀrandomꢀwriteꢀaccessesꢀwithinꢀ
a page can be performed to the same bank, as shown in
RandomꢀWRITEꢀCycles,ꢀorꢀeachꢀsubsequentꢀWRITEꢀmayꢀ
be performed to a different bank.
WRITEs
WRITEꢀburstsꢀareꢀinitiatedꢀwithꢀaꢀWRITEꢀcommand,ꢀasꢀ
shownꢀinꢀWRITEꢀCommandꢀdiagram.
WRITE Command
CLK
HIGH - Z
CKE
DataꢀforꢀanyꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsubse-
quentꢀREADꢀcommand,ꢀandꢀdataꢀforꢀaꢀfixed-lengthꢀWRITEꢀ
burstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀaꢀsubsequentꢀREADꢀ
command.ꢀOnceꢀtheꢀREADꢀcommandꢀisꢀregistered,ꢀtheꢀ
dataꢀinputsꢀwillꢀbeꢀignored,ꢀandꢀWRITEsꢀwillꢀnotꢀbeꢀex-
ecuted.ꢀAnꢀexampleꢀisꢀshownꢀinꢀWRITEꢀtoꢀREAD.ꢀDataꢀn
+ 1 is either the last of a burst of two or the last desired
of a longer burst.
CS
RAS
CAS
WE
Dataꢀ forꢀ aꢀ fixed-lengthꢀ WRITEꢀ burstꢀ mayꢀ beꢀ followedꢀ
by,ꢀorꢀtruncatedꢀwith,ꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀ
same bank (provided that auto precharge was not acti-
vated),ꢀandꢀaꢀfull-pageꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀ
withꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀsameꢀbank.ꢀTheꢀ
PRECHARGEꢀcommandꢀshouldꢀbeꢀissuedꢀtwr after the
clock edge at which the last desired input data element
isꢀregistered.ꢀTheꢀautoꢀprechargeꢀmodeꢀrequiresꢀaꢀtwr of
at least one clock plus time, regardless of frequency. In
addition,ꢀwhenꢀtruncatingꢀaꢀWRITEꢀburst,ꢀtheꢀDQMꢀsignalꢀ
must be used to mask input data for the clock edge prior
to,ꢀandꢀtheꢀclockꢀedgeꢀcoincidentꢀwith,ꢀtheꢀPRECHARGEꢀ
command.ꢀAnꢀexampleꢀisꢀshownꢀinꢀtheꢀWRITEꢀtoꢀPRE-
CHARGEꢀdiagram.ꢀDataꢀn+1 is either the last of a burst
ofꢀtwoꢀorꢀtheꢀlastꢀdesiredꢀofꢀaꢀlongerꢀburst.ꢀFollowingꢀtheꢀ
PRECHARGEꢀcommand,ꢀaꢀsubsequentꢀcommandꢀtoꢀtheꢀ
same bank cannot be issued until trp is met.
COLUMN ADDRESS
AUTO PRECHARGE
A0-A7
A8, A9, A11
A10
NO PRECHARGE
BANK ADDRESS
BA0, BA1
Theꢀstartingꢀcolumnꢀandꢀbankꢀaddressesꢀareꢀprovidedꢀwithꢀ
theꢀWRITEꢀcommand,ꢀandꢀautoꢀprechargeꢀisꢀeitherꢀenabledꢀ
or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of
theꢀburst.ꢀForꢀtheꢀgenericꢀWRITEꢀcommandsꢀusedꢀinꢀtheꢀ
following illustrations, auto precharge is disabled.
Inthecaseofafixed-lengthburstbeingexecutedtocomple-
tion,ꢀaꢀPRECHARGEꢀcommandꢀissuedꢀatꢀtheꢀoptimumꢀ
time (as described above) provides the same operation that
would result from the same fixed-length burst with auto
DuringꢀWRITEꢀbursts,ꢀtheꢀfirstꢀvalidꢀdata-in element will be
registeredcoincidentwiththeWRITEꢀcommand.Subsequent
data elements will be registered on each successive posi-
tiveꢀclockꢀedge.ꢀUponꢀcompletionꢀofꢀaꢀfixed-lengthꢀburst,ꢀ
assuming no other commands have been initiated, the
DQsꢀwillꢀremainꢀHigh-Zꢀandꢀanyꢀadditionalꢀinputꢀdataꢀwillꢀ
beꢀignoredꢀ(seeꢀWRITEꢀBurst).ꢀAꢀfull-pageꢀburstꢀwillꢀcon-
tinue until terminated. (At the end of the page, it will wrap
to column 0 and continue.)
is that it requires that the command and address buses be
availableattheappropriatetimetoissuethecommand;the
advantageꢀofꢀtheꢀPRECHARGEꢀcommandꢀisꢀthatꢀitꢀcanꢀbeꢀ
used to truncate fixed-length or full-page bursts.
Fixed-lengthꢀorꢀfull-pageꢀWRITEꢀburstsꢀcanꢀbeꢀtruncatedꢀ
withꢀtheꢀBURSTꢀTERMINATEꢀcommand.ꢀWhenꢀtruncat-
ingꢀaꢀWRITEꢀburst,ꢀtheꢀinputꢀdataꢀappliedꢀcoincidentꢀwithꢀ
theꢀBURSTꢀTERMINATEꢀcommandꢀwillꢀbeꢀignored.ꢀTheꢀ
lastꢀdataꢀwrittenꢀ(providedꢀthatꢀDQMꢀisꢀLOWꢀatꢀthatꢀtime)ꢀ
will be the input data applied one clock previous to the
BURSTꢀTERMINATEꢀcommand.ꢀThisꢀisꢀshownꢀinꢀWRITEꢀ
BurstꢀTermination,ꢀwhereꢀdataꢀn is the last desired data
element of a longer burst.
DataꢀforꢀanyꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsubse-
quentꢀWRITEꢀcommand,ꢀandꢀdataꢀforꢀaꢀfixed-lengthꢀWRITEꢀ
burstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀdataꢀforꢀaꢀWRITEꢀ
command.ꢀTheꢀnewꢀWRITEꢀcommandꢀcanꢀbeꢀissuedꢀonꢀ
anyꢀclockꢀfollowingꢀtheꢀpreviousꢀWRITEꢀcommand,ꢀandꢀtheꢀ
data provided coincident with the new command applies to
the new command.
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WRITE Burst
T0
T1
T2
T3
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
NOP
BANK,
COL n
DIN
n
DIN n+1
DON'T CARE
WRITE to WRITE
T0
T1
T2
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
WRITE
BANK,
COL n
BANK,
COL b
DIN
n
DIN n+1
DIN b
DON'T CARE
Random WRITE Cycles
T0
T1
T2
T3
CLK
COMMAND
ADDRESS
DQ
WRITE
WRITE
WRITE
WRITE
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DIN
n
DIN
b
DIN
m
DIN x
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WRITE to READ
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
DIN
n
DIN n+1
D
OUT
b
DOUT b+1
CAS Latency - 2
DON'T CARE
WP1 - WRITE to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
t
RP
PRECHARGE
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
ACTIVE
NOP
NOP
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
t
WR
DIN
n
DIN n+1
CAS Latency - 2
DON'T CARE
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WP2 - WRITE to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
tRP
PRECHARGE
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
NOP
ACTIVE
NOP
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
t
WR
DIN
n
D
IN n+1
CAS Latency - 3
DON'T CARE
WRITE Burst Termination
T0
T1
T2
CLK
BURST
TERMINATE
NEXT
COMMAND
ADDRESS
DQ
WRITE
COMMAND
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com
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Rev. F
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allꢀbanks.Theꢀbank(s)ꢀwillꢀbeꢀavailableꢀforꢀaꢀsubsequentꢀrowꢀ
IS42S16400J
IS45S16400J
PRECHARGE
PRECHARGE Command
TheꢀPRECHARGEꢀcommandꢀ(seeꢀfigure)ꢀisꢀusedꢀtoꢀdeac-
tivate the open row in a particular bank or the open row in
CLK
HIGH - Z
access some specified time (trp)ꢀafterꢀtheꢀPRECHARGEꢀ
command is issued.Input A10 determines whether one or
all banks are to be precharged, and in the case where only
oneꢀbankꢀisꢀtoꢀbeꢀprecharged,ꢀinputsꢀBA0,ꢀBA1ꢀselectꢀtheꢀ
bank.ꢀWhenꢀallꢀbanksꢀareꢀtoꢀbeꢀprecharged,ꢀinputsꢀBA0,ꢀ
BA1ꢀareꢀtreatedꢀasꢀ“Don’tꢀCare.”ꢀOnceꢀaꢀbankꢀhasꢀbeenꢀ
precharged, it is in the idle state and must be activated
priorꢀtoꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀbeingꢀissuedꢀtoꢀ
that bank.
CKE
CS
RAS
CAS
WE
POWER-DOWN
A0-A9, A11
ALL BANKS
Power-downꢀoccursꢀifꢀCKEꢀisꢀregisteredꢀLOWꢀcoincidentꢀ
withꢀaꢀNOPꢀorꢀCOMMANDꢀINHIBITꢀwhenꢀnoꢀaccessesꢀ
are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down;
if power-down occurs when there is a row active in either
bank, this mode is referred to as active power-down.
Entering power-down deactivates the input and output
buffers,ꢀexcludingꢀCKE,ꢀforꢀmaximumꢀpowerꢀsavingsꢀwhileꢀ
inꢀstandby.ꢀTheꢀdeviceꢀmayꢀnotꢀremainꢀinꢀtheꢀpower-downꢀ
statelongerthantherefreshperiod(64ms)sincenorefresh
operations are performed in this mode.
A10
BANK SELECT
BANK ADDRESS
BA0, BA1
Theꢀpower-downꢀstateꢀisꢀexitedꢀbyꢀregisteringꢀaꢀNOPꢀorꢀ
COMMANDꢀINHIBITꢀandꢀCKEꢀHIGHꢀatꢀtheꢀdesiredꢀclockꢀ
edge (meeting tcks). See figure below.
POWER-DOWN
CLK
t
CKS
≥ tCKS
CKE
COMMAND
NOP
NOP
ACTIVE
tRCD
tRAS
t
RC
All banks idle
Input buffers gated off
Enter power-down mode
Exit power-down mode
DON'T CARE
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CLOCK SUSPEND
of a suspended internal clock edge is ignored; any data
present on the DQ pins remains driven;and burst counters
are not incremented, as long as the clock is suspended.
(See following examples.)
Clock suspend mode occurs when a column access/burst
isꢀinꢀprogressꢀandꢀCKEꢀisꢀregisteredꢀLOW.ꢀInꢀtheꢀclockꢀ
suspendꢀmode,ꢀtheꢀinternalꢀclockꢀisꢀdeactivated,ꢀ“freezing”ꢀ
the synchronous logic.
ClockꢀsuspendꢀmodeꢀisꢀexitedꢀbyꢀregisteringꢀCKEꢀHIGH;ꢀ
the internal clock and related operation will resume on the
subsequent positive clock edge.
ForꢀeachꢀpositiveꢀclockꢀedgeꢀonꢀwhichꢀCKEꢀisꢀsampledꢀ
LOW,ꢀtheꢀnextꢀinternalꢀpositiveꢀclockꢀedgeꢀisꢀsuspended.ꢀ
Any command or data present on the input pins at the time
Clock Suspend During WRITE Burst
T0
T1
T2
T3
T4
T5
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
NOP
WRITE
NOP
NOP
BANK a,
COL n
DIN
n
DIN n+1
DIN n+2
DON'T CARE
Clock Suspend During READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
BANK a,
COL n
DOUT
n
D
OUT n+1
DOUT n+2
DOUT n+3
DON'T CARE
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BURST READ/SINGLE WRITE
Theꢀburstꢀread/singleꢀwriteꢀmodeꢀisꢀenteredꢀbyꢀprogrammingꢀ
the write burst mode bit (M9) in the mode register to a logic
1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of
theꢀprogrammedꢀburstꢀlength.ꢀREADꢀcommandsꢀaccess
columns according to the programmed burst length and
sequence,ꢀjustꢀasꢀinꢀtheꢀnormalꢀmodeꢀofꢀoperationꢀ(M9ꢀ
=ꢀ0).
SDRAMsꢀsupportꢀCONCURRENTꢀAUTOꢀPRECHARGE.ꢀ
FourꢀcasesꢀwhereꢀCONCURRENTꢀAUTOꢀPRECHARGEꢀ
occurs are defined below.
READ with Auto Precharge
1.ꢀInterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
AꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀREADꢀonꢀbankꢀn,ꢀ
CASꢀlatencyꢀlater.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀ
beginꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀregistered.
CONCURRENT AUTO PRECHARGE
2.ꢀInterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
AꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀREADꢀonꢀbankꢀnꢀ
when registered. DQM should be used two clocks prior
toꢀtheꢀWRITEꢀcommandꢀtoꢀpreventꢀbusꢀcontention.ꢀTheꢀ
PRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀwhenꢀtheꢀWRITEꢀtoꢀ
bank m is registered.
Anꢀaccessꢀcommandꢀ(READꢀorꢀWRITE)ꢀtoꢀanotherꢀbankꢀ
while an access command with auto precharge enabled is
executingꢀisꢀnotꢀallowedꢀbyꢀSDRAMs,ꢀunlessꢀtheꢀSDRAMꢀ
supportsꢀ CONCURRENTꢀ AUTOꢀ PRECHARGE.ꢀ ISSI
Fig CAP 1 - READ With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Idle
COMMAND
BANK n
Page Active
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
t
RP - BANK n
tRP - BANK m
Internal States
BANK m
READ with Burst of 4
Precharge
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
D
OUT
a
DOUT a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK n)
CAS Latency - 3 (BANK m)
DON'T CARE
Fig CAP 2 - READ With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
BANK n
WRITE - AP
BANK m
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
Idle
BANK n
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
Page Active
tRP - BANK n
tRP - BANK m
Internal States
BANK m
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQM
DQ
D
OUT
a
DIN
b
DIN b+1
DIN b+2
DIN b+3
CAS Latency - 3 (BANK n)
DON'T CARE
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WRITE with Auto Precharge
4.ꢀInterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
WRITE tobankmwillinterruptaWRITE onbanknwhen
3.ꢀInterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
AꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀWRITEꢀonꢀbankꢀnꢀ
whenregistered,withthedata-outappearingCASlatency
later.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀafterꢀtwr
is met, where twrꢀbeginsꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀ
registered.ꢀTheꢀlastꢀvalidꢀWRITE to bank n will be data-in
registeredꢀoneꢀclockꢀpriorꢀtoꢀtheꢀREADꢀtoꢀbankꢀm.
A
registered.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀafterꢀ
twr is met, where twrꢀbeginsꢀwhenꢀtheꢀWRITEꢀtoꢀbankꢀ
mꢀisꢀregistered.ꢀTheꢀlastꢀvalidꢀdataꢀWRITEꢀtoꢀbankꢀnꢀ
willꢀbeꢀdataꢀregisteredꢀoneꢀclockꢀpriorꢀtoꢀaꢀWRITEꢀtoꢀ
bank m.
Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4 Interrupt Burst, Write-Back
WR - BANK n
Precharge
t
tRP - BANK n
Internal States
tRP - BANK m
BANK m
Page Active
READ with Burst of 4
Precharge
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
DIN
a
DIN a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK m)
DON'T CARE
Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
WRITE - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
WR - BANK n
Precharge
t
t
RP - BANK n
Internal States
tRP - BANK m
BANK m
Page Active
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
DIN
a
DIN a+1
DIN a+2
D
IN
b
DIN b+1
DIN b+2
DIN b+3
DON'T CARE
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INITIALIꢀE AND LOAD MODE REGISTER(1)
T0
T1
Tn+1
To+1
t
CL
Tp+1
Tp+2
Tp+3
tCK
t
CH
CLK
CKE
tCKS t
CKH
t
CMS
tCMH
t
CMS
tCMH
tCMS tCMH
AUTO
REFRESH
AUTO
Load MODE
REGISTER
COMMAND
NOP
PRECHARGE
NOP
NOP
NOP
ACTIVE
REFRESH
DQM/
DQML, DQMH
t
t
AS
tAH
A0-A9, A11
A10
ROW
ROW
BANK
CODE
AS
tAH
ALL BANKS
CODE
SINGLE BANK
ALL BANKS
BA0, BA1
DQ
t
RP
t
RC
t
RC
tMRD
T
Power-up: VCC
Precharge AUTO REFRESH
AUTO REFRESH
Program MODE REGISTER(2, 3, 4)
and CLK stable all banks
At least 2 Auto-Refresh Commands
DON'T CARE
T = 100µs Min.
Notes:
1. If CSꢀisꢀHighꢀatꢀclockꢀHighꢀtime,ꢀallꢀcommandsꢀappliedꢀareꢀNOP.
2.ꢀꢀTheꢀModeꢀregisterꢀmayꢀbeꢀloadedꢀpriorꢀtoꢀtheꢀAuto-Refreshꢀcyclesꢀifꢀdesired.
3. JEDEC and PC100 specify three clocks.
4.ꢀꢀOutputsꢀareꢀguaranteedꢀHigh-Zꢀafterꢀtheꢀcommandꢀisꢀissued.
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POWER-DOWN MODE CYCLE
T0
T1
T2
Tn+1
Tn+2
tCK
t
CL
t
CH
CLK
t
CKS
t
CKH
t
CKS
tCKS
CKE
tCMS
tCMH
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
DQM/
DQML, DQMH
A0-A9, A11
A10
ROW
ROW
ALL BANKS
SINGLE BANK
tAS
tAH
BA0, BA1
DQ
BANK
BANK
High-Z
Two clock cycles
Input buffers gated
All banks idle
off while in
power-down mode
Precharge all
active banks
All banks idle, enter
power-down mode
DON'T CARE
Exit power-down mode
CASꢀꢀlatencyꢀ=ꢀ2,ꢀ3
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CLOCK SUSPEND MODE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
tCL
tCH
CLK
CKE
tCKS
t
CKH
t
CKS
t
CKH
t
CMS
tCMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
t
CMS tCMH
DQM/
DQML, DQMH
tAS
tAH
COLUMN n(2)
A0-A9, A11
A10
COLUMN m(2)
tAS
t
AH
tAS
t
AH
BA0, BA1
BANK
BANK
tDS
tDH
tAC
t
AC
tHZ
DQ
D
OUT
m
DOUT m+1
DOUT e
D
OUT e+1
tLZ
tOH
DON'T CARE
UNDEFINED
Notes:
1. CASꢀꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"
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AUTO-REFRESH CYCLE
T0
T1
T2
Tn+1
To+1
tCK
t
CL
t
CH
CLK
t
CKS CKH
t
CKE
t
CMS
tCMH
Auto
Refresh
Auto
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
Refresh
DQM/
DQML, DQMH
A0-A9, A11
A10
ROW
ROW
BANK
ALL BANKS
SINGLE BANK
BANK(s)
BA0, BA1
DQ
tAS
tAH
High-Z
tRP
t
RC
t
RC
DON'T CARE
CASꢀꢀlatencyꢀ=ꢀ2,ꢀ3
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SELF-REFRESH CYCLE
T0
T1
T2
Tn+1
To+1
To+2
t
CK
tCH
t
CL
CLK
CKE
t
CKS
t
CKH
t
CKS
≥ tRAS
t
CKS
tCMS
tCMH
Auto
Auto
COMMAND
PRECHARGE
NOP
NOP
NOP
Refresh
Refresh
DQM/
DQML, DQMH
A0-A9, A11
A10
ALL BANKS
SINGLE BANK
t
AS
tAH
BA0, BA1
DQ
BANK
High-Z
tXSR
tRP
Precharge all
active banks
Enter self
refresh mode
CLK stable prior to exiting
Exit self refresh mode
(Restart refresh time base)
DON'T CARE
Note:
1.ꢀSelf-RefreshꢀModeꢀisꢀnotꢀsupportedꢀforꢀA2ꢀgradeꢀwithꢀTa > 85oC.
42
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
READ WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
t
CKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
AS
t
AH
BA0, BA1
DQ
BANK
BANK
tAC
t
AC
t
AC
t
AC
tHZ
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
t
OH
t
OH
tOH
tOH
tRCD
tRAS
t
RC
CAS Latency
DON'T CARE
tRP
UNDEFINED
Notes:
1. CASꢀꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"
Integrated Silicon Solution, Inc. — www.issi.com
43
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
READ WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
t
CL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
PRECHARGE
ALL BANKS
NOP
ACTIVE
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ROW
AS
t
AH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BA0, BA1
DQ
BANK
BANK
t
AC
t
AC
tAC
tAC
tHZ
DOUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
tOH
tOH
tOH
tOH
tRCD
tRAS
t
RC
CAS Latency
DON'T CARE
t
RP
UNDEFINED
Notes:
1. CASꢀꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"
44
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
SINGLE READ WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS
tCMH
COMMAND
ACTIVE
NOP
NOP
NOP
READ
NOP
NOP
ACTIVE
NOP
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
AS
t
AH
BA0, BA1
BANK
BANK
tOH
tAC
DOUT m
DQ
t
HZ
DON'T CARE
UNDEFINED
tRCD
tRAS
t
RC
CAS Latency
tRP
Notes:
1. CASꢀꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ1
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"
Integrated Silicon Solution, Inc. — www.issi.com
45
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
SINGLE READ WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ALL BANKS
ROW
SINGLE BANK
BANK
AS
t
AH
DISABLE AUTO PRECHARGE
BA0, BA1
DQ
BANK
BANK
t
OH
tAC
D
OUT m
t
LZ
tHZ
DON'T CARE
UNDEFINED
tRCD
tRAS
t
RC
CAS Latency
tRP
Notes:
1. CASꢀꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ1
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"
46
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
WRITE - WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
tCL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
AS
t
AH
BA0, BA1
BANK
BANK
tDS
t
DH
t
DS
t
DH
t
DS
tDH
t
DS
tDH
DQ
DIN
m
D
IN m+
1
D
IN m+
2
D
IN m+3
tRCD
tRAS
t
RC
t
WR
tRP
DON'T CARE
Notes:
1. burstꢀlengthꢀ=ꢀ4
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"
Integrated Silicon Solution, Inc. — www.issi.com
47
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
WRITE - WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
CMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
AS
t
AH
ALL BANKS
ROW
AS
t
AH
SINGLE BANK
BANK
DISABLE AUTO PRECHARGE
BANK
BA0, BA1
BANK
tDS
t
DH
t
DS
t
DH
t
DS
tDH
tDS
tDH
DQ
DIN
m
D
IN m+
1
D
IN m+
2
D
IN m+3
tRCD
tRAS
t
RC
t
WR(3)
t
RP
DON'T CARE
Notes:
1. burstꢀlengthꢀ=ꢀ4
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"
3. tras must not be violated
48
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
SINGLE WRITE - WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
tCL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
NOP(3)
NOP(3)
NOP(3)
WRITE
NOP
NOP
NOP
ACTIVE
NOP
COMMAND
ACTIVE
tCMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
AS
t
AH
BA0, BA1
BANK
BANK
tDS
t
DH
DQ
DIN
m
tRCD
tRAS
t
RC
t
WR
tRP
DON'T CARE
Notes:
1. burstꢀlengthꢀ=ꢀ1
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"
Integrated Silicon Solution, Inc. — www.issi.comꢀ
49
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
SINGLE WRITE - WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
tCL
tCH
CLK
CKE
tCKS tCKH
t
CMS tCMH
NOP(4)
NOP(4)
PRECHARGE
NOP
ACTIVE
NOP
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
tAH
ALL BANKS
ROW
SINGLE BANK
AS
tAH
DISABLE AUTO PRECHARGE
BANK
BA0, BA1
BANK
BANK
t
DS
t
DH
DQ
DIN
m
t
t
t
RCD
RAS
RC
t
WR(3)
tRP
DON'T CARE
Notes:
1. burstꢀlengthꢀ=ꢀ1
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"
3. tras must not be violated
50
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
ALTERNATING BANK READ ACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
COLUMN m(2)
ROW
ROW
COLUMN b(2)
ROW
ROW
A0-A9, A11
A10
ROW
tAS tAH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
tAS tAH
BANK 0
BANK 3
BANK 3
BANK 0
BA0, BA1
BANK 0
t
LZ
t
OH
t
OH
tOH
tOH
tOH
DQ
D
OUT
m
D
OUT m+
1
D
OUT m+
2
D
OUT m+
3
DOUT
b
tAC
tAC
tAC
tAC
tAC
tAC
tRCD - BANK 0
tRRD
CAS Latency - BANK 0
tRP - BANK 0
tRCD - BANK 0
tRCD - BANK 3
CAS Latency - BANK 3
tRAS - BANK 0
tRC - BANK 0
DON'T CARE
Notes:
1. CASꢀꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"
Integrated Silicon Solution, Inc. — www.issi.com
51
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
READ - FULL-PAGE BURST
T0
T1
T2
T3
T4
T5
T6
Tn+1
Tn+2
Tn+3
Tn+4
t
CK
tCL
tCH
CLK
CKE
tCKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
READ
CMS CMH
NOP
NOP
NOP
NOP
NOP
BURST TERM
NOP
NOP
t
t
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
t
AH
ROW
AS
t
AH
BA0, BA1
BANK
BANK
tAC
tAC
tAC
tAC
tAC
tAC
tHZ
D
OUT
m
D
OUT m+
1
D
OUT m+
2
D
OUT m-
1
D
OUT
m
D
OUT m+1
DQ
t
LZ
t
OH
tOH
t
OH
tOH
t
OH
tOH
tRCD
CAS Latency
each row (x4) has
1,024 locations
DON'T CARE
UNDEFINED
Full page Full-page burst not self-terminating.
completion Use BURST TERMINATE command.
Notes:
1. CASꢀꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀfullꢀpage
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"
52
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
READ - DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
tAH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
AS
tAH
BA0, BA1
BANK
BANK
t
OH
tOH
tOH
t
AC
tAC
D
OUT
m
D
OUT m+
2
D
OUT m+
3
DQ
t
LZ
tLZ
t
HZ
tAC
t
HZ
DON'T CARE
UNDEFINED
t
RCD
CAS Latency
Notes:
1. CASꢀꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"
Integrated Silicon Solution, Inc. — www.issi.com
53
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
ALTERNATING BANK WRITE ACCESS
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
tCK
tCL
tCH
CLK
CKE
t
CKS tCKH
tCMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
t
CMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
COLUMN b(2)
ROW
ROW
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BANK 0
BANK 1
BANK 1
BANK 0
BA0, BA1
BANK 0
tDS
t
DH
t
DS
t
DH
tDS
t
DH
t
DS
t
DH
t
DS
t
DH
tDS
t
DH
tDS
tDH
t
DS
tDH
DQ
DIN
m
D
IN m+
1
D
IN m+
2
D
IN m+
3
D
IN
b
D
IN b+
1
D
IN b+
2
DIN b+3
t
t
t
t
RCD - BANK 0
RRD
t
WR - BANK 0
t
RP - BANK 0
t
RCD - BANK 0
t
RCD - BANK 1
tWR - BANK 1
RAS - BANK 0
RC - BANK 0
DON'T CARE
Notes:
1. burstꢀlengthꢀ=ꢀ4
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"
54
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
WRITE - FULL PAGE BURST
T0
T1
T2
T3
T4
T5
Tn+1
Tn+2
t
CK
t
CL
tCH
CLK
CKE
t
CKS CKH
t
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
BURST TERM
NOP
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
tAH
ROW
AS
tAH
BA0, BA1
BANK
BANK
t
DS
t
DH
t
DS
t
DH
tDS
t
DH
tDS
t
DH
t
DS
t
DH
t
DS
t
DH
D
IN
m
D
IN m+
1
D
IN m+
2
D
IN m+
3
DIN m-1
DQ
t
RCD
Full page completed
DON'T CARE
Notes:
1. burstꢀlengthꢀ=ꢀfullꢀpage
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"
Integrated Silicon Solution, Inc. — www.issi.com
55
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
WRITE - DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
t
CK
t
CL
tCH
CLK
CKE
t
CKS CKH
t
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
tAH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
AS
tAH
BA0, BA1
BANK
BANK
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
DIN
m
D
IN m+
2
DIN m+3
DQ
t
RCD
DON'T CARE
Notes:
1. burstꢀlengthꢀ=ꢀ4
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"
56
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
ORDERING INFORMATION
Commercial Range: 0°C to 70°C
Frequency
Speed (ns)
Order Part No.
Package
200ꢀMHzꢀ
5ꢀ
ꢀ
IS42S16400J-5TLꢀ
IS42S16400J-5BLꢀ
54-PinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballsꢀꢀ
ꢀ
ꢀ
166ꢀMHzꢀ
6ꢀ
ꢀ
IS42S16400J-6TLꢀ
IS42S16400J-6BLꢀ
54-PinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballs
ꢀ
ꢀ
143ꢀMHzꢀ
7ꢀ
ꢀ
IS42S16400J-7TLꢀ
IS42S16400J-7BLꢀ
54-PinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballsꢀꢀ
ꢀ
ꢀ
Industrial Range: -40°C to 85°C
Frequency
200ꢀMHzꢀ
166ꢀMHzꢀ
Speed (ns)
Order Part No.
Package
5ꢀ
IS42S16400J-5BLIꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballs
6ꢀ
ꢀ
IS42S16400J-6TLIꢀ
IS42S16400J-6BLIꢀ
54-PinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballs
ꢀ
ꢀ
143ꢀMHzꢀ
7ꢀ
ꢀ
ꢀ
IS42S16400J-7TLIꢀ
IS42S16400J-7BLIꢀ
IS42S16400J-7B2LIꢀ
54-PinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
ꢀ
ꢀ
ꢀ
ꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballsꢀꢀ
60-ballꢀBGA,ꢀSnAgCuꢀballsꢀ
ꢀ
ꢀ
ꢀ
Automotive Range (A1): -40°C to 85°C
Frequency
Speed (ns)
Order Part No.
Package
200ꢀMHzꢀ
5ꢀ
ꢀ
ꢀ
IS45S16400J-5TLA1ꢀ
IS45S16400J-5CTLA1ꢀ 54-PinꢀTSOPII,ꢀCu leadframe plated with matte Sn
IS45S16400J-5BLA1ꢀ
54-PinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
ꢀ
ꢀ
ꢀ
ꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballs
166ꢀMHzꢀ
6ꢀ
ꢀ
ꢀ
IS45S16400J-6TLA1ꢀ
IS45S16400J-6CTLA1ꢀ 54-PinꢀTSOPII,ꢀCu leadframe plated with matte Sn
IS45S16400J-6BLA1ꢀ
54-PinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
ꢀ
ꢀ
ꢀ
ꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballs
143ꢀMHzꢀ
7ꢀ
ꢀ
ꢀ
IS45S16400J-7TLA1ꢀ
IS45S16400J-7CTLA1ꢀ 54-PinꢀTSOPII,ꢀCu leadframe plated with matte Sn
IS45S16400J-7BLA1ꢀ
54-PinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
ꢀ
ꢀ
ꢀ
ꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballsꢀꢀ
Automotive Range (A2): -40°C to 105°C
Frequency
Speed (ns)
6
Package
OrderꢀPartꢀNo.
166 MHz
54-PinꢀTSOPII,ꢀCuꢀleadframeꢀplatedꢀwithꢀmatteꢀSn
54-ballꢀBGA,ꢀSnAgCuꢀballs
IS45S16400J-6CTLA2
IS45S16400J-6BLA2
IS45S16400J-7TLA2
IS45S16400J-7CTLA2
IS45S16400J-7BLA2
143 MHz
7
54-PinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSn
54-PinꢀTSOPII,ꢀCuꢀleadframeꢀplatedꢀwithꢀmatteꢀSn
54-ballꢀBGA,ꢀSnAgCuꢀballs
Notes:
1. Contact ISSI for leaded and copper leadframe parts support.
2.ꢀPartꢀnumbersꢀwithꢀ"L"ꢀorꢀ"N"ꢀareꢀleadfree,ꢀandꢀRoHSꢀcompliant.
Integrated Silicon Solution, Inc. — www.issi.com
57
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
58
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
Integrated Silicon Solution, Inc. — www.issi.comꢀ
59
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
60
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
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