IS61C3216B-20KI [ETC]

x16 SRAM ; X16 SRAM
IS61C3216B-20KI
型号: IS61C3216B-20KI
厂家: ETC    ETC
描述:

x16 SRAM
X16 SRAM

内存集成电路 静态存储器 光电二极管
文件: 总8页 (文件大小:75K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
IS61C3216B  
ISSI®  
DECEMBER 2000  
32K x 16 HIGH-SPEED CMOS STATIC RAM  
FEATURES  
DESCRIPTION  
The ISSI IS61C3216B is a high-speed, 512K static RAM  
organized as 32,768 words by 16 bits. It is fabricated using  
ISSI's high-performance CMOS technology. This highly reli-  
able process coupled with innovative circuit design tech-  
niques, yields fast access times with low power consumption.  
• High-speed access time: 10, 12, 15, and 20 ns  
• CMOS low power operation  
— 450 mW (typical) operating  
— 250 µW (typical) standby  
• TTL compatible interface levels  
• Single 5V 10% power supply  
• I/O compatible with 3.3V device  
The device is active when CE is HIGH. When CE is LOW  
(deselected), the device assumes a standby mode at which  
the power dissipation can be reduced down to 250 µW  
(typical) with CMOS input levels.  
• Fully static operation: no clock or refresh  
required  
Easy memory expansion is provided by using Chip Enable  
and Output Enable inputs, CE and OE. The active LOW Write  
Enable(WE)controlsbothwritingandreadingofthememory.A  
data byte allows Upper Byte (UB) and Lower Byte (LB)  
access.  
• Three state outputs  
• Industrialtemperatureavailable  
• Available in 44-pin 400-mil SOJ package and  
44-pin TSOP (Type II)  
The IS61C3216B is packaged in the JEDEC standard 44-pin  
400-mil SOJ and 44-pin TSOP (Type II).  
FUNCTIONAL BLOCK DIAGRAM  
32K x 16  
MEMORY ARRAY  
A0-A14  
DECODER  
VCC  
GND  
I/O0-I/O7  
Lower Byte  
I/O  
DATA  
COLUMN I/O  
CIRCUIT  
I/O8-I/O15  
Upper Byte  
CE  
OE  
WE  
CONTROL  
CIRCUIT  
UB  
LB  
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any  
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
12/19/00  
1
IS61C3216B  
ISSI®  
PIN CONFIGURATIONS  
44-Pin SOJ  
44-Pin TSOP (Type II)  
NC  
A14  
A13  
A12  
A11  
CE  
1
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
A0  
NC  
A14  
A13  
A12  
A11  
CE  
I/O0  
I/O1  
I/O2  
I/O3  
Vcc  
GND  
I/O4  
I/O5  
I/O6  
I/O7  
WE  
A10  
A9  
1
2
3
4
5
6
7
8
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
A0  
A1  
A2  
OE  
UB  
LB  
I/O15  
I/O14  
I/O13  
I/O12  
GND  
Vcc  
I/O11  
I/O10  
I/O9  
I/O8  
NC  
2
A1  
3
A2  
4
OE  
5
UB  
6
LB  
I/O0  
I/O1  
I/O2  
I/O3  
Vcc  
GND  
I/O4  
I/O5  
I/O6  
I/O7  
WE  
A10  
A9  
7
I/O15  
I/O14  
I/O13  
I/O12  
GND  
Vcc  
I/O11  
I/O10  
I/O9  
I/O8  
NC  
8
9
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
A3  
A4  
A5  
A6  
A3  
A4  
A8  
A7  
NC  
A8  
A5  
A7  
A6  
NC  
NC  
NC  
PIN DESCRIPTIONS  
LB  
Lower-byte Control (I/O0-I/O7)  
Upper-byte Control (I/O8-I/O15)  
No Connection  
A0-A14  
I/O0-I/O15  
CE  
Address Inputs  
UB  
Data Inputs/Outputs  
Chip Enable Input  
Output Enable Input  
Write Enable Input  
NC  
Vcc  
GND  
Power  
OE  
Ground  
WE  
TRUTH TABLE  
Mode  
WE  
CE  
OE  
LB  
UB  
I/O0-I/O7  
I/O8-I/O15 Vcc Current  
Not Selected  
X
L
X
X
X
High-Z  
High-Z  
ISB1, ISB2  
Output Disabled  
H
X
H
H
H
X
X
H
X
H
High-Z  
High-Z  
High-Z  
High-Z  
ICC  
Read  
Write  
H
H
H
H
H
H
L
L
L
L
H
L
H
L
L
DOUT  
High-Z  
DOUT  
High-Z  
DOUT  
ICC  
DOUT  
L
L
L
H
H
H
X
X
X
L
H
L
H
L
L
DIN  
High-Z  
DIN  
High-Z  
DIN  
ICC  
DIN  
2
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
12/19/00  
IS61C3216B  
ISSI®  
ABSOLUTE MAXIMUM RATINGS(1)  
Note:  
1. Stress greater than those listed under  
ABSOLUTE MAXIMUM RATINGS  
may cause permanent damage to the  
device. This is a stress rating only and  
functional operation of the device at  
these or any other conditions above  
thoseindicatedintheoperationalsec-  
tions of this specification is not im-  
plied. Exposuretoabsolutemaximum  
ratingconditionsforextendedperiods  
may affect reliability.  
Symbol Parameter  
Value  
–0.5 to +7.0  
–0.5 to +7.0  
–65 to +150  
1.5  
Unit  
V
VCC  
VTERM  
TSTG  
PT  
Supply Voltage with Respect to GND  
Terminal Voltage with Respect to GND  
Storage Temperature  
1
V
°C  
W
Power Dissipation  
IOUT  
DC Output Current (LOW)  
20  
mA  
2
OPERATING RANGE  
3
Range  
Ambient Temperature  
Speed  
VCC  
Commercial  
0°C to +70°C  
-10, -12 5V 5%  
-15, -20 5V 10%  
Industrial  
–40°C to +85°C  
-12 5V 5%  
-15, -20 5V 10%  
4
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)  
5
Symbol Parameter  
Test Conditions  
Min.  
2.4  
Max.  
Unit  
V
VOH  
VOL  
VIH  
VIL  
ILI  
Output HIGH Voltage  
VCC = Min., IOH = –4.0 mA  
VCC = Min., IOL = 8.0 mA  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage(1)  
Input Leakage  
0.4  
V
6
2.2  
–0.5  
–2  
VCC + 0.5  
V
0.8  
2
V
GND - VIN - VCC  
µA  
µA  
7
ILO  
Output Leakage  
GND - VOUT - VCC, Outputs Disabled  
–2  
2
Notes:  
1. VIL (min.) = –3.0V for pulse width less than 10 ns.  
8
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)  
9
-10 ns  
-12 ns  
-15 ns  
-20 ns  
Min. Max. Unit  
Symbol Parameter  
Test Conditions  
Min. Max. Min. Max.  
Min. Max.  
ICC  
Vcc Dynamic Operating  
VCC = Max.,  
Com.  
Ind.  
300  
270  
290  
250  
270  
230 mA  
250  
Supply Current  
IOUT = 0 mA, f = fMAX  
10  
11  
12  
ISB1  
TTL Standby Current  
(TTL Inputs)  
VCC = Max.,  
Com.  
Ind.  
40  
40  
45  
40  
45  
40  
45  
mA  
VIN = VIH or VIL  
CE • VIH , f = 0  
ISB2  
CMOS Standby  
VCC = Max.,  
Com.  
Ind.  
5
5
5
5
mA  
Current (CMOS Inputs)  
CE • VCC – 0.2V,  
VIN • VCC – 0.2V, or  
VIN - 0.2V, f = 0  
10  
10  
10  
Note:  
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
12/19/00  
3
IS61C3216B  
ISSI®  
CAPACITANCE(1)  
Symbol  
CIN  
Parameter  
Conditions  
VIN = 0V  
Max.  
Unit  
pF  
Input Capacitance  
6
8
COUT  
Input/Output Capacitance  
VOUT = 0V  
pF  
Note:  
1. Tested initially and after any design or process changes that may affect these parameters.  
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)  
-10  
-12  
-15  
-20  
Symbol  
tRC  
Parameter  
Min. Max.  
Min. Max.  
Min. Max.  
Min. Max.  
Unit  
Read Cycle Time  
10  
3
10  
10  
5
12  
3
12  
12  
5
15  
3
15  
15  
7
20  
3
20  
20  
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address Access Time  
Output Hold Time  
CE Access Time  
tOHA  
tACE  
0
0
0
0
tDOE  
OE Access Time  
(2)  
tHZOE  
OE to High-Z Output  
OE to Low-Z Output  
CE to High-Z Output  
CE to Low-Z Output  
LB, UB Access Time  
LB, UB to High-Z Output  
LB, UB to Low-Z Output  
5
6
7
8
(2)  
tLZOE  
0
5
0
6
0
7
8
(2  
tHZCE  
0
0
0
0
(2)  
tLZCE  
4
5
4
6
4
7
4
8
tBA  
0
0
0
5
tHZB  
tLZB  
5
6
7
8
5
5
5
Notes:  
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of  
0 to 3.0V and output loading specified in Figure 1a.  
2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested.  
3. Not 100% tested.  
AC TEST CONDITIONS  
Parameter  
Unit  
0V to 3.0V  
3 ns  
Input Pulse Level  
Input Rise and Fall Times  
Input and Output Timing  
and Reference Level  
1.5V  
Output Load  
See Figures 1a and 1b  
AC TEST LOADS  
319  
319  
3.3V  
3.3V  
OUTPUT  
OUTPUT  
353 Ω  
353 Ω  
30 pF  
Including  
jig and  
5 pF  
Including  
jig and  
scope  
scope  
Figure 1a.  
Figure 1b.  
4
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
12/19/00  
IS61C3216B  
ISSI®  
AC WAVEFORMS  
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = VIH, OE = VIL, UB or LB = VIL)  
1
tRC  
ADDRESS  
2
tAA  
tOHA  
tOHA  
DATA VALID  
DOUT  
PREVIOUS DATA VALID  
3
4
READ CYCLE NO. 2(1,3)  
t
RC  
5
ADDRESS  
OE  
t
AA  
t
OHA  
6
t
HZOE  
t
DOE  
LZOE  
ACE  
t
CE  
7
t
t
HZCE  
t
LZCE  
LB, UB  
8
t
BA  
t
HZB  
t
LZB  
HIGH-Z  
D
OUT  
DATA VALID  
9
Notes:  
1. WE is HIGH for a Read Cycle.  
2. The device is continuously selected. CE = VIH, OE, UB, or LB = VIL.  
3. Address is valid prior to or coincident with CE HIGH transition.  
10  
11  
12  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
12/19/00  
5
IS61C3216B  
ISSI®  
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)  
-10  
-12  
-15  
-20  
Symbol  
tWC  
Parameter  
Min. Max.  
Min. Max.  
Min. Max.  
Min. Max. Unit  
Write Cycle Time  
CE to Write End  
10  
9
12  
10  
10  
15  
11  
11  
20  
12  
12  
ns  
tSCE  
ns  
ns  
tAW  
Address Setup Time  
to Write End  
9
tHA  
Address Hold from Write End  
Address Setup Time  
1
0
5
1
0
6
1
0
7
1
0
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSA  
tPWB  
tPWE  
tSD  
LB, UB Valid to End of Write  
WE Pulse Width  
9
10  
8
11  
10  
7
12  
11  
8
7
Data Setup to Write End  
Data Hold from Write End  
WE LOW to High-Z Output  
WE HIGH to Low-Z Output  
5
6
tHD  
0
0
0
0
(2)  
tHZWE  
1
1
1
1
(2)  
tLZWE  
Notes:  
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse  
levels of 0 to 3.0V and output loading specified in Figure 1a.  
2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100%  
tested.  
3. The internal write time is defined by the overlap of CE HIGH and UB or LB, and WE LOW. All signals must be  
in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and  
Hold timing are referenced to the rising or falling edge of the signal that terminates the write.  
6
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
12/19/00  
IS61C3216B  
ISSI®  
AC WAVEFORMS  
WRITE CYCLE NO. 1 (WE Controlled)(1)  
1
tWC  
ADDRESS  
CE  
2
tHA  
tSCE  
3
tPWB  
LB, UB  
tAW  
4
tPWE  
WE  
tSA  
5
(1)  
WRITE  
tSD  
tHD  
6
D
IN  
tHZWE  
tLZWE  
HIGH-Z  
HIGH-Z  
7
D
OUT  
UNDEFINED  
UNDEFINED  
Notes:  
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on WE and a HIGH state  
on CE inputs and at least one of the LB and UB inputs being in the LOW state.  
8
9
10  
11  
12  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
12/19/00  
7
IS61C3216B  
ISSI®  
ORDERING INFORMATION  
Commercial Range: 0°C to +70°C  
Speed (ns) Order Part No. Package  
10  
12  
15  
20  
IS61C3216B-10T Plastic TSOP (Type II)  
IS61C3216B-10K 400-mil Plastic SOJ  
IS61C3216B-12T Plastic TSOP (Type II)  
IS61C3216B-12K 400-mil Plastic SOJ  
IS61C3216B-15T Plastic TSOP (Type II)  
IS61C3216B-15K 400-mil Plastic SOJ  
IS61C3216B-20T Plastic TSOP (Type II)  
IS61C3216B-20K 400-mil Plastic SOJ  
Industrial Range: –40°C to +85°C  
Speed (ns) Order Part No. Package  
12  
15  
20  
IS61C3216B-12TI Plastic TSOP (Type II)  
IS61C3216B-12KI 400-mil Plastic SOJ  
IS61C3216B-15TI Plastic TSOP (Type II)  
IS61C3216B-15KI 400-mil Plastic SOJ  
IS61C3216B-20TI Plastic TSOP (Type II)  
IS61C3216B-20KI 400-mil Plastic SOJ  
ISSI®  
IntegratedSiliconSolution,Inc.  
2231 Lawson Lane  
Santa Clara, CA 95054  
Tel: 1-800-379-4774  
Fax: (408) 588-0806  
E-mail: sales@issi.com  
www.issi.com  
8
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
12/19/00  

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