IS61LV6424-10TQI [ETC]
x24 SRAM ; X24 SRAM\n
| 型号： | IS61LV6424-10TQI |
| 厂家： | 
ETC |
| 描述： | x24 SRAM
|
| 文件： | 总10页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISSI®
DECEMBER 2000
IS61LV6424
64K x 24 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
FEATURES
DESCRIPTION
The ISSI IS61LV6424 is a high-speed, static RAM organized
as 65,536 words by 24 bits. It is fabricated using ISSI's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields ac-
cess times as fast as 9 ns with low power consumption.
• High-speed access time: 9, 10, 12, 15 ns
• CMOS low power operation
❑ 594 mW (max.) operating @ 9 ns
❑ 36 mW (max.) CMOS standby
• TTL compatible interface levels
• Single 3.3V power supply
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced down with CMOS input levels.
• Fully static operation: no clock or refresh
required
Easy memory expansion is provided by using Chip Enable
andOutputEnableinputs,CE1,CE2,andOE.TheactiveLOW
Write Enable (WE) controls both writing and reading of the
memory.
• Three state outputs
• Available in 100-pin TQFP
• Industrial temperature available
The IS61LV6424 is packaged in the JEDEC standard
100-pin TQFP
FUNCTIONAL BLOCK DIAGRAM
V
CC
GND
64K x 24
MEMORY ARRAY
ROW
DECODER
A0-A14
A15
X/Y
V/S
MULTIPLEX
ADDRESS
CONTROL
COLUMN
DECODER
CE1
CE2
OE
CONTROL
CIRCUIT
I/O DATA
I/O0-I/O23
CIRCUIT
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
1
ISSI®
IS61LV6424
PIN CONFIGURATION
100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
NC
NC
NC
NC
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
I/O12
I/O13
I/O14
I/O15
GNDQ
I/O11
I/O10
I/O9
I/O8
GNDQ
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
CCQ
VCCQ
I/O16
I/O17
NC
I/O7
I/O6
GND
NC
VCC
NC
GND
I/O18
I/O19
VCC
NC
I/O5
I/O4
V
CCQ
VCCQ
GNDQ
I/O20
I/O21
I/O22
I/O23
NC
GNDQ
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PIN DESCRIPTIONS
A0-A14Address
Inputs
A15, X/Y
I/O0-I/O23
CE1, CE2
OE
Multiplexed Address
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Address Multiplexer
No Connection
WE
V/S
NC
VCC
Power
VCCQ
Isolated Output Buffer Supply
Ground
GND
GNDQ
Isolated Output Buffer Ground
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
ISSI®
IS61LV6424
TRUTH TABLE
Mode
CE1
CE2
OE
WE
V/S
I/O0-I/O23
Vcc Current
Not Selected
H
X
X
L
X
X
X
X
X
X
High-Z
High-Z
ISB1, ISB2
1
Read Using X/Y
Read Using A15
Write Using X/Y
Write Using A15
Output Disable
L
L
L
L
L
H
H
H
H
H
L
L
H
H
L
H
L
DOUT
DOUT
DIN
ICC
ICC
ICC
ICC
ICC
X
X
H
H
L
2
L
DIN
H
X
High-Z
3
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VCC
Parameter
Value
Unit
V
4
Power Supply Voltage Relative to GND
Terminal Voltage with Respect to GND
Storage Temperature
–0.5 to 5.0
–0.5 to Vcc + 0.5
–65 to + 150
VTERM
TSTG
V
°C
5
TBIAS
Temperature Under Bias:
Com.
Ind.
–10 to + 85
–45 to + 90
°C
°C
PT
Power Dissipation
DC Output Current
2.0
20
W
IOUT
mA
6
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
7
OPERATING RANGE
Range
Ambient Temperature
0°C to +70°C
VCC (9, 10 ns)
3.3V + 10%, – 5%
3.3V + 10%, – 5%
VCC (12, 15 ns)
3.3V 10%
8
Commercial
Industrial
–40°C to +85°C
3.3V 10%
9
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
2.4
mA
2.2
–0.3
–1
Max.
Unit
10
11
12
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
—
V
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
VCC = Min., IOL
=
8.0
—
VCC + 0.3
V
V
0.8
1
GND - VIN - VCC
µA
µA
ILO
Output Leakage
GND - VOUT - VCC, Outputs Disabled
–1
1
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns).
VIH (max.) = VCC + 0.3V DC; VIH (max.) = VCC + 2.0V AC (pulse width - 2.0 ns).
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
3
ISSI®
IS61LV6424
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-9 ns
-10ns
Min. Max.
-12 ns
-15 ns
Min. Max. Unit
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
ICC
Vcc Dynamic Operating VCC = Max.,
Com.
Ind.
—
—
165
170
—
—
150
155
—
—
125
130
—
—
100
105
mA
Supply Current
IOUT = 0 mA, f = fMAX
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
Com.
—
40
—
40
—
4
35
0
—
—
30
25
mA
VIN m=aVx=IH. orf VIL, Ind.
CE1 • VIH, CE2 - VIL
—
4
5
—
4
5
—
ISB2
CMOS Standby
VCC = Max.,
Com.
Ind.
—
—
10
15
—
—
10
15
—
—
10
15
—
—
10
15
mA
Current (CMOS Inputs) CE1 • VCC – 0.2V,
CE2 - 0.2V, VIN • VCC – 0.2V,
or VIN - 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
Input Capacitance
Input/Output Capacitance
6
8
COUT
VOUT = 0V
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
2 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1 and 2
AC TEST LOADS
319 Ω
3.3V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
353 Ω
5 pF
Including
jig and
scope
1.5V
Figure 1
Figure 2
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
ISSI®
IS61LV6424
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-9
-10
-12
-15
Symbol Parameter
Min. Max.
Min. Max.
Min.
12
—
Max.
—
Min. Max.
Unit
ns
1
tRC
tAA
tAV
tOH
Read Cycle Time
9
—
—
3
—
9
10
—
—
3
—
10
10
—
15
—
—
3
—
15
15
—
Address Access Time
12
ns
2
V/S Access Time
9
—
12
ns
Output Hold Time
From MUX Change
—
3
—
ns
tOHA
Output Hold Time
3
—
9
3
—
10
3
—
3
—
15
ns
ns
3
From Address Change
tACE
CE1Access Time
—
—
—
12
—
tACE2
CE2 Access Time
4
tDOE
OE Access Time
—
0
5
3
—
0
5
3
—
0
6
3
—
0
7
3
ns
ns
ns
ns
(2)
tHZOE
OE to High-Z Output
OE to Low-Z Output
CE1 to High-Z Output
(2)
tLZOE
0
—
5
0
—
5
0
—
6
0
—
7
5
(2)
tHZCE
0
0
0
0
tHZCE2(2) CE2 to High-Z Output
(2)
tLZCE
CE to Low-Z Output
3
—
3
—
3
—
3
—
ns
tLZCE2(2) CE2 to Low-Z Output
6
Notes:
1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested.
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
5
ISSI®
IS61LV6424
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE1= OE = VIL; CE2 = VIH
)
t
RC
ADDRESS
V/S
t
AV
t
OH
t
AA
t
OHA
t
OHA
DATA VALID
PREVIOUS DATA VALID
DOUT
6424RD1.eps
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
LZOE
t
CE1
CE2
t
AV
V/S
t
tAACCEE21
t
tHHZZCCEE21
t
tLLZZCCEE21
HIGH-Z
D
OUT
DATA VALID
6424CE2_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1= VIL. CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transition.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
ISSI®
IS61LV6424
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-9
-10
-12
-15
Symbol Parameter
Min. Max.
Min. Max.
Min.
Max.
Min. Max.
Unit
ns
1
2
3
4
5
6
7
8
9
tWC
Write Cycle Time
9
—
10
—
12
—
15
—
tSCE
CE1 to Write End
CE2 to Write End
7
7
—
—
7
7
—
—
8
8
—
—
10
10
—
—
ns
tSCE
2
tAW
Address Setup Time
to Write End
7
—
7
—
8
—
10
—
ns
tHA
Address Hold from Write End
Address Setup Time
0
0
0
7
9
5
7
0
—
—
—
—
—
—
—
—
0
0
—
—
—
—
—
—
—
—
0
0
—
—
—
—
—
—
—
—
4—
—
0
0
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
6
tSA
tVS
V/S Setup Time
0
0
0
tPWE1
tPWE2
tSD
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
V/S to Write End
7
8
10
15
7
10
5
12
6
tVW
7
8
10
0
tHD
Data Hold from Write End
0
0
(2)
tHZWE
WE
LOW
to
High-Z
Output
—
3
5
—
—
7
ns
(2)
tLZWE
WE HIGH to Low-Z Output
3
—
3
—
3
—
ns
Notes:
1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1, LOW, CE2 HIGH and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write.
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
7
ISSI®
IS61LV6424
WRITE CYCLE NO. 1(CE Controlled, OE = HIGH or LOW)
t
WC
VALID ADDRESS
ADDRESS
CE1
t
tSSCCEE21
t
t
SA
t
HA
CE2
t
VW
VS
V/S
WE
t
AW
t
tPPWWEE21
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
6424CE2_WR1.eps
WRITE CYCLE NO. 2(1) (WE Controlled: OE = HIGH during Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
HIGH
CE1
CE2
t
VW
t
VS
V/S
WE
t
AW
t
PWE1
t
HZWE
t
LZWE
t
SA
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
D
IN
6424CE2_WR2.eps
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
ISSI®
IS61LV6424
WRITE CYCLE NO. 3(1) (WE Controlled: OE I S LOW DURING
WRITE CYLE)
t
WC
ADDRESS
1
VALID ADDRESS
t
HA
LOW
OE
CE1
CE2
2
LOW
HIGH
t
t
VW
3
V/S
WE
AW
t
PWE2
4
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
5
t
SD
t
HD
DATAIN VALID
DIN
6
6424CE2_WR3.eps
Note:
1. The internal Write time is defined by the overlap of CE1 = LOW, CE2 = HIGH and WE = LOW. All signals must be in valid
states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is
referenced to the rising or falling edge of the signal that terminates the Write.
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
9
ISSI®
IS61LV6424
ORDERING INFORMATION
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No.
Package
TQFP
TQFP
TQFP
TQFP
Speed (ns) Order Part No.
Package
TQFP
9
IS61LV6424-9TQ
IS61LV6424-10TQ
IS61LV6424-12TQ
IS61LV6424-15TQ
9
IS61LV6424-9TQI
IS61LV6424-10TQI
IS61LV6424-12TQI
IS61LV6424-15TQI
10
12
15
10
12
15
TQFP
TQFP
TQFP
ISSI®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
相关型号：
©2020 ICPDF网 联系我们和版权申明