IS61LV6424-15TQ_技术文档

IS61LV6424

64K x 24 HIGH-SPEED CMOS STATIC RAM

WITH 3.3V SUPPLY

FEATURES

DESCRIPTION

The ICSI IS61LV6424 is a high-speed, static RAM organized

as 65,536 words by 24 bits. It is fabricated using ICSI's high-

performance CMOS technology. This highly reliable process

coupled with innovative circuit design techniques, yields ac-

cess times as fast as 9 ns with low power consumption.

• High-speed access time: 9, 10, 12, 15 ns

• CMOS low power operation

— 594 mW (max.) operating @ 9 ns

— 36 mW (max.) CMOS standby

• TTL compatible interface levels

• Single 3.3V power supply

When CE1 is HIGH and CE2 is LOW (deselected), the device

assumes a standby mode at which the power dissipation can

be reduced down with CMOS input levels.

• Fully static operation: no clock or refresh

required

Easy memory expansion is provided by using Chip Enable and

Output Enable inputs, CE1, CE2, and OE. The active LOW

Write Enable (WE) controls both writing and reading of the

memory.

• Three state outputs

• Available in 100-pin LQFP

The IS61LV6424 is packaged in the JEDEC standard

100-pin 14*20*1.4mm LQFP.

FUNCTIONAL BLOCK DIAGRAM

V

CC

GND

64K x 24

MEMORY ARRAY

ROW

DECODER

A0-A14

A15

X/Y

V/S

MULTIPLEX

ADDRESS

CONTROL

COLUMN

DECODER

CE1

CE2

OE

CONTROL

CIRCUIT

I/O DATA

I/O0-I/O23

CIRCUIT

WE

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

Integrated Circuit Solution Inc.

AHSR012-0D

S2-95

IS61LV6424

PIN CONFIGURATION

100-Pin LQFP

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

100

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

NC

I/O12

I/O13

I/O14

I/O15

GNDQ

NC

I/O11

I/O10

I/O9

I/O8

GNDQ

VCCQ

V

CCQ

I/O7

I/O6

GND

NC

I/O16

I/O17

NC

V

CC

VCC

NC

GND

I/O18

I/O19

NC

I/O5

I/O4

VCCQ

V

CCQ

GNDQ

I/O3

I/O2

I/O1

I/O0

NC

GNDQ

I/O20

I/O21

I/O22

I/O23

NC

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

PIN DESCRIPTIONS

A0-A14

Address Inputs

A15, X/Y Multiplexed Address

I/O0-I/O23Data Inputs/Outputs

CE1, CE2 Chip Enable Input

OE

Output Enable Input

Write Enable Input

Address Multiplexer

No Connection

Power

WE

V/S

NC

Vcc

VCCQ

GND

GNDQ

Isolated Output Buffer Supply

Ground

solated Output Buffer Ground

S2-96

Integrated Circuit Solution Inc.

AHSR012-0D

IS61LV6424

TRUTH TABLE

Mode

CE1

CE2

OE

WE

V/S

I/O0-I/O23

Vcc Current

1

Not Selected

H

X

H

X

High-Z

ISB1, ISB2

Read Using X/Y

Read Using A15

Write Using X/Y

Write Using A15

Output Disable

L

H

L

H

L

H

L

DOUT

DIN

ICC

2

X

H

L

DIN

H

X

High-Z

3

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Symbol

VCC

Parameter

Value

Unit

V

4

Power Supply Voltage Relative to GND

Terminal Voltage with Respect to GND

Storage Temperature

–0.5 to 5.0

–0.5 to Vcc + 0.5

–65 to + 150

VTERM

TSTG

V

°C

5

T^BIAS

Temperature Under Bias:

Com.

Ind.

–10 to + 85

–45 to + 90

°C

PT

Power Dissipation

DC Output Current

2.0

20

W

IOUT

Note:

mA

6

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these or

any other conditions above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

7

OPERATING RANGE

Range

Ambient Temperature

0°C to +70°C

VCC (9, 10 ns)

3.3V + 10%, – 5%

VCC (12, 15 ns)

3.3V 10%

8

Commercial

Industrial

–40°C to +85°C

3.3V 10%

9

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter

Test Conditions

Min.

2.4

Max.

—

Unit

V

10

VOH

VOL

VIH

Output HIGH Voltage

VCC = Min., IOH = –4.0 mA

VCC = Min., IOL = 8.0 mA

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage⁽¹⁾

Input Leakage

—

0.4

V

_0.3V11

12

2.2

VCC

+

VIL

–0.30.8

–1

V

ILI

GND ≤ VIN ≤ VCC

1

µA

ILO

Output Leakage

GND ≤ VOUT ≤ VCC, Outputs Disabled

–1

Note:

1. V^IL(min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width ≤ 2.0 ns).

V^IH(max.) = VCC + 0.3V DC; VIH (max.) = VCC + 2.0V AC (pulse width ≤ 2.0 ns).

Integrated Circuit Solution Inc.

AHSR012-0D

S2-97

IS61LV6424

POWER SUPPLY CHARACTERISTICS⁽¹⁾(Over Operating Range)

-9 ns

-10ns

-12 ns

-15 ns

Symbol Parameter

Test Conditions

CC = Max.,

OUT = 0 mA, f = fMAX

Min. Max.

Unit

I

CC

Vcc Dynamic Operating

Supply Current

V

Com.

Ind.

—

165

170

—

150

155

—

125

130

—

100

105

mA

I

SB

1

2

TTL Standby Current

(TTL Inputs)

V

CC = Max.,

Com.

Ind.

—

40

45

—

40

45

—

35

40

—

30

25

mA

VIN = VIH or VIL, f = max.

CE1 > VIH, CE2 < VIL

ISB

CMOS Standby

VCC = Max.,

Com.

Ind.

—

10

15

—

10

15

—

10

15

—

10

15

Current (CMOS Inputs) CE1 > VCC – 0.2V,

CE2 < 0.2V, VIN > VCC – 0.2V,

or VIN < 0.2V, f = 0

Note:

1. At f = f^MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

CAPACITANCE⁽¹⁾

Symbol

CIN

Parameter

Conditions

VIN = 0V

Max.

Unit

pF

Input Capacitance

Input/Output Capacitance

6

8

COUT

VOUT = 0V

pF

Note:

1. Tested initially and after any design or process changes that may affect these parameters.

AC TEST CONDITIONS

Parameter

Unit

0V to 3.0V

2 ns

Input Pulse Level

Input Rise and Fall Times

Input and Output Timing

and Reference Level

1.5V

Output Load

See Figures 1 and 2

AC TEST LOADS

319 Ω

ZO = 50Ω

3.3V

OUTPUT

50Ω

353 Ω

5 pF

Including

jig and

scope

1.5V

Figure 1

Figure 2

S2-98

Integrated Circuit Solution Inc.

AHSR012-0D

IS61LV6424

READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾(Over Operating Range)

-9

-10

-12

-15

Symbol Parameter

Min. Max.

Min.

12

Max.

—

Min. Max.

Unit

ns

1

tRC

tAA

tAV

tOH

Read Cycle Time

Address Access Time

V/S Access Time

9

—

9

10

—

10

15

—

15

—

12

ns

2

9

10

—

12

ns

Output

Hold

Time

3—

3 —

12

3—

ns

From MUX Change

t

OHA

Output Hold

3—

10

5

3—

—

3

From Address Change

t

ACE

CE1Access Time

—

9

5

—

15

ns

ACE

2

CE2 Access Time

4

t

DOE

OE Access Time

—

30

0

6

—

7

(2)

HZOE

OE

to

High-Z

Output

0

30

3ns

—

7

(2)

LZOE

OE to Low-Z Output

0

—

5

0

—

5

—

6

0

ns

5

(2)

t

HZCE

CE1 to High-Z Output

0

HZCE2⁽²⁾CE2 to High-Z Output

(2)

t

LZCE

CE

to

Low-Z

Output

3—

3

—

3—

ns

LZCE2⁽²⁾CE2 to Low-Z Output

6

Notes:

1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V

and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested.

7

8

9

10

11

12

Integrated Circuit Solution Inc.

AHSR012-0D

S2-99

IS61LV6424

AC WAVEFORMS

READ CYCLE NO. 1^(1,2)(Address Controlled) (CE1= OE = VIL; CE2 = VIH

)

t

RC

ADDRESS

V/S

t

AV

t

OH

t

AA

t

OHA

t

OHA

DATA VALID

PREVIOUS DATA VALID

DOUT

READ CYCLE NO. 2^(1,3)

t

RC

ADDRESS

OE

t

AA

t

OHA

t

HZOE

t

DOE

LZOE

t

CE1

CE2

t

AV

V/S

t

ACE1

ACE2

t

HZCE1

HZCE2

t

LZCE1

LZCE2

HIGH-Z

D

OUT

DATA VALID

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE1= V^IL. CE2 = VIH.

3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transition.

S2-100

Integrated Circuit Solution Inc.

AHSR012-0D

IS61LV6424

WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3)(Over Operating Range)

-9

-10

-12

-15

Symbol Parameter

Min. Max.

Min.

Max.

Min. Max.

Unit

ns

1

t

WC

Write Cycle Time

9

—

10

—

12

—

15

—

SCE

CE1 to Write End

7

—

7

—

8

—

10

—

ns

tSCE2

CE2 to Write End

2

tAW

Address Setup Time

to Write End

7

—

7

—

8

—

10

—

ns

t

HA

Address Hold from Write End

Address Setup Time

0

—

4

0

—

5

0

—

6

0

—

7

ns

SA

0

3

VS

V/S Setup Time

0

PWE

SD

1

WE Pulse Width (OE = HIGH)

WE Pulse Width (OE = LOW)

Data Setup to Write End

V/S to Write End

7

8

10

15

7

2

9

10

5

12

6

4

5

7

VW

HD

7

8

10

0

5

Data Hold from Write End

WE LOW to High-Z Output

0

(2)

HZWE

—

3—

—

(2)

LZWE

WE

HIGH

to

Low-Z

Output

3—

3

—

3—

Notes:

6

1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V

and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of CE1, LOW, CE2 HIGH and WE LOW. All signals must be in valid states

to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced

to the rising or falling edge of the signal that terminates the write.

7

8

9

10

11

12

Integrated Circuit Solution Inc.

AHSR012-0D

S2-101

IS61LV6424

WRITE CYCLE NO. 1(CE Controlled, OE = HIGH or LOW)

t

WC

VALID ADDRESS

ADDRESS

CE1

t

SCE1

SCE2

t

SA

t

HA

CE2

t

VW

VS

V/S

WE

t

AW

t

PWE1

PWE2

t

HZWE

t

LZWE

HIGH-Z

DATA UNDEFINED

DOUT

t

SD

t

HD

DATAIN VALID

DIN

WRITE CYCLE NO. 2⁽¹⁾(WE Controlled: OE = HIGH during Write Cycle)

t

WC

ADDRESS

OE

VALID ADDRESS

t

HA

LOW

HIGH

CE1

CE2

t

VW

t

VS

V/S

WE

t

AW

t

PWE1

t

HZWE

t

LZWE

t

SA

HIGH-Z

DATA UNDEFINED

DOUT

t

SD

t

HD

DATAIN VALID

DIN

S2-102

Integrated Circuit Solution Inc.

AHSR012-0D

IS61LV6424

WRITE CYCLE NO. 3⁽¹⁾(WE Controlled: OE I S LOW DURING

WRITE CYLE)

t

WC

1

ADDRESS

VALID ADDRESS

t

HA

LOW

OE

CE1

CE2

2

LOW

HIGH

t

VW

3

V/S

WE

AW

t

PWE2

4

t

SA

t

HZWE

t

LZWE

HIGH-Z

DATA UNDEFINED

DOUT

5

t

SD

t

HD

DATAIN VALID

DIN

6

Note:

1. The internal Write time is defined by the overlap of CE1 = LOW, CE2 = HIGH and WE = LOW. All signals must be in valid

states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is

referenced to the rising or falling edge of the signal that terminates the Write.

7

8

9

10

11

12

Integrated Circuit Solution Inc.

AHSR012-0D

S2-103

IS61LV6424

ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Speed (ns) Order Part No.

Package

9

IS61LV6424-9TQ

IS61LV6424-10TQ

IS61LV6424-12TQ

IS61LV6424-15TQ

14*20*1.4mm LQFP

10

12

15

Integrated Circuit Solution Inc.

HEADQUARTER:

NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,

HSIN-CHU, TAIWAN, R.O.C.

TEL: 886-3-5780333

Fax: 886-3-5783000

BRANCH OFFICE:

7F, NO. 106, SEC. 1, HSIN-TAI 5^THROAD,

HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.

TEL: 886-2-26962140

FAX: 886-2-26962252

http://www.icsi.com.tw

S2-104

Integrated Circuit Solution Inc.

AHSR012-0D


型号：	IS61LV6424-15TQ
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	64K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY 64K ×24高速CMOS静态RAM与3.3V电源
文件：	总10页 (文件大小：138K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IS61LV6424-15TQ [ICSI]

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