ISPLSI1048-80LQ [ETC]
Electrically-Erasable Complex PLD ; 电可擦除可编程逻辑器件复杂\n
| 型号： | ISPLSI1048-80LQ |
| 厂家： | 
ETC |
| 描述： | Electrically-Erasable Complex PLD
|
| 文件： | 总12页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ispLSI 1048
In-System Programmable High Density PLD
Features
Functional Block Diagram
• HIGH-DENSITY PROGRAMMABLE LOGIC
— 8000 PLD Gates
Output Routing Pool
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
E7 E6 E5 E4 E3 E2 E1 E0
— 96 I/O Pins, Ten Dedicated Inputs
— 288 Registers
— High-Speed Global Interconnects
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Security Cell Prevents Unauthorized Copying
A0
A1
A2
A3
A4
A5
A6
A7
D7
D6
D5
D4
D3
D2
D1
D0
D
D
D
D
Q
Q
Q
Q
Logic
Array
Global Routing Pool (GRP)
GLB
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 80 MHz Maximum Operating Frequency
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool
CLK
—— tfpmdax= =1550nsMPHrzofpoargIantdiounstDrieallaDyevices
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested
Description
The ispLSI 1048 is a High-Density Programmable Logic
Device which contain 288 Registers, 96 Universal I/O
pins, ten Dedicated Input pins, four Dedicated Clock
Input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 1048 features 5-Volt in-system
programming and in-system diagnostic capabilities. It is
thefirstdevicewhichoffersnon-volatilereprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
The basic unit of logic on the ispLSI 1048 devices is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. F7 (see figure 1). There are a total of 48 GLBs in the
ispLSI 1048 device. Each GLB has 18 inputs, a program-
mable AND/OR/XOR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
other GLB on the device.
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Copyright©1999LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2000
1048_06
1
Specifications ispLSI 1048
Functional Block Diagram
Figure 1. ispLSI 1048 Functional Block Diagram
I/O I/O I/OI/O
95 94 93 92
I/O I/OI/OI/O
91 90 89 88
I/O I/O I/O I/O
87 86 85 84
I/O I/O I/O I/O
83 82 81 80
IN IN
11 10
I/O I/O I/OI/O
79 78 77 76
I/O I/OI/OI/O
75 74 73 72
I/O I/O I/O I/O
71 70 69 68
I/O I/O I/O I/O
67 66 65 64
IN
8
RESET
Input Bus
Output Routing Pool (ORP)
Input Bus
Output Routing Pool (ORP)
Generic
Logic Blocks
(GLBs)
IN 7
IN 6
F7
F6
F5
F4
F3
F2
F1
F0
E7
E6
E5
E4
E3
E2
E1
E0
I/O 6
I/O 6
I/O 6
I/O 6
D7
D6
D5
D4
I/O 0
I/O 1
I/O 2
I/O 3
A0
A1
A2
A3
I/O 5
I/O 5
I/O 5
I/O 4
I/O 5
I/O 6
I/O 7
Global
Routing
Pool
I/O 5
I/O 5
I/O 5
I/O 5
I/O 5
D3
D2
D1
D0
I/O 8
A4
A5
A6
A7
(GRP)
I/O 9
I/O 10
I/O 11
I/O 5
I/O 5
I/O 4
I/O 4
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
CLK 0
B0
B1
B2
B3
B4
B5
B6
B7
C0
C1
C2
C3
C4
C5
C6
C7
CLK 1
CLK 2
MODE/IN 1
Clock
Distribution
Network
IOCLK 0
IOCLK 1
Output Routing Pool (ORP)
Input Bus
Output Routing Pool (ORP)
Input Bus
Megablock
ispEN
SDO/ I/O I/O I/O I/O
IN3
16 17 18 19
I/O I/O I/O I/O
20 21 22 23
I/O I/O I/O I/O
24 25 26 27
I/O I/O I/O I/O
28 29 30 31
IN SCLK/ I/O I/O I/O I/O
IN 5 32 33 34 35
I/O I/O I/O I/O
36 37 38 39
I/O I/O I/O I/O
40 41 42 43
I/O I/O I/O I/O
44 45 46 47
Y
0
Y
1
Y
2
Y
3
4
0139F(1)-48-isp
The device also has 96 I/O cells, each of which is directly TheGRPhasasitsinputstheoutputsfromalloftheGLBs
connected to an I/O pin. Each I/O cell can be individually and all of the inputs from the bi-directional I/O cells. All of
programmed to be a combinatorial input, registered in- these signals are made available to the inputs of the
put, latched input, output or bi-directional GLBs. Delays through the GRP have been equalized to
I/O pin with 3-state control. Additionally, all outputs are minimize timing skew.
polarity selectable, active high or active low. The signal
Clocks in the ispLSI 1048 device are selected using the
levelsareTTLcompatiblevoltagesandtheoutputdrivers
Clock Distribution Network. Four dedicated clockpins
can source 4 mA or sink 8 mA.
(Y0, Y1, Y2 and Y3) are brought into the distribution
Eight GLBs, 16 I/O cells, two dedicated inputs (one network, and five clock outputs (CLK 0, CLK 1, CLK 2,
dedicated input in Megablock B and E) and one ORP are IOCLK 0 and IOCLK 1) are provided to route clocks to the
connected together to make a Megablock (see figure 1). GLBs and I/O cells. The Clock Distribution Network can
The outputs of the eight GLBs are connected to a set of also be driven from a special clock GLB (D0 on the
16 universal I/O cells by the ORP. The ispLSI 1048 ispLSI1048device). ThelogicofthisGLBallowstheuser
device contains six of these Megablocks.
to create an internal clock from a combination of internal
signals within the device.
2
Specifications ispLSI 1048
1
Absolute Maximum Ratings
Supply Voltage V .................................. -0.5 to +7.0V
cc
Input Voltage Applied........................ -2.5 to V +1.0V
CC
Off-State Output Voltage Applied ..... -2.5 to V +1.0V
CC
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T ) with Power Applied ... 150°C
J
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
PARAMETER
MIN.
MAX.
5.25
UNITS
Commercial TA = 0°C to +70°C
4.75
4.5
V
Supply Voltage
VCC
5.5
Industrial
TA = -40°C to +85°C
VIL
VIH
Input Low Voltage
Input High Voltage
0.8
V
V
0
2.0
Vcc + 1
Capacitance (TA=25oC, f=1.0 MHz)
1
SYMBOL
PARAMETER
MAXIMUM
UNITS
TEST CONDITIONS
C1
C2
Dedicated Input Capacitance
I/O and Clock Capacitance
8
pf
pf
VCC=5.0V, VIN=2.0V
10
VCC=5.0V, VI/O, VY=2.0V
1. Guaranteed but not 100% tested.
Data Retention Specifications
PARAMETER
Data Retention
MINIMUM
20
MAXIMUM
UNITS
Years
Cycles
—
—
Erase/Reprogram Cycles
10000
Table 2- 0008B
3
Specifications ispLSI 1048
Switching Test Conditions
Figure 2. Test Load
Input Pulse Levels
GND to 3.0V
≤ 3ns 10% to 90%
1.5V
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
+ 5V
1.5V
R
1
See figure 2
Device
Output
Test
Point
3-state levels are measured 0.5V from steady-state
active level.
Table 2- 0003
R
2
C *
L
Output Load Conditions (see figure 2)
*
C includes Test Fixture and Probe Capacitance.
L
Test Condition
R1
R2
CL
A
470Ω
390Ω
390Ω
390Ω
390Ω
35pF
35pF
35pF
5pF
B
Active High
Active Low
∞
470Ω
Active High to Z
at VOH - 0.5V
∞
C
Active Low to Z
470Ω
390Ω
5pF
at VOL + 0.5V
DC Electrical Characteristics
Over Recommended Operating Conditions
3
SYMBOL
PARAMETER
CONDITION
MIN. TYP.
MAX.
UNITS
V
Output Low Voltage
–
2.4
–
–
–
0.4
–
IOL =8 mA
V
V
OL
V
Output High Voltage
IOH =-4 mA
OH
µA
0V ≤ VIN ≤ VIL (MAX.)
3.5V ≤ VIN ≤ VCC
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
isp Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
–
-10
10
I
I
I
I
I
IL
µA
–
–
IH
µA
0V ≤ VIN ≤ VIL (MAX.)
0V ≤ VIN ≤ VIL
–
–
-150
-150
-200
235
260
IL-isp
IL-PU
µA
–
–
mA
mA
mA
VCC = 5V, VOUT = 0.5V
VIL = 0.5V, VIH = 3.0V Commercial
1
–
–
OS
2,4
–
165
165
I
CC
fTOGGLE = 1 MHz
Industrial
–
1. One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2. Measured using twelve 16-bit counters.
3. Typical values are at VCC = 5V and TA = 25oC.
4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec-
tion of this datasheet and Thermal Management section of this Lattice Semiconductor Data Book or CD-ROM to estimate maximum
Table 2- 0007A-48-isp
ICC.
4
Specifications ispLSI 1048
External Timing Parameters
Over Recommended Operating Conditions
-80
-70
-50
5
2
1
TEST
PARAMETER
#
DESCRIPTION
UNITS
COND.
MIN. MAX. MIN. MAX. MIN. MAX.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
–
–
–
–
1
Data Propagation Delay, 4PT bypass, ORP bypass
Data Propagation Delay, Worst Case Path
–
–
15
20
–
–
–
18
23
–
–
–
24
30.7
–
t
pd1
ns
ns
2
3
4
5
6
7
8
9
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
pd2
3
Clock Frequency with Internal Feedback
80
50
100
7
71.4
41.7
83
9
53.6
31.3
71.4
12
–
MHz
MHz
MHz
ns
max (Int.)
1
Clock Frequency with External Feedback
–
–
–
max (Ext.)
(
)
tsu2 + tco1
4
Clock Frequency, Max Toggle
–
–
–
max (Tog.)
su1
co1
h1
GLB Reg. Setup Time before Clock, 4PT bypass
GLB Reg. Clock to Output Delay, ORP bypass
GLB Reg. Hold Time after Clock, 4 PT bypass
GLB Reg. Setup Time before Clock
–
–
–
–
10
–
–
12
–
16
–
ns
0
0
0
ns
10
–
–
12
–
–
16
–
–
su2
co2
h2
ns
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
12
–
14
–
18.7
–
ns
0
0
0
ns
–
17
–
–
17
–
–
22.7
–
r1
ns
10
–
10
–
13
–
rw1
en
ns
14 Input to Output Enable
18
18
–
20
20
–
26.7
26.7
–
ns
15 Input to Output Disable
–
–
–
dis
ns
16 Ext. Sync. Clock Pulse Duration, High
17 Ext. Sync. Clock Pulse Duration, Low
5
6
7
wh
ns
5
–
6
–
7
–
wl
ns
18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)
19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
2
–
2
–
2.7
8.7
–
su5
h5
ns
6.5
–
6.5
–
–
ns
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit loadable counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions section.
Table 2- 0030A-48/80,70,50
5
Specifications ispLSI 1048
1
Internal Timing Parameters
-80
-70
-50
2
PARAMETER
DESCRIPTION
UNITS
#
MIN. MAX. MIN. MAX.
MIN. MAX.
Inputs
–
–
2.5
3.3
–
–
–
3.0
4.0
–
t
t
t
t
t
t
t
iobp
iolat
iosu
ioh
I/O Register Bypass
–
–
4.0
5.3
–
20
21
22
23
24
25
26
ns
ns
ns
ns
ns
ns
ns
I/O Latch Delay
5.3
1.5
–
6.0
0.5
–
I/O Register Setup Time before Clock
I/O Register Hold Time after Clock
I/O Register Clock to Out Delay
I/O Register Reset to Out Delay
Dedicated Input Delay
8.1
0.9
–
–
–
–
2.5
2.9
5.0
3.0
3.5
6.0
ioco
ior
3.9
4.6
8.0
–
–
–
–
–
din
–
GRP
–
–
–
–
–
–
2.1
2.5
–
–
–
–
–
–
2.5
3.0
t
t
t
t
t
t
grp1
GRP Delay, 1 GLB Load
GRP Delay, 4 GLB Loads
GRP Delay, 8 GLB Loads
GRP Delay, 12 GLB Loads
GRP Delay, 16 GLB Loads
GRP Delay, 48 GLB Loads
–
–
–
–
–
–
3.3
4.0
27
28
29
30
31
32
ns
ns
ns
ns
ns
ns
grp4
3.3
4.0
grp8
5.3
4.2
5.0
grp12
grp16
grp48
6.7
5.0
6.0
8.0
13.3
16.0
21.3
GLB
–
–
5.4
6.5
7.6
8.4
0.8
–
–
–
6.5
7.0
7.5
9.5
1.0
–
t
t
t
t
t
t
t
t
t
t
t
t
4ptbp
1ptxor
20ptxor
xoradj
gbp
4 Product Term Bypass Path Delay
1 Product Term/XOR Path Delay
20 Product Term/XOR Path Delay
–
–
8.6
9.3
10.0
12.7
1.3
–
33
34
35
36
37
38
39
40
41
42
43
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
3
–
–
XOR Adjacent Path Delay
–
–
–
GLB Register Bypass Delay
–
0.8
5.0
–
1.5
6.0
–
gsu
GLB Register Setup Time before Clock
GLB Register Hold Time after Clock
GLB Register Clock to Output Delay
GLB Register Reset to Output Delay
GLB Product Term Reset to Register Delay
GLB Product Term Output Enable to I/O Cell Delay
GLB Product Term Clock Delay
2.0
8.0
–
–
–
gh
–
2.1
2.1
8.3
8.8
2.5
2.5
10.0
9.0
gco
3.3
3.3
13.3
11.9
–
–
gr
–
–
–
ptre
–
–
–
ptoe
ptck
–
2.9 6.3 3.5 7.5
4.6 9.9
ORP
–
–
3.2
1.3
–
–
3.5
1.5
t
t
orp
ORP Delay
–
–
4.7
2.0
45
46
ns
ns
orpbp
ORP Bypass Delay
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2- 0036A-48/80,70,50.eps
6
Specifications ispLSI 1048
1
Internal Timing Parameters
-80
-70
-50
2
PARAMETER
DESCRIPTION
UNITS
#
MIN. MAX.
MIN. MAX. MIN. MAX.
Outputs
tob
toen
–
–
–
2.5
4.2
4.2
Output Buffer Delay
–
–
–
3.0
5.0
5.0
–
–
–
4.0
6.7
6.7
47
48
49
ns
ns
ns
I/O Cell OE to Output Enabled
I/O Cell OE to Output Disabled
todis
Clocks
tgy0
tgy1/2
tgcp
tioy2/3
tiocp
4.2 4.2
3.3 5.0
0.8 4.2
3.3 5.0
0.8 4.2
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
Clock Delay, Clock GLB to Global GLB Clock Line
Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
Clock Delay, Clock GLB to I/O Cell Global Clock Line
5.0 5.0 6.7 6.7
4.0 6.0 5.3 8.0
1.0 5.0 1.3 6.6
4.0 6.0 5.3 8.0
1.0 5.0 1.3 6.6
50
51
52
53
54
ns
ns
ns
ns
ns
Global Reset
–
9.2
tgr
Global Reset to GLB and I/O Registers
–
8.0
–
10.6
55
ns
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
7
Specifications ispLSI 1048
ispLSI 1048 Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Ded. In
#26
I/O Reg Bypass
GRP 4
#28
4 PT Bypass
#33
GLB Reg Bypass
#37
ORP Bypass
#46
#47
I/O Pin
#20
I/O Pin
(Output)
#48, 49
(Input)
Input
Register
GRP
Loading
Delay
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
Q
D
RST
D
Q
#45
#34, 35, 36
#55
#27, 29,
30, 31, 32
#55
#21 - 25
RST
#38, 39,
40, 41
Reset
Clock
Control
PTs
RE
OE
CK
Distribution
Y1,2,3
Y0
#51, 52,
53, 54
#42, 43,
44
#50
1
Derivations of tsu, th and tco from the Product Term Clock
t
t
t
su
= Logic + Reg su - Clock (min)
=
=
(tiobp +
t
grp4 +
#20 + #28 + #35
t
20ptxor
)
+
(tgsu) - (tiobp +
t
grp4 +
t
ptck(min)
)
(
)
+
(#38) - (#20 + #28 + #44
)
5.5 ns = (3.0 + 3.0 + 7.5) + (1.5) - (3.0 + 3.0 + 3.5)
h
= Clock (max) + Reg h - Logic
=
=
(tiobp +
t
grp4 +
#20 + #28 + #44
t
ptck(max)
)
+
(tgh) - (tiobp +
tgrp4 +
t20ptxor
)
(
)
+
(#39) - (#20 + #28 + #35
)
6.0 ns = (3.0 + 3.0 + 7.5) + (6.0) - (3.0 + 3.0 + 7.5)
co = Clock (max) + Reg co + Output
=
=
(tiobp +
t
grp4 +
#20 + #28 + #44
t
ptck(max)
)
+
(tgco
)
+
)
(torp +
tob
)
(
)
+
(#40
)
+
(#45 + #47
22.5 ns = (3.0 + 3.0 +7.5) + (2.5) + (3.5 + 3.0)
1
Derivations of tsu, th and tco from the Clock GLB
t
t
t
su
= Logic + Reg su - Clock (min)
=
=
(tiobp +
t
grp4 +
#20 + #28 + #35
t
20ptxor
)
+
(tgsu) - (tgy0(min) +
t
gco +
t
gcp(min)
)
(
)
+
(#38) - (#50 + #40 + #52
)
6.5 ns = (3.0 + 3.0 + 7.5) + (1.5) - (5.0 + 2.5 + 1.0)
h
= Clock (max) + Reg h - Logic
=
=
(tgy0(max) +
t
gco +
t
gcp(max)
#39) - (#20 + #28 + #35
)
+
(tgh) - (tiobp +
tgrp4 +
t
20ptxor
)
(
#50 + #40 + #52
)
+
(
)
5.0 ns = (5.0 + 2.5 + 5.0) + (6.0) - (3.0 + 3.0 + 7.5)
co = Clock (max) + Reg co + Output
=
=
(tgy0(max) +
t
gco +
t
gcp(max)
)
+
(tgco
)
+
(torp +
t )
ob
(
#50 + #40 + #52
)
+
(
#40 #45 + #47
)
+
(
)
21.5 ns = (5.0 + 2.5 + 5.0) + (2.5) + (3.5 + 3.0)
1. Calculations are based upon timing specifications for the ispLSI 1048-70.
8
Specifications ispLSI 1048
Maximum GRP Delay vs GLB Loads
ispLSI 1048-50
8
7
6
5
4
3
2
1
0
ispLSI 1048-70
ispLSI 1048-80
4
8
12
16
GLB Loads
0126A-48-80-isp
Power Consumption
Power consumption in the ispLSI 1048 device depends ure 3 shows the relationship between power and operat-
on two primary factors: the speed at which the device is ing speed.
operating, and the number of Product Terms used. Fig-
Figure 3. Typical Device Power Consumption vs fmax
250
ispLSI 1048
200
150
100
50
0
10
20 30
40 50 60 70 80
max (MHz)
f
Notes: Configuration of Twelve 16-bit Counters
Typical Current at 5V, 25¡C
I
I
can be estimated for the ispLSI 1048 using the following equation:
= 73 + (# of PTs * 0.23) + (# of nets * Max. freq * 0.010) where:
CC
CC
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The I
estimate is based on typical conditions (V
= 5.0V, room temperature) and an assumption of 2 GLB loads on
CC
CC
average exists. These values are for estimates only. Since the value of I
program in the device, the actual I
is sensitive to operating conditions and the
CC
should be verified.
CC
0127A-48-80-isp
9
Specifications ispLSI 1048
Pin Description
NAME
PQFP PIN NUMBERS
DESCRIPTION
I/O 0 - I/O 5
20, 21, 22, 23, 24, 25,
26, 27, 28, 29, 30, 31,
32, 33, 34, 35, 36, 37,
38, 39, 40, 41, 42, 43,
49, 50, 51, 52, 53, 54,
55, 56, 57, 58, 59, 60,
61, 62, 63, 64, 65, 66,
67, 68, 69, 70, 71, 72,
80, 81, 82, 83, 84, 85,
86, 87, 88, 89, 90, 91,
92, 93, 94, 95, 96, 97,
98, 99,100,101,102,103,
109,110,111,112,113,114,
115,116,117,118,119,120,
Input/OutputPins-ThesearethegeneralpurposeI/Opinsusedbythe
logic array.
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
1, 2, 3,
4
5, 6,
7, 8, 9, 10, 11, 12
Dedicated input pins to the device. (IN 2 and IN 9 not available)
IN 4
48,
IN 6 - IN 11
79,104,105, – 108, 13
Input – Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
ispEN
17
SDI/IN 01
19
44
Input–Thispinperformstwofunctions. Itisadedicatedinputpinwhen
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
MODE/IN 11
Input–Thispinperformstwofunctions. Itisadedicatedinputpinwhen
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
SDO/IN 31
SCLK/IN 51
47
73
Input/Output – This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
Input – This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
RESET
Y0
18
14
78
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Y1
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Y2
Y3
75
74
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
GND
46, 76,106, 16
15, 45, 77, 107
Ground (GND)
VCC
VCC
1. Pins have dual function capability.
Table 2- 0002C-48-isp
10
Specifications ispLSI 1048
Pin Configuration
ispLSI 1048 120-Pin PQFP Pinout Diagram
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
IN 11
Y0
1
2
3
4
5
6
7
8
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Y1
VCC
GND
Y2
ispLSI 1048
VCC
GND
Top View
1
ispEN
RESET
SDI/IN 0
I/O 0
Y3
1
IN 5/SCLK
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
1
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
1. Pins have dual function capability.
0124 -48-isp
11
Specifications ispLSI 1048
Part Number Description
—
1048
XX
X
X
X
ispLSI
Device Family
Grade
Blank = Commercial
I = Industrial
Package
Q = PQFP
Power
Device Number
Speed
L = Low
80 = 80 MHz
70 = 70 MHz
50 = 50 MHz
fmax
f
f
max
max
0212-80B-isp1048
ispLSI 1048 Ordering Information
COMMERCIAL
Family
ispLSI
Ordering Number
Package
f
max (MHz)
t
pd (ns)
15
80
70
50
120-Pin PQFP
120-Pin PQFP
120-Pin PQFP
ispLSI 1048-80LQ
ispLSI 1048-70LQ
ispLSI 1048-50LQ
18
24
INDUSTRIAL
Family
ispLSI
f
max (MHz)
50
t
pd (ns)
24
Ordering Number
Package
ispLSI 1048-50LQI
120-Pin PQFP
Table 2- 0041A-48-isp
12
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