ISPLSI2128A-80LQ160 [ETC]
;
| 型号： | ISPLSI2128A-80LQ160 |
| 厂家： | 
ETC |
| 描述： | 可编程逻辑 输入元件 时钟 |
| 文件： | 总12页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ispLSI 2128/A
In-System Programmable High Density PLD
Features
Functional Block Diagram
• ENHANCEMENTS
Output Routing Pool (ORP)
D7 D6
D5
D4
Output Routing Pool (ORP)
D2
D1
D0
— ispLSI 2128A is Fully Form and Function Compatible
to the ispLSI 2128, with Identical Timing
Specifcations and Packaging
D3
A0
A1
C7
C6
— ispLSI 2128A is Built on an Advanced 0.35 Micron
E2CMOS® Technology
• HIGH DENSITY PROGRAMMABLE LOGIC
D
Q
Q
Q
Q
A2
A3
C5
C4
— 6000 PLD Gates
— 128 I/O Pins, Eight Dedicated Inputs
— 128 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
D
D
D
Logic
Array
A4
A5
C3
C2
GLB
A6
A7
C1
C0
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
Global Routing Pool (GRP)
— fmax = 100 MHz Maximum Operating Frequency
— tpd = 10 ns Propagation Delay
B0
B1
B2
B3
B5
B6
B7
B4
Output Routing Pool (ORP)
Output Routing Pool (ORP)
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
0139(9A)/2128
Description
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
The ispLSI 2128 and 2128A are High Density Program-
mableLogicDevices.Thedevicescontains128Registers,
128 Universal I/O pins, eight Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 2128 and 2128A feature 5V in-
system programmability and in-system diagnostic
capabilities. The ispLSI 2128 and 2128A offer non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1 .. D7
(Figure1). Thereareatotalof32GLBsintheispLSI2128
and 2128A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/ExclusiveORarray, andfouroutputswhichcan
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright©2002LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
January 2002
2128_09
1
Specifications ispLSI 2128/A
Functional Block Diagram
Figure 1. ispLSI 2128/A Functional Block Diagram
RESET
GOE 0
Input Bus
GOE 1
Output Routing Pool (ORP)
Megablock
Output Routing Pool (ORP)
D2
D1
D3
IN 5
IN 4
Generic Logic
D7
D6
D5
D0
D4
Blocks (GLBs)
I/O 95
I/O 94
I/O 93
I/O 92
C7
C6
I/O 0
I/O 1
I/O 2
I/O 3
A0
I/O 91
I/O 90
I/O 89
I/O 88
I/O 4
I/O 5
I/O 6
I/O 7
I/O 87
I/O 86
I/O 85
I/O 84
A1
C5
C4
I/O 8
I/O 9
I/O 10
I/O 11
I/O 83
I/O 82
I/O 81
I/O 80
A2
A3
Global
Routing
Pool
I/O 12
I/O 13
I/O 14
I/O 15
I/O 79
I/O 78
I/O 77
I/O 76
C3
C2
(GRP)
I/O 16
I/O 17
I/O 18
I/O 19
I/O 75
I/O 74
I/O 73
I/O 72
A4
A5
I/O 20
I/O 21
I/O 22
I/O 23
I/O 71
I/O 70
I/O 69
I/O 68
C1
C0
I/O 24
I/O 25
I/O 26
I/O 27
I/O 67
I/O 66
I/O 65
I/O 64
A6
A7
I/O 28
I/O 29
I/O 30
I/O 31
SCLK/IN 0
MODE/IN 1
B0
B1
B2
B5
B6
B7
B3
B4
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
ispEN
0139(10A)/2128
The device also has 128 I/O cells, each of which is The GRP has as its inputs, the outputs from all of the
directly connected to an I/O pin. Each I/O cell can be GLBs andallof theinputs from thebi-directionalI/O cells.
individually programmed to be a combinatorial input, All of these signals are made available to the inputs of the
output or bi-directional I/O pin with 3-state control. The GLBs. Delays through the GRP have been equalized to
signal levels are TTL compatible voltages and the output minimize timing skew.
drivers can source 4 mA or sink 8 mA. Each output can
Clocks in the ispLSI 2128 and 2128A devices are se-
be programmed independently for fast or slow output
lected using the dedicated clock pins. Three dedicated
slew rate to minimize overall output switching noise.
clock pins (Y0, Y1, Y2) or an asynchronous clock can be
Eight GLBs, 32 I/O cells, two dedicated inputs and two selected on a GLB basis. The asynchronous or Product
ORPs are connected together to make a Megablock TermclockcanbegeneratedinanyGLBforitsownclock.
(Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI2128and2128AdevicecontainsfourMegablocks.
2
Specifications ispLSI 2128/A
1
Absolute Maximum Ratings
Supply Voltage V .................................. -0.5 to +7.0V
cc
Input Voltage Applied........................ -2.5 to V +1.0V
CC
Off-State Output Voltage Applied ..... -2.5 to V +1.0V
CC
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T ) with Power Applied ... 150°C
J
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
Commercial
Industrial
MIN.
4.75
4.5
0
MAX.
5.25
5.5
UNITS
V
V
V
V
T = 0°C to + 70°C
A
V
CC
Supply Voltage
T = -40°C to + 85°C
A
Input Low Voltage
Input High Voltage
0.8
V
V
IL
2.0
V +1
cc
IH
Table 2 - 0005/2128
Capacitance (TA=25°C, f=1.0 MHz)
SYMBOL
PARAMETER
TYPICAL
UNITS
TEST CONDITIONS
CC = 5.0V, VI/O, IN = 2.0V
VCC= 5.0V, VY= 2.0V
I/O and Dedicated Input Capacitance
Clock Capacitance
8
pf
pf
V
C1
C2
15
Table 2-0006/2128
Data Retention Specifications
PARAMETER
Data Retention
MINIMUM
20
MAXIMUM
UNITS
Years
Cycles
–
–
Erase/Reprogram Cycles
10,000
Table 2-0008/2128
3
Specifications ispLSI 2128/A
Switching Test Conditions
Figure 2. Test Load
Input Pulse Levels
GND to 3.0V
≤ 3ns 10% to 90%
1.5V
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
+ 5V
1.5V
R
1
2
See Figure 2
3-state levels are measured 0.5V from steady-state
active level.
Device
Output
Test
Point
Table 2 - 0003/2000
R
C
*
L
Output Load Conditions (see Figure 2)
TEST CONDITION
R1
470Ω
∞
R2
CL
A
B
390Ω
390Ω
390Ω
35pF
35pF
35pF
*
C includes Test Fixture and Probe Capacitance.
L
Active High
Active Low
0213A
470Ω
Active High to Z
at VOH -0.5V
∞
390Ω
5pF
C
Active Low to Z
at VOL +0.5V
470Ω
390Ω
5pF
Table 2 - 0004A/2000
DC Electrical Characteristics
Over Recommended Operating Conditions
3
SYMBOL
PARAMETER
CONDITION
MIN.
–
TYP. MAX. UNITS
Output Low Voltage
IOL= 8 mA
–
–
–
–
–
–
–
0.4
–
V
V
VOL
Output High Voltage
IOH = -4 mA
2.4
–
VOH
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
ispEN Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
0V ≤ V ≤ V (Max.)
-10
10
µA
µA
µA
µA
mA
I
I
I
I
I
IL
IN
IL
3.5V ≤ V ≤ V
–
IH
IN
CC
0V ≤ V ≤ V
–
-150
-150
-200
IL-isp
IL-PU
OS1
IN
IL
0V ≤ V ≤ V
–
IN
IL
V = 5V, VOUT = 0.5V
–
CC
Commercial
Industrial
–
–
165
165
325
–
mA
mA
V = 0.0V, V = 3.0V
fCLOCK = 1 MHz
CC2, 4
IL
IH
Operating Power Supply Current
I
Table 2-0007/2128
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using eight 16-bit counters.
3. Typical values are at VCC= 5V and T = 25°C.
A
4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM
to estimate maximum ICC
.
4
Specifications ispLSI 2128/A
External Timing Parameters
Over Recommended Operating Conditions
TEST4
COND.
-100
-80
2
PARAMETER
#
DESCRIPTION1
UNITS
MIN. MAX. MIN. MAX.
A
A
A
–
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback3
–
–
10.0
13.0
–
–
–
15.0
18.5
–
ns
ns
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
pd1
2
3
4
5
6
7
8
9
pd2
100
77.0
100
6.5
–
81.0
57.0
83.0
9.0
–
MHz
MHz
MHz
ns
max
1
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
(
)
–
–
max (Ext.)
max (Tog.)
su1
tsu2 + tco1
–
–
–
–
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
–
–
A
–
5.0
–
6.5
–
ns
co1
0.0
8.0
–
0.0
11.0
–
ns
h1
–
–
–
ns
su2
–
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
6.0
–
8.0
–
ns
co2
–
0.0
–
0.0
–
ns
h2
A
–
13.5
–
17.0
–
ns
r1
6.5
–
10.0
–
ns
rw1
B
C
B
C
–
14 Product Term OE, Enable
15.0
15.0
9.0
9.0
–
18.0
18.0
12.0
12.0
–
ns
ptoeen
ptoedis
goeen
goedis
wh
15 Product Term OE, Disable
–
–
ns
16 Global OE, Enable
–
–
ns
17 Global OE, Disable
–
–
ns
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
5.0
5.0
6.0
6.0
ns
–
–
–
ns
wl
Table 2-0030B/2128-100
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
5
Specifications ispLSI 2128/A
Internal Timing Parameters1
Over Recommended Operating Conditions
-100
-80
2
PARAMETER
#
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX.
Inputs
20 Input Buffer Delay
–
–
0.5
2.2
–
–
1.8
4.4
ns
ns
t
t
io
21 Dedicated Input Delay
din
GRP
22 GRP Delay
–
1.7
–
2.6
ns
t
grp
GLB
23 4 Product Term Bypass Path Delay
24 4 Product Term Bypass Path Delay
25 1 Product Term/XOR Path Delay
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay3
–
–
5.8
5.8
6.8
7.3
8.0
0.5
–
–
–
8.1
6.8
8.0
8.8
9.8
1.3
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
4ptbpc
4ptbpr
1ptxor
20ptxor
xoradj
gbp
–
–
–
–
–
–
28 GLB Register Bypass Delay
–
–
29 GLB Register Setup Time befor Clock
30 GLB Register Hold Time after Clock
31 GLB Register Clock to Output Delay
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
1.2
4.0
–
1.4
6.0
–
gsu
–
–
gh
0.3
1.3
6.1
8.6
0.4
1.6
8.6
9.0
gco
–
–
gro
–
–
ptre
–
–
ptoe
ptck
4.1 7.1 5.6 10.2
ORP
36 ORP Delay
–
–
1.4
0.4
–
–
2.0
0.5
ns
ns
t
t
orp
37 ORP Bypass Delay
orpbp
Outputs
38 Output Buffer Delay
–
–
–
–
–
–
–
–
–
–
2.0
10.0
4.6
ns
ns
ns
ns
ns
t
t
t
t
t
ob
1.6
10.0
4.2
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
sl
oen
odis
goe
4.6
4.2
7.4
4.8
Clocks
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
2.7
2.7
3.6 3.6
3.6 3.6
ns
ns
t
t
gy0
2.7
2.7
gy1/2
Global Reset
45 Global Reset to GLB
–
–
11.4
Table 2- 0036C/2128-100
ns
t
gr
9.2
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
6
Specifications ispLSI 2128/A
ispLSI 2128/A Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Comb 4 PT Bypass #23
Ded. In
#21
I/O Delay
#20
GRP
#22
Reg 4 PT Bypass
GLB Reg Bypass
#28
ORP Bypass
#37
#38,
39
I/O Pin
(Output)
I/O Pin
(Input)
#24
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
D
Q
#36
#25 - 27
RST
#45
#29 - 32
Reset
Control
PTs
RE
OE
CK
#33 - 35
#40, 41
#43, 44
#42
Y0,1,2
GOE0, 1
0491
Derivations of tsu, th and tco from the Product Term Clock
tsu
= Logic + Reg su - Clock (min)
= ( io + grp + 20ptxor) + ( gsu) - (
= (#20+ #22+ #26) + (#29) - (#20+ #22+ #35)
4.4 ns = (0.5 + 1.7 + 7.3) + (1.2) + (0.5 + 1.7 + 4.1)
t
t
t
t
tio + tgrp + tptck(min))
th
= Clock (max) + Reg h - Logic
= ( io + grp + ptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
t
t
t
= (#20+ #22+ #35) + (#30) - (#20+ #22+ #26)
3.8 ns = (0.5 + 1.7 + 7.1) + ( 4.0) + (0.5 + 1.7 + 7.3)
t
co
= Clock (max) + Reg co + Output
= ( io + grp + ptck(max)) + ( gco) + (
= (#20+ #22+ #35) + (#31) + (#36 + #38)
12.6 ns = (0.5 + 1.7 + 7.1) + (0.3) + (1.4 + 1.6)
t
t
t
t
torp + tob)
Table 2-0042/2128
Note: Calculations are based upon timing specifications for the ispLSI 2128/A-100L.
7
Specifications ispLSI 2128/A
Power Consumption
used. Figure 4 shows the relationship between power
and operating speed.
Power consumption in the ispLSI 2128 and 2128A de-
vices depends on two primary factors: the speed at which
the device is operating and the number of Product Terms
Figure 4. Typical Device Power Consumption vs fmax
300
250
200
ispLSI 2128/A
150
100
0
20
40 60
80 100
f
max (MHz)
Notes: Configuration of eight 16-bit counters
Typical current at 5V, 25° C
I
I
can be estimated for the ispLSI 2128/A using the following equation:
CC
(mA) = 20 + (# of PTs 0.48) + (# of nets Max freq 0.009)
*
*
*
CC
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The I
CC
estimate is based on typical conditions (V
= 5.0V, room temperature) and an assumption of two GLB loads
CC
on average exists. These values are for estimates only. Since the value of I
is sensitive to operating conditions
CC
and the program in the device, the actual I
should be verified.
CC
0127B/2128
8
Specifications ispLSI 2128/A
Pin Description
PQFP/MQFP
TQFP PIN NUMBERS
NAME
PIN NUMBERS
DESCRIPTION
27, 28, 31, 32, 33,
35, 36, 37, 38, 39,
41, 42, 43, 44, 45,
46, 47, 48, 50, 51,
52, 53, 55, 57, 58,
59, 60, 61, 62, 63,
65, 66, 67, 68, 70,
71, 72, 73, 75, 76,
77, 79, 80, 81, 82,
83, 85, 86, 87, 88,
90, 91, 92, 93, 94,
95, 96, 97, 99, 101,
102, 103, 104, 105, 115,
116, 119, 120, 121, 123,
124, 125, 126, 127, 129,
130, 131, 132, 133, 134,
135, 136, 138, 139, 140,
141, 143, 145, 146, 147,
148, 149, 150, 151, 153,
154, 155, 156, 158, 159,
160, 161, 163, 164, 165,
167, 168, 169, 170, 171,
173, 174, 175, 176, 2,
I/O 0 - I/O 4
I/O 5 - I/O 9
25, 26, 28, 29, 30,
32, 33, 34, 35, 36,
37, 38, 39, 40, 41,
42, 43, 44, 46, 47,
48, 49, 50, 52, 53,
54, 55, 56, 57, 58,
59, 60, 61, 62, 64,
65, 66, 67, 68, 69,
70, 72, 73, 74, 75,
76, 77, 78, 79, 80,
82, 83, 84, 85, 86,
87, 88, 89, 90, 92,
93, 94, 95, 96, 105,
106, 108, 109, 110, 112,
113, 114, 115, 116, 117,
118, 119, 120, 121, 122,
123, 124, 126, 127, 128,
129, 130, 132, 133, 134,
135, 136, 137, 138, 139,
140, 141, 142, 144, 145,
146, 147, 148, 149, 150,
152, 153, 154, 155, 156,
157, 158, 159, 160, 2,
Input/Output Pins - These are the general purpose I/O pins
used by the logic array.
I/O 10 - I/O 14
I/O 15 - I/O 19
I/O 20 - I/O 24
I/O 25 - I/O 29
I/O 30 - I/O 34
I/O 35 - I/O 39
I/O 40 - I/O 44
I/O 45 - I/O 49
I/O 50 - I/O 54
I/O 55 - I/O 59
I/O 60 - I/O 64
I/O 65 - I/O 69
I/O 70 - I/O 74
I/O 75 - I/O 79
I/O 80 - I/O 84
I/O 85 - I/O 89
I/O 90 - I/O 94
I/O 95 - I/O 99
I/O 100 - I/O 104
I/O 105 - I/O 109
I/O 110 - I/O 114
I/O 115 - I/O 119
I/O 120 - I/O 124
I/O 125 - I/O 127
3, 4,
8, 9,
5,
6,
7,
3, 4,
8, 9,
5,
6,
7,
12, 14, 15,
11, 13, 14,
16, 17, 18
106, 107, 112, 113
110, 109,
15, 16, 17
97, 98, 102, 103
100, 99,
IN 2 - IN 5
GOE 0, GOE 1
RESET
Dedicated input pins to the device.
Global Output Enable input pins.
22
20
Active Low (0) Reset pin which resets all of the GLB
registers in the device.
19, 21, 111
23
Y0, Y1, Y2
ispEN
18, 19, 101
21
Dedicated Clock inputs. These clock inputs are connected
to one of the clock inputs of all the GLBs on the device.
Input - Dedicated in-system programming enable input pin.
This pin is brought low to enable the programming mode.
The MODE, SDI, SDO and SCLK options become active.
Input - This pin performs two functions. When ispEN is logic
low, it functions as an input pin to load programming data
into the device. SDI is also used as one of the two control
pins for the isp state machine. When ispEN is high, it
functions as a dedicated input pin.
Input - This pin performs two functions. When ispEN is logic
low, it functions as a clock pin for the Serial Shift Register.
When ispEN is high, it functions as a dedicated input pin.
Input - This pin performs two functions. When ispEN is logic
low, it functions as pin to control the operation of the isp
state machine. When ispEN is high, it functions as a
dedicated input pin.
2
24
SDI/IN 7
22
2
25
26
SCLK/IN 0
23
24
2
MODE/IN 1
2
114
SDO/IN 6
104
Output/Input - This pin performs two functions. When ispEN
is logic low, it functions as the pin to read the isp data.
When ispEN is high, it functions as a dedicated input pin.
1, 11, 29, 49, 69,
89, 117, 137, 157
GND
VCC
1, 10, 27, 45, 63,
81, 107, 125, 143
Ground (GND)
VCC (+5V)
13, 34, 56, 78, 100,
122, 144, 166
12, 31, 51, 71, 91,
111, 131, 151
1
20, 30, 40, 54, 64,
74, 84, 98, 108, 118
128, 142, 152, 162, 172
NC
No Connect.
Table 2-0002/2128
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
9
Specifications ispLSI 2128/A
Pin Configuration
ispLSI 2128/A 160-Pin PQFP Pinout Diagram
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
1
2
3
4
5
6
7
8
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
VCC
I/O 68
I/O 67
I/O 66
GND
I/O 65
I/O 64
SDO/IN 61
IN 5
GND
I/O 114
I/O 115
I/O 116
I/O 117
I/O 118
I/O 119
I/O 120
I/O 121
GND
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O 122
VCC
I/O 123
I/O 124
I/O 125
I/O 126
I/O 127
Y0
IN 4
Y2
GOE 0
GOE 1
IN 3
Y1
ispLSI 2128/A
RESET
ispEN
1SDI/IN 7
1SCLK/IN 0
1MODE/IN 1
I/O 0
Top View
IN 2
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
VCC
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
GND
I/O 1
GND
I/O 2
I/O 3
I/O 4
VCC
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
82
81
1. Pins have dual function capability.
160-PQFP/2128A
10
Specifications ispLSI 2128/A
Pin Configuration
ispLSI 2128/A 176-Pin TQFP Pinout Diagram
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
I/O 77
I/O 76
I/O 75
I/O 74
NC1
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
VCC
1
2
3
4
5
6
7
8
GND
I/O 114
I/O 115
I/O 116
I/O 117
I/O 118
I/O 119
I/O 120
I/O 121
1NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
GND
I/O 122
VCC
I/O 68
I/O 67
I/O 66
NC1
I/O 123
I/O 124
I/O 125
I/O 126
I/O 127
Y0
GND
I/O 65
I/O 64
SDO/IN 62
IN 5
IN 4
Y2
GOE 0
GOE 1
NC1
IN 3
IN 2
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
VCC
1NC
Y1
ispLSI 2128/A
RESET
ispEN
2SDI/IN 7
2SCLK/IN 0
2MODE/IN 1
I/O 0
Top View
I/O 1
GND
1NC
I/O 2
I/O 3
I/O 4
VCC
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
1NC
I/O 10
I/O 11
I/O 12
I/O 13
I/O 58
NC1
98
97
96
95
94
93
92
91
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
GND
90
89
176-TQFP/2128A
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
11
Specifications ispLSI 2128/A
Part Number Description
ispLSI XXXXX – XXX X X
X
Device Family
Grade
Blank = Commercial
Device Number
2128
2128A
I = Industrial
Package
Q = PQFP
M = MQFP
T = TQFP
Speed
100 = 100 MHz
fmax
Power
80 = 81 MHz max
f
L = Low
0212/2128A
ispLSI 2128/A Ordering Information
COMMERCIAL
FAMILY
Fmax (MHz)
Tpd (ns)
ORDERING NUMBER
PACKAGE
160-Pin PQFP
176-Pin TQFP
160-Pin PQFP
176-Pin TQFP
100
100
81
10
10
15
15
ispLSI 2128A-100LQ160
ispLSI 2128A-100LT176
ispLSI 2128A-80LQ160
81
ispLSI 2128A-80LT176
ispLSI
100
100
81
10
10
15
15
160-Pin PQFP
176-Pin TQFP
160-Pin PQFP
176-Pin TQFP
ispLSI 2128-100LQ
ispLSI 2128-100LT
ispLSI 2128-80LQ
81
ispLSI 2128-80LT
Table 2-0041A/2128A
INDUSTRIAL
FAMILY
ispLSI
Fmax (MHz)
Tpd (ns)
ORDERING NUMBER
ispLSI 2128A-80LT176I
ispLSI 2128-80LTI
PACKAGE
176-Pin TQFP
176-Pin TQFP
81
81
15
15
Table 2-0041B/2128A
12
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