JL101ASCA [ETC]
OP-AMP|SINGLE|BIPOLAR|DIP|14PIN|CERAMIC ;
| 型号： | JL101ASCA |
| 厂家： | 
ETC |
| 描述： | OP-AMP|SINGLE|BIPOLAR|DIP|14PIN|CERAMIC |
| 文件： | 总17页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MICROCIRCUIT DATA SHEET
Original Creation Date: 06/21/95
Last Update Date: 03/28/00
MJLM101A-X REV 0A0
Last Major Revision Date: 01/19/00
SINGLE OPERATIONAL AMPLIFIER - EXTERNALLY COMPENSATED
General Description
The LM101A is a general purpose operational amplifier which features improved performance
over industry standards such as the LM709. Advanced processing techniques make possible
an order of magnitude reduction in input currents, and a redesign of the biasing circuitry
reduces the temperature drift of input current.
This amplifier offers many features which make its application nearly foolproof: overload
protection on the input and output, no latch-up when the common mode range is exceeded,
and freedom from oscillations and compensation with a single 30 pF capacitor. It has
advantages over internally compensated amplifiers in that the frequency compensation can
be tailored to the particular application. For example, in low frequency circuits it can
be overcompensated for increased stability margin. Or the compensation can be optimized
to give more than a factor of ten improvement in high frequency performance for most
applications.
In addition, the device provides better accuracy and lower noise in high impedance
circuitry. The low input currents also make it particularly well suited for long interval
integrators or timers, sample and hold circuits and low frequency waveform generators.
Further, replacing circuits where matched transistor pairs buffer the inputs of
conventional IC op amps, it can give lower offset voltage and a drift at a lower cost.
Industry Part Number
NS Part Numbers
LM101A
JL101ABCA
JL101ABGA
JL101ABHA
JL101ABPA
JL101ASCA
JL101ASGA
JL101ASHA
JL101ASPA
Prime Die
LM101A
Controlling Document
38510/10103,AMEND.2 CIR.G REV G
Processing
Subgrp Description
Temp (oC)
MIL-STD-883, Method 5004
1
Static tests at
+25
2
Static tests at
+125
-55
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
+25
Quality Conformance Inspection
5
+125
-55
6
MIL-STD-883, Method 5005
7
+25
8A
8B
9
+125
-55
+25
10
11
+125
-55
1
MICROCIRCUIT DATA SHEET
MJLM101A-X REV 0A0
Features
- Offset voltage 3 mV maximum over temperature
- Input current 100 nA maximum over temperature
- Offset current 20 nA maximum over temperature
- Guaranteed drift characteristics
- Offsets guaranteed over entire common mode and supply voltage ranges
- Slew rate of 10V/us as a summing amplifier
2
MICROCIRCUIT DATA SHEET
MJLM101A-X REV 0A0
(Absolute Maximum Ratings)
(Note 1)
Supply Voltage
+22V
+30V
Differential Input Voltage
Input Voltage
(Note 3)
+15V
Ouput Short Circuit Duration
(Note 2)
Continuous
Operating Ambient Temp. Range
Maximum Junction Temperature
-55 C to +125 C
150 C
Power Dissipation at TA = 25 C
(Note 2)
H-Pkg
H-Pkg
(Still Air)
750mW
1200mW
1000mW
1500mW
1200mW
2000mW
500mW
(500LF/Min Air Flow)
J8-Pkg (Still Air)
J8-Pkg (500LF/Min Air Flow)
J14-Pkg (Still Air)
J14-Pkg (500LF/Min Air Flow)
W-Pkg
(Still Air)
W-Pkg (500LF/Min Air Flow)
800mW
Thermal Resistance
ThetaJA
H-Pkg
H-Pkg
(Still Air)
165 C/W
89 C/W
128 C/W
75 C/W
98 C/W
59 C/W
233 C/W
155 C/W
(500LF/Min Air Flow)
J8-Pkg (Still Air)
J8-Pkg (500LF/Min Air Flow)
J14-Pkg (Still Air)
J14-Pkg (500LF/Min Air Flow)
W-Pkg
W-Pkg
(Still Air)
(500LF/Min Air Flow)
ThetaJC
H-Pkg
J8-Pkg
J14-Pkg
W-Pkg
39 C/W
26 C/W
24 C/W
26 C/W
Storage Temperature Range
-65 C to +150 C
300 C
Lead Temperature
(Soldering, 10 seconds)
ESD Tolerance
(Note 4)
2000V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Operating Ratings indicate conditions for which the device is intended to be
functional, but do not guarantee specific performance limits. For guaranteed
specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: The maximum power dissipation must be derated at elevated temperatures and is
dictated by Tjmax (maximum junction temperature), ThetaJA (package junction to
ambient thermal resistance), and TA (ambient temperature). The maximum allowable
power dissipation at any temperature is Pdmax = (Tjmax - TA)/ThetaJA or the number
given in the Absolute Maximum Ratings, whichever is lower.
Note 3: For supply voltages less than +15V, the absolute maximum input voltage is equal to
the supply voltage.
Note 4: Human body model, 100 pF discharged through 1.5k Ohms.
3
MICROCIRCUIT DATA SHEET
MJLM101A-X REV 0A0
Electrical Characteristics
DC PARAMETERS
(The following conditions apply to all the following parameters, unless otherwise specified.)
DC: +Vcc = +20V, Vcm = 0V, Rs = 50 ohms
PIN-
NAME
SUB-
SYMBOL
Vio
PARAMETER
CONDITIONS
NOTES
MIN
-2
MAX UNIT
+2
GROUPS
Input Offset
Voltage
+Vcc = 35V, -Vcc = -5V, Vcm = -15V
mV
mV
mV
mV
mV
mV
mV
mV
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
1
-3
+3
2, 3
1
+Vcc = 5V, -Vcc = -35V, Vcm = +15V
Vcm = 0V
-2
+2
-3
+3
2, 3
1
-2
+2
-3
+3
2, 3
1
+Vcc = 5V, -Vcc = -5V, Vcm = 0V
-2
+2
-3
+3
2, 3
1, 2
3
Iio
Input Offset
Current
+Vcc = 35V, -Vcc = -5V, Vcm = -15V,
Rs = 100K Ohms
-10
-20
-10
-20
-10
-20
-10
-20
-0.1
-0.1
-0.1
-0.1
-0.1
-0.1
-0.1
-0.1
+10
+20
+10
+20
+10
+20
+10
+20
75
+Vcc = 5V, -Vcc = -35V, Vcm = +15V,
Rs = 100K Ohms
1, 2
3
Vcm = 0V, Rs = 100K Ohms
1, 2
3
+Vcc = 5V, -Vcc = -5V, Vcm = 0V,
Rs = 100K Ohms
1, 2
3
Iib+
Input Bias
Current
+Vcc = 35V, -Vcc = -5V, Vcm = -15V,
Rs = 100K Ohms
1, 2
3
100
75
+Vcc = 5V, -Vcc = -35V, Vcm = +15V,
Rs = 100K Ohms
1, 2
3
100
75
Vcm = 0V, Rs = 100K Ohms
1, 2
3
100
75
+Vcc = 5V, -Vcc = -5V, Vcm = 0V,
Rs = 100K Ohms
1, 2
3
100
4
MICROCIRCUIT DATA SHEET
MJLM101A-X REV 0A0
Electrical Characteristics
DC PARAMETERS(Continued)
(The following conditions apply to all the following parameters, unless otherwise specified.)
DC: +Vcc = +20V, Vcm = 0V, Rs = 50 ohms
PIN-
NAME
SUB-
SYMBOL
Iib-
PARAMETER
CONDITIONS
NOTES
MIN
MAX UNIT
GROUPS
Input Bias
Current
+Vcc = 35V, -Vcc = -5V, Vcm = -15V,
Rs = 100K Ohms
-0.1
-0.1
-0.1
-0.1
-0.1
-0.1
-0.1
-0.1
-50
75
nA
nA
nA
nA
nA
nA
nA
nA
1, 2
3
100
75
+Vcc = 5V, -Vcc = -35V, Vcm = +15V,
Rs = 100K Ohms
1, 2
3
100
75
Vcm = 0V, Rs = 100K Ohms
1, 2
3
100
75
+Vcc = 5V, -Vcc = -5V, Vcm = 0V,
Rs = 100K Ohms
1, 2
3
100
+50
+100
+50
+100
+PSRR
-PSRR
Power Supply
Rejection Ratio
+Vcc = 10V, -Vcc = -20V
+Vcc = 20V, -Vcc = -10V
Vcc = +35V to +5V, Vcm = +15V
uV/V 1
-100
-50
uV/V 2, 3
uV/V 1
Power Supply
Rejection Ratio
-100
80
uV/V 2, 3
CMRR
Common Mode
Rejection Ratio
dB
1, 2,
3
VioADJ(+)
Adjustment for
Input Offset
Voltage
4
mV
1, 2,
3
VioADJ(-)
Adjustment for
Input Offset
Voltage
-4
mV
1, 2,
3
Ios+
Ios-
Icc
Output Short
+Vcc = 15V, -Vcc = -15V, t < 25mS,
Vcm = -15V
-60
mA
mA
1, 2,
3
Circuit Current
Output Short
Circuit Current
+Vcc = 15V, -Vcc = -15V, t <25mS,
Vcm = +15V
+60
1, 2,
3
Power Supply
Current
+Vcc = 15V, -Vcc = -15V
3
mA
mA
mA
1
2
3
2.32
3.5
+15
+18
Delta
Vio/Delta
T
Temperature
Coefficient of
Input Offset
Voltage
+25 C < TA < +125 C
+25 C < TA < -55 C
1
1
-15
-18
uV/ C 2
uV/ C 3
Delta
Iio/Delta
T
Temperature
Coefficient of
Input Offset
Current
+25 C < TA < +125 C
+25 C < TA < -55 C
1
1
-100
-200
+100
+200
pA/ C 2
pA/ C 3
5
MICROCIRCUIT DATA SHEET
MJLM101A-X REV 0A0
Electrical Characteristics
DC PARAMETERS(Continued)
(The following conditions apply to all the following parameters, unless otherwise specified.)
DC: +Vcc = +20V, Vcm = 0V, Rs = 50 ohms
PIN-
NAME
SUB-
SYMBOL
Avs-
PARAMETER
CONDITIONS
NOTES
MIN
50
MAX UNIT
GROUPS
Large Signal
(Open Loop)
Voltage Gain
Rl = 2K Ohms, Vout = -15V
2
2
2
2
2
2
2
2
2
V/mV 4
25
50
25
50
25
50
25
10
V/mV 5, 6
V/mV 4
Rl = 10K Ohms, Vout = -15V
Rl = 2K Ohms, Vout = +15V
Rl = 10K Ohms, Vout = +15V
V/mV 5, 6
V/mV 4
Avs+
Large Signal
(Open Loop)
Voltage Gain
V/mV 5, 6
V/mV 4
V/mV 5, 6
Avs
Large Signal
(Open Loop)
Voltage Gain
Vcc = +5V, Rl = 2K Ohms, Vout = +2V
Vcc = +5V, Rl = 10K Ohms, Vout = +2V
Rl = 10K Ohms, Vcm = -20V
V/mV 4, 5,
6
2
10
V/mV 4, 5,
6
Vop+
Vop-
Output Voltage
Swing
+16
+15
V
V
V
V
4, 5,
6
Rl = 2K Ohms, Vcm = -20V
4, 5,
6
Output Voltage
Swing
Rl = 10K Ohms, Vcm = 20V
-16
-15
4, 5,
6
Rl = 2K ohms, Vcm = 20V
4, 5,
6
AC PARAMETERS
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC: +Vcc = +20V, Vcm = 0V, Rs = 50 Ohms
Sr+
Sr-
Slew Rate
Slew Rate
Av = 1, Vin = -5V to +5V
0.3
0.2
0.3
0.2
V/uS 7, 8A
V/uS 8B
Av = 1, Vin = +5V to -5V
V/uS 7, 8A
V/uS 8B
TR(tr)
TR(os)
Rise Time
Overshoot
Av = 1, Vin = 50mV
Av = 1, Vin = 50mV
800
25
nS
7, 8A,
8B
%
7, 8A,
8B
NI(BB)
NI(PC)
Noise Broadband
Noise Popcorn
BW = 10Hz to 5KHz, Rs = 0 Ohms
BW = 10Hz to 5KHz, Rs = 100K Ohms
15
80
uVrms 7
uVpk 7
6
MICROCIRCUIT DATA SHEET
MJLM101A-X REV 0A0
Electrical Characteristics
DC PARAMETERS: DRIFT VALUES
(The following conditions apply to all the following parameters, unless otherwise specified.)
DC: +Vcc = +20V, Vcm = 0V, Rs = 50 Ohms. "Delta calculations performed on JAN S and QMLV devices at group
B, subgroup 5 only".
PIN-
NAME
SUB-
SYMBOL
Vio
PARAMETER
CONDITIONS
NOTES
MIN
MAX UNIT
GROUPS
Input Offset
Voltage
Vcm = 0V
-0.5
0.5
mV
nA
nA
1
Iib+
Iib-
Input Bias
Current
Vcm = 0V, Rs = 100K Ohms
Vcm = 0V, Rs = 100K Ohms
-7.5
-7.5
7.5
7.5
1
1
Input Bias
Current
Note 1: Calculated parameter.
Note 2: Datalog reading of K = V/mV.
7
MICROCIRCUIT DATA SHEET
MJLM101A-X REV 0A0
Graphics and Diagrams
GRAPHICS#
DESCRIPTION
05309HRB2
08337HRB2
09384HRA4
09413HRB1
H08CRF
CERDIP (J), 14 LEAD (B/I CKT)
CERPACK (W), 10 LEAD (B/I CKT)
METAL CAN, (H) TO-99,8 LEAD,.200 DIA P.C.(B/I CKT)
CERDIP (J), 8 LEAD (B/I CKT)
METAL CAN (H), TO-99, 8LD, .200 DIA P.C. (P/P DWG)
CERDIP (J), 8 LEAD (P/P DWG)
J08ARL
J14ARH
CERDIP (J), 14 LEAD (P/P DWG)
P000178A
P000180A
P000226A
P000227A
W10ARG
METAL CAN (H), 8 LEAD (PINOUT)
CERPACK (W), 10 LEAD (PINOUT)
CERDIP (J), 8 LEAD (PINOUT)
CERDIP (J), 14 LEAD (PINOUT)
CERPACK (W), 10 LEAD (P/P DWG)
See attached graphics following this page.
8
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N/C
N/C
N/C
1
2
3
4
5
6
7
14
13
12
11
10
9
N/C
BALANCE/
COMPENSATION
IN-
COMPENSATION
V+
OUTPUT
IN+
V-
BALANCE
N/C
N/C
8
LM101AJ-14
14 - LEAD DIP
CONNECTION DIAGRAM
TOP VIEW
P000227A
MIL/AEROSPACE OPERATIONS
2900 SEMICONDUCTOR DRIVE
SANTA CLARA, CA 95050
MICROCIRCUIT DATA SHEET
MJLM101A-X REV 0A0
Revision History
Rev ECN # Rel Date Originator Changes
0A0
M0003644 03/28/00
Rose Malone
Update MDS from MJLM101A-X, Rev. 0BL to a Fully
Release MDS MJLM101A-X, Rev. 0A0. Added Genral
Description, Features Section, Absolute Section.
Updated Note Section.
9
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