JT6N46S [ETC]
Transponder ; 转发\n
| 型号： | JT6N46S |
| 厂家： | 
ETC |
| 描述： | Transponder
|
| 文件： | 总7页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
JT6N46S
TOSHIBA CMOS Integrated Circuit Silicon Monolithic
J T 6 N 4 6 S
Single-Chip System LSI for RFID Card
The JT6N46S is a system LSI for radio frequency identification (RFID) wireless cards. The JT6N46S
incorporates an analog circuit, a data processing circuit and data memory in a single chip.
Features
•
High-noise-resistant PSK modulation:
binary phase-shift keying (BPSK) for both reader-to-RFID and RFID-to-reader transmission.
•
•
Start-stop synchronization and half-duplex transmission: with parity, 1 stop bit
High-efficiency power generation circuit using electromagnetic induction:
battery less operation, full-wave rectifier circuit, shunt regulator
•
•
Data processing logic circuit: digital PLL, security circuit
High-reliability E2PROM: 4 Kbits
Maximum write time: 7 ms (16-byte batch write)
Overwrite: 100,000 times
Data retention: 10 years
•
•
•
•
•
Selectable receive carrier frequency: 100 kHz to 500 kHz (when external antenna circuit is used)
Programmable security circuit: security level can be set
High-speed transfer rate of 25 kbps: 1/16 of receive carrier frequency = 400 kHz
High-speed multi-read of 32 IDs per second: when receive carrier frequency = 400 kHz (ID only read)
Supplied as chips or on wafer
Chip thickness: 175 µm (typ.)
000707EDA1
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the
buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and
to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or
damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the
most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling
Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy
control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The products described in this document contain components made in the United States and subject to export control of the U.S.
authorities. Diversion contrary to the U.S. law is prohibited.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
• The information contained herein is subject to change without notice.
2000-07-21 1/7
JT6N46S
System Block Diagram
0.1 µF (recommended value)
V
DD
ANT1
V
DD
Rectifier
circuit
Shunt
regulator
Voltage
detector
Data processing,
security and
multi-read functions
ANT2
GND
BGR
2
E PROM
(1 Kbit)
Transmission
circuit
Transmission
control
Modulator
Demodulator
Digital PLL
Carrier
extraction circuit
OSC
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JT6N46S
Pad Allocation
Y
1
2
3
4
5
6
7
X
0
GND
13
12
V
DD
8
ANT2 11
ANT1
10
9
2.35 mm
Pad Coordinates
Pad No.
Pad Name
X-Coordinate (µm)
Y-Coordinate (µm)
1
2
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
ANAPSK0
ANT1
−1010
−1010
−1010
−1010
−1010
−1010
−1010
226
762
622
3
482
4
342
5
202
6
62
7
−78
8
−363
−802
−466
−326
−186
−46
9
770
10
11
12
13
1020
1020
1020
1020
ANT2
V
DD
GND
Note: Values for X-and Y-coordinates are pad center values.
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JT6N46S
Pin Functions
Pin No.
Symbol
Function
Rectifier diode input, antenna connection pin 1
10
11
ANT1
ANT2
Rectifier diode input (carrier extraction input side), antenna connection pin 2
Power supply for bridge circuit output, regulator voltage and internal circuits
GND-internal circuit voltage reference
12
V
DD
13
GND
1~9
LSI test pins
LSI External Specifications
Parameter
Specifications
Power supply
Battery less-externally supplied by electromagnetic induction
Electromagnetic induction
Coupling type
Power feed frequency
100 kHz~200 kHz
Note: An antenna and a capacitor are connected externally.
Receive: PSK, Transmission: PSK
(Reply carrier frequency is half the receive carrier frequency)
Communications method
Transfer speed
Transfer method
Memory size
Write time
7.8 kbps (when receive carrier frequency is 125 kHz) 1/16 of receive carrier frequency
Half-duplex start-stop synchronization transmission (with parity, 1 stop bit)
2
1-Kbit E PROM (256 bits are used as security area.)
7 ms max (for batch write of 8 bytes)
Key checking and access level control by hardware
•
•
Incorporates two access keys (6-byte key and 2-byte status).
Using access keys, read-only or write/read privilege can be set independently for each 32-byte
area (programmable security).
Control circuit
•
•
Block write in units of 8 bytes and block read in units of 16 bytes using an access key and
physical address.
Controls multi-read using Multi-Read command.
Multi-read
10 reads/s (power feed frequency of 125 kHz when ID only is read)
Operating temperature
−20°C~+85°C
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JT6N46S
Functions and Specifications of the Core Block
The JT6N46S is comprised of the following: an RF analog block for power generation, carrier extraction and
regulation, and a digital block for data modulation, demodulation and
2
data processing an E PROM for data storage.
1. Analog Block
(1) Rectifier circuit
Receives radio wave via the (external) antenna circuit and generates DC power for operating internal
circuits with full-wave rectification.
(2) Shunt regulator
Maintains the voltage generated by the rectifier circuit at a fixed voltage, 3.1 V (typ.).
2
The digital circuits and E PROM operate using the voltage supplied by the shunt regulator.
The shunt regulator also protects internal circuits from the effects of strong electric fields.
(3) Carrier extraction circuit
Shapes the PSK-processed received carrier in to a square wave which is then input to the logic
circuits for demodulation.
(4) Oscillation circuit (OSC)
Generates a clock for the digital PLL in the logic block.
(Oscillation frequency range: 3 MHz~5 MHz)
(5) Transmission circuit (parallel transmitter circuit)
Modulates the reply using a resistance load from the ANT1 side of the rectifier circuit. The reply
carrier frequency is half the receive carrier frequency.
At reply, the JT6N46S carries out modulation by halting all blocks except those needed for
transmission and using all the power which would be dissipated by the halted blocks for reply.
(6) Voltage detector
Supports three types of voltage detector circuit for initializing the system and enabling/disabling
2
E PROM writing. As a result, operation is always stable.
2. Digital Block
(1) Demodulator
Converts the PSK signal shaped by the carrier extraction circuit of the analog block into binary data.
(2) Digital PLL
Compares the frequency of the oscillator circuit in the analog block with the signal shaped by the
carrier extraction circuit and generates a clock with a fixed frequency for operation of the entire
digital block. Using the clock the internal LSI operates in synchronize with the carrier.
(3) Data processing
2
Processes data according to the commands received. Processes include parity check, E PROM write
and read, and reset of the entire LSI.
(4) Security logic
2
Two keys can be set simultaneously using the security area allocated to the E PROM. Using the keys,
2
write/read, read or no access can be set in units of 32-byte blocks (obtained by dividing E PROM
memory area by four). (For example, with key A, read/write for a particular block can be set, while
with key B, read/write for any blocks can be set.)
(5) Status reply
Replies to a command from the R/W consist of the status followed by data. The status represents, the
internal status of the LSI to the R/W. If the LSI status is normal, status data 00H is inserted at the
beginning (without any parity, start or end bits) followed by the data. If the LSI status is abnormal,
no data follows and only the status indicating the abnormality is sent. The bit corresponding to each
abnormality condition which has occurred is set to 1 in the status field.
(6) Multi-read
Multi-read is a function used for reading multiple RFIDs in the communications area using the same
reader/writer (R/W). An RFID (LSI) generates a random number internally using the Multi-Read
command transmitted by the R/W. The RFID replies using the response timing determined by the
corresponding time slot. Thus, replies from the different RFIDs will not conflict, enabling data to be
received properly by the R/W.
Note: Depending on the reading environment, the ability to read all the data may fluctuate . In some
cases, some data may be left unread (since it cannot be undetected). Toshiba recommend the use of an
additional chip with a detection function other than the multi-read function.
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JT6N46S
Electrical Characteristics
1. Ratings
Operating Rating
DC40
Parameter
Symbol
Unit
mA
Input current
I
ANT
(between ANT1 → GND → ANT2)
Operating temperature range
Storage temperature range
T
−20~+85
°C
°C
opr
T
−50~+150
stg
*: Unless otherwise specified, the specifications are within the above operating temperature range.
2. DC Characteristics
Test
Circuit
Parameter
Symbol
Description
Min
Typ.
2.0
Max
2.2
Unit
V
Minimum operating voltage
excluding memory write
(Voltage check pin is V .)
Minimum operating voltage 1
V
(min)
DD
DD
Minimum operating voltage
including memory write
Minimum operating voltage 2
Operating current dissipation 1
Operating current dissipation 2
V
(eew)
2.7
350
400
2.9
450
500
V
DD
(Voltage check pin is V .)
DD
Current dissipation for
operations excluding memory
I
I
µA
µA
DDopr1
write (V
= 2.2 V)
DD
Current dissipation for all
operations including memory
DDopr2
write (V
= 2.9 V)
DD
3. Operation Characteristics
Test
Circuit
Parameter
Symbol
Description
Min
100
Typ.
Max
200
Unit
kHz
Carrier frequency at which
operation is possible
Receive carrier frequency
f
crr
Reply carrier frequency
Transfer rate
f
Carrier frequency at reply
Transfer speed
fcrr × 1/2
kHz
bps
psk
fcrr × 1/16
Receiving carrier frequency per
bit
Receive 1-bit frequency
16
Cycles
Reply 1-bit frequency
Reply carrier frequency per bit
8
Cycles
ms
2
E PROM write time
t
7
pw
2
5
No. of
times
E PROM overwrite
Ted
Pre
10
2
Ambient temperature:
E PROM data hold time
10
Years
−20°C~+85°C
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JT6N46S
Memory Map
Page No.
8-Byte Block
Page No.
8-Byte Block
00H
02H
04H
06H
08H
0AH
0CH
0EH
ATR data
Key 0010
Any data
Any data
Any data
Any data
Any data
Any data
01H
03H
05H
07H
09H
0BH
0DH
0FH
ATR data
Key 0101
Any data
Any data
Any data
Any data
Any data
Any data
Note 1: ATR: Answer to Reset. The LSI sends back the ATR data after receiving a reset command or self reset.
Note 2: Using the keys at 02H and 03H, access privileges can be set for the 32-byte blocks (enclosed by bold lines)
from 04H to 1FH.
Note 3: Read is performed in units of 16 bytes from even-numbered addresses, 00H, 02H···0EH.
2
Note 4: Write to E PROM is performed in units of 8 bytes to addresses matching the page numbers above.
The advantage of using this LSI is that it can be supplied as a single LSI for RFID allowing the user to configure
peripherals (e.g. antennae, and reader/writers) so as to develop the desired system. However, because the
peripheral environment may be highly user-specific, incompatibilities between the LSI and the user-configured
environment (communications failures) may occur. Please carry out sufficient research before using this LSI.
2000-07-21 7/7
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