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L6221 [ETC]

QUAD DARLINGTON SWITCH ; QUAD达林顿开关管\n
L6221
型号： L6221
厂家： ETC    ETC
描述：

QUAD DARLINGTON SWITCH
QUAD达林顿开关管\n

开关
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L6221AS L6221AD  
L6221N  
®
QUAD DARLINGTON SWITCH  
.
FOUR NON INVERTING INPUTS WITH  
ENABLE  
OUTPUT VOLTAGE UP TO 50 V  
OUTPUT CURRENT UP TO 1.8 A  
VERY LOW SATURATION VOLTAGE  
TTL COMPATIBLE INPUTS  
.
.
.
.
.
INTEGRAL FAST RECIRCULATION DIODES  
Multiwatt 15  
Powerdip 12 + 2 + 2  
DESCRIPTION  
The L6221 monolithic quad darlington switch is de-  
signed for high current, high voltage switching appli-  
cations. Each of the four switches is controlled by a  
logic input and all four are controlled by a common  
enable input. All inputsare TTL-compatiblefordirect  
connection to logic circuits.  
SO16+2+2  
Each switch consists of an open-collector darlington  
transistor plus a fast diode for switching applications  
with inductive device loads. The emitters of the four  
switches are commoned. Any number of inputs and  
outputs of the same device may be paralleled.  
ORDERING NUMBERS:  
L6221AS (Powerdip)  
L6221N (Multiwatt15)  
L6221AD (SO16+2+2)  
BLOCK DIAGRAM  
1/15  
June 2003  
L6221AS - L6221AD - L6221N  
THERMAL DATA  
Symbol  
Parameter  
SO20  
Powerdip Multiwatt15 Unit  
Rth j-pins  
Rth j-case  
Rth j-amb  
Thermal Resistance Junction-pins  
Thermal Resistance Junction-case  
Thermal Resistance Junction-ambient  
Max.  
Max.  
Max.  
17  
–
80  
14  
–
80  
–
3
35  
°C/W  
°C/W  
°C/W  
PIN CONNECTIONS (top views)  
L6221AS (Powerdip)  
L6221AD (SO16+2+2)  
OUT4  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
IN4  
IN3  
CLAMPB  
N.C.  
N.C.  
ENABLE  
GND  
GND  
VS  
OUT3  
GND  
GND  
OUT2  
N.C.  
N.C.  
IN2  
CLAMPA  
OUT1  
IN1  
D95IN231  
L6221N (Multiwatt-15)  
2/15  
L6221AS - L6221AD - L6221N  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
Parameter  
Value  
Unit  
V
Vo  
Vs  
Output Voltage  
50  
Logic Supply Voltage  
7
V
VIN, VEN  
IC  
Input Voltage, Enable Voltage  
Vs  
Continuous Collector Current (for each channel)  
Collector Peak Current (repetitive, duty cycle = 10 % ton = 5 ms)  
Collector Peak Current (non repetitive, t = 10 µs)  
Operating Temperature Range (junction)  
Storage Temperature Range  
1.8  
2.5  
A
A
A
IC  
IC  
3.2  
Top  
– 40 to + 150  
– 55 to + 150  
350  
°C  
°C  
Tstg  
Isub  
Output Substrate Current  
mA  
Ptot  
4.3  
20  
3.5  
1
2.3  
1
W
W
W
W
W
W
Total Power Dissipation at Tpins = 90 °C  
at Tcase = 90 °C  
(powerdip)  
(multiwatt)  
(SO20)  
(powerdip)  
(multiwatt)  
(SO20)  
at Tcase = 90 °C  
at Tamb = 70 °C  
at Tamb = 70 °C  
at Tamb = 70 °C  
TRUTH TABLE  
Enable  
Input  
Power Out  
H
H
L
H
L
X
ON  
OFF  
OFF  
For each input : H = High level  
L = Low level  
PIN FUNCTIONS (see block diagram)  
Name  
Function  
IN 1  
IN 2  
Input to Driver 1  
Input to Driver 2  
OUT 1  
OUT 2  
CLAMP A  
IN 3  
Output of Driver 1  
Output of Driver 2  
Diode Clamp to Driver 1 and Driver 2  
Input to Driver 3  
IN 4  
Input to Driver 4  
OUT 3  
OUT 4  
CLAMP B  
ENABLE  
VS  
Output of Driver 3  
Output of Driver 4  
Diode Clamp to Driver 3 and Driver 4  
Enable Input to All Drivers  
Logic Supply Voltage  
Common Ground  
GND  
3/15  
L6221AS - L6221AD - L6221N  
ELECTRICAL CHARACTERISTICS  
Refer to the test circuit to Fig. 1 to Fig. 9 (VS = 5V, Tamb = 25oC unless otherwise specified)  
Symbol  
Parameter  
Logic Supply Voltage  
Test Conditions  
Min . Typ . Max . Unit  
VS  
Is  
4.5  
5.5  
V
Logic Supply Current  
All Outputs ON, IC = 0.7A  
All Outputs OFF  
20  
20  
mA  
mA  
VCE(sus)  
ICEX  
Output Sustaining Voltage  
Output Leakage Current  
VIN = VINL, VEN = VEN  
IC = 100 mA  
H
46  
V
mA  
V
VCE = 50V  
VIN = VINL, VEN = VEN  
1
H
VCE(sat)  
Collector Emitter Saturation Voltage  
(one input on ; all others inputs off.)  
Vs = 4.5V  
VIN = VINH, VEN = VEN  
IC = 0.6A  
H
1
1.2  
1.6  
IC = 1A  
IC = 1.8A  
VINL, VEN  
L
Input Low Voltage  
0.8  
V
µ A  
V
IINL, IEN  
L
Input Low Current  
VIN = VINL, VEN = VEN  
L
– 100  
VINL, VEN  
H
Input High Voltage  
2.0  
IINH , IEN  
H
Input High Current  
VIN = VINH, VEN = VEN  
H
± 10 µ A  
IR  
Clamp Diode Leakage Current  
VR = 50 V, VEN = VEN  
H
100  
µ A  
VIN = VINL  
VF  
Clamp Diode Forward Voltage  
IF = 1A  
IF = 1.8A  
1.6  
2.0  
V
V
td (on)  
td (off)  
∆Is  
Turn on Delay Time  
2
5
Vp = 5V, RL = 10Ω  
Vp = 5V, RL = 10Ω  
VIN = 5V, VEN = 5V  
µ s  
µ s  
Turn off Delay Time  
Logic Supply Current Variation  
120 m A  
Iout = – 300 mA for Each Channel  
4/15  
L6221AS - L6221AD - L6221N  
TEST CIRCUITS  
(X) = Referred to Multiwatt package  
X = Referred to Powerdip package  
Figure 1 : Logic supply current.  
Set V IN = 4.5V, V EN = 0.8V, or V IN = 0.8V, V EN = 4.5V, for I S (all outputs off)  
Set V IN = 2V, V EN = 2V, for I S (all outputs on)  
Figure 2 : Output Sustaining Voltage.  
Figure 3 : Output Leakage Current.  
5/15  
L6221AS - L6221AD - L6221N  
Figure 4 :  
Collector-emitter Saturation  
Voltage  
Figure 5 : Logic Input Characteristics  
Set S1, S2 open, VIN, VEN = 0.8V for IIN L, IEN  
Set S1, S2 open, VIN, VEN = 2V for IIN H, IEN  
Set S1, S2 close, VIN, VEN = 0.8V for VIN L, VEN  
Set S1, S2 close, VIN, VEN = 2V for VIN H, VEN  
L
H
L
H
Figure 6 : Clamp Diode Leakage Current.  
Figure 7 : Clamp Diode Forward Voltage.  
6/15  
L6221AS - L6221AD - L6221N  
Figure 8 : Switching Times Test Circuit.  
Figure 9 : Switching TImes Waveforms.  
Figure 10 : Allowed Peak Collector Current ver-  
sus Duty Cycle for 1, 2, 3 or 4 Con-  
temporary Working Outputs  
Figure 11 : Allowed Peak Collector Current ver-  
sus Duty Cycle for 1, 2, 3 or 4 Con-  
temporary Working Outputs  
(L6221N)  
(L6221AS)  
7/15  
L6221AS - L6221AD - L6221N  
Figure 12 : Collector Saturation Voltage versus  
Figure 13 : Free-wheeling Diode Forward Voltage  
Collector Current  
versus Diode Current  
Figure 14 : Collector Saturation Voltage versus  
Figure 15 : Free-wheeling Diode Forward Voltage  
versus Junction Temperature  
at IF = 1A  
Junction Temperature at IC = 1A  
Figure 16 : Saturation Voltage vs. Junc-  
Figure 17 : Free-wheeling Diode Forward  
8/15  
L6221AS - L6221AD - L6221N  
APPLICATION INFORMATION  
Figure 18.  
When inductive loads are driven by L6221A/N, a  
zener diode in series with the integral free-wheeling  
diodes increases the voltage across which energy  
stored in the load is discharged and therefore  
speeds the current decay (fig. 18).  
For reliability it is suggested that the zener is chosen  
so that Vp + Vz < 35 V.  
The reasons for this are two fold :  
1) The zener voltage changes in temperature and  
current.  
2)The instantaneous power must be limitedto avoid  
the reverse second breakdown.  
Figure 19 : Driver for Solenoids up to 3A.  
Some care must be taken to ensure that the collec-  
tors are placed close together to avoid different cur-  
rent partitioning at turn-off.  
We suggest to put in parallel channel 1 and 4 and  
channel 2 and 3 as shown in figure 19 for the similar  
electrical characteristics of the logic section (turn-on  
and turn-off delay time) and the power stages (col-  
lector saturation voltage, free-wheeling diode for-  
ward voltage).  
9/15  
L6221AS - L6221AD - L6221N  
Figure 20 : Saturation Voltage versus Collector  
Figure 21 : Peak Collector Current versus Duty  
Cycle for 1 or 2 Paralleled Outputs  
Driven (L6221AS)  
Current  
Figure 22 : Peak Collector Current versus Duty  
Cycle for 1 or 2 Paralleled Outputs  
Driven (L6221N)  
10/15  
L6221AS - L6221AD - L6221N  
MOUNTING INSTRUCTION  
The Rth j-amb of the L6221AS can be reduced by sol-  
dering the GND pins to a suitable copper area of the  
printed circuit board (Fig. 23) or to an external  
heatsink (Fig. 24).  
ing a thickness of 35µ (1.4 mils). During soldering  
the pins temperature must not exceed 260 °C and  
the soldering time must not be longer than 12 sec-  
onds.  
The diagram of figure 25 shows the maximum dis-  
sipable power Ptot and the Rth j-amb as a function of  
the side " α" of two equal square copper areas hav-  
The external heatsink or printed circuit copper area  
must be connected to electrical ground.  
Figure 23 : Example of P.C. Board Copper Area  
Figure 24 : External Heatsink Mounting Example  
Which is Used as Heatsink  
Figure 25 : Maximum Dissipable Power and Junc-  
tion to Ambient Thermal Resistance  
versus Side " α"  
Figure 26 : Maximum Allowable Power Dissipa-  
tion versus Ambient Temperature  
11/15  
L6221AS - L6221AD - L6221N  
mm  
inch  
DIM.  
OUTLINE AND  
MECHANICAL DATA  
MIN. TYP. MAX. MIN. TYP. MAX.  
a1  
B
b
0.51  
0.85  
0.020  
1.40 0.033  
0.055  
0.50  
0.020  
b1  
D
E
e
0.38  
0.50 0.015  
20.0  
0.020  
0.787  
8.80  
2.54  
0.346  
0.100  
0.700  
e3  
F
17.78  
7.10  
5.10  
0.280  
0.201  
I
L
3.30  
0.130  
Powerdip 16  
Z
1.27  
0.050  
12/15  
L6221AS - L6221AD - L6221N  
mm  
inch  
DIM.  
OUTLINE AND  
MIN. TYP. MAX. MIN. TYP. MAX.  
MECHANICAL DATA  
A
B
5
0.197  
0.104  
0.063  
2.65  
1.6  
C
D
1
0.039  
E
0.49  
0.66  
1.02  
0.55 0.019  
0.75 0.026  
0.022  
0.030  
F
G
1.27  
1.52 0.040 0.050 0.060  
G1  
H1  
H2  
L
17.53 17.78 18.03 0.690 0.700 0.710  
19.6  
0.772  
20.2  
0.795  
21.9  
21.7  
22.2  
22.1  
22.5 0.862 0.874 0.886  
22.5 0.854 0.870 0.886  
L1  
L2  
L3  
L4  
L7  
M
17.65  
18.1 0.695  
0.713  
17.25 17.5 17.75 0.679 0.689 0.699  
10.3  
2.65  
4.25  
4.63  
1.9  
10.7  
10.9 0.406 0.421 0.429  
2.9 0.104 0.114  
4.55  
5.08  
4.85 0.167 0.179 0.191  
5.53 0.182 0.200 0.218  
M1  
S
2.6  
2.6  
0.075  
0.075  
0.102  
0.102  
0.152  
S1  
Dia1  
1.9  
Multiwatt15 V  
3.65  
3.85 0.144  
13/15  
L6221AS - L6221AD - L6221N  
mm  
inch  
OUTLINE AND  
MECHANICAL DATA  
DIM.  
MIN. TYP. MAX. MIN. TYP. MAX.  
A
A1  
B
C
D
E
e
2.35  
0.1  
2.65 0.093  
0.3 0.004  
0.104  
0.012  
0.020  
0.013  
0.512  
0.299  
0.33  
0.23  
12.6  
7.4  
0.51 0.013  
0.32 0.009  
13  
0.496  
0.291  
7.6  
1.27  
0.050  
H
h
10  
0.25  
0.4  
10.65 0.394  
0.75 0.010  
0.419  
0.030  
0.050  
L
1.27 0.016  
SO20  
K
0˚ (min.)8˚ (max.)  
L
h x 45˚  
A
B
A1  
K
C
e
H
D
20  
11  
E
1
10  
SO20MEC  
14/15  
L6221AS - L6221AD - L6221N  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the conse-  
quences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No  
license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this  
publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMi-  
croelectronics products are not authorized for use as critical components in life support devices or systems without express written  
approval of STMicroelectronics.  
The ST logo is a registered trademark of STMicroelectronics  
© 2003 STMicroelectronics – Printed in Italy – All Rights Reserved  
STMicroelectronics GROUP OF COMPANIES  
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco -  
Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.  
http://www.st.com  
15/15  

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