LA75505M [ETC]

;
LA75505M
型号: LA75505M
厂家: ETC    ETC
描述:

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Ordering number : ENN*6930  
Monolithic Linear IC  
LA75505M  
Adjustment Free VIF/SIF Signal Processing IC  
for TV/VCR  
Preliminary  
Overview  
Package Dimensions  
The LA75505M is a VIF/SIF signal processing IC for  
NTSC TV/VCR. It supports the 45.75 MHz and 58.75  
MHz as the IF frequencies. On-chip sound carrier trap and  
sound carrier BPF circuits make it ideal for compact and  
light-weight tuner applications. To adjust the VCO circuit,  
AFT circuit, and sound filter, 4-MHz external crystal or 4-  
MHz external signal is needed.  
unit: mm  
3112-MFP24S  
[LA75505M]  
24  
13  
Functions  
• VIF amplifier  
• VCO adjustment free PLL detection circuit  
• Digital AFT circuit  
1
12  
0.15  
12.6  
• RF AGC  
• Buzz canceller  
0.35  
1.0 0.8  
• Equalizer amplifier  
SANYO: MFP24S (300 mil)  
• Internal sound carrier BPF  
• Internal sound carrier trap  
• PLL-FM detector  
• Reference oscillation circuit  
Features  
• Internal VCO adjustment free circuit eliminating need  
for VCO coil adjustments.  
• Considerably reduces the number of required peripheral  
parts by providing on-chip sound carrier BPF and sound  
carrier trap circuits.  
• Use of digital AFT eliminates problem of AFT  
tolerance.  
• Package: MFP24S (300 mil)  
Any and all SANYO products described or contained herein do not have specifications that can handle  
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s  
control systems, or other applications whose failure can be reasonably expected to result in serious  
physical and/or material damage. Consult with your SANYO representative nearest you before using  
any SANYO products described or contained herein in such applications.  
SANYO assumes no responsibility for equipment failures that result from using products at values that  
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other  
parameters) listed in products specifications of any and all SANYO products described or contained  
herein.  
SANYO Electric Co.,Ltd. Semiconductor Company  
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN  
41301RM (OT) No. 6930-1/13  
LA75505M  
Specifications  
Maximum Ratings at Ta = 25°C  
Parameter  
Maximum supply voltage  
Allowable power dissipation  
Operating temperature  
Storage temperature  
Symbol  
Conditions  
Ratings  
Unit  
V
V
CC max  
Pd max  
Topr  
7
Ta 70°C (*Mounted on a printed circuit board)  
470  
–20 to +70  
–55 to +150  
mW  
°C  
Tstg  
°C  
Note: * Circuit board dimensions: 114.3 × 76.1 × 1.6 mm3, material: glass epoxy  
Operating Conditions at Ta = 25°C  
Parameter  
Recommended supply voltage  
Operating voltage range  
Symbol  
VCC  
Conditions  
Ratings  
5
Unit  
V
V
CC op  
4.5 to 5.5  
V
Electrical Characteristics at Ta = 25°C, V = 5.0 V, fp = 45.75 MHz  
CC  
Ratings  
typ  
Parameter  
Symbol  
Conditions  
Unit  
min  
max  
[VIF Block ]  
Circuit current  
I17  
V14H  
V14L  
Vi  
64.0  
73.6  
mA  
V
Maximum RF AGC voltage  
Minimum RF AGC voltage  
Input sensitivity  
Collector load 30 kVC2 = 9 V  
8.5  
9
0.3  
39  
0.7  
45  
V
33  
58  
dBµV  
dB  
dBµV  
V
AGC range  
GR  
Maximum allowable input  
No-signal video output voltage  
Synchronizing signal tip voltage  
Video output level  
Vimax  
V4  
92  
97  
3.6  
1.3  
2.0  
50  
3.3  
1.0  
1.7  
46  
3.9  
1.6  
2.3  
V4tip  
VO  
V
Vpp  
dB  
dB  
%
Video signal-to-noise ratio  
C-S beating  
S/N  
IC-S  
DG  
P/S = 10 dB  
Vin = 80 dBµ  
26  
32  
38  
10  
Differential gain  
3
Differential phase  
DP  
2
10  
deg  
kΩ  
PF  
V
VIF input resistance  
Ri  
2.5  
3
3.0  
6
VIF input capacitance  
Maximum AFT voltage  
Minimum AFT voltage  
AFT tolerance 1  
Ci  
V13H  
V13L  
dfa1  
dfa2  
Sf  
4.3  
0
4.7  
0.2  
±35  
±45  
80  
5.0  
0.7  
±45  
±70  
V
f = 45.75 MHz  
kHz  
kHz  
AFT tolerance 2  
f = 58.75 MHz  
AFT detection sensitivity  
AFT dead zone  
RL = 100 k//100 kΩ  
40  
120 mV/kHz  
fda  
60  
100  
kHz  
MHz  
MHz  
MHz  
MHz  
APC pull-in range (U)  
APC pull-in range (L)  
VCO maximum frequency range (U)  
VCO maximum frequency range (L)  
VCO control sensitivity  
N trap1 (4.75 MHz)  
fpu  
1.0  
1.0  
1.5  
1.5  
2.0  
–30  
–19  
10  
1.5  
1.5  
2.0  
2.0  
4.0  
–35  
–24  
40  
fpl  
dfu  
dfl  
β
8.0 kHz/mV  
NT1  
NT2  
NGD1  
wrt 1 MHz  
wrt 1 MHz  
wrt 1 MHz  
dB  
dB  
N trap2 (5.25 MHz)  
Group delay 1 NTSC (3.0 MHz)  
Group delay 1-1 NTSC (3.5 MHz)  
70  
ns  
ns  
NGD1-1 wrt 1 MHz  
70  
120  
170  
Continued on next page.  
No. 6930-2/13  
LA75505M  
Continued from preceding page.  
Ratings  
typ  
Parameter  
Symbol  
Conditions  
Unit  
min  
max  
[1st SIF Block]  
Conversion gain  
Vg  
So  
fp = 4.5 MHz, Vi = 500µV  
26  
32  
100  
106  
5.0  
3
dB  
mVrms  
dBµV  
kΩ  
SIF carrier output level  
First SIF maximum input  
First SIF input resistance  
First SIF input capacitance  
[SIF Block]  
Vi = 10 mV  
So ±2 dB  
Simax  
Ris  
6.0  
Cis  
6
pF  
Limiting sensitivity  
Vi(lim)  
Vo(FM)  
AMR  
61  
dBµV  
mVrms  
dB  
fp = 4.5 MHz, F = ±25 kHz at 400 Hz  
FM detector output voltage  
AM rejection ratio  
480  
50  
600  
60  
750  
AM = 30% at 400 Hz  
Total harmonic distortion  
FM detector output S/N  
BPF 3-dB bandwidth  
NTSC de-emphasis  
THD  
f = 4.5 MHz, F = ±25 kHz  
0.5  
1.0  
%
S/N(FM)  
BW  
55  
60  
dB  
±100  
–3  
kHz  
dB  
Ndeem fm = 2 kHz  
[Others]  
4-MHz level (during external input)  
IF system SW threshold resistance  
Split/inter SW  
X4MIN  
V12  
Terminated  
86  
dBµ  
kΩ  
V
270  
V16  
0.5  
No. 6930-3/13  
LA75505M  
System Switching  
• IF system switch  
45.75 MHz is selected as the IF frequency by leaving pin 12 (crystal oscillation) open. 58.75 MHz is selected by  
adding 220 kbetween pin 12 and GND.  
• Split/inter carrier switch  
Inter carrier is selected by setting the first SIF input (pin 16) to GND.  
Pin Assignment  
1
2
3
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
SIF INPUT  
FM FILTER  
1st SIF OUT  
VIDEO DET OUT  
EQ OUT  
FM DET OUT  
RF AGC VR  
SIF PLL FILTER  
FILTER CONTROL CAPACITOR  
VIF INPUT  
4
5
6
APC FILTER  
FLL FILTER  
VCO COIL  
VIF INPUT  
LA75505M  
7
8
GND  
VCC  
9
VCO COIL  
1st SIF INPUT  
IF AGC FILTER  
RF AGC OUT  
AFT OUT  
10  
11  
12  
SIF AGC FILTER  
NC  
REF OSC  
Top view  
No. 6930-4/13  
LA75505M  
Test Circuit  
Input Impedance Measuring Circuit (VIF, First SIF input impedance)  
Impedance analyzer  
VIF INPUT  
1st SIF INPUT  
V
CC  
+
24 23 22 21 20 19 18 17 16 15 14 13  
LA75505M  
1
2
3
4
5
6
7
8
10 11 12  
9
Top view  
No. 6930-5/13  
LA75505M  
Pin Functions  
Pin No.  
Pin  
Pin Function  
Internal Circuit  
Inputs the SIF signal from the first SIF output.  
1
SIF INPUT  
Set the input level to 90 dBµV or lower because of  
the dynamic range of the internal filter.  
This is the FM feedback filter pin. It is composed of  
a C and R filters.  
1 µF is normally used as the capacitance.  
If the capacitance is a low value, the audio output  
level is small at low frequencies.  
2
FM FILTER  
Moreover, the audio output level can be made  
smaller by increasing the resistance connected in  
series.  
Use a resistance of 3 kor higher.  
This is the first SIF output.  
In case of inter carrier, the chroma carrier is bigger  
than split carrier applications, so that it is  
recommended to connect a filter externally.  
1st SIF OUT  
3
Filter example  
Continued on next page.  
No. 6930-6/13  
LA75505M  
Continued from preceding page.  
Pin No.  
Pin  
Pin Function  
Internal Circuit  
Pin 4 is the video output pin.  
The EQ amplifier can be thought of as shown  
below.  
4
5
VIDEO-OUT  
EQ-OUT  
Therefore, the peak gain of the EQ amplifier is  
determined by Av = 1 + R/Z.  
However, note that the LA75505M being an IC with  
VCC = 5 V, setting too large an amplitude causes  
distortion in the VCC side. Use so that the white  
level is 4 V or less.  
Pin 6 is the PLL detector APC filter pin.  
Normally the following are used:  
R = 330 Ω  
C1 = 0.47 µ to 1 µF  
C2 = 100 pF  
C1 = 1 µF is effective for the overmodulation  
characteristics.  
When the PLL is locked, the signal passes via the  
path marked A in the figure, and when PLL is  
unlocked and in weak signal, the signal passes via  
the path marked B in the figure. The PLL loop gain  
can thus be switched in this manner.  
Time  
constant switch  
6
7
APC FILTER  
FLL FILTER  
output  
Pin 7 is a VCO automatic control FLL filter pin.  
Since it operates always on a small current, using a  
larger capacitance results in a slower response.  
Normally, a capacitance between 0.47 µF and 1 µF  
is used.  
Moreover, the control range for this pin is between  
about 3 V to 4.7 V. Since this range is determined  
when adjusting the VCO tank circuit, set the design  
center of L and C of VCO so that the voltage of pin  
7 is 3.6 V.  
output  
This is the VCO tank circuit for the PLL detector.  
Use a tuning capacitance of 24 pF.  
For the L and C specifications, use IF45.75 MHz  
specifications within ±1.5%, and 58.75 MHz  
specifications within ±1%. Also, design the L and C  
values so that the voltage of pin 7 is 3.6 V when  
PLL is locked while using the IF center frequency.  
8
9
VCO COIL  
Continued on next page.  
No. 6930-7/13  
LA75505M  
Continued from preceding page.  
Pin No.  
Pin  
Pin Function  
Internal Circuit  
Pin 10 is the SIF AGC filter pin. Use a capacitance  
of 0.01 µF to 0.1 µF.  
SIF AGC FILTER  
10  
10  
11  
NC  
Not connected  
This pin can be used both as the crystal resonator  
pin and IF switch.  
The 58.75-MHz mode is selected by inserting 220  
kbetween pin 12 and GND, the 45.75 MHz mode  
by leaving the pin open.  
REF OSC  
12  
4-MHz input is possible from this pin.  
In the case of 4-MHz external input, input 86 dBµ  
or more.  
Pin 13 is the AFT output pin.  
Use external resistors of 47 kand a filter  
capacitance 0.1 µF.  
The AFT circuit generates the AFT voltage by  
comparing the signal obtained by dividing the  
4-MHz reference frequency with the signal obtained  
by dividing VCO.  
Since it uses a digital phase comparator, a dead  
zone exists in the AFT center.  
13  
AFT OUT  
waveform  
Continued on next page.  
No. 6930-8/13  
LA75505M  
Continued from preceding page.  
Pin No.  
Pin  
Pin Function  
Internal Circuit  
Pin 14 is the RF AGC output.  
RF AGC max is determined by R1 and R2.  
RF AGC min is determined by R3 and R4.  
Capacitor C1 prevents oscillation and capacitor C2  
is the RF AGC filter.  
14  
RF AGC OUT  
Normally 30 kis used for R1, but if the tuner's F/E  
transistor is GaAS, the gate's impedance is lower,  
so use approx. 10 k.  
Pin 15 is the IF AGC filter pin.  
Normally, 0.01 µF to 0.02 µF polyester film  
capacitor is used.  
15  
IF AGC FILTER  
Determine the impedance based on H-SAG and  
AGC speed.  
Pin 16 can be used both as the First SIF IN and  
inter/split switch pins.  
In the case of inter carrier, connect pin 16 to GND.  
When a sound saw filter is added, the matching  
loss can be decreased by inserting L to neutralize  
the IC input capacitance and saw filter output  
capacitance.  
16  
1st SIF INPUT  
Continued on next page.  
No. 6930-9/13  
LA75505M  
Continued from preceding page.  
Pin No.  
17  
Pin  
Pin Function  
Internal Circuit  
Connect the decoupling capacitor as close as  
possible.  
VCC  
18  
GND  
Pins 19 and 20 are VIF input pins.  
To reduce the loss of signal through a saw filter,  
input registors are set to 2 k.  
VIF amplifier has three capacitive coupling  
amplifiers, direct connection from a saw filter is  
available.  
19  
20  
VIF INPUT  
Internal filters (i.e. sound carrier BPF and sound  
carrier trap) are tuned using the capacitor  
connected to pin 21.  
FILTER CONTROL  
CAPACITOR  
21  
A value between 0.47 µF and 1 µF is considered  
desirable taking video S/N, and AM and PM noise  
into consideration.  
Continued on next page.  
No. 6930-10/13  
LA75505M  
Continued from preceding page.  
Pin No.  
Pin  
Pin Function  
Internal Circuit  
Pin 22 is the SIF PLL filter pin.  
Normally use the following values.  
R: 3 kΩ  
C1: 0.01 µF  
C2: 1000 pF  
SIF PLL FILTER  
22  
When R is too large, the PLL may become  
unlocked, so use a resistance value within 6 k. A  
smaller R value results in low-pass noise.  
Pin 23 is the RF AGC VR pin.  
23  
RF AGC VR  
When this pin is connected to GND, no signal is  
appeared on pin 4 and pin 24.  
Pin 24 is the FM output pin.  
Time constance of de-emphasis is determined by  
external C, R.  
24  
FM DET OUT  
Please chose C, R to make time constance 75 µs.  
No. 6930-11/13  
LA75505M  
Sample Application Circuit  
IF INPUT  
0.01µ  
VCC(5V)  
VCC(9V)  
SAW(S)  
30k  
0.01µ  
0.01µ  
AGC OUT  
RF  
0.01µ  
0.1µ  
100µ  
3k  
AUDIO  
OUT  
1µ  
0.02µ  
15  
0.01µ  
SAW(P)  
7.5k  
47k  
47k  
13  
1000p  
23  
AFT OUT  
24  
22  
21  
20  
19  
18  
17  
16  
14  
FM  
DET  
1st  
AMP  
VIF  
S
PLL  
FM  
DET  
AMP  
AFT  
AMP  
IF  
AGC  
AGC  
FIL  
CONT  
VIDEO  
DET  
APC  
DET  
1stSIF  
DET  
Unit  
Capacitance: F  
Resistance: Ω  
LIM  
AMP  
AMP  
SW  
BPF  
EQ  
AMP  
LPF  
VCO  
TRAP  
FLL  
BPF  
1
2
3
4
5
6
7
8
9
10  
11  
12  
IF SW  
1µ  
220k  
OPEN:45.75MHz  
GND :58.75MHz  
3k  
1µ  
330  
2k  
0.01µ  
VCO COIL  
1µ  
4MHz  
X’tal  
VIDEO OUT  
CARRIER OUT  
39p  
No. 6930-12/13  
LA75505M  
Specifications of any and all SANYO products described or contained herein stipulate the performance,  
characteristics, and functions of the described products in the independent state, and are not guarantees  
of the performance, characteristics, and functions of the described products as mounted in the customer’s  
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,  
the customer should always evaluate and test devices mounted in the customer’s products or equipment.  
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all  
semiconductor products fail with some probability. It is possible that these probabilistic failures could  
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,  
or that could cause damage to other property. When designing equipment, adopt safety measures so  
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective  
circuits and error prevention circuits for safe design, redundant design, and structural design.  
In the event that any or all SANYO products (including technical data, services) described or contained  
herein are controlled under any of applicable local export control laws and regulations, such products must  
not be exported without obtaining the export license from the authorities concerned in accordance with the  
above law.  
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or  
mechanical, including photocopying and recording, or any information storage or retrieval system,  
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.  
Any and all information described or contained herein are subject to change without notice due to  
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”  
for the SANYO product that you intend to use.  
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not  
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but  
no guarantees are made or implied regarding its use or any infringements of intellectual property rights  
or other rights of third parties.  
This catalog provides information as of April, 2001. Specifications and information herein are subject to  
change without notice.  
PS No. 6930-13/13  

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