LC35256DM-10 [ETC]
;
| 型号： | LC35256DM-10 |
| 厂家： | 
ETC |
| 描述： |
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| 文件： | 总8页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : EN5823
CMOS IC
LC35256D-10, LC35256DM, DT-70/10
Dual Control Pins: OE and CE
256K (32768-word × 8-bit) SRAM
Overview
Package Dimensions
The LC35256D, LC35256DM, and LC35256DT are
32768-word × 8-bit asynchronous silicon gate CMOS
static RAMs. These devices use a 6-transistor full CMOS
memory cell, and feature low-voltage operation, low
current drain, and an ultralow standby current. They
provide two control signal inputs: an OE input for high-
speed access and a chip select (CE) input for device
selection and low power operating mode. This makes
these devices optimal for systems that require low power
or battery backup, and they allow memory to be expanded
easily. Their ultralow standby current allows capacitor-
based backup to be used as well. Since they support 3-V
operation, they are appropriate for use in portable systems
that operate from batteries.
unit: mm
3012A-DIP28
[LC35256D]
SANYO: DIP28
unit: mm
Features
3187-SOP28D
• Supply voltage range: 2.7 to 5.5 V
[LC35256DM]
— 5-V operation:
— 3-V operation:
• Access times
5.0 V±10%
2.7 to 3.6 V
— 5-V operation
LC35256DM, DT-70: 70 ns (max)
LC35256D, DM, DT-10: 100 ns (max)
— 3-V operation
LC35256DM, DT-70: 200 ns (max)
LC35256D, DM, DT-10: 500 ns (max)
• Standby current
SANYO: SOP28D
— 5-V operation: 1.0 µA (Ta ≤ 60°C),
5.0 µA (Ta ≤ 85°C)
— 3-V operation: 0.8 µA (Ta ≤ 60°C),
4.0 µA (Ta ≤ 85°C)
unit: mm
3221-TSOP28(type-I)
[LC35256DT]
• Operating temperature range: –40 to +85°C
• Data retention supply voltage: 2.0 to 5.5 V
• All I/O levels
— 5-V operation: TTL compatible
— 3-V operation: V – 0.2 V/0.2 V
CC
• Shared I/O pins and 3-state outputs
• No clock signal required.
• Packages
— 28-pin DIP (600 mil) plastic package: LC35256D
— 28-pin SOP (450 mil) plastic package: LC35256DM
— 28-pin TSOP (8 × 13.4 mm) plastic package:
LC35256DT
SANYO: TSOP28(type-I)
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
51398RM (OT) No. 5823-1/8
LC35256D-10, LC35256DM, DT-70/10
Pin Assignment
Block Diagram
Memory cell array
Output
data
Column
I/O circuit
buffer
Column
decoder
Address buffer
Pin Functions
A0 to A14
Address inputs
WE
OE
Read/write control input
Output enable input
Chip enable input
Data I/O
CE
I/O1 to I/O8
VCC, GND
Power supply, ground
No. 5823-2/8
LC35256D-10, LC35256DM, DT-70/10
Function Table
Mode
Read cycle
Write cycle
Output disable
Unselected
CE
L
OE
L
WE
H
I/O
Supply current
ICCA
Data output
L
X
L
Data input
ICCA
L
H
H
High-impedance
High-impedance
ICCA
H
X
X
ICCS
X : H or L
Specifications
Absolute Maximum Ratings
Parameter
Maximum supply voltage
Input pin voltage
Symbol
Conditions
Ratings
Unit
V
VCC max
7.0
VIN
–0.3* to VCC + 0.3
–0.3 to VCC + 0.3
–40 to +85
V
I/O pin voltage
VI/O
V
Operating temperature
Storage temperature
Topr
Tstg
°C
°C
–55 to +125
Note *: –3.0 V for pulse widths of up to 30 ns.
I/O Capacitances at Ta = 25°C, f = 1 MHz
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
10
10
I/O pin capacitance
Input pin capacitance
CI/O
CIN
VI/O = 0 V
VIN = 0 V
6
6
pF
pF
Note: These parameters are not measured in all units, but rather are only measured in sampled units.
[5-V Operation]
DC Allowable Operating Ranges at Ta = –40 to +85°C, V = 4.5 to 5.5 V
CC
Ratings
typ
Parameter
Supply voltage
Input voltages
Symbol
Conditions
Unit
min
4.5
max
VCC
VIH
VIL
5.0
5.5
VCC + 0.3
+0.8
V
V
V
2.2
–0.3*
Note *: –3.0 V for pulse widths of up to 30 ns.
DC Electrical Characteristics at Ta = –40 to +85°C, V = 4.5 to 5.5 V
CC
Ratings
Parameter
Symbol
Conditions
Unit
min
–1.0
–1.0
2.4
typ*
max
+1.0
+1.0
Input leakage current
ILI
ILO
VIN = 0 to VCC
µA
µA
V
Output leakage current
High-level output voltage
Low-level output voltage
VCE = VIH or VOE = VIH or VWE = VIL, VI/O = 0 to VCC
IOH = –1.0 mA
VOH
VOL
ICCA2
IOL = 2.0 mA
0.4
5.0
40
V
VCE = VIL, II/O = 0 mA, VIN = VIH or VIL
min LC35256DM, DT-70
mA
mA
mA
mA
µA
µA
µA
mA
Operating
35
25
TTL inputs
VCE = VIL, VIN = VIH or VIL,
current drain
ICCA3
cycle LC35256D, DM, DT-10
1 µs cycle
30
II/O = 0 mA, Duty 100%
3.5
6.0
Ta ≤ 25°C
0.01
V
CC – 0.2 V/
VCE ≥ VCC – 0.2 V,
Standby mode
current drain
ICCS1
Ta ≤ 60°C
1.0
5.0
1.0
0.2 V inputs
VIN = 0 to VCC
Ta ≤ 85°C
TTL inputs
ICCS2
VCE = VIH, VIN = 0 to VCC
Note *: Reference value at Ta = 25°C, VCC = 5 V.
No. 5823-3/8
LC35256D-10, LC35256DM, DT-70/10
AC Electrical Characteristics at Ta = –40 to +85°C, V = 4.5 to 5.5 V
CC
AC test conditions
Input pulse voltage level
Input rise and fall times
Input and output timing level
VIH = 2.4 V, VIL = 0.6 V
5 ns
1.5 V
LC35256DM, DT-70
LC35256D, DM, DT-10
One TTL gate + 30 pF (Including jig capacitances.)
One TTL gate + 100 pF (Including jig capacitances.)
Output load
Read Cycle
LC35256D, DM, DT
Parameter
Symbol
-70*
-10
Unit
min
70
max
min
100
max
Read cycle time
tRC
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
CE access time
70
70
35
100
100
50
tCA
OE access time
tOA
Output hold time
tOH
10
10
5
10
10
5
CE output enable time
OE output enable time
CE output disable time
OE output disable time
tCOE
tOOE
tCOD
tOOD
30
25
30
25
Note *: Specification values for the LC35256DM and LC35256DT.
Write Cycle
LC35256D, DM, DT
Parameter
Symbol
-70*
-10
Unit
min
70
0
max
min
max
Write cycle time
Address setup time
Write pulse width
CE setup time
tWC
tAS
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWP
55
60
0
60
70
0
tCW
tWR
tWR1
tDS
Write recovery time
CE write recovery time
Data setup time
0
0
35
0
40
0
Data hold time
tDH
CE data hold time
WE output enable time
WE output disable time
tDH1
tWOE
tWOD
0
0
5
5
30
30
Note *: Specification values for the LC35256DM and LC35256DT.
[3-V Operation]
DC Allowable Operating Ranges at Ta = –40 to +85°C, V = 2.7 to 3.6 V
CC
Ratings
typ
Parameter
Supply voltage
Input voltages
Symbol
Conditions
Unit
min
2.7
max
3.6
VCC
VIH
VIL
3.0
V
V
V
VCC – 0.2
VCC + 0.3
+0.2
–0.3*
Note *: –2.0 V for pulse widths of up to 30 ns.
No. 5823-4/8
LC35256D-10, LC35256DM, DT-70/10
DC Electrical Characteristics at Ta = –40 to +85°C, V = 2.7 to 3.6 V
CC
Ratings
Parameter
Symbol
Conditions
Unit
min
–1.0
typ*
max
+1.0
Input leakage current
ILI
VIN = 0 to VCC
µA
µA
V
Output leakage current
High-level output voltage
Low-level output voltage
ILO
VCE = VIH or VOE = VIH or VWE = VIL, VI/O = 0 to VCC
IOH = –0.5 mA
–1.0
+1.0
VOH
VOL
VCC – 0.2
IOL = 1.0 mA
0.2
10
5
V
min LC35256DM, DT-70
7
3
mA
mA
mA
µA
µA
µA
Operating
V
CC – 0.2 V/
VCE = VIL, VIN = VIH or VIL,
ICCA4
cycle LC35256D, DM, DT-10
II/O = 0 mA, Duty 100%
1 µs cycle
current drain
0.2 V inputs
1.5
0.01
2.5
Ta ≤ 25°C
Standby mode
current drain
V
CC – 0.2 V/
V
CE ≥ VCC – 0.2 V,
ICCS1
Ta ≤ 60°C
Ta ≤ 85°C
0.8
4.0
0.2 V inputs
VIN = 0 to VCC
Note *: Reference value at Ta = 25°C, VCC = 3 V.
AC Electrical Characteristics at Ta = –40 to +85°C, V = 2.7 to 3.6 V
CC
AC test conditions
Input pulse voltage level
Input rise and fall times
Input and output timing level
VIH = VCC – 0.2 V, VIL = 0.2 V
10 ns
1.5 V
LC35256DM, DT-70
LC35256D, DM, DT-10
30 pF (Including jig capacitances.)
100 pF (Including jig capacitances.)
Output load
Read Cycle
LC35256D, DM, DT
Parameter
Symbol
-70*
-10
Unit
min
200
max
min
500
max
Read cycle time
tRC
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
CE access time
200
200
100
500
500
250
tCA
OE access time
tOA
Output hold time
tOH
20
20
10
20
20
10
CE output enable time
OE output enable time
CE output disable time
OE output disable time
tCOE
tOOE
tCOD
tOOD
60
50
120
100
Note *: Specification values for the LC35256DM and LC35256DT.
No. 5823-5/8
LC35256D-10, LC35256DM, DT-70/10
Write Cycle
LC35256D, DM, DT
Parameter
Symbol
-70*
-10
Unit
min
200
0
max
min
max
Write cycle time
Address setup time
Write pulse width
CE setup time
tWC
tAS
500
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWP
140
150
0
200
250
0
tCW
tWR
tWR1
tDS
Write recovery time
CE write recovery time
Data setup time
0
0
130
0
180
0
Data hold time
tDH
CE data hold time
WE output enable time
WE output disable time
tDH1
tWOE
tWOD
0
0
10
10
60
120
Note *: Specification values for the LC35256DM and LC35256DT.
Timing Charts
1
Read Cycle *
5
*
No. 5823-6/8
LC35256D-10, LC35256DM, DT-70/10
6
Write Cycle 1 (WE write) *
5
*
6
Write Cycle 2 (CE write) *
5
*
Notes: 1. Applications must set WE high during the read cycle.
2. External circuits in the application must not apply reverse phase signals to the DOUT pins when those pins are in the output state.
3. The time tWP is the period when CE and WE are both low. It is defined as the time from the fall of WE to the rise of CE or the rise of WE, whichever
occurs first.
4. The time tCW is the period when CE and WE are both low. It is defined as the time from the fall of CE to the rise of CE or the rise of WE, whichever
occurs first.
5. The data outputs (DOUT) go to the high-impedance state if any one of the following conditions hold: OE is high, CE is high, or WE is low.
6. OE must be held either high or low during the write cycle.
7. The DOUT pins have the same phase as the write cycle write data.
No. 5823-7/8
LC35256D-10, LC35256DM, DT-70/10
Notes on Circuit Design
Take the following operations into account when designing circuits that use these products to assure that none of the
items in the maximum ratings are exceeded.
• Supply voltage variations and fluctuations
• Manufacturing variations in the electrical characteristics of the electrical components, including semiconductor
devices, resistors, and capacitors.
• Ambient temperature
• Variations and fluctuations in the input and clock signals
• Possible application of abnormal pulses
Parameters listed in the allowable operating ranges must never exceed their stipulated ranges.
If input pins to a CMOS IC are left open, through currents may occur in internal circuits to which intermediate potentials
are input and result in incorrect circuit operation. Always verify that any unused pins are set up in appropriate states.
Data Retention Characteristics at Ta = –40 to +85°C
Ratings
Parameter
Symbol
VDR
Conditions
Unit
1
min
2.0
typ*
max
5.5
Data retention supply voltage
V
CE ≥ VCC – 0.2 V
V
Ta ≤ 25°C
Ta ≤ 60°C
Ta ≤ 85°C
0.01
µA
µA
µA
ns
ns
V
CC = 3.0 V,
Data retention current drain
ICCDR
0.7
3.5
V
CE ≥ VCC – 0.2 V
Chip enable setup time
Chip enable hold time
tCDR
tR
0
2
tRC
*
Notes: 1. Reference value at Ta = 25°C, VCC = 3 V.
2. tRC: Read cycle time
Data Retention Waveforms
Data retention mode
Note *: VCCL
5-V operation: 4.5 V
3-V operation: 2.7 V
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of May, 1998. Specifications and information herein are subject to change
without notice.
PS No. 5823-8/8
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