LH28F800BVE-TV85 [ETC]
x8/x16 Flash EEPROM ; X8 / X16闪存EEPROM
| 型号： | LH28F800BVE-TV85 |
| 厂家： | 
ETC |
| 描述： | x8/x16 Flash EEPROM
|
| 文件： | 总48页 (文件大小：549K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRODUCT SPECIFICATIONS
Integrated Circuits Group
®
LH28F800BVE-TV85
Flash Memory
8M (1MB × 8/512K × 16)
(Model No.: LHF80V25)
Spec No.: EL109061B
Issue Date: September 16, 1999
LHF80V25
sharp
●Handle this document carefully for it contains material protected by international copyright law.
Any reproduction, full or in part, of this material is prohibited without the express written
permission of the company.
●When using the products covered herein, please observe the conditions written herein and the
precautions outlined in the following paragraphs. In no event shall the company be liable for any
damages resulting from failure to strictly adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application
areas. When using the products covered herein for the equipment listed in Paragraph (2),
even for the following application areas, be sure to observe the precautions given in
Paragraph (2). Never use the products for the equipment listed in Paragraph (3).
•Office electronics
•Instrumentation and measuring equipment
•Machine tools
•Audiovisual equipment
•Home appliance
•Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment which
demands high reliability, should first contact a sales representative of the company and then
accept responsibility for incorporating into the design fail-safe operation, redundancy, and
other appropriate measures for ensuring reliability and safety of the equipment and the
overall system.
•Control and safety devices for airplanes, trains, automobiles, and other
transportation equipment
•Mainframe computers
•Traffic control systems
•Gas leak detectors and automatic cutoff devices
•Rescue and security equipment
•Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands
extremely high performance in terms of functionality, reliability, or accuracy.
•Aerospace equipment
•Communications equipment for trunk lines
•Control equipment for the nuclear power industry
•Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above three
Paragraphs to a sales representative of the company.
●Please direct all queries regarding the products covered herein to a sales representative of the
company.
Rev. 1.1
LHF80V25
CONTENTS
PAGE
1
sharp
PAGE
1 INTRODUCTION..............................................................3
1.1 Features ........................................................................3
1.2 Product Overview.........................................................3
5 DESIGN CONSIDERATIONS ...................................... 20
5.1 Three-Line Output Control ....................................... 20
5.2 RY/BY# and Block Erase and Word/Byte Write
Polling...................................................................... 20
5.3 Power Supply Decoupling ........................................ 20
2 PRINCIPLES OF OPERATION........................................7
2.1 Data Protection.............................................................8
5.4 V Trace on Printed Circuit Boards........................ 20
PP
5.5 V , V , RP# Transitions....................................... 21
CC
PP
3 BUS OPERATION ............................................................8
3.1 Read..............................................................................8
3.2 Output Disable..............................................................8
3.3 Standby.........................................................................8
3.4 Deep Power-Down .......................................................8
3.5 Read Identifier Codes Operation..................................9
3.6 Write.............................................................................9
5.6 Power-Up/Down Protection...................................... 21
5.7 Power Dissipation..................................................... 21
6 ELECTRICAL SPECIFICATIONS ............................... 22
6.1 Absolute Maximum Ratings ..................................... 22
6.2 Operating Conditions................................................ 22
6.2.1 Capacitance......................................................... 22
6.2.2 AC Input/Output Test Conditions ....................... 23
6.2.3 DC Characteristics .............................................. 24
6.2.4 AC Characteristics - Read-Only Operations....... 26
6.2.5 AC Characteristics - Write Operations ............... 29
6.2.6 Alternative CE#-Controlled Writes..................... 31
6.2.7 Reset Operations ................................................. 33
6.2.8 Block Erase and Word/Byte Write Performance 34
4 COMMAND DEFINITIONS.............................................9
4.1 Read Array Command................................................12
4.2 Read Identifier Codes Command ...............................12
4.3 Read Status Register Command.................................12
4.4 Clear Status Register Command.................................12
4.5 Block Erase Command...............................................12
4.6 Word/Byte Write Command.......................................13
4.7 Block Erase Suspend Command ................................13
4.8 Word/Byte Write Suspend Command ........................14
4.9 Considerations of Suspend .........................................14
4.10 Block Locking..........................................................14
4.10.1 V =V for Complete Protection......................14
7 PACKAGE AND PACKING SPECIFICATIONS......... 35
PP
IL
4.10.2 WP#=V for Block Locking..............................14
IL
4.10.3 WP#=V for Block Unlocking..........................14
IH
Rev. 1.1
sharp
LHF80V25
2
LH28F800BVE-TV85
8M-BIT (1Mbit × 8 / 512Kbit × 16)
Smart5 Flash MEMORY
■ Smart5 Technology
■ Enhanced Data Protection Features
Absolute Protection with V =GND
4.5V-5.5V V
CC
PP
4.5V-5.5V or 11.4V-12.6V V
Block Erase and Word/Byte Write Lockout
during Power Transitions
PP
■ User-Configurable ×8 or ×16 Operation
Boot Blocks Protection with WP#=V
IL
■ High-Performance Access Time
■ Automated Word/Byte Write and Block Erase
Command User Interface
85ns(4.5V-5.5V)
Status Register
■ Operating Temperature
0°C to +70°C
■ Low Power Management
Deep Power-Down Mode
■ Optimized Array Blocking Architecture
Two 4K-word Boot Blocks
Automatic Power Savings Mode Decreases
I
in Static Mode
CC
Six 4K-word Parameter Blocks
Fifteen 32K-word Main Blocks
Top Boot Location
■ SRAM-Compatible Write Interface
■ Industry-Standard Packaging
■ Extended Cycling Capability
48-Lead TSOP
100,000 Block Erase Cycles
TM*
■ ETOX
Nonvolatile Flash Technology
■ Enhanced Automated Suspend Options
Word/Byte Write Suspend to Read
Block Erase Suspend to Word/Byte Write
Block Erase Suspend to Read
■ CMOS Process (P-type silicon substrate)
■ Not designed or rated as radiation hardened
SHARP’s LH28F800BVE-TV85 Flash memory with Smart5 technology is a high-density, low-cost, nonvolatile, read/write
storage solution for a wide range of applications. LH28F800BVE-TV85 can operate at VCC=4.5V-5.5V and VPP=4.5V-5.5V.
Its low voltage operation capability realize battery life and suits for cellular phone application.
Its Boot, Parameter and Main-blocked architecture, flexible voltage and extended cycling provide for highly flexible
component suitable for portable terminals and personal computers. Its enhanced suspend capabilities provide for an ideal
solution for code + data storage applications. For secure code storage applications, such as networking, where code is either
directly executed out of flash or downloaded to DRAM, the LH28F800BVE-TV85 offers two levels of protection: absolute
protection with VPP at GND, selective hardware boot block locking. These alternatives give designers ultimate control of their
code security needs.
The LH28F800BVE-TV85 is manufactured on SHARP’s 0.35µm ETOXTM* process technology. It come in industry-standard
package: the 48-lead TSOP ideal for board constrained applications.
*ETOX is a trademark of Intel Corporation.
Rev. 1.1
sharp
LHF80V25
3
eliminates the need for a separate 12V converter, while
PP=12V maximizes block erase and word/byte write
1 INTRODUCTION
V
performance. In addition to flexible erase and program
voltages, the dedicated VPP pin gives complete data
This datasheet contains LH28F800BVE-TV85
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the memory
organization and functionality. Section 6 covers electrical
specifications.
protection when VPP≤VPPLK
.
Table 1. VCC and VPP Voltage Combinations Offered by
Smart5 Technology
1.1 Features
VCC Voltage
4.5V-5.5V
VPP Voltage
4.5V-5.5V, 11.4V-12.6V
Key enhancements of LH28F800BVE-TV85 Smart5 Flash
memory are:
Internal VCC and VPP detection Circuitry automatically
configures the device for optimized read and write
operations.
•Smart5 Technology
•Enhanced Suspend Capabilities
•Boot Block Architecture
A Command User Interface (CUI) serves as the interface
between the system processor and internal operation of the
device. A valid command sequence written to the CUI
initiates device automation. An internal Write State
Machine (WSM) automatically executes the algorithms
and timings necessary for block erase and word/byte write
operations.
Please note following important differences:
•VPPLK has been lowered to 1.5V to support 4.5V-5.5V
block erase and word/byte write operations. The VPP
voltage transitions to GND is recommended for
designs that switch VPP off during read operation.
A block erase operation erases one of the device’s 32K-
word blocks typically within 0.39s (5V VCC, 12V VPP),
4K-word blocks typically within 0.25s (5V VCC, 12V
VPP) independent of other blocks. Each block can be
independently erased 100,000 times. Block erase suspend
mode allows system software to suspend block erase to
read or write data from any other block.
•To take advantage of Smart5 technology, allow VCC
and VPP connection to 4.5V-5.5V.
1.2 Product Overview
The LH28F800BVE-TV85 is a high-performance 8M-bit
Smart5 Flash memory organized as 1M-byte of 8 bits or
512K-word of 16 bits. The 1M-byte/512K-word of data is
arranged in two 8K-byte/4K-word boot blocks, six 8K-
byte/4K-word parameter blocks and fifteen 64K-byte/32K-
word main blocks which are individually erasable in-
system. The memory map is shown in Figure 3.
Writing memory data is performed in word/byte
increments of the device’s 32K-word blocks typically
within 8.4µs (5V VCC, 12V VPP), 4K-word blocks
typically within 17µs (5V VCC, 12V VPP). Word/byte
write suspend mode enables the system to read data or
execute code from any other flash memory array location.
Smart5 technology provides a choice of VCC and VPP
combinations, as shown in Table 1, to meet system
performance and power expectations. VPP at 4.5V-5.5V
Rev. 1.2
sharp
LHF80V25
4
The boot blocks can be locked for the WP# pin. Block
erase or word/byte write for boot block must not be carried
The Automatic Power Savings (APS) feature substantially
reduces active current when the device is in static mode
(addresses not switching). In APS mode, the typical ICCR
out by WP# to Low and RP# to VIH
.
current is 1mA at 5V VCC
.
The status register indicates when the WSM’s block erase
or word/byte write operation is finished.
When CE# and RP# pins are at VCC, the ICC CMOS
standby mode is enabled. When the RP# pin is at GND,
deep power-down mode is enabled which minimizes
power consumption and provides write protection during
reset. A reset time (tPHQV) is required from RP# switching
high until outputs are valid. Likewise, the device has a
wake time (tPHEL) from RP#-high until writes to the CUI
are recognized. With RP# at GND, the WSM is reset and
the status register is cleared.
The RY/BY# output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software polling) and status masking (interrupt
masking for background block erase, for example). Status
polling using RY/BY# minimizes both CPU overhead and
system power consumption. When low, RY/BY# indicates
that the WSM is performing a block erase or word/byte
write. RY/BY#-high Z indicates that the WSM is ready for
a new command, block erase is suspended (and word/byte
write is inactive), word/byte write is suspended, or the
device is in deep power-down mode.
The device is available in 48-lead TSOP (Thin Small
Outline Package, 1.2 mm thick). Pinout is shown in Figure
2.
The access time is 85ns (tAVQV) over the commercial
temperature range (0°C to +70°C) and VCC supply voltage
range of 4.5V-5.5V.
Rev. 1.2
LHF80V25
5
sharp
DQ0-DQ15
Input
Buffer
Output
Buffer
A-1
BYTE#
VCC
I/O
Logic
Identifier
Register
CE#
WE#
OE#
RP#
WP#
Command
User
Interface
Status
Register
Data
Comparator
RY/BY#
VPP
Y
Write
State
Machine
Y-Gating
Input
Buffer
Decoder
A0-A18
Program/Erase
Voltage
Switch
Address
Latch
15
X
VCC
32K-Word
Decoder
GND
Main blocks
Address
Counter
Figure 1. Block Diagram
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
48
A16
BYTE#
GND
DQ15/A-1
DQ7
1
2
3
4
5
6
7
8
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-LEAD TSOP
STANDARD PINOUT
12mm x 20mm
WE#
RP#
VPP
WP#
RY/BY#
A18
A17
A7
TOP VIEW
A6
A5
A4
A3
A2
A1
OE#
GND
CE#
A0
Figure 2. TSOP 48-Lead Pinout
Rev. 1.1
LHF80V25
6
sharp
Table 2. Pin Descriptions
Symbol
Type
Name and Function
ADDRESS INPUTS: Addresses are internally latched during a write cycle.
A
: Byte Select Address. Not used in ×16 mode.
: Row Address. Selects 1 of 2048 word lines.
-1
A
-1
INPUT A -A
0
10
A -A
0
18
A -A : Column Address. Selects 1 of 16 bit lines.
11 14
A -A : Main Block Address. (Boot and Parameter block Addresses are A -A .)
15 18
12 18
DATA INPUT/OUTPUTS:
DQ -DQ :Inputs data and commands during CUI write cycles; outputs data during memory array,
0
7
status register and identifier code read cycles. Data pins float to high-impedance when the chip is
INPUT/ deselected or outputs are disabled. Data is internally latched during a write cycle.
DQ -DQ
0
15
OUTPUT DQ -DQ :Inputs data during CUI write cycles in ×16 mode; outputs data during memory array
8
15
read cycles in ×16 mode; not used for status register and identifier code read mode. Data pins float
to high-impedance when the chip is deselected, outputs are disabled, or in ×8 mode (Byte#=V ).
IL
Data is internally latched during a write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense amplifiers.
CE#-high deselects the device and reduces power consumption to standby levels.
CE#
RP#
INPUT
INPUT
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal
automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations
which provides data protection during power transitions. Exit from deep power-down sets the
device to read array mode. With RP#=V , block erase or word/byte write can operate to all
HH
blocks without WP# state. Block erase or word/byte write with V <RP#<V produce spurious
IH
HH
results and should not be attempted.
OE#
INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on
the rising edge of the WE# pulse.
WE#
INPUT
INPUT
INPUT
WRITE PROTECT: Master control for boot blocks locking. When V , locked boot blocks cannot
IL
WP#
be erased and programmed.
BYTE ENABLE: BYTE# V places device in ×8 mode. All data is then input or output on DQ
,
IL
0-7
BYTE#
and DQ
float. BYTE# V places the device in ×16 mode , and turns off the A input buffer.
8-15
IH -1
READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is performing an
internal operation (block erase or word/byte write). RY/BY#-high Z indicates that the WSM is
ready for new commands, block erase is suspended, and word/byte write is inactive, word/byte
write is suspended, or the device is in deep power-down mode.
OPEN
DRAIN
OUTPUT
RY/BY#
BLOCK ERASE AND WORD/BYTE WRITE POWER SUPPLY: For erasing array blocks or
writing words/bytes. With V ≤V
, memory contents cannot be altered. Block erase and
word/byte write with an invalid V (see DC Characteristics) produce spurious results and should
PP
PPLK
V
SUPPLY
PP
PP
not be attempted.
DEVICE POWER SUPPLY: Do not float any power pins. With V ≤V
, all write attempts to
CC
LKO
V
SUPPLY
the flash memory are inhibited. Device operations at invalid V voltage (see DC Characteristics)
CC
CC
produce spurious results and should not be attempted.
GND
NC
SUPPLY GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internal connected; it may be driven or floated.
Rev. 1.1
LHF80V25
7
sharp
2 PRINCIPLES OF OPERATION
[A18-A0]
Top Boot
The LH28F800BVE-TV85 Smart5 Flash memory includes
an on-chip WSM to manage block erase and word/byte
write functions. It allows for: 100% TTL-level control
inputs, fixed power supplies during block erasure and
word/byte write, and minimal processor overhead with
RAM-like interface timings.
7FFFF
4K-word Boot Block
0
1
7F000
7EFFF
4K-word Boot Block
7E000
7DFFF
4K-word Parameter Block
4K-word Parameter Block
4K-word Parameter Block
4K-word Parameter Block
4K-word Parameter Block
4K-word Parameter Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
0
7D000
7CFFF
1
7C000
7BFFF
After initial device power-up or return from deep power-
down mode (see Bus Operations), the device defaults to
read array mode. Manipulation of external memory control
pins allow array read, standby and output disable
operations.
2
7B000
7AFFF
3
7A000
79FFF
4
79000
78FFF
Status register and identifier codes can be accessed
5
through the CUI independent of the V voltage. High
78000
77FFF
PP
voltage on V
enables successful block erasure and
PP
0
70000
6FFFF
word/byte writing. All functions associated with altering
memory contents−block erase, word/byte write, status and
identifier codes−are accessed via the CUI and verified
through the status register.
1
68000
67FFF
2
60000
5FFFF
3
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the block erase and word/byte write.
The internal algorithms are regulated by the WSM,
including pulse repetition, internal verification and
margining of data. Addresses and data are internally latch
during write cycles. Writing the appropriate command
outputs array data, accesses the identifier codes or outputs
status register data.
58000
57FFF
4
50000
4FFFF
5
48000
47FFF
6
40000
3FFFF
7
38000
37FFF
8
30000
2FFFF
Interface software that initiates and polls progress of block
erase and word/byte write can be stored in any block. This
code is copied to and executed from system RAM during
flash memory updates. After successful completion, reads
are again possible via the Read Array command. Block
erase suspend allows system software to suspend a block
erase to read/write data from/to blocks other than that
which is suspend. Word/byte write suspend allows system
software to suspend a word/byte write to read data from
any other flash memory array location.
9
28000
27FFF
10
11
12
13
14
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
00000
Figure 3. Memory Map
Rev. 1.1
LHF80V25
8
sharp
2.1 Data Protection
3.2 Output Disable
Depending on the application, the system designer may
With OE# at a logic-high level (V ), the device outputs
IH
choose to make the V
power supply switchable
are disabled. Output pins (DQ -DQ ) are placed in a
PP
0
15
(available only when memory block erases or word/byte
writes are required) or hardwired to V . The device
high-impedance state.
PPH1/2
accommodates either design practice and encourages
optimization of the processor-memory interface.
3.3 Standby
CE# at a logic-high level (V ) places the device in
IH
When V ≤V
, memory contents cannot be altered.
standby mode which substantially reduces device power
consumption. DQ -DQ outputs are placed in a high-
PP
PPLK
The CUI, with two-step block erase or word/byte write
command sequences, provides protection from unwanted
0
15
impedance state independent of OE#. If deselected during
block erase or word/byte write, the device continues
functioning, and consuming active power until the
operation completes.
operations even when high voltage is applied to V . All
write functions are disabled when V is below the write
lockout voltage V
PP
CC
or when RP# is at V . The device’s
LKO
IL
boot blocks locking capability for WP# provides
additional protection from inadvertent code or data
alteration by block erase and word/byte write operations.
Refer to Table 6 for write protection alternatives.
3.4 Deep Power-Down
RP# at V initiates the deep power-down mode.
IL
In read modes, RP#-low deselects the memory, places
output drivers in a high-impedance state and turns off all
internal circuits. RP# must be held low for a minimum of
3 BUS OPERATION
The local CPU reads and writes flash memory in-system.
All bus cycles to or from the flash memory conform to
standard microprocessor bus cycles.
100 ns. Time t
is required after return from power-
PHQV
down until initial memory access outputs are valid. After
this wake-up interval, normal operation is restored. The
CUI is reset to read array mode and status register is set to
80H.
3.1 Read
Information can be read from any block, identifier codes
During block erase or word/byte write modes, RP#-low
will abort the operation. RY/BY# remains low until the
reset operation is complete. Memory contents being
altered are no longer valid; the data may be partially
or status register independent of the V voltage. RP# can
PP
be at either V or V
.
IH
HH
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes or Read
Status Register) to the CUI. Upon initial device power-up
or after exit from deep power-down mode, the device
automatically resets to read array mode. Six control pins
dictate the data flow in and out of the component: CE#,
OE#, WE#, RP#, WP# and BYTE#. CE# and OE# must be
driven active to obtain data at the outputs. CE# is the
device selection control, and when active enables the
selected memory device. OE# is the data output
(DQ -DQ ) control and when active drives the selected
erased or written. Time t
is required after RP# goes
PHWL
to logic-high (V ) before another command can be
IH
written.
As with any automated device, it is important to assert
RP# during system reset. When the system comes out of
reset, it expects to read from the flash memory. Automated
flash memories provide status information when accessed
during block erase or word/byte write modes. If a CPU
reset occurs with no flash memory reset, proper CPU
initialization may not occur because the flash memory
may be providing status information instead of array data.
SHARP’s flash memories allow proper CPU initialization
following a system reset through the use of the RP# input.
In this application, RP# is controlled by the same RESET#
signal that resets the system CPU.
0
15
memory data onto the I/O bus. WE# must be at V and
IH
RP# must be at V or V . Figure 11, 12 illustrates read
IH
HH
cycle.
Rev. 1.1
LHF80V25
9
sharp
3.5 Read Identifier Codes Operation
3.6 Write
The read identifier codes operation outputs the
manufacturer code and device code (see Figure 4). Using
the manufacturer and device codes, the system CPU can
automatically match the device with its proper algorithms.
Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection and
clearing of the status register. When V =4.5V-5.5V and
CC
V
=V
, the CUI additionally controls block erasure
PP
PPH1/2
and word/byte write.
[A18-A0]
7FFFF
The Block Erase command requires appropriate command
data and an address within the block to be erased. The
Word/Byte Write command requires the command and
address of the location to be written.
Reserved for Future Implementation
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active. The
address and data needed to execute a command are latched
on the rising edge of WE# or CE# (whichever goes high
first). Standard microprocessor write timings are used.
Figures 13 and 14 illustrate WE# and CE# controlled write
operations.
00002
00001
00000
Device Code
Manufacturer Code
4 COMMAND DEFINITIONS
Figure 4. Device Identifier Code Memory Map
When the V voltage ≤ V
, Read operations from the
PP
PPLK
status register, identifier codes, or blocks are enabled.
Placing V on V enables successful block erase
PPH1/2
PP
and word/byte write operations.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these commands.
Rev. 1.1
LHF80V25
10
sharp
(1,2)
Table 3.1. Bus Operations(BYTE#=V )
IH
(3)
Mode
Read
Notes
8
RP#
or
CE#
OE#
WE#
Address
V
DQ
D
RY/BY#
X
PP
0-15
V
IH
V
V
V
X
X
IL
IL
IH
OUT
V
HH
V
V
or
IH
Output Disable
V
V
V
X
X
High Z
X
X
IL
IH
IH
HH
or
V
V
IH
Standby
10
4,10
8
V
X
X
X
X
X
X
X
X
X
High Z
High Z
Note 5
IH
HH
Deep Power-Down
Read Identifier Codes
V
X
High Z
High Z
IL
or
V
V
See
Figure 4
IH
V
V
V
IL
IL
IH
HH
V
V
or
IH
Write
6,7,8
V
V
V
X
X
D
X
IL
IH
IL
IN
HH
(1,2)
Table 3.2. Bus Operations(BYTE#=V )
IL
(3)
Mode
Read
Notes
8
RP#
or
CE#
OE#
WE# Address
V
DQ
D
DQ
RY/BY#
High Z X
PP
0-7
8-15
V
IH
V
V
V
X
X
X
IL
IL
IH
IH
OUT
V
HH
V
V
or
IH
Output Disable
V
V
V
X
High Z High Z
X
IL
IH
HH
V
V
or
IH
Standby
10
4,10
8,9
V
X
X
X
X
X
X
X
X
High Z High Z
High Z High Z
Note 5 High Z
X
IH
HH
Deep Power-Down
Read Identifier Codes
V
X
X
High Z
High Z
IL
or
V
V
See
Figure 4
IH
V
V
V
IH
IL
IL
HH
V
V
or
IH
Write
6,7,8
V
V
V
X
X
D
IN
X
X
IL
IH
IL
HH
NOTES:
1. Refer to DC Characteristics. When V ≤V
, memory contents can be read, but not altered.
PP
PPLK
2. X can be V or V for control pins and addresses, and V
or V
for V . See DC Characteristics for V
and
IL
IH
PPLK
PPH1/2
PP
PPLK
V
voltages.
PPH1/2
3. RY/BY# is V when the WSM is executing internal block erase or word/byte write algorithms. It is High Z during when
OL
the WSM is not busy, in block erase suspend mode (with word/byte write inactive), word/byte write suspend mode or
deep power-down mode.
4. RP# at GND±0.2V ensures the lowest deep power-down current.
5. See Section 4.2 for read identifier code data.
6. Command writes involving block erase or word/byte write are reliably executed when V =V
and V =4.5V-5.5V.
CC
PP
PPH1/2
Block erase or word/byte write with V <RP#<V produce spurious results and should not be attempted.
IH
HH
7. Refer to Table 4 for valid D during a write operation.
IN
8. Never hold OE# low and WE# low at the same timing.
9.
A
set to V or V in byte mode (BYTE#=V ).
-1
IL
IL
IH
IH
IL
10. WP# set to V or V .
Rev. 1.1
LHF80V25
11
sharp
(7)
Table 4. Command Definitions
Bus Cycles
First Bus Cycle
Second Bus Cycle
(1)
(2)
(3)
(1)
(2)
(3)
Command
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Req’d.
Notes
4
Oper
Addr
Data
Oper
Addr
Data
1
≥2
2
Write
Write
Write
Write
Write
X
X
FFH
90H
70H
50H
20H
Read
Read
IA
X
ID
X
SRD
1
X
2
5
BA
Write
Write
BA
D0H
WD
40H or
10H
Word/Byte Write
2
1
1
5,6
Write
Write
Write
WA
X
WA
Block Erase and Word/Byte
Write Suspend
5
5
B0H
D0H
Block Erase and Word/Byte
Write Resume
X
NOTES:
1. BUS operations are defined in Table 3.1 and Table 3.2.
2. X=Any valid address within the device.
IA=Identifier Code Address: see Figure 4. A set to V or V in Byte Mode (BYTE#=V ).
-1
IL
IH
IL
BA=Address within the block being erased. The each block can select by the address pin A through A combination.
18
12
WA=Address of memory location to be written.
3. SRD=Data read from status register. See Table 7 for a description of the status register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID=Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer and device codes. See Section 4.2 for
read identifier code data.
5. If the block is boot block, WP# must be at V or RP# must be at V
operations. Attempts to issue a block erase or word/byte write to a boot block while WP# is V or RP# is V .
6. Either 40H or 10H are recognized by the WSM as the word/byte write setup.
to enable block erase or word/byte write
IH
HH
IH
IH
7. Commands other than those shown above are reserved by SHARP for future device implementations and should not be
used.
Rev. 1.1
LHF80V25
12
sharp
4.1 Read Array Command
4.4 Clear Status Register Command
Upon initial device power-up and after exit from deep
power-down mode, the device defaults to read array mode.
This operation is also initiated by writing the Read Array
command. The device remains enabled for reads until
another command is written. Once the internal WSM has
started a block erase or word/byte write, the device will
not recognize the Read Array command until the WSM
completes its operation unless the WSM is suspended via
an Erase Suspend or Word/Byte Write Suspend command.
The Read Array command functions independently of the
Status register bits SR.5, SR.4, SR.3 or SR.1 are set to
"1"s by the WSM and can only be reset by the Clear Status
Register command. These bits indicate various failure
conditions (see Table 7). By allowing system software to
reset these bits, several operations (such as cumulatively
erasing multiple blocks or writing several words/bytes in
sequence) may be performed. The status register may be
polled to determine if an error occurred during the
sequence.
To clear the status register, the Clear Status Register
command (50H) is written. It functions independently of
the applied V Voltage. RP# can be V or V . This
V
voltage and RP# can be V or V
.
PP
IH
HH
4.2 Read Identifier Codes Command
PP
IH
HH
command is not functional during block erase or
word/byte write suspend modes.
The identifier code operation is initiated by writing the
Read Identifier Codes command. Following the command
write, read cycles from addresses shown in Figure 4
retrieve the manufacturer and device codes (see Table 5
for identifier code values). To terminate the operation,
write another valid command. Like the Read Array
command, the Read Identifier Codes command functions
independently of the V voltage and RP# can be V or
4.5 Block Erase Command
Erase is executed one block at a time and initiated by a
two-cycle command. A block erase setup is first written,
followed by an block erase confirm. This command
sequence requires appropriate sequencing and an address
within the block to be erased (erase changes all block data
to FFFFH). Block preconditioning, erase, and verify are
handled internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written, the
device automatically outputs status register data when read
(see Figure 5). The CPU can detect block erase completion
by analyzing the output data of the RY/BY# pin or status
register bit SR.7.
PP
IH
V
. Following the Read Identifier Codes command, the
HH
following information can be read:
Table 5. Identifier Codes
Address
Data
Code
[A -A ] [DQ -DQ ]
18
0
7
0
Manufacture Code
Device Code
00000H
00001H
B0H
4CH
When the block erase is complete, status register bit SR.5
should be checked. If a block erase error is detected, the
status register should be cleared before system software
attempts corrective actions. The CUI remains in read
status register mode until a new command is issued.
4.3 Read Status Register Command
The status register may be read to determine when a block
erase or word/byte write is complete and whether the
operation completed successfully. It may be read at any
time by writing the Read Status Register command. After
writing this command, all subsequent read operations
output data from the status register until another valid
command is written. The status register contents are
latched on the falling edge of OE# or CE#, whichever
This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Block Erase command sequence will
result in both status register bits SR.4 and SR.5 being set
to "1". Also, reliable block erasure can only occur when
V
=4.5V-5.5V and V =V
. In the absence of this
occurs. OE# or CE# must toggle to V before further
CC
PP
PPH1/2
IH
high voltage, block contents are protected against erasure.
reads to update the status register latch. The Read Status
If block erase is attempted while V ≤V , SR.3 and
Register command functions independently of the V
PP
PPLK
PP
SR.5 will be set to "1". Successful block erase for boot
blocks requires that the corresponding if set, that
WP#=V or RP#=V . If block erase is attempted to
voltage. RP# can be V or V
.
IH
HH
IH
HH
boot block when the corresponding WP#=V
or
IL
RP#=V , SR.1 and SR.5 will be set to "1". Block erase
IH
operations with V <RP#<V
produce spurious results
IH
HH
and should not be attempted.
Rev. 1.1
LHF80V25
13
sharp
4.6 Word/Byte Write Command
4.7 Block Erase Suspend Command
Word/byte write is executed by a two-cycle command
sequence. Word/byte write setup (standard 40H or
alternate 10H) is written, followed by a second write that
specifies the address and data (latched on the rising edge
of WE#). The WSM then takes over, controlling the
word/byte write and write verify algorithms internally.
After the word/byte write sequence is written, the device
automatically outputs status register data when read (see
Figure 6). The CPU can detect the completion of the
word/byte write event by analyzing the RY/BY# pin or
status register bit SR.7.
The Block Erase Suspend command allows block-erase
interruption to read or word/byte write data in another
block of memory. Once the block-erase process starts,
writing the Block Erase Suspend command requests that
the WSM suspend the block erase sequence at a
predetermined point in the algorithm. The device outputs
status register data when read after the Block Erase
Suspend command is written. Polling status register bits
SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to "1").
RY/BY# will also transition to High Z. Specification
t
defines the block erase suspend latency.
WHRZ2
When word/byte write is complete, status register bit SR.4
should be checked. If word/byte write error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for "1"s that do not successfully write
to "0"s. The CUI remains in read status register mode until
it receives another command.
At this point, a Read Array command can be written to
read data from blocks other than that which is suspended.
A Word/Byte Write command sequence can also be issued
during erase suspend to program data in other blocks.
Using the Word/Byte Write Suspend command (see
Section 4.8), a word/byte write operation can also be
suspended. During a word/byte write operation with block
erase suspended, status register bit SR.7 will return to "0"
Reliable word/byte writes can only occur when
V
=4.5V-5.5V and V =V
. In the absence of this
CC
PP
PPH1/2
high voltage, memory contents are protected against
word/byte writes. If word/byte write is attempted while
and the RY/BY# output will transition to V . However,
SR.6 will remain "1" to indicate block erase suspend
status.
OL
V
≤V
, status register bits SR.3 and SR.4 will be set
PP
PPLK
to "1". Successful word/byte write for boot blocks requires
that the corresponding if set, that WP#=V or RP#=V
The only other valid commands while block erase is
suspended are Read Status Register and Block Erase
Resume. After a Block Erase Resume command is written
to the flash memory, the WSM will continue the block
erase process. Status register bits SR.6 and SR.7 will
.
HH
IH
If word/byte write is attempted to boot block when the
corresponding WP#=V or RP#=V , SR.1 and SR.4 will
IL
IH
be set to "1". Word/byte write operations with
V <RP#<V produce spurious results and should not be
IH
HH
automatically clear and RY/BY# will return to V . After
attempted.
OL
the Erase Resume command is written, the device
automatically outputs status register data when read (see
Figure 7). V must remain at V
(the same V
PP
PPH1/2
PP
level used for block erase) while block erase is suspended.
RP# must also remain at V or V (the same RP# level
IH
HH
used for block erase). WP# must also remain at V or V
IL
IH
(the same WP# level used for block erase). Block erase
cannot resume until word/byte write operations initiated
during block erase suspend have completed.
Rev. 1.1
LHF80V25
14
sharp
4.8 Word/Byte Write Suspend Command
4.10 Block Locking
The Word/Byte Write Suspend command allows
word/byte write interruption to read data in other flash
memory locations. Once the word/byte write process
starts, writing the Word/Byte Write Suspend command
requests that the WSM suspend the word/byte write
sequence at a predetermined point in the algorithm. The
device continues to output status register data when read
after the Word/Byte Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can determine
when the word/byte write operation has been suspended
(both will be set to "1"). RY/BY# will also transition to
This Boot Block Flash memory architecture features two
hardware-lockable boot blocks so that the kernel code for
the system can be kept secure while other blocks are
programmed or erased as necessary.
4.10.1 V =V for Complete Protection
PP
IL
The V
programming voltage can be held low for
PP
complete write protection of all blocks in the flash device.
4.10.2 WP#=V for Block Locking
IL
High Z. Specification t
suspend latency.
defines the word/byte write
WHRZ1
The lockable blocks are locked when WP#=V ; any
IL
program or erase operation to a locked block will result in
an error, which will be reflected in the status register. For
top configuration, the top two boot blocks are lockable.
For the bottom configuration, the bottom tow boot blocks
are lockable. Unlocked blocks can be programmed or
At this point, a Read Array command can be written to
read data from locations other than that which is
suspended. The only other valid commands while
word/byte write is suspended are Read Status Register and
Word/Byte Write Resume. After Word/Byte Write
Resume command is written to the flash memory, the
WSM will continue the word/byte write process. Status
register bits SR.2 and SR.7 will automatically clear and
erased normally (Unless V is below V
).
PP
PPLK
4.10.3 WP#=V for Block Unlocking
IH
RY/BY# will return to V . After the Word/Byte Write
Resume command is written, the device automatically
OL
WP#=V unlocks all lockable blocks.
IH
outputs status register data when read (see Figure 8). V
PP
These blocks can now be programmed or erased.
must remain at V
(the same V level used for
PPH1/2
PP
word/byte write) while in word/byte write suspend mode.
RP# must also remain at V or V (the same RP# level
WP# controls 2 boot blocks locking and V provides
protection against spurious writes. Table 6 defines the
write protection methods.
PP
IH
HH
used for word/byte write). WP# must also remain at V or
IL
V
(the same WP# level used for word/byte write).
IH
4.9 Considerations of Suspend
After the suspend command write to the CUI, read status
register command has to write to CUI, then status register
bit SR.6 or SR.2 should be checked for places the device
in suspend mode.
Table 6. Write Protection Alternatives
Operation
V
RP#
X
WP#
X
Effect
PP
V
All Blocks Locked.
All Blocks Locked.
All Blocks Unlocked.
2 Boot Blocks Locked.
All Blocks Unlocked.
IL
Block Erase
or
V
X
IL
>V
V
X
PPLK
HH
Word/Byte Write
V
V
IH
IL
V
IH
Rev. 1.1
LHF80V25
15
sharp
Table 7. Status Register Definition
WSMS
7
ESS
ES
5
WBWS
VPPS
WBWSS
2
DPS
1
R
0
6
4
3
NOTES:
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
Check RY/BY# or SR.7 to determine block erase or
word/byte write completion. SR.6-0 are invalid while
SR.7="0".
1 = Ready
0 = Busy
SR.6 = ERASE SUSPEND STATUS (ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
If both SR.5 and SR.4 are "1"s after a block erase attempt,
an improper command sequence was entered.
SR.4 = WORD/BYTE WRITE STATUS (WBWS)
1 = Error in Word/Byte Write
0 = Successful Word/Byte Write
SR.3 = V STATUS (VPPS)
SR.3 does not provide a continuous indication of V level.
PP
PP
1 = V Low Detect, Operation Abort
The WSM interrogates and indicates the V level only after
PP
PP
0 = V OK
Block Erase or Word/Byte Write command sequences. SR.3
is not guaranteed to reports accurate feedback only when
PP
SR.2 = WORD/BYTE WRITE SUSPEND STATUS
(WBWSS)
V
≠V
.
PP
PPH1/2
1 = Word/Byte Write Suspended
0 = Word/Byte Write in Progress/Completed
The WSM interrogates the WP# and RP# only after Block
Erase or Word/Byte Write command sequences. It informs
the system, depending on the attempted operation, if the
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = WP# or RP# Lock Detected, Operation Abort
0 = Unlock
WP# is not V RP# is not V
.
IH,
HH
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
SR.0 is reserved for future use and should be masked out
when polling the status register.
Rev. 1.1
LHF80V25
16
sharp
Start
Bus
Command
Comments
Operation
Data=20H
Write
Write
Erase Setup
Write 20H,
Addr=Within Block to be Erased
Block Address
Erase
Data=D0H
Confirm
Addr=Within Block to be Erased
Write D0H,
Block Address
Read
Status Register Data
Read Status
Register
Check SR.7
Suspend Block
Erase Loop
Standby
1=WSM Ready
0=WSM Busy
No
0
Suspend
Repeat for subsequent block erasures.
SR.7=
Block Erase
Yes
Full status check can be done after each block erase or after a sequence of
block erasures.
1
Write FFH after the last operation to place device in read array mode.
Full Status
Check if Desired
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Bus
Read Status Register
Data(See Above)
Command
Comments
Operation
Check SR.3
Standby
1=V Error Detect
PP
1
SR.3=
V
Range Error
PP
Check SR.1
Standby
Standby
Standby
1=Device Protect Detect
0
Check SR.4,5
Both 1=Command Sequence Error
1
Device Protect Error
SR.1=
Check SR.5
1=Block Erase Error
0
SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status
Register Command in cases where multiple blocks are erased
before full status is checked.
1
Command Sequence
Error
SR.4,5=
If error is detected, clear the Status Register before attempting
retry or other error recovery.
0
1
SR.5=
Block Erase Error
0
Block Erase Successful
Figure 5. Automated Block Erase Flowchart
Rev. 1.1
LHF80V25
17
sharp
Start
Bus
Command
Comments
Operation
Data=40H or 10H
Write
Write
Write 40H or 10H,
Address
Setup Word/Byte Write
Word/Byte Write
Addr=Location to Be Written
Data=Data to Be Written
Addr=Location to Be Written
Write Word/Byte
Data and Address
Read
Status Register Data
Read
Status Register
Check SR.7
Suspend Word/Byte
Write Loop
Standby
1=WSM Ready
0=WSM Busy
No
0
Suspend
Word/Byte Write
Repeat for subsequent byte writes.
SR.7=
Yes
SR full status check can be done after each Word/Byte write, or after a sequence of
Word/Byte writes.
1
Write FFH after the last Word/Byte write operation to place device in
read array mode.
Full Status
Check if Desired
Word/Byte Write
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus
Command
Comments
Operation
Check SR.3
Standby
1=V Error Detect
PP
1
SR.3=
V
Range Error
PP
Check SR.1
Standby
Standby
1=Device Protect Detect
0
Check SR.4
1=Data Write Error
1
Device Protect Error
SR.1=
SR.4,SR.3 and SR.1 are only cleared by the Clear Status Register
command in cases where multiple locations are written before
full status is checked.
0
If error is detected, clear the Status Register before attempting
retry or other error recovery.
1
SR.4=
Word/Byte Write Error
0
Word/Byte Write
Successful
Figure 6. Automated Word/Byte Write Flowchart
Rev. 1.1
LHF80V25
18
sharp
Start
Bus
Command
Comments
Operation
Erase
Data=B0H
Addr=X
Write
Read
Write B0H
Suspend
Status Register Data
Addr=X
Read
Status Register
Check SR.7
1=WSM Ready
0=WSM Busy
Standby
0
0
Check SR.6
SR.7=
1
1=Block Erase Suspended
0=Block Erase Completed
Standby
Write
Erase
Data=D0H
Addr=X
Resume
Block Erase Completed
SR.6=
1
Read or
Word/Byte
Write?
Read
Word/Byte Write
Read Array Data
Word/Byte Write Loop
No
Done?
Yes
Write FFH
Write D0H
Block Erase Resumed
Read Array Data
Figure 7. Block Erase Suspend/Resume Flowchart
Rev. 1.1
LHF80V25
19
sharp
Start
Bus
Command
Comments
Operation
Data=B0H
Addr=X
Word/Byte Write
Suspend
Write
Read
Write B0H
Status Register Data
Addr=X
Read
Status Register
Check SR.7
1=WSM Ready
0=WSM Busy
Standby
Standby
0
Check SR.2
SR.7=
1=Word/Byte Write Suspended
0=Word/Byte Write Completed
1
Data=FFH
Addr=X
Write
Read
Write
Read Array
0
Word/Byte Write
Completed
SR.2=
Read Array locations other
than that being written.
1
Data=D0H
Addr=X
Word/Byte Write
Resume
Write FFH
Read Array Data
Done
No
Reading
Yes
Write D0H
Write FFH
Word/Byte Write
Resumed
Read Array Data
Figure 8. Word/Byte Write Suspend/Resume Flowchart
Rev. 1.1
LHF80V25
20
sharp
5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
5.3 Power Supply Decoupling
Flash memory power switching characteristics require
careful device decoupling. System designers are interested
in three supply current issues; standby current levels,
active current levels and transient peaks produced by
falling and rising edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’ capacitive and
inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks.
Each device should have a 0.1µF ceramic capacitor
connected between its V and GND and between its V
The device will often be used in large memory arrays.
SHARP provides three control inputs to accommodate
multiple memory connections. Three-line control provides
for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will not
occur.
CC
PP
and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to package
leads. Additionally, for every eight devices, a 4.7µF
electrolytic capacitor should be placed at the array’s power
To use these control inputs efficiently, an address decoder
should enable CE# while OE# should be connected to all
memory devices and the system’s READ# control line.
This assures that only selected memory devices have
active outputs while deselected memory devices are in
standby mode. RP# should be connected to the system
POWERGOOD signal to prevent unintended writes during
system power transitions. POWERGOOD should also
toggle during system reset.
supply connection between V
and GND. The bulk
CC
capacitor will overcome voltage slumps caused by PC
board trace inductance.
5.4 V Trace on Printed Circuit Boards
PP
Updating flash memories that reside in the target system
requires that the printed circuit board designer pay
attention to the V Power supply trace. The V pin
5.2 RY/BY#, Block Erase and Word/Byte
Write Polling
PP
PP
supplies the memory cell current for word/byte writing
and block erasing. Use similar trace widths and layout
considerations given to the V power bus. Adequate V
RY/BY# is an open drain output that should be connected
CC
PP
to V by a pull up resistor to provide a hardware method
CC
supply traces and decoupling will decrease V voltage
PP
of detecting block erase and word/byte write completion.
It transitions low after block erase or word/byte write
commands and returns to High Z when the WSM has
finished executing the internal algorithm.
spikes and overshoots.
RY/BY# can be connected to an interrupt input of the
system CPU or controller. It is active at all times. RY/BY#
is also High Z when the device is in block erase suspend
(with word/byte write inactive), word/byte write suspend
or deep power-down modes.
Rev. 1.2
LHF80V25
21
sharp
A system designer must guard against spurious writes for
voltages above V when V is active. Since both
WE# and CE# must be low for a command write, driving
5.5 V , V , RP# Transitions
CC PP
V
CC
LKO
PP
Block erase and word/byte write are not guaranteed if V
PP
either to V will inhibit writes. The CUI’s two-step
falls outside of a valid V
range, V falls outside of
IH
PPH1/2
CC
command sequence architecture provides added level of
protection against data alteration.
a valid 4.5V-5.5V range, or RP#≠V or V . If V error
IH
HH
PP
is detected, status register bit SR.3 is set to "1" along with
SR.4 or SR.5, depending on the attempted operation. If
WP# provide additional protection from inadvertent code
RP# transitions to V during block erase or word/byte
IL
or data alteration. The device is disabled while RP#=V
regardless of its control inputs state.
IL
write, RY/BY# will remain low until the reset operation is
complete. Then, the operation will abort and the device
will enter deep power-down. The aborted operation may
leave data partially altered. Therefore, the command
sequence must be repeated after normal operation is
5.7 Power Dissipation
When designing portable systems, designers must consider
battery power consumption not only during device
operation, but also for data retention during system idle
time. Flash memory’s nonvolatility increases usable
battery life because data is retained when system power is
removed.
restored. Device power-off or RP# transitions to V clear
the status register.
IL
The CUI latches commands issued by system software and
is not altered by V or CE# transitions or WSM actions.
PP
Its state is read array mode upon power-up, after exit from
deep power-down or after V transitions below V
.
CC
LKO
In addition, deep power-down mode ensures extremely
low power consumption even when system power is
applied. For example, portable computing products and
other power sensitive applications that use an array of
devices for solid-state storage can consume negligible
After block erase or word/byte write, even after V
PP
transitions down to V
, the CUI must be placed in read
PPLK
array mode via the Read Array command if subsequent
access to the memory array is desired.
power by lowering RP# to V standby or sleep modes. If
IL
access is again needed, the devices can be read following
5.6 Power-Up/Down Protection
the t
and t
wake-up cycles required after RP# is
PHQV
PHWL
first raised to V . See AC Characteristics− Read Only
IH
The device is designed to offer protection against
accidental block erasure or word/byte writing during
power transitions. Upon power-up, the device is
and Write Operations and Figures 11, 12, 13 and 14 for
more information.
indifferent as to which power supply (V
or V
)
PP
CC
powers-up first. Internal circuitry resets the CUI to read
array mode at power-up.
Rev. 1.1
LHF80V25
22
sharp
*WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage. These
are stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may affect device
reliability.
6 ELECTRICAL SPECIFICATIONS
6.1 Absolute Maximum Ratings*
Operating Temperature
During Read, Block Erase and
Word/Byte Write.................................0°C to +70°C
(1)
NOTES:
Temperature under Bias...................... -10°C to +80°C
Storage Temperature ................................ -65°C to +125°C
Voltage On Any Pin
1. Operating temperature is for commercial temperature
product defined by this specification.
2. All specified voltages are with respect to GND.
Minimum DC voltage is -0.5V on input/output pins
and -0.2V on V and V pins. During transitions,
(2)
CC
PP
(except V , V , and RP#) ............ -0.5V to +7.0V
CC
PP
this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input/output pins and V is
(2)
CC
V
V
Supply Voltage................................ -0.2V to +7.0V
CC
V
V
+0.5V which, during transitions, may overshoot to
+2.0V for periods <20ns.
CC
CC
Update Voltage during Block
Erase and Word/Byte Write .........-0.2V to +14.0V
PP
3. Maximum DC voltage on V and RP# may overshoot
(2,3)
(2,3)
(4)
PP
to +14.0V for periods <20ns.
4. Output shorted for no more than one second. No more
than one output shorted at a time.
RP# Voltage ........................................-0.5V to +14.0V
Output Short Circuit Current................................100mA
6.2 Operating Conditions
Temperature and V Operating Conditions
CC
Symbol
Parameter
Min.
Max.
+70
5.5
Unit
°C
Test Condition
T
Operating Temperature
0
Ambient Temperature
A
V
V
Supply Voltage (4.5V-5.5V)
4.5
V
CC
CC
(1)
6.2.1 CAPACITANCE
T =+25°C, f=1MHz
A
Symbol
Parameter
Typ.
Max.
Unit
Condition
C
C
Input Capacitance
Output Capacitance
7
9
10
12
pF
pF
V =0.0V
IN
OUT
IN
V
=0.0V
OUT
NOTE:
1. Sampled, not 100% tested.
Rev. 1.2
LHF80V25
23
sharp
6.2.2 AC INPUT/OUTPUT TEST CONDITIONS
3.0
1.5
INPUT
1.5
TEST POINTS
OUTPUT
0.0
AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 9. Transient Input/Output Reference Waveform for V =4.5V-5.5V
CC
Test Configuration Capacitance Loading Value
Test Configuration
=4.5V-5.5V
C (pF)
L
1.3V
V
50
CC
1N914
RL=3.3kΩ
DEVICE
UNDER
TEST
OUT
CL Includes Jig
Capacitance
CL
Figure 10. Transient Equivalent Testing Load
Circuit
Rev. 1.1
LHF80V25
24
sharp
6.2.3 DC CHARACTERISTICS
DC Characteristics
V
=5V±0.5V
Test
CC
Sym.
Parameter
Input Load Current
Notes
1
Typ.
Max.
Unit
µA
Conditions
I
I
I
V
=V Max.
LI
CC CC
±1
V =V or GND
IN
CC
Output Leakage Current
1
V
V
=V Max.
LO
CC
CC
±10
100
µA
µA
=V or GND
OUT
CC
V
Standby Current
1,3,6,
10
CMOS Inputs
V =V Max.
CC
CE#=RP#=V ±0.2V
CCS
CC
30
CC
CC
1,3,6
TTL Inputs
0.4
2
mA
µA
V
=V Max.
CC CC
CE#=RP#=V
IH
I
I
V
V
Deep Power-Down Current
Read Current
1,10
RP#=GND±0.2V
(RY/BY#)=0mA
CCD
CC
10
50
I
OUT
1,5,6
CMOS Inputs
V =V Max., CE#=GND
CC
f=8MHz, I
CCR
CC
mA
CC
=0mA
OUT
TTL Inputs
V =V Max., CE#=GND
CC
65
mA
CC
f=8MHz, I
=0mA
OUT
I
I
V
V
V
Word/Byte Write Current
Block Erase Current
1,7
1,7
35
30
30
25
mA
mA
mA
mA
V
V
V
V
=4.5V-5.5V
CCW
CC
CC
CC
PP
PP
PP
PP
=11.4V-12.6V
=4.5V-5.5V
CCE
=11.4V-12.6V
I
I
Word/Byte Write or Block
1,2
1
CCWS
CCES
1
10
mA
CE#=V
IH
Erase Suspend Current
I
V
Standby or Read Current
±2
10
±15
200
5
µA
µA
V
V
≤V
PPS
PP
PP
CC
I
I
I
>V
PPR
PPD
PPW
PP
CC
V
V
Deep Power-Down Current
Word/Byte Write Current
1
0.1
µA
RP#=GND±0.2V
PP
PP
1,7
40
30
25
20
mA
mA
mA
mA
V
V
V
V
=4.5V-5.5V
PP
PP
PP
PP
=11.4V-12.6V
=4.5V-5.5V
I
V
Block Erase Current
1,7
1
PPE
PP
=11.4V-12.6V
I
I
V
Word/Byte Write or Block Erase
PPWS
PPES
PP
10
200
µA
V
=V
PP
PPH1/2
Suspend Current
Rev. 1.1
LHF80V25
25
sharp
DC Characteristics (Continued)
V
=5V±0.5V
Max.
CC
Sym.
Parameter
Input Low Voltage
Input High Voltage
Notes
Min.
-0.5
Unit
V
Test Conditions
V
V
7
7
0.8
IL
V
+0.5
IH
CC
2.4
V
V
V
V
V
V
V
V
V
V
V
Output Low Voltage
3,7
3,7
3,7
V
I
=V Min.
OL
CC
CC
0.45
=5.8mA
OL
Output High Voltage
(TTL)
V
I
=V Min.
OH1
OH2
CC
CC
2.4
=-2.5mA
OH
Output High Voltage
(CMOS)
0.85
V
I
=V Min.
CC
CC
V
=-2.0mA
CC
OH
V
-0.4
V
I
=V Min.
CC
CC
CC
=-100µA
OH
V
V
V
V
Lockout Voltage during Normal
4,7
PPLK
PPH1
PPH2
PP
1.5
5.5
Operations
V
Voltage during Word/Byte Write
PP
4.5
or Block Erase Operations
V
Voltage during Word/Byte Write
PP
11.4
12.6
or Block Erase Operations
V
V
V
Lockout Voltage
2.0
V
V
LKO
CC
RP# Unlock Voltage
8,9
11.4
12.6
Unavailable WP#
HH
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal V voltage and T =+25°C.
CC
A
2. I
and I
are specified with the device de-selected. If read or word/byte written while in erase suspend mode, the
CCWS
CCES
device’s current draw is the sum of I
3. Includes RY/BY#.
or I
and I
or I
, respectively.
CCWS
CCES
CCR
CCW
4. Block erases and word/byte writes are inhibited when V ≤V
, and not guaranteed in the range between V
(max.)
PP
PPLK
PPLK
and V
(min.), between V
(max.) and V
(min.) and above V
(max.).
PPH1
PPH1
PPH2
PPH2
5. Automatic Power Savings (APS) reduces typical I
to 1mA at 5V V in static operation.
CCR
CC
6. CMOS inputs are either V ±0.2V or GND±0.2V. TTL inputs are either V or V .
CC
IL
IH
7. Sampled, not 100% tested.
8. Boot block erases and word/byte writes are inhibited when the corresponding RP#=V and WP#=V . Block erase and
IH
IL
word/byte write operations are not guaranteed with V <RP#<V and should not be attempted.
IH
HH
9. RP# connection to a V supply is allowed for a maximum cumulative period of 80 hours.
HH
10. BYTE# input level is V ±0.2V in word mode or GND±0.2V in byte mode. WP# input level is V ±0.2V or GND±0.2V.
CC
CC
Rev. 1.2
LHF80V25
26
sharp
(1)
6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS
V
=4.5V-5.5V, T =0°C to +70°C
A
CC
Sym.
Parameter
Notes
2
Min.
85
Max.
Unit
ns
t
t
t
t
t
t
t
t
t
Read Cycle Time
AVAV
AVQV
ELQV
PHQV
GLQV
ELQX
EHQZ
GLQX
GHQZ
Address to Output Delay
CE# to Output Delay
85
85
ns
ns
RP# High to Output Delay
OE# to Output Delay
400
45
ns
2
3
3
3
3
ns
CE# to Output in Low Z
CE# High to Output in High Z
OE# to Output in Low Z
OE# High to Output in High Z
0
0
ns
55
10
ns
ns
ns
Output Hold from Address, CE# or OE# Change, Whichever
Occurs First
t
3
0
ns
OH
t
t
t
BYTE# and A to Output Delay
3
3
85
30
5
ns
ns
ns
FVQV
FLQZ
ELFV
-1
BYTE# Low to Output in High Z
CE# to BYTE# High or Low
3,4
NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to t
3. Sampled, not 100% tested.
-t
after the falling edge of CE# without impact on t
.
ELQV
ELQV GLQV
4. If BYTE# transfer during reading cycle, exist the regulations separately.
Rev. 1.1
LHF80V25
27
sharp
Device
Address Selection
Standby
VIH
Data Valid
ADDRESSES(A)
Address Stable
VIL
tAVAV
VIH
CE#(E)
VIL
tEHQZ
VIH
OE#(G)
VIL
tGHQZ
VIH
WE#(W)
VIL
tGLQV
tELQV
tGLQX
tELQX
tOH
VOH
HIGH Z
HIGH Z
DATA(D/Q)
(DQ -DQ
Valid Output
)
15
0
VOL
tAVQV
V
CC
tPHQV
VIH
RP#(P)
VIL
Figure 11. AC Waveform for Read Operations
Rev. 1.1
LHF80V25
28
sharp
Device
Address Selection
Standby
VIH
Data Valid
ADDRESSES(A)
Address Stable
VIL
tAVAV
VIH
CE#(E)
VIL
tEHQZ
VIH
OE#(G)
VIL
tGHQZ
tELFV
tGLQV
tFVQV
VIH
BYTE#(F)
VIL
tELQV
tGLQX
tOH
VOH
HIGH Z
HIGH Z
HIGH Z
HIGH Z
DATA(D/Q)
Valid
Output
Data Output
tFLQZ
(DQ -DQ )
0
7
tELQX
VOL
tAVQV
VOH
DATA(D/Q)
(DQ -DQ
Data
Output
)
15
8
VOL
Figure 12. BYTE# timing Waveform
Rev. 1.1
LHF80V25
29
sharp
(1)
6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS
V
=4.5V-5.5V, T =0°C to +70°C
CC
A
Sym.
Parameter
Notes
Min.
85
1
Max.
Unit
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
AVAV
PHWL
ELWL
WLWH
PHHWH
SHWH
VPWH
AVWH
DVWH
WHDX
WHAX
WHEH
WHWL
WHRL
WHGL
QVVL
QVPH
RP# High Recovery to WE# Going Low
CE# Setup to WE# Going Low
WE# Pulse Width
2
10
40
100
100
100
40
40
0
RP# V Setup to WE# Going High
2
2
2
3
3
HH
WP# V Setup to WE# Going High
IH
V
Setup to WE# Going High
PP
Address Setup to WE# Going High
Data Setup to WE# Going High
Data Hold from WE# High
Address Hold from WE# High
CE# Hold from WE# High
5
10
30
WE# Pulse Width High
WE# High to RY/BY# Going Low
Write Recovery before Read
90
0
0
V
Hold from Valid SRD, RY/BY# High Z
2,4
2,4
2,4
5
PP
RP# V Hold from Valid SRD, RY/BY# High Z
0
HH
WP# V Hold from Valid SRD, RY/BY# High Z
0
QVSL
IH
BYTE# Setup to WE# Going High
BYTE# Hold from WE# High
40
85
FVWH
WHFV
5
NOTES:
1. Read timing characteristics during block erase and word/byte write operations are the same as during read-only operations.
Refer to AC Characteristics for read-only operations.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A and D for block erase or word/byte write.
IN
IN
4. V should be held at V
(and if necessary RP# should be held at V ) until determination of block erase or
PP
PPH1/2
HH
word/byte write success (SR.1/3/4/5=0).
5. If BYTE# switch during reading cycle, exist the regulations separately.
Rev. 1.1
LHF80V25
30
sharp
1
2
3
4
5
6
VIH
VIL
AIN
AIN
ADDRESSES(A)
tWHAX
tAVWH
tAVAV
VIH
VIL
CE#(E)
OE#(G)
tWHEH
tELWL
tWHGL
VIH
VIL
tWHQV1,2
tWHWL
VIH
VIL
WE#(W)
tWLWH
tDVWH
tWHDX
VIH
VIL
High Z
Valid
SRD
DATA(D/Q)
BYTE#(F)
RY/BY#(R)
WP#(S)
DIN
DIN
DIN
tPHWL
tFVWH
tWHFV
VIH
VIL
tWHRL
High Z
VOL
VIH
VIL
tSHWH
tQVSL
tPHHWH
tQVPH
VHH
VIH
RP#(P)
VIL
tVPWH
tQVVL
VPPH2,1
VPPLK
VIL
V (V)
PP
NOTES:
1. VCC power-up and standby.
2. Write block erase or word/byte write setup.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
Figure 13. AC Waveform for WE#-Controlled Write Operations
Rev. 1.2
LHF80V25
31
sharp
(1)
6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES
V
=4.5V-5.5V, T =0°C to +70°C
A
CC
Sym.
Parameter
Notes
Min.
85
1
Max.
Unit
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
AVAV
PHEL
WLEL
ELEH
PHHEH
SHEH
VPEH
AVEH
DVEH
EHDX
EHAX
EHWH
EHEL
EHRL
EHGL
QVVL
QVPH
QVSL
FVEH
EHFV
RP# High Recovery to CE# Going Low
WE# Setup to CE# Going Low
CE# Pulse Width
2
0
50
100
100
100
40
40
0
RP# V Setup to CE# Going High
2
2
2
3
3
HH
WP# V Setup to CE# Going High
IH
V
Setup to CE# Going High
PP
Address Setup to CE# Going High
Data Setup to CE# Going High
Data Hold from CE# High
Address Hold from CE# High
WE# Hold from CE# High
CE# Pulse Width High
5
0
25
CE# High to RY/BY# Going Low
Write Recovery before Read
90
0
0
V
Hold from Valid SRD, RY/BY# High Z
2,4
2,4
2,4
5
PP
RP# V Hold from Valid SRD, RY/BY# High Z
0
HH
WP# V Hold from Valid SRD, RY/BY# High Z
0
IH
BYTE# Setup to CE# Going High
BYTE# Hold from CE# High
40
85
5
NOTES:
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive
WE# times should be measured relative to the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A and D for block erase or word/byte write.
IN
IN
4. V should be held at V
(and if necessary RP# should be held at V ) until determination of block erase or
PP
PPH1/2
HH
word/byte write success (SR.1/3/4/5=0).
5. If BYTE# switch during reading cycle, exist the regulations separately.
Rev. 1.1
LHF80V25
32
sharp
1
2
3
4
5
6
VIH
VIL
AIN
AIN
ADDRESSES(A)
tEHAX
tAVEH
tAVAV
VIH
VIL
tEHEL
tELEH
tDVEH
CE#(E)
tEHGL
VIH
VIL
OE#(G)
VIH
VIL
WE#(W)
tEHQV1,2
tEHWH
tEHDX
tWLEL
VIH
VIL
High Z
Valid
SRD
DATA(D/Q)
BYTE#(F)
RY/BY#(R)
WP#(S)
DIN
DIN
DIN
tPHEL
tFVEH
tEHFV
VIH
VIL
tEHRL
High Z
VOL
tSHEH
tQVSL
VIH
VIL
VHH
VIH
VIL
tPHHEH
tQVPH
RP#(P)
tVPEH
tQVVL
VPPH2,1
VPPLK
VIL
V (V)
PP
NOTES:
1. VCC power-up and standby.
2. Write block erase or word/byte write setup.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
Figure 14. AC Waveform for CE#-Controlled Write Operations
Rev. 1.2
LHF80V25
33
sharp
6.2.7 RESET OPERATIONS
High Z
RY/BY#(R)
VOL
VIH
RP#(P)
VIL
tPLPH
(A)Reset During Read Array Mode
High Z
RY/BY#(R)
VOL
tPLRZ
VIH
RP#(P)
VIL
tPLPH
(B)Reset During Block Erase or Word/Byte Write
5V
VCC
VIL
t5VPH
VIH
RP#(P)
VIL
(C)RP# rising Timing
Figure 15. AC Waveform for Reset Operation
Reset AC Specifications
V
=4.5V-5.5V
Max.
CC
Sym.
Parameter
Notes
Min.
Unit
ns
RP# Pulse Low Time
t
100
PLPH
(If RP# is tied to V , this specification is not applicable)
CC
t
t
RP# Low to Reset during Block Erase or Word/Byte Write
1,2
3
12
µs
ns
PLRZ
5VPH
V
4.5V to RP# High
100
CC
NOTES:
1. If RP# is asserted while a block erase or word/byte write operation is not executing, the reset will complete within 100ns.
2. A reset time, t , is required from the later of RY/BY# going High Z or RP# going high until outputs are valid.
PHQV
3. When the device power-up, holding RP# low minimum 100ns is required after V has been in predefined range and also
CC
has been in stable there.
Rev. 1.1
LHF80V25
34
sharp
(3)
6.2.8 BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE
V
=5V±0.5V, T =0°C to +70°C
A
CC
V
=4.5V-5.5V
V
=11.4V-12.6V
PP
(1)
PP
(1)
Sym.
Parameter
Notes
Typ.
Max.
Typ.
Max.
Unit
t
t
Word/Byte Write Time 32K word Block
4K word Block
2
2
12.2
18.3
0.4
8.4
17
µs
µs
s
WHQV1
EHQV1
Block Write Time
32K word Block
4K word Block
32K word Block
4K word Block
2,4
2,4
2
0.28
0.07
0.39
0.25
0.08
0.46
0.26
s
t
t
Block Erase Time
s
WHQV2
EHQV2
2
s
t
t
Word/Byte Write Suspend Latency Time
to Read
WHRZ1
EHRZ1
5
6
4
5
µs
µs
t
t
WHRZ2
EHRZ2
Erase Suspend Latency Time to Read
9.6
12
9.6
12
NOTES:
1. Typical values measured at T =+25°C and nominal voltages. Subject to change based on device characterization.
A
2. Excludes system-level overhead.
3. Sampled but not 100% tested.
4. All values are in word mode (BYTE#=V ). At byte mode (BYTE#=V ), those values are double.
IH
IL
Rev. 1.1
i
sharp
A-1 RECOMMENDED OPERATING CONDITIONS
A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
VCC(min)
VCC
GND
*1
tVR
tR
t2VPH
tPHQV
VIH
(P)
RP#
(RST#)
VIL
VCCWH1/2
(VPPH1/2)
*2
(V)
VCCW
(VPP)
GND
tR or tF
tR or tF
tAVQV
VIH
Valid
Address
ADDRESS (A)
VIL
tR
tF
tELQV
VIH
VIL
VIH
VIL
VIH
VIL
VIH
(E)
CE#
(W)
WE#
tR
tF
tGLQV
(G)
OE#
(S)
WP#
VIL
VOH
High Z
Valid
Output
DATA
(D/Q)
V
OL
*1 t5VPH for the device in 5V operations.
*2 To prevent the unwanted writes, system designers should consider the VCCW (VPP) switch, which connects VCCW (VPP)
to GND during read operations and VCCWH1/2 (VPPH1/2) during write or erase operations.
See the application note AP-007-SW-E for details.
Figure A-1. AC Timing at Device Power-Up
For the AC specifications t , t , t in the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“
VR
R
F
described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in
the next page.
Rev. 1.10
ii
sharp
A-1.1.1 Rise and Fall Time
Symbol
Parameter
Notes
1
Min.
0.5
Max.
Unit
t
t
t
V
Rise Time
CC
30000
µs/V
µs/V
µs/V
VR
Input Signal Rise Time
Input Signal Fall Time
1, 2
1, 2
1
1
R
F
NOTES:
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations.
t (Max.) and t (Max.) for RP# (RST#) are 100µs/V.
R
F
Rev. 1.10
iii
sharp
A-1.2 Glitch Noises
Do not input the glitch noises which are below V (Min.) or above V (Max.) on address, data, reset, and control signals,
IH
IL
as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Input Signal
VIH (Min.)
Input Signal
VIH (Min.)
VIL (Max.)
VIL (Max.)
Input Signal
Input Signal
(a) Acceptable Glitch Noises
(b) NOT Acceptable Glitch Noises
Figure A-2. Waveform for Glitch Noises
See the “DC CHARACTERISTICS“ described in specifications for V (Min.) and V (Max.).
IH
IL
Rev. 1.10
iv
sharp
(1)
A-2 RELATED DOCUMENT INFORMATION
Document No.
Document Name
AP-001-SD-E
AP-006-PT-E
AP-007-SW-E
Flash Memory Family Software Drivers
Data Protection Method of SHARP Flash Memory
RP#, V Electric Potential Switching Circuit
PP
NOTE:
1. International customers should contact their local SHARP or distribution sales office.
Rev. 1.10
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty
for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS
AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A
PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental
or consequential economic or property damage.
NORTH AMERICA
EUROPE
ASIA
SHARP Corporation
SHARP Microelectronics
of the Americas
5700 NW Pacific Rim Blvd.
Camas, WA 98607, U.S.A.
Phone: (360) 834-2500
Fax: (360) 834-8903
SHARP Microelectronics Europe
Sonninstraße 3
20097 Hamburg, Germany
Phone: (49) 40 2376-2286
Fax: (49) 40 2376-2232
http://www.sharpsme.com
Integrated Circuits Group
2613-1 Ichinomoto-Cho
Tenri-City, Nara, 632, Japan
Phone: +81-743-65-1321
Fax: +81-743-65-1532
http://www.sharp.co.jp
http://www.sharpsma.com
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