LM6118J/883 [ETC]
OP-AMP|DUAL|BIPOLAR|DIP|8PIN|CERAMIC ;型号: | LM6118J/883 |
厂家: | ETC |
描述: | OP-AMP|DUAL|BIPOLAR|DIP|8PIN|CERAMIC 放大器 |
文件: | 总13页 (文件大小:137K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MICROCIRCUIT DATA SHEET
Original Creation Date: 12/19/94
Last Update Date: 08/24/98
MNLM6118-X REV 0C1
Last Major Revision Date: 12/19/94
FAST SETTING DUAL OPERATIONAL AMPLIFIER
General Description
The LM6118 series are monolithic fast-setting unity-gain-compensated dual operational
amplifiers with +20mA output drive capability. The PNP input stage has a typical bias
current of 200nA, and the operating supply voltage is +5V to +20V.
These dual op amps use slew enhancement with special mirror circuitry to achieve fast
response and high gain with low total supply current.
The amplifiers are built on a junction-isolated VIP(TM) (Vertically Integrated PNP)
process which produces fast PNP's that complement the standard NPN's.
Industry Part Number
NS Part Numbers
LM6118
LM6118E/883 *
LM6118J/883 **
Prime Die
LM6118
Controlling Document
5962-9156501M2A*, MPA**
Processing
Subgrp Description
Temp (oC)
MIL-STD-883, Method 5004
1
Static tests at
+25
2
Static tests at
+125
-55
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Settling time at
Settling time at
Settling time at
+25
Quality Conformance Inspection
5
+125
-55
6
MIL-STD-883, Method 5005
7
+25
8A
8B
9
+125
-55
+25
10
11
12
13
14
+125
-55
+25
+125
-55
1
MICROCIRCUIT DATA SHEET
MNLM6118-X REV 0C1
Features
- Low offset voltage
- 0.01% setting time
- Slew rate Av = -1
- Slew rate Av = +1
- Gain bandwidth
0.2mV
400nS
140V/uS
75V/uS
17MHz
5.5mA
- Total supply current
- Output drives 50 Ohm load (+1V)
Applications
- D/A converters
- Fast integrators
- Active filters
2
MICROCIRCUIT DATA SHEET
MNLM6118-X REV 0C1
(Absolute Maximum Ratings)
(Note 1)
Total Supply Voltage
Input Voltage
42V
(V+ - 1V) to (V-)
+10mA
Differential Input Current
(Note 2)
Output Current
(Note 3)
Internally Limited
Power Dissipation
(Note 4)
500mW
ESD Tolerance
(C = 100pF, R = 1.5k Ohm)
+4kV
Junction Temperature
150 C
Storage Temperature Range
-65 C to +150 C
300 C
Lead Temperature
(Soldering, 10 seconds)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
DC and AC electrical specifications do not apply when operating the device beyond its
rated operating conditions.
Note 2: The inputs are shunted with three series-connected diodes back-to-back for input
differential clamping. Therefore differential input voltages greater than about 1.8V
will cause excessive current to flow unless limited to less than 10mA.
Note 3: Current limiting protects the output from a short to ground or any voltage less than
the supplies. With a continuous overload, the package dissipation must be taken into
account and heat sinking provided when necessary.
Note 4: Devices must be derated using a thermal resistance (Tja) of 90 C/W for the J and 80
C/W for the E package, and Tjc of 12 C/W for both packages.
Recommended Operating Conditions
Operating Temperature Range
LM6118
-55 C to +125 C
3
MICROCIRCUIT DATA SHEET
MNLM6118-X REV 0C1
Electrical Characteristics
DC PARAMETERS
(The following conditions apply to all the following parameters, unless otherwise specified.)
DC: +5V < Vs < +20V, Vcm = 0V, Vout = 0V, Iout = 0A, RS = 10K
PIN-
NAME
SUB-
SYMBOL
Vio
PARAMETER
CONDITIONS
NOTES
MIN
MAX UNIT
1.0
GROUPS
Input Offset
Voltage
Vs = +15V
Vs = +15V
-1.0
-2.0
-1.5
-2.5
-50
-250
-10
-10
-350
-950
90
mV
mV
mV
mV
nA
nA
nA
nA
nA
nA
dB
dB
dB
dB
dB
dB
mA
mA
mA
mA
1
2.0
1.5
2.5
50
2, 3
1
V- + 3V < Vcm < V+ - 3.5V
V- + 3V < Vcm < V+ - 3.5V
2, 3
1
Iio
Iib
Input Offset
Current
V- + 3V < Vcm < V+ - 3.5V
V- + 3V < Vcm < V+ - 3.5V
250
350
950
10
2, 3
1
Input Bias
Current
V- + 3V < Vcm < V+ - 3.5V (Positive)
V- + 3V < Vcm < V+ - 3.5V (Positive)
V- + 3V < Vcm < V+ - 3.5V (Negative)
V- + 3V < Vcm < V+ - 3.5V (Negative)
2, 3
1
10
2, 3
1
CMRR
PSRR+
PSRR-
PSI
Input Common Mode V- + 3V < Vcm < V+ - 3.5V, Vs = +20V
Rejection Ratio
V- + 3V < Vcm < V+ - 3.5V, Vs = +20V
85
2, 3
1
Positive Power
Supply Rejection
Ratio
V- = 15V, 5V < V+ < 20V
V- = 15V, 5V < V+ < 20V
V+ = 15V, -20V < V- < -5V
V+ = 15V, -20V < V- < -5V
Vs = +15V
90
85
2, 3
1
Negative Power
Supply Rejection
Ratio
90
85
2, 3
1
Total Supply
Current
0.6
0.6
10
7
Vs = +15V
7.5
100
-10
2, 3
1
Ios
Output Current
Limit
Vs = +15V, Pulsed (Sink)
Vs = +15V, Pulsed (Source)
Vout = +16V, RL = 10K, Vs = +20V
Vout = +16V, RL = 10K, Vs = +20V
-100
150
100
50
1
AV
Large Signal
Voltage Gain
V/mV 4
V/mV 5, 6
V/mV 4
Vout = +10V, RL = 500, Vs = +15V,
(+20mA)
Vout = +10V, RL = 500, Vs = +15V,
(+20mA)
30
V/mV 5, 6
4
MICROCIRCUIT DATA SHEET
MNLM6118-X REV 0C1
Electrical Characteristics
AC PARAMETERS
PIN-
NAME
SUB-
SYMBOL
SR+
PARAMETER
CONDITIONS
NOTES
MIN
50
MAX UNIT
GROUPS
Slew Rate,
Positive
Vs = +15V, Vout = +10V, RS = RF = 2K,
CF = 10pF, AV = +1
V/uS 4
Vs = +15V, Vout = +10V, RS = RF = 2K,
CF = 10pF, AV = +1
30
V/uS 5, 6
V/uS 4
Vs = +15V, Vout = +10V, RS = RF = 2K,
CF = 10pF, AV = -1
100
50
Vs = +15V, Vout = +10V, RS = RF = 2K,
CF = 10pF, AV = -1
V/uS 5, 6
V/uS 4
SR-
Slew Rate,
Negative
Vs = +15V, Vout = +10V, RS = RF = 2K,
CF = 10pF, AV = +1
50
Vs = +15V, Vout = +10V, RS = RF = 2K,
CF = 10pF, AV = +1
30
V/uS 5, 6
V/uS 4
Vs = +15V, Vout = +10V, RS = RF = 2K,
CF = 10pF, AV = -1
100
50
Vs = +15V, Vout = +10V, RS = RF = 2K,
CF = 10pF, AV = -1
V/uS 5, 6
GBW
Gain-Bandwidth
Product
Vs = +15V, fo = 200KHz
Vs = +15V, fo = 200KHz
14
10
MHz 4
MHz 5, 6
0.01% Setting
Time AV = -1
Delta Vout = 10V, Vs = +15V, RS=RF=2K,
CF = 10pF
1
1
600
750
nS
4
Delta Vout = 10V, Vs = +15V, RS=RF=2K,
CF = 10pF
nS
5, 6
Note 1: Setting time separate insertion separate program.
5
MICROCIRCUIT DATA SHEET
MNLM6118-X REV 0C1
Graphics and Diagrams
GRAPHICS#
DESCRIPTION
06086HRC4
06192HRA4
E20ARE
CERDIP (J), 8 LEAD (B/I CKT)
LCC (E), TYPE C, 20 TERMINAL (B/I CKT)
LCC (E), TYPE C, 20 TERMINAL(P/P DWG)
CERDIP (J), 8 LEAD (P/P DWG)
J08ARL
P000016A
P000017A
CERDIP (J), 8 LEAD (PIN OUT)
LCC (E), TYPE C, 20 TERMIAL (PIN OUT)
See attached graphics following this page.
6
ECN
REV
A1
B1
APPROVALS
DATE
GENERAL NOTES:
1. GENERIC - INDUSTRY TYPE DEVICES THAT MAY BE
USED WITH THIS CIRCUIT SHALL BE AS SPECIFIED IN
NSC BURN-IN CIRCUIT LIST R512B-04.
R Wallace
P. Reid
5/4/82
7/22/92
G. Wardwell 7/26/93
G. Wardwell
G. Wardwell 2/27/96
C1
C2
C3
C4
2. ALL 1/4 AND 1/2 WATT RESISTORS SHALL BE METAL FILM.
ALL 1, 2, AND 3 WATT RESISTORS SHALL BE WIRE WOUND.
TOLERANCE SHALL BE +/-5% UNLESS OTHERWISE SPECIFIED.
3. ALL VOLTAGES SPECIFIED SHALL BE MEASURED AT THE
“DEVICE UNDER TEST” PIN AND SHALL BE MINIMUM VALUES
UNLESS OTHERWISE SPECIFIED.
05907
06590
07469
7/1/94
T Trinh
2/3/98
4. WHEN APPLICABLE, CLOCK PULSES SPECIFIED SHALL HAVE 50%
DUTY CYCLE.
5. THIS DRAWING COMPLIES WITH MIL-PRF-38535, WHEN APPLICABLE.
V+
1
2
8
Note 7
7
6
5
3
v-
C1
4
Note 7
C1
Note 7
V+ = 7.5V, V- = -7.5V
V+ = +15V, V- = -15V
LMC6062, LMC6462
LMC6482, LM6142
LMC662, LPC662
LM6118, LM6172
DUT CONDITIONS
LIMITS
COMPONENT REQUIREMENTS PER POSITION
LIMITS
REF
SYMBOL
UNITS
QTY
DESCRIPTION
SYMBOL
UNITS
DESIG.
MIN.
MAX.
MIN.
MAX.
+/- 0.5V
+/- 0.5V
(See Note 7)
(See Note 7)
C1
2
0.1 uF X7R +/- 20%
V+
V-
NOTES:
6. LM6118, LMC662, LPC662, LMC6482
LMC6062, LMC6462, LM6142, LM6172
OF
SH
1
BURN-IN CIRCUIT
CUSTOMER
1
N
PACKAGE
MIL
NSC
TEST CONDITION
MIL/AEROSPACE OPERATIONS
TYPE
Note 6
A
J8
2900 SEMICONDUCTOR DRIVE
SANTA CLARA, CA 95050
ORIGINATOR
DATE
CHECKED BY
DATE
DRAWING NUMBER
REV
06086HR
C4
TXT
2/3/98
ECN
REV
A1
A2
A3
A4
APPROVALS
DATE
GENERAL NOTES:
1. GENERIC - INDUSTRY TYPE DEVICES THAT MAY BE
USED WITH THIS CIRCUIT SHALL BE AS SPECIFIED IN
NSC BURN-IN CIRCUIT LIST R512B-04.
2. ALL 1/4 AND 1/2 WATT RESISTORS SHALL BE METAL FILM.
ALL 1, 2, AND 3 WATT RESISTORS SHALL BE WIRE WOUND.
TOLERANCE SHALL BE +/-5% UNLESS OTHERWISE SPECIFIED.
3. ALL VOLTAGES SPECIFIED SHALL BE MEASURED AT THE
“DEVICE UNDER TEST” PIN AND SHALL BE MINIMUM VALUES
UNLESS OTHERWISE SPECIFIED.
R Wallace
11/20/90
12/7/94
4/28/98
7/16/98
06202
07573
07618
G Wardwell
J. GOMEZ
J. GOMEZ
4. WHEN APPLICABLE, CLOCK PULSES SPECIFIED SHALL HAVE 50%
DUTY CYCLE.
5. THIS DRAWING COMPLIES WITH MIL-PRF-38535, WHEN APPLICABLE.
V+
+15V
3
4
2
1
20
19
18
5
6
7
17
16
TOP
VIEW
C1
15
14
8
9
10
11
12
13
V-
-15V
C1
DUT CONDITIONS
COMPONENT REQUIREMENTS PER POSITION
LIMITS
LIMITS
MIN. MAX.
REF
SYMBOL
UNITS
QTY
DESCRIPTION
SYMBOL
UNITS
DESIG.
MIN.
14.5
-15.5
MAX.
15.5
C1
2
V+
V-
VOLTS
VOLTS
0.1 uF X7R 20%
-14.5
NOTES:
OF
SH
1
BURN-IN CIRCUIT
1
N
CUSTOMER
PACKAGE
TYPE
MIL
DATE
NSC
TEST CONDITION
MIL/AEROSPACE OPERATIONS
E20
LM6118
A
2900 SEMICONDUCTOR DRIVE
SANTA CLARA, CA 95050
ORIGINATOR
DATE
CHECKED BY
DRAWING NUMBER06192HRREV A4
J. GOMEZ
7/16/98
OUT A
-IN A
+IN A
V-
V+
1
2
3
4
8
7
6
5
OUT B
-IN B
+IN B
LM6118J/883
CONNECTION DIAGRAM
8 LEAD DIP
(TOP VIEW)
P000016A
V+
OUT A
3 2 1 2019
18
4
5
6
7
8
17
16
15
14
OUT B
-IN B
-IN A
TOP
+IN A
VIEW
9 10111213
V-
+IN B
LM6118E/883
CONNECTION DIAGRAM
20 LEAD LCC
(TOP VIEW)
P000017A
MICROCIRCUIT DATA SHEET
MNLM6118-X REV 0C1
Revision History
Rev ECN # Rel Date Originator Changes
0B0
M0001718 08/24/98
Barbara Lopez
Changed: MNLM6118-X Rev. 0A0 to MNLM6118-X Rev. 0B0.
0C1
M0002760 08/24/98
Rose Malone
Update MDS: MNLM6118-X Rev. 0B0 to MNLM6118-X Rev.
0C1. Updated Burn-In graphics. Updated Subgroups to
match SMD.
7
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