MB89630R [ETC]
8-bit Proprietary Microcontroller; 8位微控制器专有
| 型号： | MB89630R |
| 厂家： | 
ETC |
| 描述： | 8-bit Proprietary Microcontroller |
| 文件： | 总59页 (文件大小：814K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12531-2E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89630R Series
MB89635R/T635R/636R/637R/T637R
MB89P637/W637/PV630
■ OUTLINE
The MB89630R series has been developed as a general-purpose version of the F2MC*-8L family consisting of
proprietary 8-bit, single-chip microcontrollers.
In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as
dual-clock control system, five operating speed control stages, a UART, timers, a PWM timer, a serial interface,
an A/D converter, an external interrupt, and a watch prescaler.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• High-speed operating capability at low voltage
• Minimum execution time: 0.4 µs@3.5 V, 0.8 µs@2.7 V
• F2MC-8L family CPU core
Multiplication and division instructions
16-bit arithmetic operations
Test and branch instructions
Instruction set optimized for controllers
Bit manipulation instructions, etc.
• Five types of timers
8-bit PWM timer: 2 channels (Also usable as a reload timer)
8-bit pulse-width count timer (Continuous measurement capable, applicable to remote control, etc.)
16-bit timer/counter
21-bit timebase timer
• UART
CLK-synchronous/CLK-asynchronous data transfer capable (6, 7, and 8 bits)
• Serial interface
Switchable transfer direction to allows communication with various equipment.
• 10-bit A/D converter
Start by an external input capable
(Continued)
MB89630R Series
(Continued)
• External interrupt: 4 channels
Four channels are independent and capable of wake-up from low-power consumption modes (with an edge
detection function).
• Low-power consumption modes
Stop mode (Oscillation stops to minimize the current consumption.)
Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)
Subclock mode
Watch mode
• Bus interface function
With hold and ready function
■ PACKAGE
64-pin Plastic SH-DIP
64-pin Plastic QFP
64-pin Plastic QFP
(DIP-64P-M01)
(FPT-64P-M06)
(FPT-64P-M09)
64-pin Ceramic SH-DIP
64-pin Ceramic MQFP
64-pin Ceramic MDIP
(DIP-64C-A06)
(MQP-64C-P01)
(MDP-64C-P02)
2
MB89630R Series
■ PRODUCT LINEUP
Part number
MB89635R MB89636R MB89637R MB89T635R MB89T637R MB89P637 MB89W637 MB89PV630
Item
Classification
Piggyback/
evaluation
EPROM product (for
product evaluation
and
One-time
PROM
product
Mass-produced products
(mask ROM products)
External ROM
products
development)
16 K × 8 bits 24 K × 8 bits 32 K × 8 bits
ROM size
32 K × 8 bits
(Internal PROM, to be 32 K × 8 bits
(internal
(internal
(internal
mask ROM) mask ROM) mask ROM)
Fixed to external ROM programmed with
general-purpose
(external
ROM)
EPROM programmer)
RAM size
512 × 8 bits 768 × 8 bits 1024 × 8 bits 512 × 8bits
1024 × 8 bits
1 K × 8 bits
CPU functions
The number of instructionns:
Instruction bit length:
Instruction length:
136
8 bits
1 to 3 bytes
1, 8, 16 bits
Data bit length:
Minimum execution time:
Interrupt processing time:
0.4 to 6.4 µs/10 MHz, 61 µs@32.768 kHz
3.6 to 57.6 µs/10 MHz, 562.5 µs@32.768 kHz
Ports
Input ports:
5 (All also serve as peripherals.)
8 (All also serve as peripherals.)
4 (All also serve as peripherals.)
8 (All also serve as bus control.)
28 (27 ports also serve as bus pins and peripherals.)
53
Output ports (N-ch open-drain):
I/O ports (N-ch open-drain):
Output ports (CMOS):
I/O ports (CMOS):
Total:
Clock timer
21 bits × 1 (in main clock)/15 bits × 1 (at 32.768 kHz)
8-bit PWM
timer
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs to 3.3 ms) × 2
channels
7/8-bit resolution PWM operation (conversion cycle: 51.2 µs to 839 ms) × 2 channels
8-bit pulse
width count
timer
8-bit timer operation (overflow output capable, operating clock cycle: 0.4 to 12.8 µs)
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 to 12.8 µs)
8-bit pulse width measurement operation (capable of continuous measurement, and
measurement of “H” pulse width/ “L” pulse width/ from ↑ to ↑/from ↓ to ↓)
16-bit timer/
counter
16-bit timer operation (operating clock cycle: 0.4 µs)
16-bit event counter operation (rising edge/falling edge/both edge selectable)
8-bit serial I/O
8 bits
LSB first/MSB first selectable
One clock selectable from four transfer clocks
(one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs)
UART
Capable of switching two I/O systems by software
Transfer data length (6, 7, and 8 bits)
Transfer rate (300 to 62500 bps. at 10 MHz osciliation)
10-bit A/D
converter
10-bit resolution × 8 channels
A/D conversion mode (conversion time: 13.2 µs)
Sense mode (conversion time: 7.2 µs)
Capable of continuous activation by an external activation or an internal timer
(Continued)
3
MB89630R Series
(Continued)
Part number
MB89635R MB89636R MB89637R MB89T635R MB89T637R MB89P637 MB89W637 MB89PV630
Item
External
interrupt input
4 independent channels (edge selection, interrupt vector, source flag).
Rising edge/falling edge selectable
Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.)
Standby mode
Process
Sleep mode, stop mode, watch mode, and subclock mode
CMOS
Operating
voltage*
2.2 V to 6.0 V
2.7 V to 6.0 V
MBM27C256A-20CZ
MBM27C256A-20TV
EPROM for use
* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
In the case of the MB89PV630, the voltage varies with the restrictions of the EPROM for use.
■ PACKAGE AND CORRESPONDING PRODUCTS
MB89636R
MB89635R
Package
MB89637R
MB89P637
MB89W637
MB89PV630
MB89T635R
MB89T637R
DIP-64P-M01
FPT-64P-M06
FPT-64P-M09
DIP-64C-A06
MQP-64C-P01
MDP-64C-P02
×
×
×
×
×*
×
×*
×*
×
×
×
×
×
×
×
×
×
×
×
: Available
×: Not available
* : To convert pin pitches, an adapter socket (manufacturer: Sun Hayato Co., Ltd.) is available.
64SD-64QF2-8L: For conversion from (DIP-64P-M01, DIP-64C-A06, or MDP-64C-P02) to FPT-64P-M09
Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403
FAX (81)-3-5396-9106
Note: For more information about each package, see section “■ Package Dimensions.”
4
MB89630R Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following points:
On the MB89P637/W637, the program area starts from address 8007H but on the MB89PV630 and MB89637R
starts from 8000H.
• On the MB89P637/W637, addresses 8000H to 8006H comprise the option setting area, option settings can be
read by reading these addresses. On the MB89PV630/MB89637R, addresses 8000H to 8006H could also be
used as a program ROM. However, do not use these addresses in order to maintain compatibility of the
MB89P637/W637.
• The stack area, etc., is set at the upper limit of the RAM.
• The external area is used.
2. Current Consumption
• In the case of the MB89PV630, add the current consumed by the EPROM which connected to the top socket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume
more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is
the same. (For more information, see sections “■Electrical Characteristics” and “■Example Characteristics.”)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product.
Before using options check section “■ Mask Options.”
Take particular care on the following points:
• A pull-up resistor cannot be set for P50 to P53 on the MB89P637 and MB89W637.
• Options are fixed on the MB89PV630, MB89T635R, and MB89T637R.
4. Differences between the MB89630 and MB89630R Series
• Memory access area
There are no difference between the access area of MB89635/MB89635R, and that of MB89637/MB89637R.
The access area of MB89636 is different from that of the MB89636R when using in external bus mode.
Memory area
Address
MB89636
MB89636R
0000H to 007FH
0080H to 037FH
0380H to 047FH
0480H to 7FFFH
8000H to 9FFFH
A000H to FFFFH
I/O area
I/O area
RAM area
RAM area
Access prohibited
External area
External area
ROM area
Access prohibited
ROM area
5
MB89630R Series
• Other specifications
Both MB89630 series and MB89630R is the same.
• Electrical specifications/electrical characteristics
Electrical specifications of the MB89630R series are the same as that of the MB89630 series.
Electrical characteristics of both the series are much the same.
■ CORRESPONDENCE BETWEEN THE MB89630 AND MB89630R SERIES
• The MB89630R series is the reduction version of the MB89630 series.
• The the MB89630 and MB89630R series consist of the following products:
MB89630 series MB89635 MB89T635 MB89636 MB89637
MB89T637
MB89P637 MB89W637 MB89PV630
MB89630R series MB89635R MB89T635R MB89636R MB89637R MB89T637R
6
MB89630R Series
■ PIN ASSIGNMENT
(Top view)
1
VCC
P31/UO1
P30/UCK1
P43/PTO1
P42/UI2
P41/UO2
P40/UCK2
P53/PTO2
P52
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
P32/UI1
P33/SCK1
P34/SO1
P35/SI1
P36/PWC
P37/WTO
VSS
3
65
66
67
68
69
70
71
72
73
74
75
76
77
78
VCC
A14
A13
A8
VPP
A12
A7
92
91
90
89
88
87
86
85
84
83
82
81
80
79
4
5
6
A6
7
A9
A5
8
A11
A4
9
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/A08
P11/A09
P12/A10
P13/A11
P14/A12
P15/A13
P16/A14
P17/A15
P20/BUFC
P21/HAK
P22/HRQ
P23/RDY
P24/CLK
P25/WR
P26/RD
P27/ALE
P51/BZ
P50/ADST
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
AVCC
A3
OE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A10
A2
A1
CE
O8
O7
O6
O5
O4
A0
O1
O2
O3
VSS
AVR
AVSS
Each pin inside
the dashed line is
for MB89PV630 only.
P74/EC
P73/INT3
P72/INT2
P71/INT1/X0A*
P70/INT0/X1A*
RST
MOD0
MOD1
X0
X1
VSS
(DIP-64P-M01)
(DIP-64C-A06)
(MDP-64C-P02)
*: When the dual-clock system is selected.
(Top view)
P51/BZ
P50/ADST
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
AVCC
AVR
AVSS
P74/EC
P73/INT3
P72/INT2
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/A08
P11/A09
P12/A10
P13/A11
P14/A12
P15/A13
P16/A14
P17/A15
9
10
11
12
13
14
15
16
(FPT-64P-M09)
*: When the dual-clock system is selected.
7
MB89630R Series
(Top view)
P52
P51/BZ
1
2
3
4
5
6
7
8
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P37/WTO
VSS
P50/ADST
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
AVCC
AVR
AVSS
P74/EC
P73/INT3
P72/INT2
P71/INT1/X0A*
P70/INT0/X1A*
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/A08
P11/A09
P12/A10
P13/A11
P14/A12
P15/A13
P16/A14
P17/A15
P20/BUFC
85
86
87
88
89
90
91
92
93
77
76
75
74
73
72
71
70
69
9
10
11
12
13
14
15
16
17
18
19
Each pin inside the dashed line
is for MB89PV630 only.
(FPT-64P-M06)
(MQP-64C-P01)
*: When the dual-clock system is selected.
• Pin assignment on package top (MB89PV630 only)
Pin no.
65
Pin name
N.C.
VPP
Pin no.
73
Pin name
A2
Pin no.
81
Pin name
N.C.
O4
Pin no.
89
Pin name
OE
66
74
A1
82
90
N.C.
A11
A9
67
A12
A7
75
A0
83
O5
91
68
76
N.C.
O1
84
O6
92
69
A6
77
85
O7
93
A8
70
A5
78
O2
86
O8
94
A13
A14
VCC
71
A4
79
O3
87
CE
95
72
A3
80
VSS
88
A10
96
N.C.: Internally connected. Do not use.
8
MB89630R Series
■ PIN DESCRIPTION
Pin no.
Circuit
type
Pin name
Function
SH-DIP*1
MDIP*2
QFP1*4
QFP2*3
MQFP*5
23
30
31
28
29
27
22
23
20
21
19
X0
X1
A
D
C
Main clock crystal oscillator pins
24
21
MOD0
MOD1
RST
Operating mode selection pins
Connect directly to VCC or VSS.
22
20
Reset I/O pin
This pin is an N-ch open-drain output type with a
pull-up resistor, and a hysteresis input type.
“L” is output from this pin by an internal reset
source. The internal circuit is initialized by the
input of “L”.
56 to 49 48 to 41 49 to 42 P00/AD0 to
P07/AD7
F
General-purpose I/O ports
When an external bus is used, these ports
function as the multiplex pins of the lower address
output and the data I/O.
48 to 41 40 to 33 41 to 34 P10/A08 to
P17/A157
F
General-purpose I/O ports
When an external bus is used, these ports
function as an upper address output.
40
39
38
32
31
30
33
32
31
P20/BUFC
P21/HAK
P22/HRQ
H
General-purpose output port
When an external bus is used, this port can also
be used as a buffer control output by setting the
BCTR.
H
F
General-purpose output port
When an external bus is used, this port can also
be used as a hold acknowledge by setting the
BCTR.
General-purpose output port
When an external bus is used, this port can also
be used as a hold request input by setting the
BCTR.
37
36
35
34
29
28
27
26
30
29
28
27
P23/RDY
P24/CLK
P25/WR
P26/RD
F
H
H
H
General-purpose output port
When an external bus is used, this port functions
as a ready input.
General-purpose output port
When an external bus is used, this port functions
as a clock output.
General-purpose output port
When an external bus is used, this port functions
as a write signal output.
General-purpose output port
When an external bus is used, this port functions
as a read signal output.
(Continued)
*1: DIP-64P-M01, DIP-64C-A06
*2: MDP-64C-P02
*4: FPT-64P-M06
*5: MQP-M64C-P01
*3: FPT-64P-M09
9
MB89630R Series
(Continued)
Pin no.
Circuit
type
SH-DIP*1
MDIP*2
QFP1*4
MQFP*5
Pin name
P27/ALE
Function
QFP2*3
33
25
26
H
General-purpose output port
When an external bus is used, this port functions
as an address latch signal output.
2
58
59
P30/UCK1
G
General-purpose I/O port
Also serves as the clock I/O 1 for the UART.
This port is a hysteresis input type.
1
57
55
58
56
P31/UO1
P32/UI1
F
General-purpose I/O port
Also serves as the data output 1 for the UART.
63
G
General-purpose I/O port
Also serves as the data input 1 for the UART.
This port is a hysteresis input type.
62
54
55
P33/SCK1
G
General-purpose I/O port
Also serves as the data input for the 8-bit serial
I/O.
This port is a hysteresis input type.
61
60
53
52
54
53
P34/SO1
P35/SI1
F
General-purpose I/O port
Also serves as the data output for the 8-bit serial
I/O.
G
General-purpose I/O port
Also serves as the data input for the 8-bit serial
I/O.
This port is a hysteresis input type.
59
51
52
P36/PWC
G
General-purpose I/O port
Also serves as the measured pulse input for the
8-bit pulse width counter.
This port is a hysteresis input type.
58
6
50
62
51
63
P37/WTO
P40/UCK2
F
General-purpose I/O port
Also serves as the toggle output for the 8-bit pulse
width counter.
G
General-purpose I/O port
Also serves as the clock I/O 2 for the UART.
This port is a hysteresis input type.
5
4
61
60
62
61
P41/UO2
P42/UI2
F
General-purpose I/O port
Also serves as the data output 2 for the UART.
G
General-purpose I/O port
Also serves as the data input 2 for the UART.
This port is a hysteresis input type.
3
59
2
60
3
P43/PTO1
P50/ADST
F
K
General-purpose I/O port
Also serves as the toggle output for the 8-bit PWM
timer.
10
General-purpose I/O port
Also serves as an A/D converter external
activation.
This port is a hysteresis input type.
(Continued)
*1: DIP-64P-M01, DIP-64C-A06
*2: MDP-64C-P02
*4: FPT-64P-M06
*5: MQP-M64C-P01
*3: FPT-64P-M09
10
MB89630R Series
(Continued)
Pin no.
QFP2*3
1
Circuit
type
Pin name
P51/BZ
Function
SH-DIP*1
MDIP*2
QFP1*4
MQFP*5
9
2
J
General-purpose I/O port
Also serves as a buzzer output.
8
7
64
63
1
P52
J
J
General-purpose I/O port
64
P53/PTO2
General-purpose I/O port
Also serves as the toggle output for the 8-bit PWM
timer.
11 to 18
3 to 10
4 to 11 P60/AN0 to
P67/AN7
I
N-ch open-drain output ports
Also serve as an A/D converter analog input.
26,
25
18,
17
19,
18
P70/INT0/X1A,
P71/INT1/X0A
B/E
Input-only ports
These ports are a hysteresis input type.
Also serve as an external interrupt input (at single-
clock operation).
Subclock crystal oscillator pins (at dual-clock
operation)
24,
23
16,
15
17,
16
P72/INT2,
P73/INT3
E
E
Input-only ports
Also serve as an external interrupt input.
These ports are a hysteresis input type.
22
14
15
P74/EC
General-purpose input port
Also serves as the external clock input for the
16-bit timer/counter.
This port is a hysteresis input type.
64
32, 57
19
56
24,49
11
57
25, 50
12
VCC
—
—
—
—
—
Power supply pin
VSS
Power supply (GND) pin
AVCC
AVR
AVSS
A/D converter power supply pin
A/D converter reference voltage input pin
20
12
13
21
13
14
A/D converter power supply pin
Use this pin at the same voltage as VSS.
*1: DIP-64P-M01, DIP-64C-A06
*2: MDP-64C-P02
*4: FPT-64P-M06
*5: MQP-M64C-P01
*3: FPT-64P-M09
11
MB89630R Series
• External EPROM pins (MB89PV630 only)
Pin no.
Pin name
VPP
I/O
Function
MDIP
MQFP
65
66
O
O
“H” level output pin
Address output pins
66
67
68
69
70
71
72
73
74
67
68
69
70
71
72
73
74
75
A12
A7
A6
A5
A4
A3
A2
A1
A0
75
76
77
77
78
79
O1
O2
O3
I
Data input pins
78
80
VSS
O
I
Power supply (GND) pin
Data input pins
79
80
81
82
83
82
83
84
85
86
O4
O5
O6
O7
O8
84
87
CE
O
ROM chip enable pin
Outputs “H” during standby.
85
86
88
89
A10
OE
O
O
Address output pin
ROM output enable pin
Outputs “L” at all times.
87
88
89
91
92
93
A11
A9
A8
O
Address output pins
90
91
92
—
94
95
96
A13
A14
VCC
O
O
O
EPROM power supply pin
65
76
81
90
N.C.
—
Internally connected pins
Be sure to leave them open.
12
MB89630R Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• Crystal or ceramic oscillation type (main clock)
X1
X0
External clock input selection versions of MB89PV630,
MB89P637, MB89W637, MB89635R, MB89T635R,
MB89636R, MB89637R, and MB89T637R
At an oscillation feedback resistor of approximately
1 MΩ@5.0 V
Standby control signal
B
• Crystal or ceramic oscillation type (subclock)
MB89PV630, MB89P637, MB89W637, MB89635R,
MB89636R, and MB89637R with dual-clock system
At an oscillation feedback resistor of approximately
4.5 MΩ@5.0 V
X1A
X0A
Standby control signal
C
• At an output pull-up resistor (P-ch) of approximately
50 kΩ@5.0 V
• Hysteresis input
R
P-ch
N-ch
D
E
• Hysteresis input
R
• Pull-up resistor optional (except P70 and P71)
F
• CMOS output
• CMOS input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional (except P22 and P23)
(Continued)
13
MB89630R Series
(Continued)
Type
Circuit
Remarks
G
• CMOS output
• Hysteresis input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
• CMOS output
H
P-ch
N-ch
I
• Analog input
• CMOS input
N-ch
Analog input
J
R
P-ch
N-ch
• Pull-up resistor optional
• Hysteresis input
K
R
P-ch
N-ch
• Pull-up resistor optional
14
MB89630R Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
couldcausemalfunctions, evenifitoccurswithintheratedrange. StabilizingvoltagesuppliedtotheICistherefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 Hz to 60 Hz) and the
transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power
is switched.
6. Precautions when Using an External Clock
When an external clock is used, oscillation stabilization time is required even for power-on reset (option selection)
and wake-up from stop mode.
15
MB89630R Series
■ PROGRAMMING TO THE EPROM ON THE MB89P637
The MB89P637 is an OTPROM version of the MB89630 series.
1. Features
• 32-Kbytes PROM on chip
• Options can be set using the EPROM programmer.
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in each mode is illustrated below.
EPROM mode
(Corresponding addresses
on the EPROM programmer)
Normal operating mode
I/O
0000H
0080H
0100H
0200H
Register
RAM
0480H
8000H
8007H
External area
0000H
0007H
Option setting area
Option setting area
Program area
(EPROM)
32 KB
PROM
32 KB
FFFFH
7FFFH
3. Programming to the EPPROM
In EPROM mode, the MB89P637 functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer by using the dedicated socket adapter.
However, the electronic signature mode cannot be used.
When the operating ROM area for a single chip is 32 Kbytes (8007H to FFFFH) the EPROM can be programmed
as follows:
16
MB89630R Series
• Programming procedure
(1) Set the EPROM programmer to the MBM27C256A-20CZ and MBM27C256A-20TV.
(2) Load program data into the EPROM programmer at 0007H to 7FFFH. (Note that addresses 8000H to FFFFH
in the operating mode assign to 0000H to 7FFFH in EPROM mode).
(3) Load option data into addresses 0000H to 0006H of the EPROM programmer.
(For information about each corresponding option, see “8. OTPROM Option Bit Map.”)
(4) Program with the EPROM programmer.
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. Erasure
In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an
ultraviolet light source. A dosage of 10 W-seconds/cm2 is required to completely erase an internal EPROM. This
dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (Å)) with intensity
of 12000 µW/cm2 for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all
filters should be removed from the UV light source prior to erasure.
It is important to note that the internal EPROM and similar devices, will erase with light sources having wave-
lengths shorter than 4000 Å. Although erasure time will be much longer than with UV source at 2537 Å,
nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and
exposure to them should be prevented to realize maximum system reliability. If used in such an environment,
the package windows should be covered by an opaque label or substance.
17
MB89630R Series
7. EPROM Programmer Socket Adapter
Part No.
Package
MB89P637-SH
SH-DIP-64
MB89P637PF
QFP-64
Compatible socket adapter
Sun Hayato Co., Ltd.
ROM-64SD-28DP-8L
ROM-64QF-28DP-8L
Inquiry: Sun Hayato Co., Ltd.: TEL : (81)-3-3986-0403
FAX: (81)-3-5396-9106
8. OTPROM Option Bit Map
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Vacancy
Vacancy
Vacancy
Single/dual-
clock system
1: Dual clock
Oscillation stabilization (/FCH)
11:218/FCH 01:217/FCH
Reset pin Power-on
output
1: Yes
0: No
reset
1: Yes
0: No
0000H
Readable
Readable
Readable
and writable and writable and writable 0: Single clock
10:214/FCH 00:24/FCH
P07
P06
P05
P04
P03
P02
P01
P00
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
0001H
0002H
0003H
0004H
P17
P16
P15
P14
P13
P12
P11
P10
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
P37
P36
P35
P34
P33
P32
P31
P30
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Vacancy
Vacancy
P43
P42
P41
P40
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Readable
Readable
Readable
Readable
and writable and writable and writable and writable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
P74
P73
P72
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
0005H
0006H
Readable
Readable
Readable
Readable
and writable and writable
Readable
and writable and writable and writable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Reserved bit
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Readable
and writable and writable and writable and writable and writable and writable and writable and writable
Note: Each bit is set to ‘1’ as the initialized value.
18
MB89630R Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20CZ, MBM27C256A-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
Adapter socket part number
LCC-32 (Rectangle)
ROM-32LC-28DP-YG
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403
FAX: (81)-3-5396-9106
3. Memory Space
Memory space in each mode, such as 32-Kbyte PROM, option area is diagrammed below.
Address
0000H
Single chip
Corresponding addresses on the EPROM programmer
I/O
0080H
0480H
RAM
Not available
Not available
8000H
8007H
0000H
Not available
0007H
PROM
32 KB
EPROM
32 KB
FFFFH
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0007H to 7FFFH.
(3) Program to 0000H to 7FFFH with the EPROM programmer.
19
MB89630R Series
■ BLOCK DIAGRAM
X0
X1
Main clock oscillator
Subclock oscillator
(32.768 kHz)
X0A
X1A
21-bit timebase timer
Clock controller
CMOS I/O port
8-bit PWC timer
P37/WTO
P36/PWC
Reset circuit
(Watchdog timer)
RST
P35/SI1
P34/SO1
P33/SCK1
8-bit serial I/O
Watch prescaler
CMOS I/O port
P32/UI1
P31/UO1
P00/AD0
to P07/AD7
8
8
P30/UCK1
UART
P40/UCK2
P41/UO2
P42/UI2
P10/A08
to P17/A15
MOD0
MOD1
UART baud rate
generator
External bus
interface
P27/ALE
P26/RD
P25/WR
CMOS I/O port
P43/PTO1
P24/CLK
P23/RDY
P22/HRQ
P21/HAK
P20/BUFC
N-ch open-drain I/O port
CMOS output port
P53/PTO2
P52
8-bit PWM timer
Buzzer output
P51/BZ
RAM
P50/ADST
3
AVCC, AVSS,
10-bit A/D converter
AVR
F2MC-8L
CPU
8
8
P60/AN0
to P67/AN7
N-ch open-drain output port
Input port
ROM
P70/INT0
P71/INT1
P72/INT2
P73/INT3
4
External interrupt
Other pins
VCC × 2, VSS × 2
16-bit timer/counter
P74/EC
20
MB89630R Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89630R series offer 64 Kbytes of memory for storing all of I/O, data, and program
areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area.
The data area can be divided into register, stack, and direct areas according to the application. The program
area is located at exactly the opposite end of I/O area, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89630R series is structured as illustrated below.
• Memory space
MB89637R
MB89T637R
MB89P637
MB89W637
MB89635R
MB89T635R
MB89PV630
I/O
MB89636R
I/O
0000H
0080H
0000H
0080H
0000H
0080H
0100H
0000H
0080H
I/O
I/O
RAM
1024 KB
RAM
1 KB
RAM
512 B
RAM
768 B
0100H
0200H
0100H
0200H
0100H
0200H
Register
Register
Register
Register
0200H
0280H
0380H
0480H
*3
0480H
8000H
8007H
0480H
External area
*2
External area
*2
External area
8000H
8000H
8007H
External area
*3
A000H
ROM*1
32 KB
External ROM
32 KB
C000H
FFFFH
ROM*1
24 KB
ROM*1
16 KB
FFFFH
FFFFH
FFFFH
*1: The ROM area is an external area depending on the mode.
The internal ROM cannot be used on the MB89T635R and MB89T637R.
*2: Addresses 8000H to 8006H for the MB89P637 and MB89W637 comprise an option area, do not use
this area for the MB89PV630 and MB89637R.
*3: The access is forbidden in the external bus mode.
21
MB89630R Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:
Program counter (PC):
Accumulator (A):
A 16-bit register for indicating the instruction storage positions
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T): A16-bit register which performs arithmetic operations with the accumulator
Whentheinstructionisan8-bitdataprocessinginstruction, thelowerbyteisused.
Index register (IX):
Extra pointer (EP):
Stack pointer (SP):
Program status (PS):
A16-bit register for index modification
A16-bit pointer for indicating a memory address
A16-bit register for indicating a stack area
A16-bit register for storing a register pointer, a condition code
Initial value
16 bits
PC
A
: Program counter
: Accumulator
FFFDH
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
T
: Temporary accumulator
: Index register
IX
EP
SP
PS
: Extra pointer
: Stack pointer
: Program status
I-flag = 0, IL1, IL0 = 11
The other bit values are indeterminate.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
• Structure of the program status register
15
14
13
12
11
10
9
8
7
6
I
5
4
3
2
Z
1
0
PS
RP
Vacancy Vacancy Vacancy
H
IL1, IL0
N
V
C
RP
CCR
22
MB89630R Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
• Rule for conversion of actual addresses of the general-purpose register area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to ‘0’ otherwise. This flag is for decimal adjustment instructions.
I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared
to ‘0’ at the reset.
IL1, IL0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
0
IL0
0
Interrupt level
High-low
High
1
0
1
1
0
2
3
1
1
Low
N-flag: Set to ‘1’ if the MSB becomes to ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ when the bit
is cleared to ‘0’.
Z-flag: Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise.
V-flag: Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to ‘0’ if the
overflow doesnot occur.
C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to ‘0’
otherwise.
Set to the shift-out value in the case of a shift instruction.
23
MB89630R Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers and up to a total of 32 banks can be used on the MB89653A (RAM 512 × 8 bits). The bank
currently in use is indicated by the register bank pointer (RP).
• Register bank configuraiton
This address = 0100H + 8 × (RP)
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
32 banks
Memory area
24
MB89630R Series
■ I/O MAP
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Read/write
(R/W)
(W)
Register name
PDR0
Register description
Port 0 data register
DDR0
Port 0 data direction register
Port 1 data register
(R/W)
(W)
PDR1
DDR1
Port 1 data direction register
Port 2 data register
(R/W)
(W)
PDR2
BCTR
External bus pin control register
Vacancy
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(W)
SYCC
STBC
WDTE
TBCR
WPCR
CHG3
PDR3
DDR3
PDR4
DDR4
BUZR
PDR5
PDR6
PDR7
PCR1
PCR2
RLBR
TMCR
TCHR
TCLR
System clock control register
System clock control register
Watchdog timer control register
Timebase timer control register
Watch prescaler control register
Port 3 switching register
Port 3 data register
Port 3 data direction register
Port 4 data register
(R/W)
(W)
Port 4 data direction register
Buzzer register
(R/W)
(R/W)
(R/W)
(R)
Port 5 data register
Port 6 data register
Port 7 data register
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
PWC pulse width control register 1
PWC pulse width control register 2
PWC reload buffer register
16-bit timer control register
16-bit timer count register (H)
16-bit timer count register (L)
Vacancy
(R/W)
(R/W)
SMR1
SDR1
Serial mode register
Serial data register
Vacancy
Vacancy
(Continued)
25
MB89630R Series
(Continued)
Address
20H
Read/write
(R/W)
Register name
ADC1
Register description
A/D converter control register 1
A/D converter control register 2
A/D converter data register (H)
A/D converter data register (L)
External interrupt control register 1
External interrupt control register 2
21H
(R/W)
ADC2
22H
(R/W)
ADDH
23H
(R/W)
ADDL
24H
(R/W)
EIC1
25H
(R/W)
EIC2
26H
Vacancy
Vacancy
PWM timer control register 1
27H
28H
(R/W)
(R/W)
(R/W)
(W)
CNTR1
CNTR2
CNTR3
COMR1
COMR2
SMC
29H
PWM timer control register 2
PWM timer control register 3
PWM timer compare register 1
PWM timer compare register 2
UART serial mode control register
UART serial rate control register
UART serial status/data register
2AH
2BH
2CH
2DH
2EH
2FH
(W)
(R/W)
(R/W)
(R/W)
SRC
SSD
(R)
(W)
SIDR
SODR
UART serial input data control register
UART serial output data control register
30H
31H to 7BH
7CH
Vacancy
(W)
(W)
(W)
ILR1
ILR2
ILR3
Interrupt level setting register 1
Interrupt level settingregister 2
Interrupt level setting register 3
7DH
7EH
7FH
Vacancy
Note: Do not use vacancies.
26
MB89630R Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
VCC
VSS – 0.3
VSS – 0.3
VSS + 7.0
VSS + 7.0
V
V
*
*
Power supply voltage
AVCC
AVR must not exceed
“AVCC + 0.3 V”.
A/D converter reference input voltage
Input voltage
AVR
VSS – 0.3
VSS + 7.0
V
VI
VSS – 0.3
VSS – 0.3
VSS – 0.3
VSS – 0.3
VCC + 0.3
VSS + 7.0
VCC + 0.3
VSS + 7.0
20
V
V
Except P50 to P53
P50 to P53
VI2
VO
VO2
IOL
V
Except P50 to P53
P50 to P53
Output voltage
V
“L” level maximum output current
“L” level average output current
mA
Average value (operating
current × operating rate)
IOLAV
∑IOL
4
mA
mA
mA
mA
mA
mA
mA
“L” level total maximum output current
“L” level total average output current
“H” level maximum output current
“H” level average output current
“H” level total maximum output current
“H” level total average output current
100
40
Average value (operating
current × operating rate)
∑IOLAV
IOH
–20
–4
Average value (operating
current × operating rate)
IOHAV
∑IOH
∑IOHAV
–50
–20
Average value (operating
current × operating rate)
Power consumption
Operating temperature
Storage temperature
PD
500
+85
mW
°C
TA
–40
–55
Tstg
+150
°C
* : Use AVCC and VCC set at the same voltage.
Take care so that AVCC does not exceed VCC, such as when power is turned on.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
27
MB89630R Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max
Normal operation
assurance range*
MB89635R/637R
2.2*
6.0*
V
VCC
Normal operation
assurance range*
MB89PV630/P637/
W637/T635R/T637R
Power supply voltage
2.7*
1.5
6.0*
6.0
V
V
Retains the RAM state in
stop mode
AVCC
A/D converter reference input voltage
Operating temperature
AVR
3.0
AVCC
+85
V
TA
–40
°C
* : These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1
and “5. A/D Converter Electrical Characteristics.”
Figure 1 Operating Voltage vs. Main Clock Operating Frequency
6
5
4
Analog accuracy assured in the
AVCC = 3.5 V to 6.0 V range
Operation assurance range
3
2
1
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
Main clock operating frequency (at an instruction cycle of 4/FCH) (MHz)
4.0 2.0
0.8
0.4
Minimum execution time (instruction cycle) (µs)
Note: The shaded area is assured only for the MB89635R/636R/637R.
Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH.
Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the
operating speed is switched using a gear.
28
MB89630R Series
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
29
MB89630R Series
3. DC Characteristics
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Parameter
Pin name
Condition
Unit
Remarks
Min.
Typ.
Max.
P00 to P07, P10 to P17,
P22, P23, P31, P34,
P37, P41, P43,
P51 to P53
with pull-up
resistor
VIH1
VIH2
VIHS
0.7 VCC
VCC + 0.3
V
V
V
P51 to P53
Without pull-up
resistor
P51 to P53
VSS + 6.0
VCC + 0.3
0.7 VCC
0.8 VCC
“H” level input
voltage
RST, MOD0, MOD1,
P30, P32, P33, P35,
P36, P40, P42,P50,
P72 to P74
P50 with
pull-up resistor
Without pull-up
resistor
P50, P70, P71
0.8 VCC
VSS + 6.0
0.3 VCC
V
V
VIHS2
P00 to P07, P10 to P17,
P22, P23, P31, P34,
P37, P41, P43
VSS − 0.3
VIL
P30, P32, P33, P35,
P36, P40, P42,
P50 to P53,
P70 to P74,
RST,
“L” level input
voltage
VSS − 0.3
VILS
0.2 VCC
VSS + 6.0
V
V
MOD0, MOD1
Open-drain
output pin
application
voltage
P50 to P53
VSS − 0.3
VD
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P43
“H” level output
voltage
VOH
IOH = –2.0 mA
IOL = 4.0 mA
4.0
V
V
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P43, P50 to P53,
P60 to P67, RST
“L” level output
voltage
VOL
0.4
P00 to P07, P10 to P17,
P20 to P23, P30 to P37,
P40 to P43, P50 to P53,
P70 to P74,
Input leakage
current
(Hi-z output
leakage current)
Without pull-up
resistor
ILI
0.0 V < VI < VCC
±5
µA
MOD0, MOD1
(Continued)
30
MB89630R Series
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Parameter
Pull-up
Pin name
Condition
Unit
Remarks
Min.
Typ.
Max.
P00 to P07, P10 to P17,
P30 to P37, P40 to P43,
P50 to P53, P72 to P74
With pull-up
resistor
RPULL
VI = 0.0 V
FCH = 10 MHz
25
50
100
kΩ
resistance
CC = 5.0 V
ICC1
V
—
12
20
mA
*2
tinst = 0.4 µs
MB89635R/T635R/
636R/637R/T637R/
PV630
FCH = 10 MHz
VCC = 3.0 V
tinst*2 = 6.4 µs
—
—
—
1.0
1.5
3
2
2.5
7
mA
mA
mA
ICC2
MB89P637/W637
FCH = 10 MHz
VCC = 5.0 V
tinst*2 = 0.4 µs
ICCS1
FCH = 10 MHz
VCC = 3.0 V
tinst*2 = 6.4 µs
ICCS2
—
0.5
1.5
mA
MB89635R/T635R/
636R/637R/T637R/
PV630
FCL = 32.768 kHz,
VCC = 3.0 V
Subclock mode
—
—
50
100
700
µA
µA
ICCL
Power supply
current*1
VCC
MB89P637/W637
500
FCL = 32.768 kHz,
VCC = 3.0 V
Subclock sleep
mode
ICCLS
—
25
3
50
µA
FCL = 32.768 kHz,
VCC = 3.0 V
• Watch mode
• Mainclock stop
mode at dual-
clock system
ICCT
—
15
µA
TA = +25°C
• Subclock stop
mode
• Main clock stop
mode at single-
clock system
ICCH
—
—
1
µA
(Continued)
31
MB89630R Series
(Continued)
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Parameter
Pin name
Condition
Unit
Remarks
Min.
Typ.
Max.
FCH = 10 MHz,
when A/D
conversion
operates.
IA
—
6
—
mA
Power supply
current*1
AVCC
FCH = 10 MHz,
TA = +25°C,
when A/D
IAH
—
—
—
1
µA
conversion in
a stop.
Other than AVCC,
AVSS, VCC, and VSS
Input capacitance CIN
f = 1 MHz
10
—
pF
*1: The power supply current is measured at the external clock.
In the case of the MB89PV630, the current consumed by the connected EPROM and ICE is not counted.
*2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
4. AC Characteristics
(1) Reset Timing
(VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Condition
Unit
Remarks
Parameter
Min.
Max.
RST “L” pulse width
tZLZH
—
48 tHCYL
—
ns
tZLZH
RST
0.2 VCC
0.2 VCC
32
MB89630R Series
(2) Specification for Power-on Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Condition
Unit
Remarks
Parameter
Min.
Max.
Power supply rising time
Power supply cut-off time
tR
—
1
50
ms
ms
Power-on reset function only
—
Min. interval time for the next
power-on reset
tOFF
—
Note: Make sure that power supply rises within the selected oscillation stabilization time.
Ifpowersupplyvoltageneedstobevariedinthecourseofoperation, asmoothvoltageriseisrecommended.
tOFF
tR
2.0 V
0.2 V
0.2 V
0.2 V
V
CC
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Typ.
—
Symbol Pin name Condition
Unit
Remarks
Parameter
Clock frequency
Clock cycle time
Min.
1
Max.
10
FCH
X0, X1
MHz
kHz
ns
FCL
X0A, X1A
X0, X1
—
32.768
—
—
tHCYL
tLCYL
100
—
1000
—
X0A, X1A
30.5
µs
—
PWH
PWL
X0
20
—
—
—
15.2
—
—
—
10
ns
µs
ns
External clock
External clock
External clock
Input clock pulse width
PWLH
PWLL
X0A
X0
Input clock rising/falling tCR
time
tCF
33
MB89630R Series
• Main clock timing condition
tHCYL
PWH
PWL
tCR
tCF
0.8 VCC
0.8 VCC
X 0
0.2 VCC
0.2 VCC
0.2 VCC
• Main clock configurations
When a crystal
or
ceramic reasonator is used
When an external clock is used
X0
X1
X0
X1
Open
• Subclock timing condition
tLCYL
PWLH
PWLL
tCR
tCF
0.8 VCC
0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
• Subclock configurations
When a crystal
or
ceramic reasonator is used
When an external clock is used
X0A
X1A
X0A
X1A
Open
34
MB89630R Series
(4) Instruction Cycle
Parameter
Symbol
Value (typical)
Unit
Remarks
(4/FCH) tinst = 0.4 µs, operating at
FCH = 10 MHz
4/FCH, 8/FCH, 16/FCH, 64/FCH
µs
Instruction cycle
(minimum execution time)
tinst
tinst = 61.036 µs, operating at
FCL = 32.768 kHz
2/FCL
µs
Note: Operating at 10 MHz, the cycle varies with the set execution time.
(5) Clock Output Timing
(VCC = 5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Value
Pin
Symbol
Condition
Unit Remarks
Parameter
name
Min.
1/2 tinst*
Max.
—
Clock time
CLK ↑ → CLK ↓
tCYC
CLK
CLK
µs
µs
—
tCHCL
1/4 tinst* – 70 ns
1/4 tinst*
* : For information on tinst, see “(4) Instruction Cycle.”
tCYC
tCHCL
2.4 V
2.4 V
CLK
0.8 V
35
MB89630R Series
(6) Bus Read Timing
(VCC = 5.0 V±10%, 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name Condition
Unit Remarks
Parameter
Min.
1/4 tinst*– 64 ns
1/2 tinst*– 20 ns
1/2 tinst*
Max.
—
RD, A15 to A08,
AD7 to AD0
Valid address → RD ↓ time tAVRL
µs
RD
RD pulse width
tRLRH
tAVDV
tRLDV
tRHDX
tRHLH
—
µs
Valid address → data read
AD7 to AD0,
A15 to A08
200
120
—
µs No wait
µs No wait
µs
time
RD, AD7 to AD0
1/2 tinst*– 80 ns
0
RD ↓ → data read time
RD ↑ → data hold time
RD ↑ → ALE ↑ time
AD7 to AD0,
RD
—
RD, ALE
1/4 tinst*– 40 ns
1/4 tinst*– 40 ns
1/4 tinst*– 40 ns
0
—
—
—
—
—
µs
µs
µs
ns
µs
RD ↑ → address loss time tRHAX
RD, A15 to A08
RD ↓ → CLK ↑ time
CLK ↓ → RD ↑ time
RD ↓ → BUFC ↓ time
tRLCH
tCLRH
tRLBL
RD, CLK
RD, BUFC
–5
A15 to A08,
AD7 to AD0,
BUFC
BUFC ↑ → valid address
time
tBHAV
5
—
µs
* : For information on tinst, see “(4) Instruction Cycle.”
2.4 V
CLK
0.8 V
t
RHLH
ALE
0.8 V
0.7 VCC
0.3 VCC
2.4 V
0.7 VCC
0.3 VCC
2.4 V
AD
0.8 V
0.8 V
t
RHDX
t
AVDV
2.4V
2.4 V
0.8 V
2.4 V
0.8 V
t
RLCH
t
CLRH
A
0.8V
t
AVRL
t
RHAX
t
RLDV
t
RLRH
RD
2.4 V
0.8 V
0.8 V
t
RLBL
t
BHAV
2.4 V
BUFC
36
MB89630R Series
(7) Bus Write Timing
Parameter
(VCC = 5.0 V±10%, FCH = 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name Condition
Unit Remarks
Min.
Max.
Valid address → ALE ↓ time tAVLL
1/4 tinst*1 – 64 ns*2
—
µs
AD7 to AD0,
ALE
A15 to A08
ALE ↓ time → address loss
tLLAX
5
—
ns
time
Valid address → WR ↓ time tAVWL
WR, ALE
WR
1/4 tinst*1 – 60 ns*2
1/2 tinst*1 – 20 ns*2
1/2 tinst*1 – 60 ns*2
1/4 tinst*1 – 40 ns*2
1/4 tinst*1 – 40 ns*2
1/4 tinst*1 – 40 ns*2
1/4 tinst*1 – 40 ns*2
0
—
—
—
—
—
—
—
—
—
—
µs
µs
µs
µs
µs
µs
µs
ns
µs
µs
WR pulse width
tWLWH
tDVWH
tWHAX
tWHDX
tWHLH
tWLCH
tCLWH
tLHLL
AD7 to AD0, WR
Write data → WR ↑ time
WR ↑ → address loss time
WR ↑ → data hold time
WR ↑ → ALE ↑ time
WR ↓ → CLK ↑ time
CLK ↓ → WR ↑ time
ALE pulse width
WR, A15 to A08
—
AD7 to AD0, WR
WR, ALE
WR, CLK
ALE
1/4 tinst*1 – 35 ns*2
1/4 tinst*1 – 30 ns*2
ALE ↓ → CLK ↑ time
tLLCH
ALE,CLK
*1: For information on tinst, see “(4) Instruction Cycle.”
*2: This characteristics are also applicable to the bus read timing.
2.4 V
CLK
ALE
AD
A
0.8 V
tLHLL
tLLCH
tWHLH
2.4 V
0.8 V
0.8 V
tAVLL
tLLAX
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
tDVWH
tWHDX
2.4 V
tCLWH
2.4 V
0.8 V
tWLCH
0.8 V
tWHAX
tAVWL
tWLWH
WR
2.4 V
0.8V
37
MB89630R Series
(8) Ready Input Timing
(VCC = 5.0 V±10%, FCH = 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name Condition
Unit Remarks
Parameter
Min.
60
Max.
—
RDY valid → CLK ↑ time
CLK ↑ → RDY loss time
tYVCH
tCHYX
ns
ns
*
*
RDY, CLK
—
0
—
* : This characteristics are also applicable to the read cycle.
CLK
2.4 V
2.4 V
ALE
AD
Address
Data
A
WR
tYVCH tCHYX
RDY
tYVCH
tCHYX
Note: The bus cycle is also extended in the read cycle in the same manner.
38
MB89630R Series
(9) Serial I/O Timing
(VCC = 5.0 V±10%, FCH = 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min.
Max.
SCK1, UCK1,
UCK2
Serial clock cycle time
tSCYC
2 tinst*
—
µs
SCK1 ↓ → SO1 time
UCK1 ↓ → UO1 time
UCK2 ↓ → UO2 time
SCK1, SO1
UCK1, UO1
UCK2, UO2
tSLOV
–200
200
—
ns
µs
µs
Internal
shift clock
mode
Valid SI1 → SCK1 ↑
Valid UI1 → UCK1 ↑
Valid UI2 → UCK2 ↑
SI1, SCK1
UI1, UCK1
UI2, UCK2
tIVSH
1/2 tinst*
1/2 tinst*
SCK1 ↑ → valid SI1 hold time
UCK1 ↑ → valid UI1 hold time tSHIX
UCK2 ↑ → valid UI2 hold time
SCK1, SI1
UCK1, UI1
UCK2, UI2
—
SCK1, UCK1,
UCK2
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
tSLSH
1 tinst*
1 tinst*
—
—
µs
µs
SCK1, UCK1,
UCK2
SCK1 ↓ → SO1 time
UCK1 ↓ → UO1 time
UCK2 ↓ → UO2 time
SCK1, SO1
UCK1, UO1
UCK2, UO2
tSLOV
External
shift clock
mode
0
200
—
ns
µs
µs
Valid SI1 → SCK1 ↑
Valid UI1 → UCK1 ↑
Valid UI2 → UCK2 ↑
SI1, SCK1
UI1, UCK1
UI2, UCK2
tIVSH
1/2 tinst*
1/2 tinst*
SCK1 ↓ → valid SI1 hold time
UCK1 ↓ → valid UI1 hold time tSHIX
UCK2 ↓ → valid UI2 hold time
SCK1, SI1
UCK1, UI1
UCK2, UI2
—
* : For information on tinst, see “(4) Instruction Cycle.”
39
MB89630R Series
• Internal shift clock mode
tSCYC
SCK1
UCK1
UCK2
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
SO1
UO1
UO2
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SI1
UI1
UI
• External shift clock mode
tSHSL
tSLSH
0.8 VCC
0.8 VCC
SCK1
UCK1
UCK2
0.2 VCC
0.2 VCC
tSLOV
2.4 V
0.8 V
SO1
UO1
UO2
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
SI1
UI1
UI
0.2 VCC
40
MB89630R Series
(10) Peripheral Input Timing
Parameter
(VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
tILIH1
Pin name
PWC, INT0 to INT3,EC
ADST
Unit
Remarks
Min.
2 tinst*
2 tinst*
28 tinst*
28 tinst*
28 tinst*
28 tinst*
Max.
—
Peripheral input “H” pulse width 1
Peripheral input “L” pulse width 1
Peripheral input “H” pulse width 2
Peripheral input “L” pulse width 2
Peripheral input “H” pulse width 3
Peripheral input “L” pulse width 3
µs
µs
tIHIL1
tILIH2
tIHIL2
tILIH3
tIHIL3
—
—
µs A/D mode
µs A/D mode
µs Sense mode
µs Sense mode
—
—
ADST
—
* : For information on tinst, see “(4) Instruction Cycle.”
tIHIL1
tILIH1
PWC,
EC,
INT0 to INT3
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tIHIL2
tILIH2
(tIHIL3)
(tILIH3)
ADST
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
41
MB89630R Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = 3.5 V to 6.0 V, FCH = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Typ.
—
Pin
name
Parameter
Resolution
Symbol
Unit Remarks
Min.
—
Max.
10
bit
Linearity error
—
—
±2.0
±1.5
±3.0
LSB
LSB
—
—
Differential linearity error
Total error
—
—
—
—
LSB
At AVCC = VCC
AVSS – 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB
Zero transition voltage
VOT
mV
mV
AN0 to
AN7
Full-scale transition
voltage
AVR – 3.5 LSB AVR – 1.5 LSB AVR + 0.5 LSB
VFST
Interchannel disparity
—
—
—
4
LSB
—
—
At 10 MHz
µs
A/D mode conversion time
13.2
—
oscillation
Analog port input current
Analog input voltage
Reference voltage
IAIN
—
—
—
—
10
µA
V
AN0 to
AN7
0.0
0.0
AVR
AVCC
—
V
—
Reference voltage
supply current
IR
—
200
µA AVR = 5.0 V
42
MB89630R Series
6. A/D Converter Glossary
• Resolution
Analog changes that are identifiable with the A/D converter
• Linearity error
The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with
the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics
• Differential linearity error
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error (unit: LSB)
The difference between theoretical and actual conversion values caused by the zero transition error, full-scale
transition error, linearity error, quantization error, and noise
Theoretical I/O characteristics
Total error
3FF
3FE
3FD
3FF
3FE
3FD
VFST
Actual conversion
value
1.5 LSB
{1 LSB × N + 0.5 LSB}
004
003
002
001
004
003
002
001
VNT
VOT
Actual conversion
value
1 LSB
Theoretical value
0.5 LSB
AVR
AVR
AVSS
AVSS
Analog input
Analog input
VFST – VOT
VNT – {1 LSB × N + 0.5 LSB}
Digital output N total error =
1 LSB =
(V)
1022
1 LSB
(Continued)
43
MB89630R Series
(Continued)
Zero transition error
Full-scale transition error
004
Theoretical value
Actual conversion
value
3FF
3FE
3FD
3FC
Actual conversion
value
003
002
VFST
(Actual
measurement)
Actual conversion
value
001
Actual conversion value
VOT (Actual measurement)
Analog input
AVR
AVSS
Analog input
Differential linearity error
Theoretical value
Linearity error
3FF
3FE
3FD
Actual conversion
N + 1
value
Actual conversion
value
{1 LSB × N + VOT}
V(N + 1)T
VFST
(Actual
N
V
NT
measurement)
004
003
002
001
N – 1
N – 2
VNT
Actual conversion value
Theoretical value
Actual conversion value
VOT (Actual measurement)
AVR
– 1
AVSS
AVR
AVSS
Analog input
Analog input
VNT – {1 LSB × N + VOT}
V(N + 1)T – VNT
Digital output N differential linearity error =
Digital output N linearity error =
1 LSB
1 LSB
44
MB89630R Series
7. Notes on Using A/D Converter
• Input impedance of the analog input pins
The output impedance of the external circuit for the analog input must satisfy the followingconditions.
If the output impedance of the external circuit is too high, an analog voltage sampling time might beinsufficient
(sampling time = 6 µs at 10MHz oscillation.) Therefore, it is recommended to keep the output impedance of the
external circuit below 10 kΩ .
• Analog input circuit model
Analog input
C0
Converter
RON1
RON2
C1
RON1: Approx. 1.5 kΩ
RON2: Approx. 1.5 kΩ
C0: Approx. 60 pF
C1: Approx. 4 pF
Note: The values mentioned here should be used as a guideline.
• Error
The smaller the | AVR–AVss |, the greater the error would become relatively.
45
MB89630R Series
■ CHARACTERISTICS EXAMPLE
(2) “H” Level Output Voltage
(1) “L” Level Output Voltage
VOL vs. IOL
VCC - VOH vs. IOH
VCC - VOH (V)
1.0
VOL (V)
VCC = 3.0 V
VCC = 4.0 V
TA = +25°C
TA = +25°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VCC = 2.5 V
VCC = 3.0 V
0.5
0.4
0.3
0.2
0.1
VCC = 5.0 V
VCC = 6.0 V
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.0
–0.5 –1.0 –1.5 –2.0 –2.5 –3.0
IOH (mA)
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
(3) “H” Level Input Voltage/“L” Level Input
Voltage (CMOS Input)
(4) “H” Level Input Voltage/“L” Level Input
Voltage (Hysteresis Input)
VIN vs. VCC
VIN (V)
5.0
TA = +25°C
VIN vs. VCC
VIN (V)
4.5
VIHS
5.0
4.0
TA = +25°C
4.5
3.5
3.0
2.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VILS
2.0
1.5
1.0
0.5
0.0
0
1
2
3
4
5
6
7
VCC (V)
VIHS: Threshold as the input voltage in hysteresis
characteristics is set to “H” level
0
1
2
3
4
5
6
7
VCC (V)
VILS: Threshold as the input voltage in hysteresis
characteristics is set to “L” level
46
MB89630R Series
(5) Power Supply Current (External Clock)
ICC1 vs. VCC, ICC2 vs. VCC
ICC (mA)
16
ICCS1 vs. VCC, ICCS2 vs. VCC
ICCS (mA)
5.0
FCH = 10MHz
TA = +25°C
FCH = 10MHz
14
4.5
4.0
TA = +25°C
12
Divide by 4
(ICC1)
3.5
3.0
10
8
Divide by 4
(ICCS1)
2.5
2.0
6
4
2
0
Divide by 8
Divide by 8
1.5
1.0
Divide by 16
Divide by 64
(ICCS2)
Divide by 16
0.5
0
Divide by 64
(ICC2)
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VCC (V)
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VCC (V)
ICCL vs. VCC
ICCLS vs. VCC
ICCL (µA)
ICCLS (µA)
200
50
TA = +25°C
TA = +25°C
45
40
180
160
140
120
35
30
100
80
25
20
60
40
15
10
20
0
5
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VCC (V)
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VCC (V)
(Continued)
47
MB89630R Series
(Continued)
I CCT vs. V CC
I CCH vs. V CC
I CCT (µA)
I CCH (µA)
20
18
16
2.0
TA = +25°C
TA = +25°C
1.8
1.6
14
12
1.4
1.2
10
8
1.0
0.8
6
4
0.6
0.4
2
0
0.2
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
V CC (V)
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
V CC (V)
(6) Pull-up Resistance
R PULL vs. V CC
R PULL (kΩ)
1000
TA = +25°C
100
10
1
2
3
4
5
6
V CC (V)
48
MB89630R Series
■ INSTRUCTIONS (136 INSTRUCTIONS)
Execution instructions can be divided into the following four groups:
• Transfer
• Arithmetic operation
• Branch
• Others
Table 1 lists symbols used for notation of instructions.
Table 1 Instruction Symbols
Symbol
dir
Meaning
Direct address (8 bits)
off
Offset (8 bits)
ext
#vct
#d8
#d16
dir: b
rel
Extended address (16 bits)
Vector table number (3 bits)
Immediate data (8 bits)
Immediate data (16 bits)
Bit direct address (8:3 bits)
Branch relative address (8 bits)
Register indirect (Example: @A, @IX, @EP)
@
A
AH
AL
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of accumulator A (8 bits)
Lower 8 bits of accumulator A (8 bits)
T
TH
TL
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of temporary accumulator T (8 bits)
Lower 8 bits of temporary accumulator T (8 bits)
Index register IX (16 bits)
IX
EP
PC
SP
PS
dr
CCR
RP
Ri
Extra pointer EP (16 bits)
Program counter PC (16 bits)
Stack pointer SP (16 bits)
Program status PS (16 bits)
Accumulator A or index register IX (16 bits)
Condition code register CCR (8 bits)
Register bank pointer RP (5 bits)
General-purpose register Ri (8 bits, i = 0 to 7)
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
×
Indicates that the contents of × is the target of accessing.
( × )
(( × ))
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic: Assembler notation of an instruction
~:
#:
The number of instructions
The number of bytes
Operation: Operation of an instruction
TL, TH, AH:
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH prior to the instruction executed.
• 00 becomes 00.
N, Z, V, C:
OP code:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
49
MB89630R Series
Table 2 Transfer Instructions (48 instructions)
Mnemonic
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
~
#
Operation
TL
TH AH NZVC OP code
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
(dir) ← (A)
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
45
46
61
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
47
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
48 to 4F
04
05
06
60
92
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
07
(A) ← (Ri)
(dir) ← d8
08 to 0F
85
86
87
88 to 8F
D5
( (IX) +off ) ← d8
( (EP) ) ← d8
–
–
–
–
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
–
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
D4
D7
E3
E4
C5
C6
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)
(A) ← (EP)
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
+ + + +
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
(EP) ← d16
(IX) ← (A)
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
SETB dir: b
CLRB dir: b
XCH A,T
A8 to AF
A0 to A7
42
AL
AL
–
–
–
–
AH
–
–
–
XCHW A,T
43
F7
F6
F5
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
–
–
F0
Note: During byte transfer to A, T ← A is restricted to low bytes.
Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
50
MB89630R Series
Table 3 Arithmetic Operation Instructions (62 instructions)
Mnemonic
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
~
#
Operation
(A) ← (A) + (Ri) + C
TL
TH AH NZVC OP code
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + –
– – – –
– – – –
+ + – –
+ + + –
– – – –
– – – –
+ + – –
– – – –
– – – –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + – +
28 to 2F
24
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
–
D2
D0
01
11
63
73
53
12
dH
dH
00
dH
dH
dH
–
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) (T)
(A) ← (A) (T)
(A) ← (A) (T)
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
(TL) − (AL)
(T) − (A)
–
–
13
03
→
→
C
A
A
←
←
C
ROLC A
2
1
–
–
–
+ + – +
02
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
14
15
17
16
(A) − (Ri)
18 to 1F
84
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
DAS
XOR A
94
52
54
55
57
56
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
58 to 5F
62
AND A,#d8
AND A,dir
64
65
(A) ← (AL) (dir)
(Continued)
51
MB89630R Series
(Continued)
Mnemonic
~
#
Operation
(A) ← (AL) ( (EP) )
TL
TH AH NZVC OP code
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + + +
+ + + +
– – – –
– – – –
67
66
68 to 6F
72
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(dir) – d8
74
75
77
76
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
78 to 7F
95
97
96
98 to 9F
C1
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
DECW SP
D1
Table 4 Branch Instructions (17 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V N = 1 then PC ← PC + rel
If V N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– + – –
– + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
Restore
FD
FC
F9
F8
FB
FA
FF
FE
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
RETI
–
Table 5 Other Instructions (9 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – R
– – – S
– – – –
– – – –
40
50
41
51
00
81
91
80
90
CLRI
SETI
52
MB89630R Series
■ INSTRUCTION MAP
53
MB89630R Series
■ MASK OPTIONS
MB89635R
MB89636R
MB89637R
MB89PV630
MB89T635R
MB89T637R
MB89P637
MB89W637
Part number
No.
Specifywhen
ordering
Set with EPROM
programmer
Specifying procedure
Setting not possible
masking
Pull-up resistors
P00 to P07, P10 to P17,
P30 to P37, P40 to P43,
P50 to P53, P72 to P74
Selectable by
pin
Fixed to “without pull-up
resistor”
1
Can be set per pin*
Setting possible
Power-on reset selection
2
3
With power-on reset
Selectable
Fixed to “with power-on reset”
Without power-on reset
Selection of the main clock
oscillation stabilization time
(at 10 MHz)
Approx. 218/FCH (Approx. 26.2 ms)
Approx. 217/FCH (Approx. 13.1 ms)
Approx. 214/FCH (Approx. 1.6 ms)
Approx. 24/FCH (Approx. 0 ms)
FCH : Main clock frequency
Fixed to 218/FCH
(Approx. 26.2 ms)
Selectable
Setting possible
Reset pin output
Reset output provided
No reset output
4
5
Selectable
Selectable
Setting possible
Setting possible
Fixed to “with reset output”
MB89PV630-101 Single-clock system
MB89T635R-101 Single-clock system
MB89T637R-101 Single-clock system
Single/dual-clock system option
Single clock
Dual clock
MB89PV630-102 Dual-clock systems
MB89T635R-102 Dual-clock systems
MB89T637R-102 Dual-clock systems
* : Pull-up resistors cannot be set for P50 to P53.
54
MB89630R Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB89635RP-SH
MB89T635RP-SH
MB89636RP-SH
MB89637RP-SH
MB89P637P-SH
MB89T637RP-SH
64-pin Plastic SH-DIP
(DIP-64P-M01)
MB89635RPF
MB89T635RPF
MB89636RPF
MB89637RPF
MB89P637PF
MB89T637RPF
64-pin Plastic QFP
(FPT-64P-M06)
MB89635RPFM
MB89636RPFM
MB89637RPFM
MB89T635PFM
64-pin Plastic QFP
(FPT-64P-M09)
64-pin Ceramic SH-DIP
(DIP-64C-A06)
MB89W637C-SH
MB89PV630CF
MB89PV630C-SH
64-pin Ceramic MQFP
(MQP-64C-P01)
64-pin Ceramic MDIP
(MDP-64C-P02)
55
MB89630R Series
■ PACKAGE DIMENSIONS
64-pin Plastic SH-DIP
(DIP-64P-M01)
58.00+–00..5252
2.283–+..002028
INDEX-1
INDEX-2
17.00±0.25
(.669±.010)
5.65(.222)MAX
3.00(.118)MIN
0.25±0.05
(.010±.002)
1.00+–00.50
.039+–0.020
0.45±0.10
(.018±.004)
0.51(.020)MIN
19.05(.750)
TYP
15°MAX
1.778±0.18
(.070±.007)
1.778(.070)
MAX
55.118(2.170)REF
C
1994 FUJITSU LIMITED D64001S-3C-4
Dimensions in mm (inches)
64-pin Plastic QFP
(FPT-64P-M06)
24.70±0.40(.972±.016)
20.00±0.20(.787±.008)
3.35(.132)MAX
(Mounting height)
0.05(.002)MIN
(STAND OFF)
51
33
52
32
14.00±0.20 18.70±0.40
(.551±.008) (.736±.016)
12.00(.472)
REF
16.30±0.40
(.642±.016)
INDEX
64
20
"A"
1
19
LEAD No.
0.15±0.05(.006±.002)
Details of "B" part
1.00(.0394)
TYP
0.40±0.10
(.016±.004)
M
0.20(.008)
Details of "A" part
0.25(.010)
"B"
0.30(.012)
0.18(.007)MAX
0.63(.025)MAX
0.10(.004)
18.00(.709)REF
22.30±0.40(.878±.016)
0
10°
1.20±0.20
(.047±.008)
Dimensions in mm (inches)
C
1994 FUJITSU LIMITED F64013S-3C-2
56
MB89630R Series
64-pin Plastic QFP
(FPT-64P-M09)
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
+0.20
48
33
32
1.50–0.10
(Mounting height)
.059+–..000048
49
9.75
(.384)
REF
13.00
(.512)
NOM
1 PIN INDEX
64
17
M
1
16
Details of "A" part
0.10±0.10
LEAD No.
"A"
+0.05
0.65(.0256)TYP
0.30±0.10
(.012±.004)
0.127–0.02
0.13(.005)
+.002
(STAND OFF)
.005–.001
(.004±.004)
0.50±0.20
(.020±.008)
0.10(.004)
0
10°
C
Dimensions in mm (inches)
1994 FUJITSU LIMITED F64018S-1C-2
64-pin Ceramic SH-DIP
(DIP-64C-A06)
56.90±0.56
(2.240±.022)
8.89(.350) DIA
TYP
R1.27(.050)
REF
18.75±0.25
(.738±.010)
INDEX AREA
1.27±0.25
(.050±.010)
5.84(.230)MAX
0.25±0.05
(.010±.004)
3.40±0.36
(.134±.014)
1.778±0.180
(.070±.007)
0.90±0.10
(.0355±.0040)
0.46–+00..0183
.018+–..000035
19.05±0.25
(.750±.010)
0°~9°
1.45(.057)
MAX
55.118(2.170)REF
C
Dimensions in mm (inches)
1994 FUJITSU LIMITED D64006SC-1-2
57
MB89630R Series
64-pin Ceramic MQFP
(MQP-64C-P01)
18.70(.736)TYP
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
12.00(.472)TYP
INDEX AREA
1.00±0.25
(.039±.010)
1.20–+00..2400
.047–+..000186
1.00±0.25
(.039±.010)
1.27±0.13
(.050±.005)
18.12±0.20
(.713±.008)
22.30±0.33
(.878±.013)
12.02(.473)
TYP
18.00(.709)
TYP
10.16(.400)
14.22(.560)
TYP
0.30(.012)
TYP
24.70(.972)
TYP
TYP
0.40±0.10
(.016±.004)
1.27±0.13
(.050±.005)
0.30(.012)TYP
7.62(.300)TYP
9.48(.373)TYP
11.68(.460)TYP
0.40±0.10
(.016±.004)
1.20–+00..2400
.047–+..000186
10.82(.426)
MAX
0.15±0.05
(.006±.002)
0.50(.020)TYP
C
Dimensions in mm (inches)
1994 FUJITSU LIMITED M64004SC-1-3
64-pin Ceramic MDIP
(MDP-64C-P02)
0°~9°
56.90±0.64
(2.240±.025)
15.24(.600)
TYP
18.75±0.30
(.738±.012)
19.05±0.30
(.750±.012)
INDEX AREA
2.54±0.25
(.100±.010)
0.25±0.05
(.010±.002)
33.02(1.300)REF
1.27±0.25
(.050±.010)
10.16(.400)MAX
0.46–+00..0183
0.90±0.13
(.035±.005)
3.43±0.38
(.135±.015)
1.778±0.25
(.070±.010)
.018+–..000035
55.12(2.170)REF
Dimensions in mm (inches)
C
1994 FUJITSU LIMITED M64002SC-1-4
58
MB89630R Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F9609
FUJITSU LIMITED Printed in Japan
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