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ML610Q172 [ETC]

The low power micro controller corresponding to 5v for household appliances;
ML610Q172
型号： ML610Q172
厂家： ETC    ETC
描述：

The low power micro controller corresponding to 5v for household appliances
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FEDL610Q172-01  
Issue Date: Oct 25, 2013  
ML610Q172/ML610Q173  
The low power micro controller corresponding to 5v for household appliances  
I
GENERAL DESCRIPTION  
This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as 10-bit  
A/D converter, timer, PWM, synchronous serial port, UART, I2C bus interface (master), Battery level detect  
circuit, LCD driver, are incorporated around 8-bit CPU nX-U8/100.  
The CPU nX-U8/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe  
line architecture parallel procesing.  
The on-chip debug function that is installed enables program debugging and programming.  
FEATURES  
• CPU  
− 8-bit RISC CPU (CPU name: nX-U8/100)  
− Instruction system:16-bit instructions  
− Instruction set:Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit  
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic  
shift, and so on  
− On-Chip debug function  
− Minimum instruction execution time  
Approx 30.5 μs (at 32.768kHz system clock)  
Approx 0.122 μs (at 8.192MHz system clock)＠VDD = 2.2 to 5.5V  
• Internal memory  
− Internal 128-Kbyte flash ROM(64K × 16-bit) (including unusable 1KByte TEST area)  
− Internal 2-Kbyte Data Flash (1-Kbyte × 2)  
− Internal 4-Kbyte RAM (4096 × 8 -bit)  
• Interrupt controller  
− 1 non-maskable interrupt sources (Internal source: 1, External source: 1)  
− 24 maskable interrupt sources (Internal source: 20, External source: 4)：ML610Q172  
− 26 maskable interrupt sources (Internal source: 22, External source: 4)：ML610Q173  
• Time base counter  
− Low-speed time base counter × 1 channel  
− High-speed time base counter × 1 channel  
• Watchdog timer  
− Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second  
− Free running  
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)  
• Timers  
− 8 bits × 6ch (16-bit configuration available)  
1/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
• PWM  
− Resolution 16 bits × 3 channel(IGBT control)  
• Synchronous serial port  
− 2ch  
− Master/slave selectable  
− LSB first/MSB first selectable  
− 8-bit length/16-bit length selectable  
• UART  
− Half-duplex  
− TXD/RXD × 2 channels  
− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits  
− Positive logic/negative logic selectable  
− Built-in baud rate generator  
• I2C bus interface  
− Master function only  
− Fast mode (400kbit/s@8MHz), Standard mode (100kbit/s@8MHz)  
• Successive approximation type A/D converter  
− 10-bit A/D converter  
− Input: 12ch （Maximum）：ML610Q172  
− Input: 8ch （Maximum）：ML610Q173  
− Conversion time: 12.75μs per channel  
•
Analog Comparator（ML610Q173 only）  
− 2ch  
− Interrupt allow edge selection and sampling selection  
• General-purpose ports ×45（Maximum）  
− Input-only port × 6ch  
− Output-only port × 2ch (including secondary functions)  
− Input/output × 15ch (including secondary functions)  
− Input/output × 22ch (including LCD driver functions)  
• LCD driver  
− 96 dots max. (24 seg × 4 com), 1/1 to 1/4 duty  
− Frame frequency selectable (approx. 64Hz, 73Hz, 85Hz, 102Hz, 32Hz, 128Hz, 171Hz, and 256Hz)  
− LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable  
− LCD drive voltage generation：external or internal selectable  
•
Power supply voltage detect function  
− Judgment voltages:  
One of 4 levels  
− Judgment accuracy: ±2% (Typ.)  
• Reset  
− Reset through the RESET_N pin  
− Reset by the watchdog timer (WDT) overflow  
• Clock  
− Low-speed clock (This LSI can not guarantee the operation withoug low-speed clock)  
Crystal oscillation (32.768 kHz) or Built-in RC oscillation (32.7kHz)  
− High-speed clock  
Built-in oscillation (8.192MHz/8MHz), Crystal/Ceramic oscillation (8MHz), external clock  
2/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
• Power management  
− HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).  
− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral  
circuits are stopped.)  
− Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the  
oscillation clock)  
− Block control function: Operation of an intact functional block circuit is powerd down. (register reset and clock  
stop)  
• Shipment  
− 64-pin QFP (QFP64-P-1414-0.80)  
− ML610Q172-xxxGA (blank product: ML610Q172-NNNGA)  
− ML610Q173-xxxGA (blank product: ML610Q173-NNNGA)  
xxx: ROM code number  
• Guaranteed operating range  
− Operating temperature: −40°C to 85°C  
− Operating voltage: VDD = 2.2V to 5.5V, VREF = 4.5V to 5.5V  
ML610Q174 exists as 80 pin versions of this LSI. The difference between ML610Q174 / ML610Q172 / ML610Q173 is  
shown below. Refer to "ML610Q174 user's manual" for the details of ML610Q174.  
The difference between ML610Q174 / ML610Q172 / ML610Q173  
Function  
ML610Q174  
80PinQFP  
12ch  
ML610Q172  
64PinQFP  
12ch  
ML610Q173  
64PinQFP  
8ch  
Shipment  
Successive approximation type  
A/D converter  
Analog Comparator  
maskable interrupt  
LCD driver  
レ（2ch）  
―
24*1  
レ（2ch）  
26  
26  
32seg x 4com  
24seg x 4com  
24seg x 4com  
Output-only port  
P22,P23 pins  
P90,P91 pins  
Input/output port  
P34,P35 pins  
P50,P51 pins  
P42,P43 pins  
P52,P53 pins  
6
2
2
レ
レ
―
―
―
―
19  
レ
レ
レ
レ
15  
レ
15  
―
―
レ
レ
―
―
レ
Input/output port  
（including LCD driver functions）  
30  
22  
22  
PC0～PC7 pins  
レ
―
―
レ：exists、－：nothing  
*1：Analog Comparator interrupt：The difference of two factors  
3/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
BLOCK DIAGRAM  
Block diagram of the ML610Q172.  
Symbols with an asterisk “*” indicate that each of them is the secondary or tertiary function of the corresponding port.  
CPU (nX-U8/100) Large Model  
EPSW1～3  
ELR1～3  
LR  
ECSR1～3  
DSR/CSR  
PC  
GREG  
0～15  
PSW  
EA  
Timing  
Controller  
ALU  
SP  
Program  
Memory  
（Flash）  
BUS  
Controller  
Instruction  
Decoder  
Instruction  
Register  
On-Chip  
ICE  
128Kbyte  
VDD  
VSS  
INT  
2
Data-bus  
SCK0*1, SCK1*1  
SIN0*1, SIN1*1  
SSIO  
RESET_N  
TEST0  
SOUT0*, SOUT1*11  
RESET &  
TEST  
INT  
2
RAM  
4096byte  
TEST1_N  
RXD0*1, RXD1*1  
TXD0*1, TXD1*1  
UART  
INT  
1
INT  
1
Interrupt  
Controller  
XT0  
XT1  
SDA*1  
SCL*1  
I2C  
OSC  
OSC0*  
OSC1*  
INT  
4
INT  
3
PWM4*1  
PWM5*1  
PWM6*1  
PW45EV0  
PW45EV1  
TBC  
LSCLK*  
OUTCLK*  
PWM  
INT  
6
8bit Timer  
VDDL  
POWER  
×6  
PW6EV0  
PW6EV1  
INT  
VDD  
VSS  
INT  
4
INT  
1
P00 to P03  
P10 to P11  
P20 to P21  
P30 to P35*3  
P36  
WDT  
BLD  
VREF  
10bit-ADC  
AIN0 to AIN11＊3  
GPIO  
P40 to P41  
P44 to P47*3  
P50 to P51*3  
P80 to P85*2  
PD0 to PD7*2  
PF0 to PF7*2  
*1 Secondary or tertiary function  
*2 Select I/O port or LCD driver  
COM0 to COM3*2  
LCD  
Driver  
*3 Select I/O port or A/D converter input  
SEG0 to SEG7  
SEG16 to SEG23*2  
SEG32 to SEG39*2  
LCD  
Bias  
VL1, VL2, VL3  
4/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
Block diagram of the ML610Q173.  
Symbols with an asterisk “*” indicate that each of them is the secondary or tertiary function of the corresponding port.  
CPU (nX-U8/100) Large Model  
EPSW1～3  
ELR1～3  
LR  
ECSR1～3  
DSR/CSR  
PC  
GREG  
0～15  
PSW  
EA  
Timing  
Controller  
ALU  
SP  
Program  
Memory  
（Flash）  
BUS  
Controller  
Instruction  
Decoder  
Instruction  
Register  
On-Chip  
ICE  
128Kbyte  
VDD  
VSS  
INT  
2
Data-bus  
SCK0*1, SCK1*1  
SIN0*1, SIN1*1  
SSIO  
RESET_N  
TEST0  
SOUT0*, SOUT1*11  
RESET &  
TEST  
INT  
2
RAM  
4096byte  
TEST1_N  
RXD0*1, RXD1*1  
TXD0*1, TXD1*1  
UART  
INT  
1
INT  
1
Interrupt  
Controller  
XT0  
XT1  
SDA*1  
SCL*1  
I2C  
OSC  
OSC0*  
OSC1*  
INT  
4
INT  
3
PWM4*1  
PWM5*1  
PWM6*1  
PW45EV0  
PW45EV1  
TBC  
LSCLK*  
OUTCLK*  
PWM  
INT  
6
8bit Timer  
VDDL  
POWER  
×6  
PW6EV0  
PW6EV1  
INT  
VDD  
VSS  
INT  
4
INT  
1
P00 to P03  
P10 to P11  
P20 to P23  
P30 to P33*3  
P36  
WDT  
BLD  
VREF  
10bit-ADC  
AIN0 to AIN7＊3  
GPIO  
P40 to P43  
INT  
2
P44 to P47*3  
CMP0P＊4  
CMP0M＊4  
P52 to P53  
CMP  
P80 to P85*2  
CMP1P＊4  
PD0 to PD7*2  
PF0 to PF7*2  
CMP1M＊4  
*1 Secondary or tertiary function  
*2 Select I/O port or LCD driver  
COM0 to COM3*2  
LCD  
Driver  
*3 Select I/O port or A/D converter input  
SEG0 to SEG7  
SEG16 to SEG23*2  
SEG32 to SEG39*2  
*4 Select I/O port or Analog comparator input  
LCD  
Bias  
VL1, VL2, VL3  
5/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
PIN CONFIGURATION  
ML610Q172 QFP package product  
48pin  
33pin  
49pin  
32pin  
PF0/SEG32/SIN0  
PF1/SEG33/SCK0  
49  
50  
51  
52  
53  
54  
55  
P80/COM0  
P81/COM1  
P82/COM2  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
PF2/SEG34/ RXD0/SOUT0  
PF3/SEG35/TXD0/PWM4/TXD1  
PF4/SEG36/SIN1/PWM4  
P83/COM3  
P84/VL1  
P85/VL2  
VL3  
PF5/SEG37/SCK1/PWM5  
PF6/SEG38/RXD1/SOUT1/PWM6  
PF7/SEG39/TXD1/TXD0  
56  
57  
P36/LSCLK  
RESET_N  
XT1  
TEST0  
TEST1_N  
58  
59  
60  
61  
62  
63  
64  
P00/EXI0/PW45EV0  
P01/EXI1/PW6EV0  
P02/EXI2/RXD0  
XT0  
VDDL  
VDD  
P03/EXI3/RXD1  
VSS  
P20/LED0/LSCLK/PWM4  
P21/LED1/OUTCLK/PWM5  
P11/OSC1  
P10/OSC0  
64pin  
17pin  
16pin  
1pin  
6/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
ML610Q173 QFP package product  
48pin  
33pin  
49pin  
32pin  
PF0/SEG32/SIN0  
PF1/SEG33/SCK0  
49  
50  
51  
52  
53  
54  
55  
P80/COM0  
P81/COM1  
P82/COM2  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
PF2/SEG34/ RXD0/SOUT0  
PF3/SEG35/TXD0/PWM4/TXD1  
PF4/SEG36/SIN1/PWM4  
P83/COM3  
P84/VL1  
P85/VL2  
VL3  
PF5/SEG37/SCK1/PWM5  
PF6/SEG38/RXD1/SOUT1/PWM6  
PF7/SEG39/TXD1/TXD0  
56  
57  
P36/LSCLK  
RESET_N  
XT1  
TEST0  
TEST1_N  
58  
59  
60  
61  
62  
63  
64  
P00/EXI0/PW45EV0  
P01/EXI1/PW6EV0  
P02/EXI2/RXD0  
XT0  
VDDL  
VDD  
P03/EXI3/RXD1  
VSS  
P20/LED0/LSCLK/PWM4  
P21/LED1/OUTCLK/PWM5  
P11/OSC1  
P10/OSC0  
64pin  
17pin  
16pin  
1pin  
7/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
LIST OF PINS  
ML610Q172 / ML610Q173  
Primary function  
Secondary function  
Tertiary function  
Pin  
Pin  
No.  
Pin  
Pin  
I/O  
Description  
I/O  
Description  
I/O  
Description  
name  
name  
name  
Negative power supply pin  
Positive power supply pin  
1,19  
20  
Vss  
VDD  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Power supply for internal logic  
(internally generated)  
21  
VDDL  
Power supply pin for LCD bias  
Input/output pin for testing  
Input/output pin for testing  
Reset input pin  
26  
57  
58  
24  
22  
23  
VL3  
TEST0  
TEST1_N  
RESET_N  
XT0  
⎯
I/O  
I/O  
I
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Low-speed clock oscillation pin  
Low-speed clock oscillation pin  
I
XT1  
O
Reference power supply pin of  
Successive-approximation type  
ADC  
VREF  
I
16  
59  
60  
61  
62  
⎯
⎯
⎯
⎯
⎯
⎯
Input port /  
P00/EXI0/  
PW45EV0  
I
I
I
I
External interrupt /  
PW45EV0 input  
Input port /  
External interrupt/  
PW6EV0 input  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
P01/EXI1/  
PW6EV0  
Input port /  
P02/EXI2/  
RXD0  
External interrupt  
UART0 data input  
Input port /  
External interrupt /  
UART1 data input  
P03/EXI3/  
RXD1  
High-speed clock  
oscillation pin  
High-speed clock  
oscillation pin  
Low-speed clock  
output  
P10  
P11  
I
Input port  
17  
18  
63  
64  
OSC0  
OSC1  
I
⎯
⎯
⎯
O
⎯
I
Input port  
O
O
O
⎯
⎯
P20/  
LED0  
O
O
Output port / LED drive  
Output port / LED drive  
LSCLK  
OUTCLK  
PWM4  
PWM5  
PWM4 output  
PWM5 output  
Low-speed clock  
output  
P21/  
LED1  
O
Input/output port /  
PW45EV1 input /  
Successive approximation type  
ADC input  
Input/output port /  
PW6EV1 input /  
Successive approximation type  
ADC input  
P30/  
PW45EV1  
/AIN0  
I/O  
I/O  
⎯
⎯
⎯
15  
⎯
⎯
⎯
⎯
P31/  
PW6EV1  
AIN1  
⎯
⎯
⎯
⎯
⎯
⎯
14  
13  
⎯
⎯
⎯
⎯
Input/output port /  
P32/  
AIN2  
I/O Successive approximation type  
ADC input  
Input/output port /  
I/O Successive approximation type  
ADC input  
⎯
⎯
P33/  
AIN3  
⎯
⎯
⎯
⎯
⎯
⎯
12  
25  
⎯
⎯
Low-speed  
clock output  
P36  
I/O Input/output port  
LSCLK  
O
Input/output port /  
Timer0 /  
I/O PWM4 external clock input/  
Successive approximation type  
ADC input  
Input/output port/  
Timer1 /  
I/O PWM5 external clock input/  
Successive approximation type  
ADC input  
P44/  
T0P4CK/  
AIN4  
SSIO0 data  
input  
SIN0  
I
11  
10  
⎯
⎯
⎯
⎯
⎯
⎯
SSIO0  
synchronous  
clock  
P45/  
T1P5CK/  
AIN5  
SCK0  
I/O  
input/output  
8/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
ML610Q172 / ML610Q173  
Secondary function  
Primary function  
Tertiary function  
Fourthly function  
Pin  
No.  
Pin  
Pin  
Pin  
Pin  
I/O  
Description  
I/O  
Description  
I/O Description  
I/O Description  
name  
name  
name  
name  
P80/  
COM0  
P81/  
COM1  
P82/  
COM2  
P83/  
COM3  
Input/output port /  
LCD common pin  
Input/output port /  
LCD common pin  
Input/output port /  
LCD common pin  
Input/output port /  
LCD common pin  
Input/output port /  
I/O  
I/O  
I/O  
I/O  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
32  
31  
30  
29  
⎯
⎯
⎯
⎯
⎯
⎯
P84/  
VL1  
I/O Power supply pin  
for LCD bias  
Input/output port/  
I/O Power supply pin  
for LCD bias  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
28  
27  
P85/  
VL2  
SEG0  
SEG1  
SEG2  
SEG3  
SEG4  
SEG5  
SEG6  
SEG7  
O
O
O
O
O
O
O
O
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
33  
34  
35  
36  
37  
38  
39  
40  
PD0 /  
SEG16  
PD1 /  
SEG17  
PD2 /  
SEG18  
PD3 /  
SEG19  
PD4 /  
SEG20  
PD5 /  
SEG21  
PD6 /  
SEG22  
PD7 /  
SEG23  
Input/output port /  
LCD segment pin  
Input/output port /  
LCD segment pin  
Input/output port /  
LCD segment pin  
Input/output port /  
LCD segment pin  
Input/output port /  
LCD segment pin  
Input/output port /  
LCD segment pin  
Input/output port /  
LCD segment pin  
Input/output port /  
LCD segment pin  
Input/output port /  
LCD segment pin  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
I
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
41  
42  
43  
44  
45  
46  
47  
48  
49  
⎯
⎯
⎯
⎯
⎯
⎯
PF0 /  
SEG32  
SSIO0 data  
input  
SIN0  
SSIO0  
PF1 /  
SEG33  
Input/output port /  
LCD segment pin  
synchronou  
s clock  
I/O  
SCK0  
I/O  
⎯
⎯
⎯
⎯
⎯
⎯
50  
input/output  
SSIO0 data  
output  
PWM4  
output  
SSIO1 data  
input  
SSIO1  
synchronou  
s clock  
PF2 /  
SEG34  
PF3 /  
SEG35  
PF4 /  
Input/output port /  
LCD segment pin  
Input/output port /  
LCD segment pin  
Input/output port /  
LCD segment pin  
UART0  
data input  
UART0  
I/O  
I/O  
I/O  
RXD0  
TXD0  
⎯
I
SOUT0  
PWM4  
SIN1  
O
O
I
⎯
⎯
O
O
⎯
51  
52  
53  
UAR1  
data output  
PWM4  
O
⎯
TXD1  
PWM4  
data output  
⎯
⎯
SEG36  
output  
PF5 /  
SEG37  
Input/output port /  
LCD segment pin  
PWM5  
output  
I/O  
SCK1  
I/O  
PWM5  
O
⎯
⎯
54  
input/output  
SSIO1 data  
output  
PF6 /  
SEG38  
PF7 /  
Input/output port /  
LCD segment pin  
Input/output port /  
LCD segment pin  
UART1  
data input  
UART1  
PWM6  
output  
UAR0  
I/O  
I/O  
RXD1  
TXD1  
I
SOUT1  
O
PWM6  
TXD0  
O
O
55  
56  
O
⎯
⎯
⎯
SEG39  
data input  
data output  
9/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
ML610Q172  
Primary function  
Secondary function  
Tertiary function  
Fourthly function  
Pin  
No.  
Pin  
Pin  
Pin  
Pin  
I/O  
Description  
I/O  
Description  
I/O Description  
I/O Description  
name  
name  
name  
name  
I2C data  
input/output  
I2C clock  
P40  
P41  
I/O Input/output port  
I/O Input/output port  
SDA  
SCL  
⎯
I/O  
I/O  
⎯
⎯
⎯
⎯
⎯
O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
2
3
4
5
6
7
⎯
⎯
⎯
⎯
⎯
input/output  
P34/  
AIN11  
P35/  
AIN10  
P51/  
AIN9  
P50/  
AIN8  
Input/output port /  
I/O  
PWM4  
output  
PWM5  
output  
ADC input *1  
⎯
⎯
⎯
⎯
PWM4  
PWM5  
⎯
Input/output port /  
I/O  
ADC input *1  
⎯
⎯
O
Input/output port /  
I/O  
⎯
⎯
ADC input *1  
⎯
⎯
⎯
⎯
Input/output port /  
I/O  
⎯
⎯
⎯
ADC input *1  
Input/output port /  
Timer9,B external  
P47/  
T9BCK/  
AIN7  
PWM5  
output  
8
9
I
PWM5  
O
O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
clock input /  
ADC input *1  
Input/output port /  
Timer8,A /  
P46/  
T8AP6CK/  
AIN6  
SSIO0 data  
output  
I
PWM6  
external  
SOUT0  
clock input /  
ADC input *1  
*1：Successive approximation type ADC input  
ML610Q173  
Primary function  
Secondary function  
Tertiary function  
Fourthly function  
Pin  
No.  
Pin  
Pin  
Pin  
Pin  
I/O  
Description  
I/O  
I/O  
Description  
I/O Description  
I/O Description  
name  
name  
name  
name  
I2C data  
input/output  
SSIO0 data  
input  
P40  
P41  
I/O Input/output port  
SDA  
SCL  
SIN0  
I
⎯
⎯
⎯
⎯
⎯
⎯
2
3
SSIO0  
I2C clock  
input/output  
synchronou  
s clock  
I/O Input/output port  
I/O  
SCK0  
I/O  
⎯
input/output  
UART0  
data input  
UART0  
SSIO0 data  
output  
PWM4  
output  
P42  
P43  
I/O Input/output port  
I/O Input/output port  
RXD0  
TXD0  
I
SOUT0  
PWM4  
O
⎯
⎯
4
5
UAR1  
data output  
O
O
TXD1  
O
data output  
Input/output port /  
I/O Comparator1  
non-inverting input  
Input/output port /  
I/O Comparator0  
non-inverting input  
Input/output port /  
Timer9,B external  
P53/  
CMP1P  
UART1  
data input  
PWM6  
O
UAR0  
data output  
TXD1  
RXD1  
O
I
PWM6  
TXD0  
O
6
7
output  
P52/  
CMP0P  
UART1  
data input  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
P47/  
T9BCK/  
AIN7/  
clock input /  
PWM5  
output  
I
PWM5  
O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ADC input *1  
/
8
9
CMP1M  
Comparator1  
inverting input  
Input/output port /  
Timer8,A /  
P46/  
T8AP6CK/  
AIN6/  
PWM6  
external  
SSIO0 data  
output  
I
clock input /  
⎯
SOUT0  
O
ADC input *1  
/
CMP0M  
Comparator0  
inverting input  
*1：Successive approximation type ADC input  
10/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
PIN DESCRIPTION  
Primary/  
Logic  
Pin name  
I/O  
Description  
Secondary  
Power supply  
Negative power supply pin  
Positive power supply pin  
VSS  
VDD  
—
—
—
—
—
—
Positive power supply pin for internal logic (internally generated). Connect  
capacitors (CL) (see Measuring Circuit 1) between this pin and VSS  
VDDL  
VL1  
—
—
—
—
—
—
.
Power supply pins for LCD bias (external input). This function is allocated  
to the primary function of the P84 pin.  
Power supply pins for LCD bias (external input). This function is allocated  
to the primary function of the P85 pin.  
VL2  
—
—
—
—
—
—
Power supply pins for LCD bias (external input)  
VL3  
Test  
TEST0  
Input/output pin for testing. This pin has a pull-down resistor built in.  
Input/output pin for testing. This pin has a pull-up resistor built in.  
I/O  
I/O  
—
—
Positive  
TEST1_N  
System  
Negative  
Reset input pin. When this pin is set to a “L” level, the device is placed in  
system reset mode and the internal circuit is initialized. If after that this pin  
is set to a “H” level, program execution starts. This pin has a pull-up  
resistor built in.  
RESET_N  
I
I
—
—
Negative  
—
Crystal connection pin for low-speed clock. A 32.768 kHz crystal oscillator  
(see measuring circuit 1) is connected to this pin. Capacitors CDL and CGL  
are connected across this pin and VSS as required.  
Crystal/ceramic connection pin for high-speed clock.  
A 8MHz crystal or ceramic is connected to this pin. Capacitors CDH and  
XT0  
XT1  
O
I
—
—
—
—
—
OSC0  
OSC1  
O
O
—
—
CGH (see measuring circuit 1) are connected across this pin and VSS  
.
Low-speed clock output. This function is allocated to the secondary function  
of the P20/P36 pin.  
LSCLK  
Secondary  
Secondary  
High-speed clock output. This function is allocated to the secondary  
function of the P21 pin.  
OUTCLK  
O
—
General-purpose input port  
P00 to P03  
P10 to P11  
I
I
General-purpose input ports. Provided with a secondary function for each  
port. Cannot be used as ports if their secondary functions are used.  
Primary  
Primary  
Positive  
Positive  
General-output input port  
General-purpose output ports.Provided with a secondary function for each  
port. Cannot be used as ports if their secondary functions are used.  
P20 to P21  
O
General-purpose input/output port（ML610Q172）  
P30 to P36  
General-purpose input/output ports.Provided with a secondary  
function for each port. Cannot be used as ports if their secondary  
functions are used.  
P40 to P41, P44 to P47  
P50 to P51  
I/O  
Primary  
Positive  
P80 to P85  
PD0 to PD7  
General-purpose input/output ports.Provided with a LCD segment  
for each port. Cannot be used as ports if LCD segment are used.  
PF0 to PF7  
General-purpose input/output port（ML610Q173）  
P30 to P33, P36  
General-purpose input/output ports.Provided with a secondary  
function for each port. Cannot be used as ports if their secondary  
functions are used.  
P40 to P47  
P52 to P53  
P80 to P85  
PD0 to PD7  
PF0 to PF7  
I/O  
Primary  
Positive  
General-purpose input/output ports.Provided with a LCD segment  
for each port. Cannot be used as ports if LCD segment are used.  
11/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
Primary/  
Logic  
Pin name  
I/O  
Description  
Secondary  
UART（ML610Q172）  
Secondary  
Fourthly  
UART0 data output pin. Allocated to the secondary function of the PF3 pins  
and the fourthly function of the PF7 pins.  
TXD0  
RXD0  
TXD1  
RXD1  
O
I
Positive  
UART0 data input pin. Allocated to the primary function of the P02 pin and  
the secondary function of the PF2 pins.  
Secondary Positive  
Secondary  
Positive  
UART1 data output pin. Allocated to the secondary function of the PF7 pins  
and the fourthly function of the PF3 pins.  
O
I
Fourthly  
UART1 data input pin. Allocated to the primary function of the P03 pin and  
the secondary function of the PF6 pins.  
Secondary Positive  
UART（ML610Q173）  
Secondary  
Positive  
UART0 data output pin. Allocated to the secondary function of the P43 and  
PF3 pins and the fourthly function of the P53 and PF7 pins.  
TXD0  
RXD0  
TXD1  
O
I
Fourthly  
UART0 data input pin. Allocated to the primary function of the P02 pin and  
the secondary function of the P42 and PF2 pins.  
Secondary Positive  
Secondary  
Positive  
UART1 data output pin. Allocated to the secondary function of the P53 and  
PF7 pins and the fourthly function of the P43 and PF3 pins.  
O
I
Fourthly  
UART1 data input pin. Allocated to the primary function of the P03 pin and  
the secondary function of the P52 and PF6 pins.  
RXD1  
Secondary Positive  
I2C bus interface  
I2C data input/output pin. This pin is used as the secondary function of the  
P40 pin. This pin has an NMOS open drain output. When using this pin as a  
function of the I2C, externally connect a pull-up resistor.  
I2C clock output pin. This pin is used as the secondary function of the P41  
pin. This pin has an NMOS open drain output. When using this pin as a  
function of the I2C, externally connect a pull-up resistor.  
SDA  
SCL  
I/O  
I/O  
Secondary Positive  
Secondary Positive  
Synchronous serial (SSIO)  
Synchronous serial data input pin.  
ML610Q172：Allocated to the tertiary function of the P44 and PF0 pins.  
SIN0  
I
Tertiary  
Tertiary  
Tertiary  
Positive  
—
ML610Q173：Allocated to the tertiary function of the P40 and P44 and PF0  
pins.  
Synchronous serial clock input/output pin.  
ML610Q172：Allocated to the tertiary function of the P45 and PF1 pins.  
SCK0  
SOUT0  
I/O  
O
ML610Q173：Allocated to the tertiary function of the P41 and P45 and PF1  
pins.  
Synchronous serial data output pin.  
ML610Q172：Allocated to the tertiary function of the P46 and PF2 pins.  
Positive  
ML610Q173：Allocated to the tertiary function of the P42 and P46 and PF2  
pins.  
Synchronous serial data input pin. Allocated to the tertiary function of the  
PF4 pins.  
SIN1  
I
Tertiary  
Tertiary  
Tertiary  
Positive  
—
Synchronous serial clock input/output pin. Allocated to the tertiary function  
of the PF5 pins.  
SCK1  
SOUT1  
I/O  
O
Synchronous serial data output pin. Allocated to the tertiary function of the  
PF6 pins.  
Positive  
12/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
Primary/  
Logic  
Pin name  
I/O  
Description  
Secondary  
PWM（ML610Q172）  
PWM4 output pin. Allocated to the tertiary function of the P34 and P20 and  
PF3 and PF4 pins.  
PWM4  
O
Tertiary  
Positive  
PWM5 output pin. Allocated to the tertiary function of the P35 and P47 and  
P21 and PF5 pins.  
PWM5  
PWM6  
T0P4CK  
O
O
I
Tertiary  
Tertiary  
Primary  
Positive  
Positive  
—
PWM6 output pin. Allocated to the tertiary function of the PF6 pins.  
External clock input pin for timer 0 and PWM4. Allocated to the primary  
function of the P44 pin.  
External clock input pin for timer 1 and PWM5. Allocated to the primary  
function of the P45 pin.  
T1P5CK  
I
I
Primary  
Primary  
—
—
External clock input pin for timer 8 and timer A and PWM6. Allocated to the  
primary function of the P46 pin.  
T8AP6CK  
PW45EV0  
PW45EV1  
PW6EV0  
PW6EV1  
Control start /stop pin for PWM4 and PWM5. Allocated to the primary  
function of the P00 and P30 pins.  
I
I
Primary  
Primary  
—
—
Control start /stop pin for PWM6. Allocated to the primary function of the  
P01 and P31 pins.  
PWM（ML610Q173）  
PWM4 output pin. Allocated to the tertiary function of the P43 and P20 and  
PF3 and PF4 pins.  
Positive  
PWM4  
O
Tertiary  
PWM5 output pin. Allocated to the tertiary function of the P47 and P21 and  
PF5 pins.  
Positive  
Positive  
—
PWM5  
PWM6  
T0P4CK  
O
O
I
Tertiary  
Tertiary  
Primary  
PWM6 output pin. Allocated to the tertiary function of the P53 and PF6 pins.  
External clock input pin for timer 0 and PWM4. Allocated to the primary  
function of the P44 pin.  
External clock input pin for timer 1 and PWM5. Allocated to the primary  
function of the P45 pin.  
—
—
T1P5CK  
I
I
Primary  
Primary  
External clock input pin for timer 8 and timer A and PWM6. Allocated to the  
primary function of the P46 pin.  
T8AP6CK  
PW45EV0  
PW45EV1  
PW6EV0  
PW6EV1  
Control start /stop pin for PWM4 and PWM5. Allocated to the primary  
function of the P00 and P30 pins.  
—
—
I
I
Primary  
Primary  
Control start /stop pin for PWM6. Allocated to the primary function of the  
P01 and P31 pins.  
13/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
Primary/  
Logic  
Pin name  
I/O  
Description  
Secondary  
External interrupt  
EXI0–EXI3  
External maskable interrupt input pins. It is possible, for each bit, to specify  
whether the interrupt is enabled and select the interrupt edge by software.  
Allocated to the primary function of the P00–P03 pins.  
Positive/  
Negative  
Primary  
I
Timer  
External clock input pin for timer 0 and PWM4. Allocated to the primary  
function of the P44 pin.  
T0P4CK  
I
I
I
I
Primary  
Primary  
Primary  
Primary  
—
—
—
—
External clock input pin for timer 1 and PWM5. Allocated to the primary  
function of the P45 pin.  
T1P5CK  
External clock input pin for timer 8 and timer A and PWM6. Allocated to the  
primary function of the P46 pin.  
T8AP6CK  
External clock input pin for timer 9 and timer B. Allocated to the primary  
function of the P47 pin.  
T9BCK  
LED drive  
Positive/  
Negative  
Pins for LED driving. Allocated to the primary function of the P20–P21 pins.  
LED0-LED1  
O
Primary  
Successive-approximation type A/D converter（ML610Q172）  
Reference power supply pin for successive approximation type A/D  
converter.  
VREF  
I
—
—
—
—
Analog inputs to Ch0–Ch11 of the successive-approximation type A/D  
converter. Allocated to the secondary function of the P30 to P35 and P44 to  
P47 and P50 to P51 pins.  
AIN0–AIN11  
I
Successive-approximation type A/D converter（ML610Q173）  
Reference power supply pin for successive approximation type A/D  
converter.  
VREF  
I
—
—
—
—
Analog inputs to Ch0–Ch7 of the successive-approximation type A/D  
converter. Allocated to the secondary function of the P30 to P33 and P44 to  
P47 pins.  
AIN0–AIN7  
I
Analog Comparator（ML610Q173）  
Non-inverting input for comparator0. This pin is used as the primary  
function of the P52 pin.  
CMP0P  
CMP0M  
CMP1P  
CMP1M  
I
I
I
I
—
—
—
—
—
—
—
—
Inverting input for comparator0. This pin is used as the primary function of  
the P46 pin.  
Non-inverting input for comparator1. This pin is used as the primary  
function of the P53 pin.  
Inverting input for comparator1. This pin is used as the primary function of  
the P47 pin.  
LCD driver  
LCD common output pins.  
LCD segment output pins.  
COM0 to COM3  
SEG0 to SEG7  
O
O
—
—
—
—
SEG16 to SEG23  
SEG32 to SEG39  
LCD segment output pins. Allocated to the secondary function of the  
PD0 to PD7 and PF0 to PF7 pins.  
O
—
—
14/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
TERMINATION OF UNUSED PINS  
How to Terminate Unused Pins  
Pin  
Product  
Recommended pin termination  
*1  
RESET_N  
TEST0  
TEST1_N  
VREF  
VL3  
P00 to P03  
P10 to P11  
P20 to P21  
P30 to P33 （AIN0 to AIN3）  
P34 to P35 （AIN11, AIN10）  
P36  
P40 to P41  
P42 to P43  
P44 to P47 （AIN4 to AIN7）  
P50 to P51 （AIN8 to AIN9）  
P52 to P53  
―
open  
open  
open  
*1  
―
*1  
―
*1  
―
Connect to VDD  
open  
Connect VDD or VSS  
Connect VDD or VSS  
open  
*1  
―
*1  
―
*1  
―
*1  
―
*1  
―
open  
open  
open  
open  
open  
open  
open  
open  
open  
open  
open  
open  
ML610Q172  
―
*1  
*1  
―
ML610Q173  
―
*1  
ML610Q172  
ML610Q173  
―
*1  
P80 to P85  
*1  
SEG0 to SEG7  
PD0 to PD7 （SEG16 to 23）  
PF0 to PF7 （SEG32 to 39）  
―
*1  
―
*1  
―
*1：ML610Q172、ML610Q173 common  
Note:  
For unused input ports or unused input/output ports, if the corresponding pins are configured as high-impedance inputs  
and left open, the supply current may become excessively large. Therefore, it is recommended to configure those pins as  
either inputs with a pull-down resistor/pull-up resistor or outputs.  
15/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
ELECTRICAL CHARACTERISTICS  
Absolute Maximum Ratings  
(VSS = 0V)  
Parameter  
Symbol  
Condition  
Rating  
Unit  
Power supply voltage 1  
Power supply voltage 2  
Power supply voltage 3  
Power supply voltage 4  
Power supply voltage 5  
Reference voltage  
VDD  
VDDL  
VL1  
Ta = 25°C  
Ta = 25°C  
Ta = 25°C  
Ta = 25°C  
Ta = 25°C  
Ta = 25°C  
Ta = 25°C  
Ta = 25°C  
−0.3 to +7.0  
−0.3 to +3.6  
−0.3 to +2.33  
−0.3 to +4.66  
−0.3 to +7.0  
V
V
V
V
V
V
V
V
V
VL2  
VL3  
VREF  
VAI  
−0.3 to VDD+0.3  
−0.3 to VDD+0.3  
−0.3 to VDD+0.3  
−0.3 to VDD+0.3  
Analog input voltage  
Input voltage  
VIN  
Output voltage  
VOUT  
Ta = 25°C  
Port3,4,5,8,D,F  
Ta = 25°C  
Output current 1  
IOUT1  
−12 to +11  
mA  
Output current 2  
IOUT2  
PD  
Port2 Ta = 25°C  
−12 to +20  
1
mA  
W
Power dissipation  
Storage temperature  
Ta = 25°C  
TSTG  
―
−55 to +150  
°C  
Recommended Operating Conditions  
(VSS  
=
0V)  
Parameter  
Operating temperature  
Operating voltage  
Symbol  
TOP  
Condition  
Range  
Unit  
°C  
V
―
―
―
−40 to +85  
2.2 to 5.5  
4.5 to VDD  
VDD  
Reference voltage  
VREF  
V
Analog input voltage  
VAI  
fOP  
fXTL  
CV  
―
VSS to VREF  
30k to 8.4M  
32.768k  
10±30%  
1±30%  
V
Operating frequency (CPU)  
Low-speed crystal oscillation frequency  
Capacitor externally connected to VDD pin  
Capacitor externally connected to Vref pin  
―
―
―
Hz  
Hz  
μF  
μF  
CAV  
―
Use 32.768KHz Crystal  
Oscillator DT-26  
(DAISHINKU CORP.)  
CDL  
CGL  
12 to 25  
12 to 25  
Low-speed crystal oscillation  
external capacitor  
pF  
Hz  
High-speed crystal/ceramic oscillation  
frequency  
fXTH  
―
8M / 8.192M  
CDH  
CGH  
―
―
47±30%  
47±30%  
High-speed crystal oscillation  
external capacitor*  
pF  
Capacitor externally connected to VDDL pin  
CL  
―
10±30%  
μF  
* CGH and CDH are built into, external capacity is unnecessary for CSTLS8M00G56 (made by Murata Mfg.).  
16/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
Flash Memory Operating Conditions  
(VSS = 0V)  
Parameter  
Operating temperature  
Operating voltage  
Symbol  
TOP  
Condition  
Data flash memory, At write/erase  
Flash ROM, At write/erase  
At write/erase  
Range  
-40 to +85  
0 to +40  
2.2 to 5.5  
6000  
Unit  
°C  
VDD  
CEPD  
CEPP  
YDR  
V
Data flash memory  
Flash ROM  
Maximum rewrite count  
Data retention period  
times  
years  
100  
10  
―
Parameter  
Symbol  
TBERASE  
TSERASE  
TWRITE  
Condition  
Min.  
―
Typ. Max.  
Unit  
ms  
μs  
Block erase time  
Sector erase time  
1 word write time  
―
―
―
―
―
―
100  
100  
40  
―
―
*1: At the writing of a flash ROM, it is necessary to supply voltage to VDDL pin within the limits of the above-mentioned  
regulation. Pulldown resistance is built in the VPP pin.  
DC Characteristics (1 of 7)  
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)  
Measuring  
circuit  
Parameter  
Symbol  
TXTH  
Condition  
Min.  
Typ.  
2
Max.  
20  
Unit  
ms  
s
High-speed crystal oscillation  
start time  
―
―
―
Low-speed crystal oscillation  
TXTL  
―
0.6  
2
start time*1  
Typ  
-5%  
Typ  
+5%  
Low-speed RC oscillator  
frequency  
fLCR  
Ta= -10 to 60°C  
32.7k  
8.192  
Hz  
1
LSCLK=32.768kHz  
1000 clock average  
Typ  
-1%  
Typ  
+1%  
PLL oscillation frequency  
fPLL  
MHz  
Reset pulse width  
Reset noise rejection pulse  
width  
PRST  
―
100  
―
―
―
μs  
PNRST  
―
―
0.4  
*1: Use 32.768KHz Crystal Oscillator DT-26 (Daishinku) with capacitance CGL/CDL＝12pF.  
Reset  
VIL1  
VIL1  
PRST  
RESET_N  
Reset by RESET_N pin  
17/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
DC Characteristics (2 of 7)  
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)  
Meas  
Parameter  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit uring  
circuit  
LD3 to 0 = 0H  
2.35  
2.80  
3.70  
4.60  
LD3 to 0 = 3H  
LD3 to 0 = 9H  
LD3 to 0 = FH  
Typ.  
-2%  
Typ.  
+2%  
BLD threshold  
voltage  
Ta = 25°C  
VBLD  
V
1
DC Characteristics (3 of 7)  
( ML610Q173 only )  
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)  
Meas  
Parameter  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit uring  
circuit  
CMPnM  
VIN  
VDD  
-1.4  
―
0
―
―
5
Common mode  
Input voltage  
V
CMPnP  
VIN  
―
0
VDD  
100  
1
1
Input offset voltage  
Response time  
―
―
―
―
VCMPOF  
TCMP  
mV  
CMPnP = CMPnM ± 100mV  
CMP0,CMP1 operating  
―
30  
μS  
μA  
Supply current  
（Operating）  
―
ICMP  
DC Characteristics (4 of 7)  
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)  
Meas  
Parameter  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit uring  
circuit  
Typ.  
-5%  
Typ.  
+5%  
Typ.  
Ta = -10 to +70℃  
Ta = -10 to +70℃  
RLH  
RLL  
200  
20  
LCD built-in division  
resistance  
kΩ  
1
Typ.  
-20%  
+20%  
DC Characteristics (5 of 7)  
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)  
Meas  
Parameter  
Symbol  
IDD1  
Condition  
Min. Typ. Max. Unit uring  
circuit  
CPU: In STOP state  
-40 to +35℃  
-40 to +85℃  
-40 to +35℃  
-40 to +85℃  
―
―
―
―
0.7  
0.7  
2.0  
2.0  
6
22  
7
Low-speed/high-speed  
oscillation: Stopped  
Supply current 1  
VDD=3.0V  
CPU: In HALT state  
(LTBC,WBC: Operating*2)  
High-speed oscillation: Stopped  
μA  
Supply current 2  
IDD2  
1
24  
VDD=3.0V  
CPU: Running at 32kHz*1  
High-speed oscillation: Stopped  
VDD=3.0V  
-40 to +35℃  
-40 to +85℃  
―
―
13  
13  
20  
42  
Supply current 3  
Supply current 4  
IDD3  
IDD4  
CPU: Running at 8MHz Crystal/ceramic oscillating  
mode*2  
VDD=5.0V  
―
5
8
mA  
*1: Case when the CPU operating rate is 100% (with no HALT state)  
*2 : Significant bits of BLKCON0 to BLKCON7 registers are all “1”.  
18/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
DC Characteristics (6 of 7)  
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)  
Measuring  
circuit  
Parameter  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit  
Output voltage 1  
(P20 to P21)  
(P30 to P36)  
(P40 to P47)  
(P50 to P53)  
(P80 to P85)  
(PD0 to PD7)  
(PF0 to PF7)  
Output voltage 2  
(P20–P21)  
VDD  
−0.5  
VOH1  
VOL1  
IOH1 = −0.5mA  
―
―
―
0.5  
IOL1 = +0.5mA  
―
V
2
IOL2 = +10mA  
VDD ≥ 4.5V  
When LED drive  
mode is selected  
When I2C mode is  
selected  
VOL2  
VOL3  
―
―
―
―
0.5  
0.4  
Output voltage 3  
(P40–P41)  
IOL3 = +3mA  
Output leakage  
current  
VOH = VDD  
(in high-impedance state)  
IOOH  
IOOL  
―
―
―
1
(P20 to P21)  
(P30 to P36)  
(P40 to P47)  
(P50 to P53)  
(P80 to P85)  
(PD0 to PD7)  
(PF0 to PF7)  
μA  
3
VOL = VSS  
(in high-impedance state)  
−1  
―
VL3=3V、VOL=0.3V  
VL3=5V、VOL=0.5V  
VL3=3V、VOH=2.7V  
VL3=5V、VOH=4.5V  
VL3=3V、VOL=0.3V  
VL3=5V、VOL=0.5V  
VL3=3V、VOH=2.7V  
VL3=5V、VOH=4.5V  
VIH1 = VDD  
15  
100  
―
―
15  
70  
―
―
0
40  
200  
-30  
-90  
30  
―
―
IOL1  
IOH1  
IOL2  
IOH2  
Output current 1  
COM0 to COM3  
-15  
-45  
―
μA  
3
Output current 2  
SEG0 to SEG7  
SEG16 to SEG23  
SEG32 to SEG39  
150  
-13  
-40  
―
―
-6  
-20  
1
Input current 1  
(RESET_N)  
(TEST1_N)  
IIH1  
IIL1  
VIL1 = VSS  
−1500 −300  
−20  
Input current 2  
(P00 to P03)  
(P10 to P11)  
(P30 to P36)  
(P40 to P47)  
(P50 to P53)  
(P80 to P85)  
(PD0 to PD7)  
(PF0 to PF7)  
Input current 3  
(TEST0)  
IIH2  
IIL2  
VIH2 = VDD (when pulled down)  
2
30  
−30  
―
250  
VIL2 = VSS (when pulled up)  
−250  
―
−2  
μA  
4
VIH2 = VDD  
(in high-impedance state)  
IIH2Z  
1
VIL2 = VSS  
(in high-impedance state)  
IIL2Z  
-1  
―
―
IIH3  
IIL3  
VIH3 = VDD  
VIL3 = VSS  
20  
-1  
300  
1500  
―
―
19/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
DC Characteristics (7 of 7)  
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)  
Measuring  
circuit  
Parameter  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit  
Input voltage 1  
(RESET_N)  
(TEST0)  
0.7×  
VDD  
VIH1  
VIL1  
―
―
VDD  
(TEST1_N)  
(P00 to P03)  
(P10 to P11)  
(P30 to P36)  
(P40 to P47)  
(P50 to P53)  
(P80 to P85)  
(PD0 to PD7)  
V
5
0.3×  
VDD  
―
0
―
(PF0 to PF7)  
Input pin capacitance  
(RESET_N)  
(TEST0)  
(TEST1_N)  
(P00 to P03)  
(P10 to P11)  
(P30 to P36)  
(P40 to P47)  
(P50 to P53)  
(P80 to P85)  
(PD0 to PD7)  
f = 10kHz  
CIN  
Vrms = 50mV  
―
―
10  
pF  
―
Ta = 25°C  
(PF0 to PF7)  
20/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
Measuring Circuits  
Measuring circuit 1  
CGL  
CDL  
XT0  
XT1  
CL3  
CL2  
CL1  
VL3  
VL2  
VL1  
32.768kHz  
crystal  
CGH  
OSC0  
CDH  
OSC1  
8MHz  
crystal  
VDD VREF VDDL  
VSS  
A
CV  
CL  
CGL  
CDL  
CGH  
CDH  
：10μF  
：10μF  
：12pF  
：12pF  
：47pF  
：47pF  
CV  
CL  
CL1,C L2,C L3：0.22μF  
32.768kHz Crystal oscillator  
(DMX-26 DAISHINKU Corp.)  
8MHz Crystal oscillator  
CSTLS8M00G56（MURATA Corp.）  
it has built-in CGH, and CDH  
Measuring circuit 2  
(*2)  
VIH  
V
(*1)  
VIL  
VL1 VL2 VL3  
VSS  
VDD VDDL VREF  
(*1) Input logic circuit to determine the specified measuring conditions.  
(*2) Measured at the specified output pins.  
21/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
Measuring circuit 3  
(*2)  
A
VIH  
(*1)  
VIL  
VDDL VREF  
VSS  
VDD  
(*1) Input logic circuit to determine the specified measuring conditions.  
(*2) Measured at the specified output pins.  
Measuring circuit 4  
(*3)  
A
VSS  
VDD VDDL VREF  
*3: Measured at the specified input pins.  
Measuring circuit 5  
VIH  
(*1)  
VIL  
VSS  
VDD VDDL VREF  
*1: Input logic circuit to determine the specified measuring conditions.  
22/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
AC Characteristics (External Interrupt)  
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)  
Parameter  
External interrupt disable  
period  
Symbol  
TNUL  
Condition  
Interrupt: Enabled (MIE = 1),  
CPU: NOP operation  
Min.  
2.5×  
sysclk  
Typ.  
Max.  
3.5×  
sysclk  
Unit  
―
μs  
P00–P03  
(Rising-edge interrupt)  
tNUL  
tNUL  
tNUL  
P00–P03  
(Falling-edge interrupt)  
P00–P03  
(Both-edge interrupt)  
23/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
AC Characteristics (Synchronous Serial Port)  
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)  
Parameter  
SCK input cycle  
(slave mode)  
Symbol  
tSCYC  
Condition  
Min.  
10  
Typ.  
―
Max.  
―
Unit  
μs  
ns  
High-speed oscillation stopped  
During high-speed oscillation  
500  
―
―
SCK output cycle  
(master mode)  
tSCYC  
tSW  
―
―
SCK(*1)  
―
sec  
High-speed oscillation stopped  
During high-speed oscillation  
4
―
―
SCK(*1)  
―
―
SCK(*1)  
μs  
SCK input pulse width  
(slave mode)  
200  
SCK(*1)  
×0.4  
ns  
SCK output pulse width  
(master mode)  
SOUT output delay time  
(slave mode)  
SOUT output delay time  
(master mode)  
―
―
―
sec  
ns  
tSW  
tSD  
tSD  
×0.5  
×0.6  
―
―
180  
―
―
80  
ns  
SIN input setup time  
(slave mode)  
SIN input hold time  
―
―
50  
50  
―
―
―
―
ns  
ns  
tSS  
tSH  
*1: Clock period selected by SnCK3–0 of the serial port n mode register (SIOnMOD1)  
tSCYC  
tSW  
tSW  
SCKn*  
SOUTn  
SINn*  
tSD  
tSD  
tSS  
tSH  
*: Indicates the secondary function of the corresponding port.  
24/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
AC Characteristics (I2C Bus Interface: Standard Mode 100kHz)  
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)  
Rating  
Parameter  
SCL clock frequency  
Symbol  
Condition  
Unit  
Min.  
0
Typ.  
Max.  
100  
fSCL  
⎯
⎯
⎯
kHz  
SCL hold time  
tHD:STA  
4.0  
⎯
⎯
μs  
(start/restart condition)  
SCL ”L” level time  
SCL ”H” level time  
SCL setup time  
(restart condition)  
SDA hold time  
SDA setup time  
SDA setup time  
(stop condition)  
Bus-free time  
tLOW  
tHIGH  
⎯
⎯
4.7  
4.0  
⎯
⎯
⎯
⎯
μs  
μs  
tSU:STA  
⎯
4.7  
⎯
⎯
μs  
tHD:DAT  
tSU:DAT  
⎯
⎯
0
0.25  
⎯
⎯
⎯
⎯
μs  
μs  
tSU:STO  
tBUF  
⎯
⎯
4.0  
4.7  
⎯
⎯
⎯
⎯
μs  
μs  
AC Characteristics (I2C Bus Interface: Fast Mode 400kHz)  
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)  
Rating  
Parameter  
SCL clock frequency  
Symbol  
Condition  
Unit  
Min.  
0
Typ.  
Max.  
400  
fSCL  
⎯
⎯
⎯
kHz  
SCL hold time  
tHD:STA  
0.6  
⎯
⎯
μs  
(start/restart condition)  
SCL ”L” level time  
SCL ”H” level time  
SCL setup time  
(restart condition)  
SDA hold time  
SDA setup time  
SDA setup time  
(stop condition)  
Bus-free time  
tLOW  
tHIGH  
⎯
⎯
1.3  
0.6  
⎯
⎯
⎯
⎯
μs  
μs  
tSU:STA  
⎯
0.6  
⎯
⎯
μs  
tHD:DAT  
tSU:DAT  
⎯
⎯
0
0.1  
⎯
⎯
⎯
⎯
μs  
μs  
tSU:STO  
tBUF  
⎯
⎯
0.6  
1.3  
⎯
⎯
⎯
⎯
μs  
μs  
Start  
condition  
Restart  
condition  
Stop  
condition  
P40/SDA  
P41/SCL  
tBUF  
tSU:STO  
tHD:STA  
tLOW tHIGH  
tSU:STA tHD:STA  
tSU:DAT tHD:DAT  
25/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
Electrical Characteristics of Successive Approximation Type A/D Converter  
(VDD=4.5 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)  
Parameter  
Resolution  
Symbol  
n
Condition  
―
Min.  
―
Typ.  
―
Max.  
10  
Unit  
bits  
Integral non-linearity error  
Differential non-linearity  
error  
IDL  
2.7V ≤ VREF ≤ 5.5V  
−4  
―
+4  
DNL  
2.7V ≤ VREF ≤ 5.5V  
−3  
―
+3  
LSB  
Zero-scale error  
Full-scale error  
Input impedance  
Reference voltage  
VOFF  
FSE  
RI  
―
―
―
−4  
−4  
―
―
―
―
―
+4  
+4  
5k  
Ω
VREF  
4.5  
VDD  
V
φ/CH  
Conversion time  
HSCLK=3.0M to 8.4MHz  
―
102  
―
tCONV  
φ: Period of high-speed clock (HSCLK)  
VDD  
Reference  
voltage  
VREF  
VDDL  
1μF  
10μF  
A
AIN0  
～
AIN11  
RI≤5kΩ  
0.1μF  
-
10μF  
+
Analog input  
VSS  
26/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
PACKAGE DIMENSIONS  
Notes for Mounting the Surface Mount Type Package  
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.  
Therefore, before you perform reflow mounting, contact LAPIS SEMICONDUCTOR’s responsible sales person for the  
product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature  
and times).  
27/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
REVISION HISTORY  
Page  
Previous  
Document No.  
Date  
Description  
Current  
Edition  
Edition  
FEDL610Q172-01  
Oct 25, 2013  
–
–
Final edition 1  
28/29  
FEDL610Q172-01  
ML610Q172/ML610Q173  
NOTES  
No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS  
Semiconductor Co., Ltd.  
The content specified herein is subject to change for improvement without notice.  
The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter  
"Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be  
obtained from LAPIS Semiconductor upon request.  
Examples of application circuits, circuit constants and any other information contained herein illustrate the  
standard usage and operations of the Products. The peripheral conditions must be taken into account when  
designing circuits for mass production.  
Great care was taken in ensuring the accuracy of the information specified in this document. However, should  
you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall  
bear no responsibility for such damage.  
The technical information specified herein is intended only to show the typical functions of and examples of  
application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any  
license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties.  
LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such  
technical information.  
The Products specified in this document are intended to be used with general-use electronic equipment or  
devices (such as audio visual equipment, office-automation equipment, communication devices, electronic  
appliances and amusement devices).  
The Products specified in this document are not designed to be radiation tolerant.  
While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a  
Product may fail or malfunction for a variety of reasons.  
Please be sure to implement in your equipment using the Products safety measures to guard against the  
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as  
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whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction  
manual.  
The Products are not designed or manufactured to be used with any equipment, device or system which requires  
an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human  
life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace  
machinery, nuclear-reactor controller, fuel-controller or other safety device). LAPIS Semiconductor shall bear  
no responsibility in any way for use of any of the Products for the above special purposes. If a Product is  
intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing.  
If you intend to export or ship overseas any Product or technology specified herein that may be controlled under  
the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the  
Law.  
Copyright 2013 LAPIS Semiconductor Co., Ltd.  
29/29  

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SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

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VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

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VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

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SI9135_11

 SMBus Multi-Output Power-Supply Controller

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SI9136_11

 Multi-Output Power-Supply Controller

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SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

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SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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VISHAY
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