ML610Q340 [ETC]
8-bit Microcontroller with Voice Output Function;
| 型号： | ML610Q340 |
| 厂家： | 
ETC |
| 描述： | 8-bit Microcontroller with Voice Output Function 微控制器 |
| 文件： | 总26页 (文件大小：464K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL610Q340FULL-01
Issue Date: January 7, 2010
ML610Q340/ML610340
8-bit Microcontroller with Voice Output Function
GENERAL DESCRIPTION
Equipped with an LAPIS Semiconductor original 8-bit CPU nX-U8/100, the ML610Q340/ML610340 is a
high-performance 8-bit CMOS microcontroller that integrates a wide variety of peripherals such as a timer,
synchronous serial port, and voice output function. The nX-U8/100 CPU is capable of executing instructions
efficiently on a one-instruction-per-clock-pulse basis through parallel processing by the 3-stage pipelined
architecture. The microcontroller is also equipped with a flash memory that has achieved low voltage and low
power consumption (at read) equivalent to mask ROMs, so it is best suited to battery-driven applications such as
cellular phones. In addition, it has an on-chip debugging function, which allows software debugging/rewriting
with the LSI mounted on the board.
FEATURES
CPU
8-bit RISC CPU (CPU name: nX-U8/100)
Instruction repertoire: 16-bit length instructions
Instruction set: Transfer, arithmetic operations, comparison, logical operations, multiply/divide operations,
bit manipulation, bit logical operations, jump, conditional jump, call return stack manipulation, and
arithmetic shift instructions.
Built-in on-chip debugging function
Minimum instruction execution time:
0.244 s (@ 4.096 MHz system clock)
Internal memory
ML610Q340
Has 96-Kbyte flash memory (48K 16-bit) built in. (including unusable 1KByte TEST area)
ML610340
Has 96-Kbyte mask memory (48K 16-bit) built in. (including unusable 1KByte TEST area)
Has 512-byte RAM (512 8-bit) built in.
Interrupt controller
Non-maskable interrupt: 2 sources (1 internal source and 1 external sources)
Maskable interrupt: 12 sources (8 internal sources and 4 external sources)
Time-base counter
Low-speed side time-base counter 1ch
High-speed side time-base counter 1ch
Watchdog timer
Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second
Free-running
Selectable overflow period: 4 types (125 ms, 500 ms, 2 sec, 8 sec)
Timer
8-bit 2ch (16-bit configuration also enabled)
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Voice output function
Voice synthesis method: 4-bit ADPCM2 / 8-bit non-linear PCM / 8-bit PCM / 16-bit PCM
Sampling frequency: 6.4/8/10.7/12.8/16/21.3/25.6/32 kHz
Speaker amplifier output power
1W(at 5V)
Synchronous serial port
Master/slave selectable
LSB/MSB-first selectable
8-bit/16-bit length selectable
General-purpose port
Input-only port 4ch
Output-only port 4ch (those as secondary functions are also included)
Input-output port 4ch (those as secondary functions are also included)
Reset
Resetting by the RESET_N pin
Resetting upon power-on detection
Resetting upon WDT overflow detection
Clock
Low-speed side clock
Internal frequency division (1/128 of the high-speed side clock)
High-speed side clock
Crystal/ceramic oscillation (4.096 MHz), external clock
Power management
HALT mode: Halts the execution of instructions issued by the CPU (the peripheral circuits continue
operating)
STOP mode: Stops low-speed and high-speed oscillation (the CPU and the peripheral circuits stop
operating)
Clock gear: Allows changing the frequency of the high-speed system clock by software (oscillator clock
divided by 1, 2, 4, or 8)
Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused
peripherals.
Shipment
30-pin SSOP
High-speed side clock ：Crystal/ceramic oscillation (4.096 MHz)
Flash Memory ：ML610Q340-xxxMB (blank product: ML610Q340-NNNMB)
Mask Memory ：ML610340-xxxMB
High-speed side clock ：external clock
Flash Memory ：ML610Q340J-xxxMB (blank product: ML610Q340J-NNNMB)
Mask Memory ：ML610340J-xxxMB
xxx: ROM code number
Guaranteed operating range
Operating temperature: 40C to +85C
Operating voltage: VDD = 2.2 to 5.5 V, SPVDD = 2.3 to 5.5 V
(Be sure to apply the same voltage to all the power supplies.)
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FEDL610Q340FULL-01
ML610Q340/340
BLOCK DIAGRAM
ML610Q340
Figure 1 is a block diagram of the ML610Q340.
Symbols with an asterisk “*” indicate that each of them is the secondary or tertiary function of the corresponding
port.
CPU (nX-U8/100)
EPSW13
ELR13
LR
ECSR13
DSR/CSR
PC
GREG
015
PSW
EA
Timing
Controller
ALU
SP
Program
Memory
(Flash)
BUS
Controller
VPP
Instruction
Decoder
Instruction
Register
On-Chip
ICE
96 Kbytes
Data-bus
VDD
VSS
INT
1
SCK0*
SIN0*
SSIO
RAM
512 bytes
RESET_N
TEST
SOUT0*
RESET &
TEST
Interrupt
Controller
INT
4
OSC0
OSC1
INT
5
OSC
TBC
NMI
P00 to P03
LSCLK*
OUTCLK*
INT
2
8-bit Timer
GPIO
P20 to P23
P40 to P43
2
VDDL
Power
INT
1
WDT
SPVDD
SPVSS
INT
1
SG
SPP
SPM
AOUT
VOICECNT
SPIN
Figure 1 Block Diagram of ML610Q340
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ML610Q340/340
ML610340
Figure 2 is a block diagram of the ML610340.
Symbols with an asterisk “*” indicate that each of them is the secondary or tertiary function of the corresponding
port.
CPU (nX-U8/100)
EPSW13
ELR13
LR
ECSR13
DSR/CSR
PC
GREG
015
PSW
EA
Timing
Controller
ALU
SP
Program
Memory
(Mask)
BUS
Controller
Instruction
Decoder
Instruction
Register
On-Chip
ICE
96 Kbytes
Data-bus
VDD
VSS
INT
1
SCK0*
SIN0*
SSIO
RAM
512 bytes
RESET_N
TEST
SOUT0*
RESET &
TEST
Interrupt
Controller
INT
4
OSC0
OSC1
INT
5
OSC
TBC
NMI
P00 to P03
LSCLK*
OUTCLK*
INT
2
8-bit Timer
GPIO
P20 to P23
P40 to P43
VDDL
2
Power
INT
1
SPVDD
SPVSS
WDT
INT
1
SG
SPP
SPM
VOICECNT
AOUT
SPIN
Figure 2 Block Diagram of ML610340
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PIN CONFIGURATION
ML610Q340 SSOP package product
NC: No Connection
Figure 3 Pin Configuration of ML610Q340 Package Product
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ML610Q340/340
ML610340 SSOP package product
NC: No Connection
Figure 4 Pin Configuration of ML610340 Package Product
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LIST OF PINS
Primary function
Secondary function
Tertiary function
PAD
No
Pin name
I/O
Description
Pin name
I/O
Description
Pin name I/O
Description
Negative power
supply pin
Positive power supply
pin
Power supply for
internal logic
(internally generated)
Negative power
supply pin for built-in
speaker amplifier
Positive power supply
pin for built-in speaker
amplifier
Power supply pin for
flash memory
Input/output pin for
testing
10,22
1
Vss
VDD
4
VDDL
27
SPVSS
26
5
SPVDD
VPP(*)
12
11
TEST
I/O
I
RESET_N
Reset input pin
Connection pin for
high-speed clock
oscillation
2
OSC0
I
Connection pin for
high-speed clock
oscillation
3
OSC1
AOUT
SPIN
O
O
I
P11
I
Input port
24
25
LINE output
Analog input to the
built-in speaker
amplifier
Reference power
supply pin of the
built-in speaker
amplifier
23
SG
O
Positive output pin of
the built-in speaker
amplifier
Negative output pin of
the built-in speaker
amplifier
Input port,
non-maskable
interrupt
30
29
17
SPP
SPM
NMI
O
O
I
Input port / External
interrupt
Input port / External
interrupt
Input port / External
interrupt
Input port / External
interrupt
Output port / LED
drive
Output port / LED
drive
Output port / LED
drive
Output port / LED
drive
16
15
14
13
21
20
19
18
P00/EXI0
P01/EXI1
P02/EXI2
P03/EXI3
P20/LED0
P21/LED1
P22/LED2
P23/LED3
I
I
O
I
I
Low-speed
clock output
high-speed
clock output
O
O
O
O
LSCLK
OUTCLK
O
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ML610Q340/340
Primary function
Secondary function
Tertiary function
PAD
No
Pin name
P40
I/O
Description
Pin name
I/O
Description
Pin name I/O
Description
SSIO0 data
input
9
I/O Input/output port
SIN0
I
SSIO0
synchronous
clock
8
P41
I/O Input/output port
SCK0
I/O
input/output
SSIO0 data
output
7
6
P42
P43
I/O Input/output port
I/O Input/output port
SOUT0
O
*: Applies to the ML610Q340.
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PIN DESCRIPTION
Primary/
Pin name
I/O
Description
Secondary/
Tertiary
Logic
Power supply
VSS
Negative power supply pin
Positive power supply pin
—
—
—
—
—
—
—
—
—
VDD
VDDL
Positive power supply pin for internal logic (internally generated)
Capacitors CL(see measuring circuit 1) are connected between
this pin and VSS
SPVSS
SPVDD
Negative power supply pin for built-in speaker amplifier
—
—
—
—
—
—
—
—
—
Positive power supply pin for built-in speaker amplifier
Power supply pin for flash memory
VPP(*)
Test
TEST
Input/output pin for testing. Has a pull-down resistor built in.
I/O
I
—
—
Positive
System
RESET_N
Reset input pin. When this pin is set to a “L” level, the device is
placed in system reset mode and the internal circuit is initialized.
If after that this pin is set to a “H” level, program execution
starts. This pin has a pull-up resistor built in.
Negative
OSC0
OSC1
Pins for connecting a crystal unit for high speed clock.
Connect a 4.096 MHz crystal unit (see Measuring Circuit 1) to
these pins. Also, connect capacitors (CDH and CGH) between
these pins and VSS as required.
I
—
—
—
—
O
LSCLK
Low-speed clock output. This function is allocated to the
secondary function of the P20 pin.
High-speed clock output. This function is allocated to the
secondary function of the P21 pin.
O
O
Secondary
Secondary
—
—
OUTCLK
General-purpose Input port
P00–P03 General-purpose input ports.
I
Primary
Primary
Positive
Positive
General-purpose Output port
P20–P23
General-purpose output ports.
O
Provided with a secondary function. Cannot be used as ports if
their secondary function is used.
General-purpose Input/output port
P40–P43
General-purpose input/output ports.
I/O
Provided with a secondary function. Cannot be used as ports if
their secondary function is used.
Primary
Positive
*Applies to the ML610Q340.
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Primary/
Pin name
I/O
Description
Secondary/
Tertiary
Logic
Synchronous serial (SSIO)
SIN0
I
Synchronous serial data input pin. Allocated to the tertiary
function of the P40 pin.
Tertiary
Tertiary
Tertiary
Positive
—
SCK0
SOUT0
I/O Synchronous serial clock input/output pin. Allocated to the
tertiary function of the P41 pin.
O
Synchronous serial data output pin. Allocated to the tertiary
function of the P42 pin.
Positive
External interrupt
NMI
Positive/
Negative
I
I
External non-maskable interrupt input pin. The interrupt occurs
on both the rising and falling edges.
External maskable interrupt input pins. It is possible, for each
bit, to specify whether the interrupt is enabled and select the
interrupt edge by software. Allocated to the primary function of
the P00–P03 pins.
Primary
Primary
Positive/
Negative
EXI0–3
LED drive
LED0–3
Primary
—
Positive/
Negative
O
NMOS open drain pins to allow direct driving of LED. Allocated
to the secondary function of the P20–P23 pins.
Voice output function
AOUT
—
O
LINE output pin. When you use built-in speaker amplifier,
connect with the SPIN pin.
—
—
—
—
—
—
—
—
SPIN
SG
SPP
SPM
I
Analog input pin of the internal speaker amplifier.
Reference voltage output pin of the internal speaker amplifier.
Positive output pin of the internal speaker amplifier.
Negative output pin of the internal speaker amplifier.
O
O
O
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ML610Q340/340
TERMINATION OF UNUSED PINS
How to Terminate Unused Pins
Pin
Recommended pin termination
VPP
Open
Open
Open
VSS
RESET_N
TEST
SPVDD
SPVSS
VSS
AOUT
Open
Open
Open
Open
Open
VDD or VSS
Open
Open
SPIN
SG
SPP
SPM
P00–P03
P20–P23
P40–P43
Note:
It is recommended to configure the unused input ports and input/output ports as inputs with pull-down
resistors/pull-up resistors or outputs since the supply current may become excessively large if those pins are left
open in the high impedance input setting.
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(VSS = SPVSS = 0V)
Parameter
Power supply voltage 1
Power supply voltage 2
Power supply voltage 3
Power supply voltage 4
Input voltage
Symbol
VDD
Condition
Ta = 25C
Ta = 25C
Ta = 25C
Ta = 25C
Ta = 25C
Ta = 25C
P4, Ta = 25C
P2, Ta = 25C
Ta = 25C
―
Rating
Unit
V
0.3 to +7.0
0.3 to +7.0
0.3 to +3.6
0.3 to +9.5
0.3 to VDD+0.3
0.3 to VDD+0.3
12 to +11
SPVDD
VDDL
VPP
V
V
V
VIN
V
Output voltage
VOUT
IOUT1
IOUT2
PD
V
Output current 1
mA
mA
mW
C
Output current 2
12 to +20
Power dissipation
Storage temperature
861
TSTG
55 to +150
Recommended Operating Conditions
(VSS = SPVSS = 0V)
Parameter
Symbol
Condition
Range
Unit
Operating temperature
TOP
VDD
―
―
―
―
40 to +85
2.2 to 5.5
C
Operating voltage
V
SPVDD
fOP
2.3 to 5.5
Operating frequency (CPU)
High-speed crystal/ceramic
oscillation frequency
437k to 4.2M
Hz
Hz
fXTH
―
4.0M, 4.096M
High-speed crystal oscillation
external capacitor
CDH
CGH
―
―
15 to 32
15 to 32
pF
F
F
Capacitor externally connected
to VDDL pin
Capacitor externally connected
to SG pin
CL
―
―
1030%
0.130%
CSG
12/26
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ML610Q340/340
Flash Memory Operating Conditions
(VSS = SPVSS = 0V)
Parameter
Symbol
Condition
At write/erase
At write/erase
At write/erase (*1)
At write/erase (*1)
―
Range
Unit
Operating temperature
TOP
VDD
VDDL
VPP
CEP
YDR
0 to +40
2.7 to 3.6
2.5 to 2.75
7.7 to 8.3
80
C
Operating voltage
V
Maximum rewrite count
Data retention period
times
years
―
10
*1: When writing data to, or erasing data from, flash ROM, it is necessary to apply a voltage within the range
specified above to the VDDL pin.
DC Characteristics (1 of 5)
(VDD = SPVDD = 2.2 to 5.5V, VSS = SPVSS = 0V,
Ta = 40 to +85C, unless otherwise specified)
Measuring
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
circuit
High-speed oscillation start
time
TXTH
PRST
―
―
―
―
100
―
2
20
―
ms
Reset pulse width
Reset noise rejection pulse
width
―
―
1
s
PNRST
0.4
Time from power-on reset to
power-up
TPOR
―
―
―
10
ms
Reset
VIL1
VIL1
PRST
RESET_N
Reset by RESET_N pin
0.9VDD
VDD
0.1VDD
TPOR
Power-on reset
13/26
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DC Characteristics (2 of 5)
(VDD = SPVDD = 2.3 to 5.5V, VSS = SPVSS = 0V,
Ta = 40 to +85C, unless otherwise specified)
Measuring
circuit
Parameter
Symbol
Condition
Min.
10
Typ.
Max.
Unit
k
V
LINE amplifier output
load resistance
LINE amplifier output
voltage range
RLA
VAD
At 1/2VDD output
At output load
VDD1/6
0.95
VDD5/6
1.05
SG output voltage
VSG
RSG
RLSP
―
―
―
DVDD/2
96
V
k
V
DD/2
VDD/2
SG output resistance
SPM, SPP output load
resistance
57
8
135
―
―
SPVDD = 3.3V,
f = 1kHz,
1
RSPO = 8,
THD 10%
At SPIN Input
SPVDD = 5.0V,
f = 1kHz,
PSPO1
—
0.5
—
W
Speaker amplifier output
power
RSPO = 8,
THD 10%
At SPIN Input
PSPO2
VOF
—
1
—
W
SPVDD=3.0V,
SPIN – SPM gain
= +6dB
Output offset voltage
between SPM and SPP
with no signal present
50
—
+50
mV
With a load of 8
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DC Characteristics (3 of 5) ML610Q340
(VDD = SPVDD = 2.2 to 5.5V, VSS = SPVSS = 0V,
Ta = 40 to +85C, unless otherwise specified)
Measuring
Min. Typ. Max. Unit
circuit
Parameter
Symbol
IDD1
Condition
CPU: In STOP state.
Low-speed/high-speed
oscillation: stopped
Ta +40C
Ta +85C
―
0.5
2.0
Supply current 1
A
―
0.5
8
VDD =
SPVDD = 3.0V
VDD =
SPVDD = 5.0V
VDD =
CPU: Running at
4.096MHz
―
―
―
1.7
2.2
3
4
4
Supply current 4
Supply current 5
IDD4
IDD5
Crystal/ceramic
oscillating mode *1
1
CPU: Running at
4.096MHz
Crystal/ceramic
oscillating mode *1
During voice playback
(no output load)
mA
12
SPVDD = 3.0V
VDD =
SPVDD = 5.0V
―
8
12
*1: Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera).
DC Characteristics ML610340
(VDD = SPVDD = 2.2 to 5.5V, VSS = SPVSS = 0V,
Ta = 40 to +85C, unless otherwise specified)
Measuring
Min. Typ. Max. Unit
circuit
Parameter
Symbol
IDD1
Condition
CPU: In STOP state.
Low-speed/high-speed
oscillation: stopped
Ta +40C
Ta +85C
―
0.5
2.0
Supply current 1
A
―
0.5
8
VDD =
SPVDD = 3.0V
VDD =
SPVDD = 5.0V
VDD =
CPU: Running at
4.096MHz
―
―
―
0.75
1.5
3
4
4
Supply current 4
Supply current 5
IDD4
IDD5
Crystal/ceramic
oscillating mode *1
1
CPU: Running at
4.096MHz
Crystal/ceramic
oscillating mode *1
During voice playback
(no output load)
mA
12
SPVDD = 3.0V
VDD =
SPVDD = 5.0V
―
8
12
*1: Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera).
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DC Characteristics (4 of 5)
(VDD = SPVDD = 2.2 to 5.5V, VSS = SPVSS = 0V,
Ta = 40 to +85C, unless otherwise specified)
Measuring
circuit
Parameter
Symbol
Condition
Min.
Typ. Max. Unit
VDD
0.5
Output voltage 1
(P20–P23)
VOH1
VOL1
IOH1 = 0.5mA
―
―
―
―
(P40–P43)
0.5
0.5
IOL1 = +0.5mA
―
V
2
IOL2 = +5mA
―
Output voltage 2
(P20–P23)
When LED drive
mode is selected
VDD 2.2V
IOL2 = +8mA
VDD 2.3V
VOL2
―
―
―
―
0.5
1
Output leakage
current
(P20–P23)
(P40–P43)
IOOH
IOOL
VOH = VDD (in high-impedance state)
A
3
VOL = VSS (in high-impedance state)
1
―
―
―
IIH1
IIL1
VIH1 = VDD
VIL1 = VSS
0
1
20
250
2
Input current 1
(RESET_N)
1500 300
IIH2
IIL2
VIH2 = VDD (when pulled down)
VIL2 = VSS (when pulled up)
VIH2 = VDD (in high-impedance state)
VIL2 = VSS (in high-impedance state)
VIH3 = VDD
2
250
―
30
30
―
Input current 2
(NMI)
(P00–P03)
(P40–P43)
A
4
IIH2Z
IIL2Z
IIH3
IIL3
1
1
―
―
20
-1
300
―
1500
―
Input current 3
(TEST)
VIL3 = VSS
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DC Characteristics (5 of 5)
(VDD = SPVDD = 2.2 to 5.5V, VSS = SPVSS = 0V,
Ta = 40 to +85C, unless otherwise specified)
Measuring
circuit
Parameter
Symbol
VIH1
Condition
Min.
Typ.
Max.
Unit
Input voltage 1
(RESET_N)
(TEST)
0.7
VDD
―
―
VDD
(NMI)
(P00–P03)
(P11)
0.3
VDD
VIL1
―
―
0
―
―
(P40–P43)
Hysteresis width
(RESET_N)
(TEST)
V
5
0.05
VDD
0.4
VDD
(NMI)
(P00–P03)
(P11)
VT
(P40–P43)
Input pin capacitance
(NMI)
f = 10kHz
(P00–P03)
(P11)
CIN
V
rms = 50mV
―
―
10
pF
―
Ta = 25C
(P40–P43)
Hysteresis Width
VT
VDD
Input signal
VSS
VDDL
VSS
Internal signal
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Measuring Circuits
Measuring circuit 1
C4
C34
C3
C2
CGH
CDH
OSC0
C12
C1
P11/OSC1
VDD
4.096MHz
crystal unit
CV
CL
CSG
CGH
CDH
: 1 F
VDDL
SPVDD
VSS
SPVSS
SG
: 10 F
: 0.1 F
: 24 pF
: 24 pF
A
CV
CL
CSG
4.096 MHz crystal unit:
HC49SFWB (Kyocera)
Measuring circuit 2
(*2)
V
VIH
(*1)
VIL
VDD VDDL
SPVDD VSS
SPVSS
*1: Input logic circuit to determine the specified measuring conditions.
*2: Measured at the specified output pins.
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Measuring circuit 3
(*2)
VIH
A
(*1)
VIL
VSS
VDD VDDL
SPVDD
SPVSS
*1: Input logic circuit to determine the specified measuring conditions.
*2: Measured at the specified output pins.
Measuring circuit 4
(*3)
A
VSS
VDD VDDL
SPVDD
SPVSS
*3: Measured at the specified input pins.
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FEDL610Q340FULL-01
ML610Q340/340
Measuring circuit 5
VIH
(*1)
VIL
VDD VDDL
SPVDDVSS
SPVSS
*1: Input logic circuit to determine the specified measuring conditions.
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FEDL610Q340FULL-01
ML610Q340/340
AC Characteristics (External Interrupt)
(VDD = SPVDD = 2.2 to 5.5V, VSS = SPVSS = 0V,
Ta = 40 to +85C, unless otherwise specified)
Parameter
External interrupt disable
period
Symbol
TNUL
Condition
Interrupt: Enabled (MIE = 1),
CPU: NOP operation
Min.
2.5
sysclk
Typ.
Max.
3.5
sysclk
Unit
―
s
P00–P03
(Rising-edge interrupt)
tNUL
tNUL
tNUL
P00–P03
(Falling-edge interrupt)
NMI, P00–P03
(Both-edge interrupt)
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ML610Q340/340
AC Characteristics (Synchronous Serial Port)
(VDD = SPVDD = 2.2 to 5.5V, VSS = SPVSS = 0V,
Ta = 40 to +85C, unless otherwise specified)
Parameter
SCK input cycle
(slave mode)
Symbol
tSCYC
Condition
Min.
10
Typ.
―
Max.
―
Unit
s
ns
High-speed oscillation stopped
During high-speed oscillation
500
―
―
SCK output cycle
(master mode)
tSCYC
tSW
―
―
SCK(*1)
―
sec
High-speed oscillation stopped
During high-speed oscillation
4
―
―
―
―
s
SCK input pulse width
(slave mode)
200
ns
SCK output pulse width
(master mode)
SOUT output delay time
(slave mode)
SOUT output delay time
(master mode)
SCK(*1)
0.4
SCK(*1)
0.5
SCK(*1)
0.6
―
―
―
sec
ns
tSW
tSD
tSD
―
―
180
―
―
80
ns
SIN input setup time
(slave mode)
SIN input hold time
―
―
50
50
―
―
―
―
ns
ns
tSS
tSH
*1: Clock period selected by S0CK3–0 of the serial port 0 mode register (SIO0MOD1)
tSCYC
tSW
tSW
SCK0*
SOUT0*
SIN0*
tSD
tSD
tSS
tSH
*: Indicates the secondary function of the corresponding port.
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FEDL610Q340FULL-01
ML610Q340/340
PACKAGE DIMENSIONS
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
The heat resistance (example) of this LSI is shown below. Heat resistance (θJa) changes with the size and the
number of layers of a substrate.
Die pad on the back of a package
100%
partial ground contact area
JEDEC
PCB
（W/L/t＝76.2/114.5/1.6（mm））
PCB Layer
4L
Air cooling conditions
Heat resistance（θJa）
Calm（0m/sec）
45[℃/W]
Power consumption of Chip PMax
at OutputPower 1W (5V)
Power consumption of Chip PMax
at OutputPower 0.5W (3.3V)
0.818[W]
0.283[W]
TjMax of this LSI is 125℃. TjMax is expressed with the following formulas.
TjMax = TaMax + θJa × PMax
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FEDL610Q340FULL-01
ML610Q340/340
Mounting area for package lead soldering to PCB (reference data) is shown below.
Die pad on the back of a package should connect with the substrate of opening or a VSS for heat dissipation.
24/26
FEDL610Q340FULL-01
ML610Q340/340
REVISION HISTORY
Page
Previous
Edition
Document No.
Date
Description
Current
Edition
FEDL610Q340FULL-01 Jan 7, 2010
–
–
Formally edition 1
25/26
FEDL610Q340FULL-01
ML610Q340/340
NOTICE
No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS
Semiconductor Co., Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be
obtained from LAPIS Semiconductor upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor
shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples of
application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any
license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties.
LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such
technical information.
The Products specified in this document are intended to be used with general-use electronic equipment or
devices (such as audio visual equipment, office-automation equipment, communication devices, electronic
appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such
as derating, redundancy, fire control and fail-safe designs. LAPIS Semiconductor shall bear no responsibility
whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the
instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system which
requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat
to human life or create a risk of human injury (such as a medical instrument, transportation equipment,
aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). LAPIS
Semiconductor shall bear no responsibility in any way for use of any of the Products for the above special
purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales
representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled
under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit
under the Law.
Copyright 2008 - 2011 LAPIS Semiconductor Co., Ltd.
26/26
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