ML610Q385 [ETC]
8-bit Microcontroller with Voice Output Function;
| 型号： | ML610Q385 |
| 厂家： | 
ETC |
| 描述： | 8-bit Microcontroller with Voice Output Function 微控制器 |
| 文件： | 总29页 (文件大小：480K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL610Q380FULL-01
Issue Date: Mar 9, 2012
ML610Q380/ML610Q383
ML610Q384/ML610Q385
8-bit Microcontroller with Voice Output Function
I
GENERAL DESCRIPTION
Equipped with a 8-bit CPU nX-U8/100, the ML610Q380/383/384/385 is a high-performance 8-bit CMOS
microcontroller that integrates a wide variety of peripherals such as 12-bit A/D converter, timer, PWM,
synchronous serial port, UART, I２C bus interface (master), Battery level detect circuit, LCD driver, voice output
function and speaker amplifier. The nX-U8/100 CPU is capable of executing instructions efficiently on a
one-instruction-per-clock-pulse basis through parallel processing by the 3-stage pipelined architecture.
In addition, it has an on-chip debugging function, which allows software debugging/rewriting with the LSI
mounted on the board.
FEATURES
• CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system:16-bit instructions
− Instruction set:Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic
shift, and so on
− On-Chip debug function
− Minimum instruction execution time
Approx 30.5 μs (at 32.768kHz system clock)
Approx 0.122 μs (at 8.192MHz system clock)＠DVDD = 2.2 to 5.5V
• Internal memory
− Has 128-Kbyte flash ROM(64K × 16-bit) built in. (1K byte of test domain that it cannot be used is
included)
− Has 2-Kbyte RAM (2048 × 8 bits) built in.
− Has maximum of 16-Mbit P2ROM (only ML610Q383/384/385)
P2ROM capacity: ML610Q383 (4M bit), ML610Q384 (8M bit), and ML610Q385 (16M bit)
• Interrupt controller
− 2 non-maskable interrupt sources (Internal source: 1, External source: 1)
− 24 maskable interrupt sources (Internal source: 20, External source: 4)
• Time base counter
− Low-speed time base counter × 1 channel
− High-speed time base counter × 1 channel
• Watchdog timer
− Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
• Timers
− 8 bits × 6ch (16-bit configuration available)
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FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
• PWM
− Resolution 16 bits × 2 channel(IGBT control)
• Voice output function
− Voice synthesis method: 4-bit ADPCM2 / 8bit non-linear PCM / straight 8-bit PCM / straight 16-bit PCM
− Sampling frequency: 6.4/8/10.7/12.8/16/21.3/25.6/32 kHz
• D/A converter
− 12-bit D/A converter
• Speaker amplifier output power
− 0.6W(at 5V)
− Thermal detection circuit
− Disconnection detection circuit
• Synchronous serial port
− 2ch ( For ML610Q383/384/385, SSIO1 is used for P2ROM access inside a chip.)
− Master/slave selectable
− LSB first/MSB first selectable
− 8-bit length/16-bit length selectable
• UART
− Half-duplex
− TXD/RXD × 2 channels
− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
− Positive logic/negative logic selectable
− Built-in baud rate generator
• I2C bus interface
− Master function only
− Fast mode (400kbit/s@4MHz), Standard mode (100kbit/s@4MHz)
• Successive approximation type A/D converter
− 10-bit A/D converter
− Input: 8ch （Maximum）
− Conversion time: 12.75μs per channel
• General-purpose ports ×45（Maximum）
− Non-maskable interrupt input port × 1ch
− Input-only port × 6ch
− Output-only port × 4ch (including secondary functions)
− Input/output × 18ch (including secondary functions)
− Input/output × 16ch (including LCD driver functions)
• LCD driver
− 96 dots max. (24 seg × 4 com), 1/1 to 1/4 duty
− Frame frequency selecable (approx. 64Hz, 73Hz, 85Hz, 102Hz, 32Hz, 128Hz, 171Hz, and 256Hz)
− LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable
•
Power supply voltage detect function
− Judgment voltages: One of 4 levels
− Judgment accuracy: ±2% (Typ.)
2/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
• Reset
− Reset through the RESET_N pin
− Reset by the watchdog timer (WDT) overflow
• Clock
− Low-speed clock (This LSI can not guarantee the operation withoug low-speed clock)
Crystal oscillation (32.768 kHz) or Built-in RC oscillation (32.7kHz)
− High-speed clock
Built-in oscillation (8.192MHz), Crystal/Ceramic oscillation (8MHz), external clock
• Power management
− HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).
− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral
circuits are stopped.)
− Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the
oscillation clock)
− Block control function: Operation of an intact functional block circuit is powerd down. (register reset and clock
stop)
• Shipment
− 80-pin QFP (P-QFP80-1414-0.80-TK9-MC)
ML610Q380-xxxGA (blank product: ML610Q380-NNNGA)
ML610Q383-xxxGA (blank product: ML610Q383-NNNGA)
ML610Q384-xxxGA (blank product: ML610Q384-NNNGA)
ML610Q385-xxxGA (blank product: ML610Q385-NNNGA)
xxx: ROM code number
• Guaranteed operating range
− Operating temperature: −40°C to 70°C
− Operating voltage: DVDD = P5VDD=2.2V to 5.5V, SPVDD = 4.5V to 5.5V, VREF = 4.5V to 5.5V
3/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
BLOCK DIAGRAM
Block diagram of ML610Q380
Figure 1-1 is a block diagram of the ML610Q380.
Symbols with an asterisk “*” indicate that each of them is the secondary or tertiary function of the corresponding port.
CPU (nX-U8/100) Large Model
EPSW1-3
PSW
ELR1-3
LR
ECSR1-3
DSR/CSR
PC
GREG
0-15
EA
Timing
Controller
ALU
SP
Program
Memory
（Flash）
BUS
Controller
VPP
Instruction
Decoder
Instruction
Register
On-Chip
ICE
128Kbyte
P5VDD
VDD
VSS
INT
2
Data-bus
SCK0*1, SCK1*1
SIN0*1, SIN1*1
SSIO
RESET_N
TEST0
TEST1_N
SOUT0*1, SOUT1*1
RESET &
TEST
INT
2
RAM
2048byte
RXD0*1, RXD1*1
TXD0*1, TXD1*1
UART
XT0
XT1
INT
1
OSC
Interrupt
Controller
OSC0*
OSC1*
SDA*1
SCL*1
I2C
LSCLK*
OUTCLK*
INT
4
INT
2
PWM4*1
PWM5*1
TBC
PWM
PW45EV0*1
PW45EV1*1
VDDL
POWER
INT
6
8bit Timer
× 6
INT
5
INT
1
NMI
INT
P00 to P03
P10 to P11
P20 to P23
P30 to P33*3
SG
AOUT
VOICECNT
WDT
GPIO
SPVDD
SPVSS
P34 to P35
P40 to P43
P44 to P47*3
P50 to P53
PC0 to PC7*2
PD0 to PD7*2
SPEAKER
AMP
SPP
SPM
SG
SPIN
BLD
VDD
VSS
INT
1
COM0 to COM3
LCD
Driver
SEG0 to SEG7
VREF
SEG8 to SEG23*2
10bit-ADC
AIN0 to AIN3*3
AIN4 to AIN7*3
LCD
Drive Voltage
VL1, VL2, VL3
*1 Secondary or tertiary function
*2 Select I/O port or LCD driver
*3 Select I/O port or A/D converter input
4/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
Block diagram of ML610Q383/384/385
Figure 1-2 is a block diagram of the ML610Q383/384/385.
Symbols with an asterisk “*” indicate that each of them is the secondary or tertiary function of the corresponding port.
CPU (nX-U8/100) Large
EPSW1～3
ELR1～3
LR
ECSR1～3
DSR/CSR
PC
GREG
0～15
PSW
EA
Timing
Controller
ALU
SP
Program
Memory
（Flash）
BUS
Controller
VPP
Instruction
Decoder
Instruction
Register
On-Chip
ICE
128Kbyte
DVDD
VSS
INT
2
Data-bus
SCK0*1, SCK1*4
SIN0*1, SIN1*4
SSIO
RESET_N
TEST0
TEST1_N
SOUT0*, SOUT1*4
RESET &
TEST
INT
2
RAM
2048byte
INT
1
RXD0*1, RXD1*1
TXD0*1, TXD1*1
UART
XT0
XT1
INT
1
OSC
OSC0*
OSC1*
LSCLK*
OUTCLK*
Interrupt
Controller
SDA*1
SCL*1
I2C
INT
4
INT
2
TBC
PWM4*1
PWM5*1
PWM
VDDL
VDDR
PW45EV0*1
POWER
INT
6
PW45EV1*1
8bit Timer
INT
5
INT
1
×6
NMI
INT
P00 to P03
P10 to P11
P20 to P23
P30 to P33*3
P34 to P35
P40 to P43
P44 to P47*3
SG
VOICECNT
AOUT
SPVDD
SPVSS
WDT
GPIO
SPEAKER
AMP
SPP
SPM
SG
SPIN
BLD
VDD
VSS
INT
1
PC0 to PC7*2
PD0 to PD7*2
VREF
AIN0 to AIN3*3
10bit-ADC
AIN4 to AIN7＊3
PVPP
*1 P50(SIN1)
PSO
PSCK
*1 P51(SCK1)
*1 P52(SOUT1)
*1 P53
COM0 to COM3
SEG0 to SEG7
SEG8 to SEG23*2
GPIO
LCD
Driver
PSI
PCSB
16Mbit
P2ROM
LCD
Drive Voltage
VL1, VL2, VL3
*1 Secondary or tertiary function
*2 Select I/O port or LCD driver
*3 Select I/O port or A/D converter input
4
*
For P2ROM
5/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
PIN CONFIGURATION (ML610Q383/384/385)
ML610Q380 QFP package product
SPM
SPP
PC3/SEG11
PC2/SEG10
PC1/SEG9
PC0/SEG8
SEG7
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P20/LED0
P21/LED1
P22/LED2
P23/LED3
VSS
SEG6
SEG5
SEG4
P50/SIN1
P53/TXD1
SEG3
(NC)
SEG2
SEG1
SEG0
COM0
COM1
COM2
COM3
VL3
P5VDD
P00/INT0
P01/INT1
P02/INT2
P03/INT3
VREF
P30/AIN0
P31/AIN1
VL2
P32/AIN2
P33/AIN3
VL1
P52/SOUT1
NC: No Connection
6/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
ML610Q383/384/385 QFP package product
SPM
SPP
PC3/SEG11
PC2/SEG10
PC1/SEG9
PC0/SEG8
SEG7
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P20/LED0
P21/LED1
P22/LED2
P23/LED3
VSS
SEG6
SEG5
SEG4
TEST00
TEST03
SEG3
PVPP
VDDR
SEG2
SEG1
SEG0
COM0
COM1
COM2
COM3
VL3
P00/INT0
P01/INT1
P02/INT2
P03/INT3
VREF
P30/AIN0
P31/AIN1
VL2
P32/AIN2
P33/AIN3
VL1
TEST02
7/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
LIST OF PINS
Primary function
Description
Secondary function
Tertiary function
Pin
No.
Pin
Pin
Pin
I/O
I/O
Description
I/O
Description
name
name
name
Negative power supply pin
Positive power supply pin
12,67
13
Vss
DVDD
VDDL
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Power supply for internal logic
(internally generated)
Negative power supply pin for
built-in speaker amplifier
Positive power supply pin for
built-in speaker amplifier
For P50 to P53 power supply pin
For P2ROM SIOport
14
SPVSS
60
59
SPVDD
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
*1
P5VDD
71
*2
VDDR
power supply pin
High voltage power supply pin of
data to building P2ROM
70
PVPP*2
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Power supply pin for Flash ROM
Power supply pin for LCD bias
Power supply pin for LCD bias
Power supply pin for LCD bias
Input/output pin for testing
Input/output pin for testing
Reset input pin
17
22
23
24
54
55
11
15
16
VPP
VL1
⎯
⎯
⎯
⎯
I/O
I/O
I
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
VL2
VL3
TEST0
TEST1_N
RESET_N
XT0
Low-speed clock oscillation pin
Low-speed clock oscillation pin
LINE output
I
XT1
O
AOUT
O
57
58
Analog input to the built-in
speaker amplifier
Reference power supply pin of
the built-in speaker amplifier
Positive output pin of the built-in
speaker amplifier
Negative output pin of the
built-in speaker amplifier
Reference power supply pin of
Successive-approximation type
ADC
Input port,
non-maskable interrupt
Input port /
External interrupt /
PW45EV0 input
Input port /
SPIN
SG
I
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
O
O
O
56
62
61
SPP
SPM
VREF
NMI
I
76
53
72
73
74
⎯
⎯
⎯
⎯
⎯
⎯
I
I
I
I
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
P00/EXI0/
PW45EV0
P01/EXI1
External interrupt
Input port /
External interrupt
UART0 data input
Input port /
External interrupt /
UART1 data input
P02/EXI2/
RXD0
P03/EXI3/
RXD1
I
75
⎯
⎯
⎯
⎯
⎯
⎯
High-speed clock
oscillation pin
High-speed clock
oscillation pin
Low-speed clock
output
P10
P11
I
I
Input port
18
19
63
OSC0
OSC1
I
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Input port
O
O
O
P20/
LED0
O
Output port / LED drive
LSCLK
OUTCLK
P21/
LED1
P22/
LED2
P23/
Low-speed clock
output
O
O
O
Output port / LED drive
Output port / LED drive
Output port / LED drive
64
65
66
⎯
⎯
O
O
⎯
TM9OUT
TMBOUT
Timer9 output
TimerB output
⎯
⎯
⎯
⎯
⎯
⎯
LED3
8/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
Primary function
Description
Secondary function
Tertiary function
Pin
No.
Pin
Pin
Pin
I/O
I/O
I/O
Description
I/O
Description
name
name
name
Input/output port /
PW45EV1 input /
Successive approximation type
ADC input
P30/
PW45EV1
/AIN0
77
⎯
⎯
⎯
⎯
⎯
⎯
Input/output port /
P31/AIN1
P32/AIN2
P33/AIN3
I/O Successive approximation type
ADC input
Input/output port /
I/O Successive approximation type
ADC input
Input/output port /
I/O Successive approximation type
ADC input
78
79
80
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
P34
P35
I/O Input/output port
I/O Input/output port
PWM4
PWM5
O
O
PWM4 output
PWM5 output
5
6
⎯
⎯
⎯
⎯
⎯
⎯
I2C data
SSIO0 data
input
P40
I/O Input/output port
SDA
I/O
SIN0
I
7
input/output
SSIO0
synchronous
clock
I2C clock
input/output
P41
I/O Input/output port
SCL
I/O
SCK0
I/O
8
input/output
SSIO0 data
output
UART0 data
input
UART0 data
output
P42
P43
I/O Input/output port
I/O Input/output port
RXD0
TXD0
I
SOUT0
PWM4
O
O
9
O
PWM4 output
10
Input port /
P44/
T0P4CK/
AIN4
Timer0 external clock input /
SSIO0 data
input
1
2
3
4
I
I
I
PWM4 external clock input/
Successive approximation type
ADC input
SIN0
SCK0
I
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Input port /
SSIO0
synchronous
clock
P45/
T1P5CK/
AIN5
Timer1 external clock input /
PWM5 external clock input/
Successive approximation type
ADC input
I/O
O
input/output
Input port /
P46/
T8ACK/
AIN6
Timer8 external clock input /
TimerA external clock input /
Successive approximation type
ADC input
SSIO0 data
output
SOUT0
PWM5
Input port /
P47/
T9BCK/
AIN7
Timer9 external clock input /
TimerB external clock input /
Successive approximation type
ADC input
I
O
PWM5 output
P50*1
TESTO0*2
P51*1
Input/output port
SSIO1 data
input
SSIO1
synchronous
clock
68
20
I/O
SIN1
I
⎯
⎯
⎯
⎯
⎯
⎯
I/O Input/output port
SCK1
I/O
TESTO1*2
input/output
SSIO1 data
output
P52*1
TESTO2*2
P53*1
Input/output port
I/O
UART1 data
input
UART1 data
input
21
69
RXD1
TXD1
I
SOUT1
O
I/O Input/output port
O
⎯
⎯
⎯
TESTO3*2
COM0
28
27
O
O
LCD common pin
LCD common pin
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
COM1
26
25
29
COM2
COM3
SEG0
O
O
O
LCD common pin
LCD common pin
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
30
31
32
SEG1
SEG2
SEG3
O
O
O
LCD segment pin
LCD segment pin
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
9/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
Primary function
Description
Secondary function
Tertiary function
Pin
No.
Pin
Pin
Pin
I/O
I/O
Description
I/O
Description
name
name
name
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
SEG4
SEG5
SEG6
SEG7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
O
O
O
O
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
⎯
⎯
⎯
⎯
⎯
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
LCD segment
pin
LCD segment
pin
LCD segment
pin
LCD segment
pin
LCD segment
pin
LCD segment
pin
LCD segment
pin
LCD segment
pin
LCD segment
pin
LCD segment
pin
LCD segment
pin
LCD segment
pin
LCD segment
pin
LCD segment
pin
LCD segment
pin
LCD segment
pin
I/O Input/output port
I/O Input/output port
I/O Input/output port
I/O Input/output port
I/O Input/output port
I/O Input/output port
I/O Input/output port
I/O Input/output port
I/O Input/output port
I/O Input/output port
I/O Input/output port
I/O Input/output port
I/O Input/output port
I/O Input/output port
I/O Input/output port
I/O Input/output port
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
*1：It applies to ML610Q380.、*2：It applies to ML610Q383/384/385.
10/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
Supplementation: Only ML610Q383/384/385. ( ML610Q380 doesn't correspond.)
P50 to P53 is connected with building P2ROM by the inside of the chip into,
and each function exists.
(The external pin name becomes TESTO0 to TESTO3. Please give the external terminal processing to
me as an opening.)
Connected with P2ROM content is shown as follows.
The pins of built-in P2ROM
PSO
Explanation
Serial-data output
connected with P50/SIN1 (Tertiary functional) inside.
Serial-data output
connected with P51/SCK1 (Tertiary functional) inside
Serial-data input
PSCK
PSI
connected with P52/SOUT1 (Tertiary functional) inside
Chip select input
connected with P53 (Primary functional) inside
PCSB
11/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
PIN DESCRIPTION
Primary/
Logic
Pin name
I/O
Description
Secondary
Power supply
VSS
Negative power supply pin
Positive power supply pin
—
—
—
—
—
—
DVDD
Positive power supply pin for internal logic (internally generated). Connect
VDDL
—
—
—
capacitors (CL) (see Measuring Circuit 1) between this pin and VSS
Negative power supply pin for built-in speaker amplifier
Positive power supply pin for built-in speaker amplifier
Port5 IF power supply pin.(Only ML610Q380)
.
SPVSS
SPVDD
P5VDD
—
—
—
—
—
—
—
—
—
supply the power supply of the SPI memory when you connect the SPI
memory with external.Besides, supply the same level as DVDD.
VDDR
P2ROM built in Positive power supply(Inner generation) pin.
—
—
—
—
(Only ML610Q383/384/385)Connect capacitors (CR) (see Measuring Circuit
1) between this pin and VSS
.
PVPP
—
High voltage power supply pin of the data write to building P2ROM into.
Besides, fix at the VSS level.
Power supply pin for programming Flash ROM.
Power supply pins for LCD bias (external input)
Power supply pins for LCD bias (external input)
Power supply pins for LCD bias (external input)
VPP
VL1
VL2
VL3
—
—
—
—
—
—
—
—
—
—
—
—
Test
TEST0
I/O Input/output pin for testing. Has a pull-down resistor built in.
I/O Input/output pin for testing. Has a pull-up resistor built in.
—
—
Positive
TEST1_N
System
Negative
Reset input pin. When this pin is set to a “L” level, the device is placed in
system reset mode and the internal circuit is initialized. If after that this pin
is set to a “H” level, program execution starts. This pin has a pull-up
resistor built in.
RESET_N
I
—
Negative
—
Crystal connection pin for low-speed clock. A 32.768 kHz crystal oscillator
I
XT0
—
(see measuring circuit 1) is connected to this pin. Capacitors CDL and CGL
XT1
O
I
—
—
—
—
are connected across this pin and VSS as required.
OSC0
OSC1
Secondary
Secondary
External input pin for high-speed clock. This function is allocated to the
secondary function of the P10 pin.
O
Low-speed clock output. This function is allocated to the secondary function
of the P20 pin.
LSCLK
O
O
Secondary
Secondary
—
—
High-speed clock output. This function is allocated to the secondary
function of the P21 pin.
OUTCLK
General-purpose input port
P00 to P03
P10 to P11
I
I
General-purpose input ports. Provided with a secondary function for each
port. Cannot be used as ports if their secondary functions are used.
Primary
Primary
Positive
Positive
General-output input port
General-purpose output ports.Provided with a secondary function for each
port. Cannot be used as ports if their secondary functions are used.
P20 to P23
O
12/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
Primary/
Pin name
I/O
Description
Secondary/ Logic
Tertiary
General-purpose input/output port
P30 to P35
General-purpose input/output ports.Provided with a secondary function for
each port. Cannot be used as ports if their secondary functions are used.
I/O
P40 to P47
P50 to P53
PC0 to PC7
PD0 to PD7
UART
Primary
Positive
I/O
General-purpose input/output ports.Provided with a LCD segment for each
port. Cannot be used as ports if LCD segment are used.
TXD0
O
I
UART0 data output pin. Allocated to the secondary function of the P43 pin. Secondary Positive
UART0 data input pin. Allocated to the primary function of the P02 pin and
Secondary Positive
RXD0
TXD1
RXD1
the secondary function of the P42 pin.
O
I
UART1 data output pin. Allocated to the secondary function of the P53 pin. Secondary Positive
UART1 data input pin. Allocated to the primary function of the P03 pin and
Secondary Positive
the secondary function of the P52 pin.
I2C bus interface
I2C data input/output pin. This pin is used as the secondary function of the
P40 pin. This pin has an NMOS open drain output. When using this pin as
SDA
SCL
I/O
Secondary Positive
Secondary Positive
a function of the I2C, externally connect a pull-up resistor.
I2C clock output pin. This pin is used as the secondary function of the P41
pin. This pin has an NMOS open drain output. When using this pin as a
function of the I2C, externally connect a pull-up resistor.
I/O
Synchronous serial (SSIO)
Synchronous serial data input pin. Allocated to the tertiary function of the
P40 pin and P44 pin.
SIN0
I
I/O
O
Tertiary
Tertiary
Tertiary
Tertiary
Tertiary
Tertiary
Positive
—
Synchronous serial clock input/output pin. Allocated to the tertiary function
of the P41 pin and P45 pin.
SCK0
SOUT0
SIN1
Synchronous serial data output pin. Allocated to the tertiary function of the
P42 pin and P46 pin.
Positive
Positive
—
Synchronous serial data input pin. Allocated to the tertiary function of the
P50 pin .
I
Synchronous serial clock input/output pin. Allocated to the tertiary function
of the P51 pin.
SCK1
I/O
O
Synchronous serial data output pin. Allocated to the tertiary function of the
P52 pin.
SOUT1
PWM
Positive
PWM4 output pin. Allocated to the tertiary function of the P34 and P43 pins.
PWM5 output pin. Allocated to the tertiary function of the P35and P47 pins.
PWM4
O
O
I
Tertiary
Tertiary
Primary
Primary
Positive
Positive
—
PWM5
External clock input pin for timer 0 and PWM4. Allocated to the primary
function of the P44 pin.
T0P4CK
T1P5CK
External clock input pin for timer 1 and PWM5. Allocated to the primary
function of the P45 pin.
I
—
PW45EV0
PW45EV1
Control start /stop pin for PWM4 and PWM5. Allocated to the primary
function of the P00 pin and P30 pin.
I
Primary
—
13/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
Primary/
Pin name
I/O
Description
Secondary/ Logic
Tertiary
External interrupt
NMI
External non-maskable interrupt input pin. The interrupt occurs on both the
rising and falling edges.
Positive/
Negative
I
I
Primary
Primary
External maskable interrupt input pins. It is possible, for each bit, to specify
whether the interrupt is enabled and select the interrupt edge by software.
Allocated to the primary function of the P00–P03 pins.
Positive/
Negative
EXI0–EXI3
Timer
External clock input pin for timer 0 and PWM4. Allocated to the primary
function of the P44 pin.
T0P4CK
I
I
I
I
Primary
Primary
Primary
Primary
Tertiary
Tertiary
—
—
External clock input pin for timer 1 and PWM5. Allocated to the primary
function of the P45 pin.
T1P5CK
T8ACK
T9BCK
External clock input pin for timer 8 and timer A. Allocated to the primary
function of the P46 pin.
—
External clock input pin for timer 9 and timer B. Allocated to the primary
function of the P47 pin.
—
Timer9 overflow output pin. Allocated to the secondary function of the P22
pin.
TM9OUT
O
O
Positive
Positive
TimerB overflow output pin. Allocated to the secondary function of the P23
pin.
TMBOUT
LED drive
LED0-LED3
Positive/
Negative
O
Pins for LED driving. Allocated to the primary function of the P20–P23 pins.
Primary
Voice output function
LINE output pin.
AOUT
O
—
—
The case of built-in speaker amplifier use, connect with the SPIN pin.
Analog input pin of the internal speaker amplifier.
SPIN
SG
I
—
—
—
—
—
—
—
—
O
O
O
Reference voltage output pin of the internal speaker amplifier.
Positive output pin of the internal speaker amplifier.
Negative output pin of the internal speaker amplifier.
SPP
SPM
Successive-approximation type A/D converter
Reference power supply pin for successive approximation type A/D
converter.
VREF
I
I
—
—
Analog inputs to Ch0–Ch7 of the successive-approximation type A/D
converter. Allocated to the secondary function of the P30 to P33 and P44 to
P47 pins.
AIN0–AIN7
LCD driver
COM0 to
COM3
LCD common output pins.
LCD segment output pins.
O
O
O
—
—
—
—
—
—
SEG0 to
SEG7
SEG8 to
SEG23
LCD segment output pins. Allocated to the secondary function of the PC0
to PC7 and PD0 to PD7 pins.
14/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
TERMINATION OF UNUSED PINS
How to Terminate Unused Pins
Pin
Recommended pin termination
VPP
open
RESET_N
TEST0
TEST1_N
VREF
open
open
open
Connect to DVDD
SPVDD
SPVSS
P5VDD
Connect to DVDD
Connect to DVSS
Connect to DVDD
*1
AOUT
open
SPIN
open
SG
open
SPP
open
SPM
open
P00 to P03
Connect DVDD or VSS
P10 to P11
Connect DVDD or VSS
P20 to P23
P30 to P33 (AIN0 to AIN3)
P34 to P35
P40 to P43
P44 to P47 (AIN4 to AIN7)
P50 to P53
COM0 to COM3
SEG0 to SEG7
PC0 to PC7 （SEG8 to15）
PD0 to PD7 （SEG16 to 23）
open
open
open
open
open
open
open
open
open
open
Note:
*1. Only ML610Q380 is applied.
For unused input ports or unused input/output ports, if the corresponding pins are configured as high-impedance inputs
and left open, the supply current may become excessively large. Therefore, it is recommended to configure those pins as
either inputs with a pull-down resistor/pull-up resistor or outputs.
15/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(VSS = SPVSS = 0V)
Parameter
Symbol
Condition
Rating
Unit
V
Power supply voltage 1
DVDD
Ta = 25°C
−0.3 to +7.0
Power supply voltage 2
Power supply voltage 3
Power supply voltage 4
Power supply voltage 5
SPVDD
VPP
VL1
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
−0.3 to +7.0
−0.3 to +9.5
−0.3 to +2.33
−0.3 to +4.66
V
V
V
V
VL2
Power supply voltage 6
Power supply voltage 7
Reference voltage
Analog input voltage
Input voltage
VL3
P5VDD
VREF
VAI
Ta = 25°C
Ta=25℃
−0.3 to +7.0
-0.3～+7.0
V
V
V
V
V
V
Ta = 25°C
Ta = 25°C
Ta = 25°C
−0.3 to DVDD+0.3
−0.3 to DVDD+0.3
−0.3 to DVDD+0.3
−0.3 to DVDD+0.3
VIN
Output voltage
VOUT
Ta = 25°C
Port3,4,5,C,D,COM,SEG,
Ta = 25°C
Output current 1
IOUT1
−12 to +11
mA
Output current 2
IOUT2
PD
Port2,9 Ta = 25°C
−12 to +20
1
mA
W
Power dissipation
Storage temperature
Ta = 25°C
TSTG
―
−55 to +150
°C
Recommended Operating Conditions
(VSS = SPVSS = 0V)
Parameter
Symbol
Condition
Range
Unit
Operating temperature
TOP
―
―
―
−40 to +70
2.2 to 5.5
2.2 to 5.5
°C
DVDD
P5VDD
Operating voltage
V
SPVDD
fOP
fXTL
CV
CSV
C1
CAV
CDL
―
4.5 to 5.5
30k to 8.4M
32.768k
10±30%
1±30%
1±30%
1±30%
12 to 25
Operating frequency (CPU)
Low-speed crystal oscillation frequency
Capacitor externally connected to DVDD pin
Capacitor externally connected to SPVDD pin
Capacitor externally connected to VPP pin
Capacitor externally connected to Vref pin
―
―
―
―
―
Hz
Hz
μF
μF
μF
μF
―
Use 32.768KHz Crystal
Oscillator DT-26S
(DAISHINKU CORP.)
Low-speed crystal oscillation
external capacitor
pF
CGL
fXTH
12 to 25
High-speed crystal/ceramic oscillation
frequency
―
8M/8.192M
Hz
pF
CDH
CGH
―
―
47±30%
47±30%
High-speed crystal oscillation
external capacitor*
Capacitor externally connected to VDDL pin
Capacitor externally connected to VDDR pin
Capacitor externally connected to VL1,2,3 pin
CL
CR
―
―
―
10±30%
1±30%
μF
μF
μF
CL1,2,3
0.22±30%
Capacitor externally connected to AOUT pin –
SPIN pin
Capacitor externally connected to SG pin
CAOSP
CSG
―
―
0.022±30%
0.1±30%
μF
μF
* CGH and CDH are built into, external capacity is unnecessary for CSTLS8M00G56-A0 (made by Murata
Mfg.).
16/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
Flash Memory Operating Conditions
(VSS = SPVSS = 0V)
Parameter
Symbol
TOP
DVDD
VDDL
VPP
Condition
At write/erase
At write/erase
At write/erase*1
At write/erase1
―
Range
0 to +40
2.7 to 5.5
2.5 to 2.75
7.7 to 8.3
80
Unit
Operating temperature
°C
Operating voltage
V
Maximum rewrite count
Data retention period
CEPP
YDR
times
years
―
10
*1: At the writing of a flash ROM, it is necessary to supply voltage to VDDL pin within the limits of the
above-mentioned regulation. Pulldown resistance is built in the VPP pin.
DC Characteristics (1 of 6)
(DVDD= P5VDD=SPVDD= 2.2 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified)
Measuring
circuit
Parameter
Symbol
Condition
Min.
Typ.
2
Max.
20
Unit
ms
s
High-speed crystal oscillation
start time
TXTH
―
―
―
Low-speed crystal oscillation
TXTL
―
0.6
2
start time*2
Typ
-5%
Typ
+5%
Low-speed RC oscillator
frequency
fLCR
―
32.7k
8.192
Hz
1
LSCLK=32.768kHz
100 clock average
Typ
-1%
Typ
+1%
PLL oscillation frequency
Reset pulse width
fPLL
MHz
PRST
―
100
―
―
―
μs
Reset noise rejection pulse
width
PNRST
―
―
0.4
*1: Use 32.768KHz Crystal Oscillator DT-26 (Daishinku) with capacitance CGL/CDL＝12pF.
Reset
VIL1
VIL1
PRST
RESET_N
Reset by RESET_N pin
17/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
DC Characteristics (2 of 6)
(DVDD= P5VDD=SPVDD= 4.5 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified)
Measuring
circuit
Parameter
Symbol
VAD
Condition
Min.
Typ.
Max.
Unit
V
LINE amplifier output
voltage range
At 10kΩ load for VSS
SPVDD×1/6
⎯
SPVDD×5/6
0.95 ×
SPVDD/2
57
1.05 ×
SPVDD/2
135
SG output voltage
VSG
RSG
RLSP
―
―
―
SPVDD/2
V
kΩ
Ω
SG output resistance
96
8
SPM, SPP output load
resistance
―
―
SPVDD = 5.0V,
f = 1kHz,
RSPO = 8Ω,
THD ≥ 10%
At SPIN Input
1
Speaker amplifier output
power
PSPO1
—
0.6
—
—
W
SPVDD=5.0V,
SPIN – SPM gain =
+0dB
Output offset voltage
between SPM and SPP
with no signal present
VOF
−50
+50
mV
With a load of 8Ω
DC Characteristics (3 of 6)
(DVDD= P5VDD=SPVDD= 2.2 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified)
Meas
Parameter
Symbol
VBLD
Condition
Min.
Typ.
Max.
Unit uring
circuit
LD3 to 0 = 0H
2.35
2.80
3.70
4.60
LD3 to 0 = 3H
LD3 to 0 = 9H
LD3 to 0 = FH
Typ.
-2%
Typ.
+2%
BLD threshold
voltage
Ta = 25°C
V
1
DC Characteristics (4 of 6)
(DVDD= P5VDD=SPVDD= 2.2 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified)
Meas
Parameter
Symbol
Condition
Min. Typ. Max. Unit uring
circuit
CPU: In STOP state
Supply current 1
Supply current 2
Supply current 3
Supply current 4
Low-speed/high-speed oscillation: Stopped
DVDD=3.0V
IDD1
IDD2
IDD3
IDD4
―
―
―
―
0.7
2.0
13
5
22
24
42
8
CPU: In HALT state (LTBC,WBC: Operating*2)
High-speed oscillation: Stopped
DVDD=3.0V
μA
1
CPU: Running at 32kHz*1
High-speed oscillation: Stopped
DVDD=3.0V
CPU: Running at 8.192MHz Crystal/ceramic
oscillating mode*2
mA
DVDD = SPVDD = 5.0V
*1: Case when the CPU operating rate is 100% (with no HALT state)
*2 : Significant bits of BLKCON0 to BLKCON4 registers are all “1”.
18/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
DC Characteristics (5 of 6)
(DVDD= P5VDD=SPVDD= 2.2 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified)
Measuring
circuit
Parameter
Symbol
VOH1
Condition
Min.
Typ.
Max.
Unit
Output voltage 1
(P20 to P23)
(P30 to P35)
(P40 to P47)
(P50 to P53)
(PC0 to PC7)
(PD0 to PD7)
Output voltage 2
(P20–P23)
DVDD
−0.5
IOH1 = −0.5mA
―
―
―
0.5
VOL1
IOL1 = +0.5mA
―
V
2
IOL2 = +10mA
DVDD ≥ 4.5V
When LED drive
mode is selected
When I2C mode is
selected
VOL2
VOL3
―
―
―
―
0.5
0.4
Output voltage 3
(P40–P41)
IOL3 = +3mA
Output leakage
current
VOH = DVDD
(in high-impedance state)
IOOH
IOOL
―
―
―
1
(P20 to P23)
(P30 to P35)
(P40 to P47)
(P50 to P53)
(PC0 to PC7)
(PD0 to PD7)
μA
3
VOL = VSS
(in high-impedance state)
−1
―
VL3=3V、VOL=0.3V
VL3=5V、VOL=0.5V
VL3=3V、VOH=2.7V
VL3=5V、VOH=4.5V
VL3=3V、VOL=0.3V
VL3=5V、VOL=0.5V
VL3=3V、VOH=2.7V
VL3=5V、VOH=4.5V
VIH1 = DVDD
15
100
―
―
15
70
―
―
0
40
200
-30
-90
30
―
―
IOL1
IOH1
IOL2
IOH2
Output current 1
COM0 to COM3
-15
-45
―
μA
3
150
-13
-40
―
―
Output current 2
SEG0 to SEG23
-6
-20
1
Input current 1
(RESET_N)
(TEST1_N)
Input current 2
(NMI)
(P00 to P03)
(P10 to P11)
(P30 to P35)
(P40 to P47)
(P50 to P53)
(PC0 to PC7)
(PD0 to PD7)
IIH1
IIL1
VIL1 = VSS
−1500 −300
−20
IIH2
IIL2
VIH2 = DVDD (when pulled down)
2
30
−30
―
250
VIL2 = VSS (when pulled up)
−250
―
−2
μA
4
VIH2 = DVDD
(in high-impedance state)
IIH2Z
1
VIL2 = VSS
(in high-impedance state)
IIL2Z
-1
―
―
IIH3
IIL3
VIH3 = DVDD
VIL3 = VSS
20
-1
300
1500
Input current 3
(TEST0)
―
―
19/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
DC Characteristics (6 of 6)
(DVDD= P5VDD=SPVDD= 2.2 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified)
Measuring
circuit
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Input voltage 1
(RESET_N)
(TEST0)
0.7×
DVDD
VIH1
―
―
DVDD
(TEST1_N)
(NMI)
(P00 to P03)
(P10 to P11)
(P30 to P35)
(P40 to P43)
(P50 to P53)
(PC0 to PC7)
(PD0 to PD7)
V
5
0.3×
DVDD
VIL1
―
0
―
Input pin capacitance
(RESET_N)
(TEST0)
(TEST1_N)
(NMI)
f = 10kHz
Vrms = 50mV
Ta = 25°C
(P00 to P03)
(P10 to P11)
(P30 to P35)
(P40 to P43)
(P50 to P53)
(PC0 to PC7)
(PD0 to PD7)
CIN
―
―
10
pF
―
20/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
Measuring Circuits
Measuring circuit 1
CGL
XT0
XT1
CL3
VL3
CDL
32.768kHz
crystal
CL2
VL2
CGH
OSC0
OSC1
CL1
VL1
CDH
1
DVDD
V
VDDLV
DDR
2 SG VSS SPVSS
※
※
8MHz
crystal
REFSPV
DD P5VDD
A
CV
CL
CR
CSG
CGL
CDL
CGH
CDH
：10μF
：10μF
：10μF
：0.1μF
：12pF
：12pF
：47pF
：47pF
CV
CL
CR CSG
CL1,C L2,C L3：0.22μF
32.768kHz Crystal oscillator
(DMX-26S DAISHINKU Corp.)
8MHz Crystal oscillator
CSTLS8M00G56-A0（MURATA
Corp.）it has built-in CGH, and CDH
Measuring circuit 2
(*2)
VIH
(*1)
V
VIL
1
2 VDDL VREF SPVDD
※
※
VL1 VL2 VL3
VSS SPVSS
DV
DDP5VDD VDDR
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
※1. Only ML610Q380 is applied.
※2. Only ML610Q383/384/385 is applied.
21/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
Measuring circuit 3
(*2)
VIH
A
(*1)
VIL
※
P5V
DD VDDR
VDDL
V
REF SPVDD
VSS SPVSS
DVDD
*1: Input logic circuit to determine the specified measuring conditions.
*2: Measured at the specified output pins.
Measuring circuit 4
(*3)
A
2 VDDL VREF SPVDD
VSS SPVSS
※
DDP5VDD※ VDDR
DV
*3: Measured at the specified input pins.
Measuring circuit 5
VIH
(*1)
VIL
※
1 VDDR
※
DVDD
2 VDDL VREFSPVDD
VSS SPVSS
P5VDD
*1: Input logic circuit to determine the specified measuring conditions.
※1. Only ML610Q380 is applied.
※2. Only ML610Q383/384/385 is applied.
22/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
AC Characteristics (External Interrupt)
(DVDD= P5VDD=SPVDD= 2.2 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified)
Parameter
External interrupt disable
period
Symbol
Condition
Interrupt: Enabled (MIE = 1),
CPU: NOP operation
Min.
2.5×
sysclk
Typ.
Max.
3.5×
sysclk
Unit
TNUL
―
μs
P00–P03
tNUL
tNUL
tNUL
(Rising-edge interrupt)
P00–P03
(Falling-edge interrupt)
NMI, P00–P03
(Both-edge interrupt)
23/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
AC Characteristics (Synchronous Serial Port)
(DVDD= P5VDD=SPVDD= 2.2 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified)
Parameter
Symbol
Condition
Min.
10
Typ.
―
Max.
―
Unit
μs
ns
High-speed oscillation stopped
During high-speed oscillation
SCK input cycle
(slave mode)
tSCYC
500
―
―
SCK output cycle
(master mode)
tSCYC
tSW
―
―
SCK(*1)
―
sec
High-speed oscillation stopped
During high-speed oscillation
4
―
―
SCK(*1)
―
―
SCK(*1)
μs
SCK input pulse width
(slave mode)
200
SCK(*1)
×0.4
ns
SCK output pulse width
(master mode)
SOUT output delay time
(slave mode)
SOUT output delay time
(master mode)
―
―
―
sec
ns
tSW
tSD
tSD
×0.5
×0.6
―
―
180
―
―
80
ns
SIN input setup time
(slave mode)
SIN input hold time
―
―
50
50
―
―
―
―
ns
ns
tSS
tSH
*1: Clock period selected by S0CK3–0 of the serial port 0 mode register (SIO0MOD1)
tSCYC
tSW
tSW
SCK0*
SOUT0
SIN0*
tSD
tSD
tSS
tSH
*: Indicates the secondary function of the corresponding port.
24/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
AC CHARACTERISTICS (I2C Bus Interface: Standard Mode 100kHz)
(DVDD= P5VDD=SPVDD= 2.2 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
0
Typ.
Max.
100
SCL clock frequency
fSCL
⎯
⎯
⎯
kHz
SCL hold time
tHD:STA
4.0
⎯
⎯
μs
(start/restart condition)
SCL ”L” level time
tLOW
tHIGH
⎯
⎯
4.7
4.0
⎯
⎯
⎯
⎯
μs
μs
SCL ”H” level time
SCL setup time
(restart condition)
SDA hold time
SDA setup time
SDA setup time
(stop condition)
Bus-free time
tSU:STA
⎯
4.7
⎯
⎯
μs
tHD:DAT
tSU:DAT
⎯
⎯
0
0.25
⎯
⎯
⎯
⎯
μs
μs
tSU:STO
tBUF
⎯
⎯
4.0
4.7
⎯
⎯
⎯
⎯
μs
μs
AC CHARACTERISTICS (I2C Bus Interface: Fast Mode 400kHz)
(DVDD= P5VDD=SPVDD= 2.2 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
0
Typ.
Max.
400
SCL clock frequency
fSCL
⎯
⎯
⎯
kHz
SCL hold time
tHD:STA
0.6
⎯
⎯
μs
(start/restart condition)
SCL ”L” level time
SCL ”H” level time
SCL setup time
(restart condition)
SDA hold time
SDA setup time
SDA setup time
(stop condition)
Bus-free time
tLOW
tHIGH
⎯
⎯
1.3
0.6
⎯
⎯
⎯
⎯
μs
μs
tSU:STA
⎯
0.6
⎯
⎯
μs
tHD:DAT
tSU:DAT
⎯
⎯
0
0.1
⎯
⎯
⎯
⎯
μs
μs
tSU:STO
tBUF
⎯
⎯
0.6
1.3
⎯
⎯
⎯
⎯
μs
μs
Start
condition
Restart
condition
Stop
condition
P40/SDA
P41/SCL
tBUF
tSU:STO
tHD:STA
tLOW tHIGH
tSU:STA tHD:STA
tSU:DAT tHD:DAT
25/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
Electrical Characteristics of Successive Approximation Type A/D Converter
(DVDD= P5VDD=SPVDD= 4.5 to 5.5V, VSS = SPVSS=0V, Ta=−40 to +70°C, unless otherwise specified)
Parameter
Resolution
Symbol
n
Condition
―
Min.
―
Typ.
―
Max.
10
Unit
bits
Integral non-linearity error
Differential non-linearity
error
IDL
2.7V ≤ VREF ≤ 5.5V
−4
―
+4
DNL
2.7V ≤ VREF ≤ 5.5V
−3
―
+3
LSB
Zero-scale error
Full-scale error
Input impedance
Reference voltage
VOFF
FSE
RI
―
―
―
−4
−4
―
―
―
―
―
+4
+4
5k
Ω
VREF
4.5
DVDD
V
φ/CH
Conversion time
HSCLK=3.0M to 8.4MHz
―
102
―
tCONV
φ: Period of high-speed clock (HSCLK)
DVDD
Reference
voltage
VREF
VDDL
1μF
10μF
10μF
A
VDDR
AIN0
～
AIN7
RI≤5kΩ
0.1μF
-
10μF
+
Analog input
VSS
26/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact LAPIS SEMICONDUCTOR’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature
and times).
27/29
FEDL610Q380FULL-01
ML610Q380/ML610Q383/ML610Q384/ML610Q385
REVISION HISTORY
Page
Previous
Document No.
Date
Description
Current
Edition
Edition
FEDL610Q380FULL-01 Mar 09, 2012
–
–
Formal edition 1
28/29
FEDL610Q380FULL-01
ML610Q380/ML610Q385
NOTES
No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS
Semiconductor Co., Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be
obtained from LAPIS Semiconductor upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor
shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples of
application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any
license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties.
LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such
technical information.
The Products specified in this document are intended to be used with general-use electronic equipment or
devices (such as audio visual equipment, office-automation equipment, communication devices, electronic
appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such
as derating, redundancy, fire control and fail-safe designs. LAPIS Semiconductor shall bear no responsibility
whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the
instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system which
requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat
to human life or create a risk of human injury (such as a medical instrument, transportation equipment,
aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). LAPIS
Semiconductor shall bear no responsibility in any way for use of any of the Products for the above special
purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales
representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled
under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit
under the Law.
Copyright 2011-2012 LAPIS Semiconductor Co., Ltd.
29/29
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