MT7628 [ETC]
Embedded MIPS24KEc (580 MHz) with 64 KB I-Cache and 32 KB D-cache;
| 型号： | MT7628 |
| 厂家： | 
ETC |
| 描述： | Embedded MIPS24KEc (580 MHz) with 64 KB I-Cache and 32 KB D-cache |
| 文件： | 总53页 (文件大小：1847K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MT7628 DATASHEET
© 2014 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Specifications are subject to change without notice.
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MT7628
Chip Name
Confidential B
Overview
The MT7628 router-on-a-chip includes an 802.11n MAC and baseband, a 2.4 GHz radio and FEM, a 580 MHz
MIPS® 24K™ CPU core, a 5-port 10/100 fast ethernet switch. The MT7628 includes everything needed to build
an AP router from a single chip. The embedded high performance CPU can
Applications:
. Routers
. NAS devices
. Dual band
process advanced applications effortlessly, such as routing, security and VoIP. The
MT7628 also includes a selection of interfaces to support a variety of applications,
such as a USB port for accessing external storage.
Features
concurrent routers
. Embedded MIPS24KEc (580 MHz) with 64 KB I-
Cache and 32 KB D-Cache
. 5-port 10/100 FE PHY
. Internet Of Thing
. An optimized PMU
. Green AP
. 2T2R 2.4 GHz with 300 Mbps PHY data rate
. Legacy 802.11b/g and HT 802.11n modes
. 20/40 MHz channel bandwidth
. Legacy 802.11b/g and HT 802.11n modes
. Reverse Data Grant (RDG)
Intelligent Clock Scaling (exclusive)
DDRII: ODT off, Self-refresh mode
. I2C, I2S, SPI, PCM, UART, JTAG, GPIO
. Maximal Ratio Combining (MRC)
. Space Time Block Coding (STBC)
. MCM 8 Mbytes DDR1 KGD (MT7628KN)
. 16-bit DDR1/2 up to 128/256 Mbytes
(MT7628AN/KN)
. 16 Multiple BSSID
. WEP64/128, TKIP, AES, WPA, WPA2, WAPI
. QoS: WMM, WMM-PS
. WPS: PBC, PIN
. Voice Enterprise: 802.11k+r
. AP Firmware: Linux 2.6 SDK, eCOS with IPv6
. SPI/SD-XC/eMMC
. x1 USB 2.0 Host, x1 PCIe Root Complex
Functional Block Diagram
16-Bit DDR1/DDR2
EJTAG
To CPU
interrupts
INTC
DRAM
Controller
MIPS 24KEc
64 KB I-Cache
32 KB D-Cache
(580 MHz)
Timer
SPI
OCP_IF
OCP Bridge
Arbiter
SPI
NFC
NAND
RBUS (SYS_CLK)
PBUS
UART
GPIO
UART
GPIO
/LED
I2C
I2C
I2S
PCIe 1.1
WLAN
11n 2x2
Switch
(5FE)
Single Port
USB 2.0 PHY
SDHC
GDMA
PHY
I2S
5-Port EPHY
RJ45 x5
PCIe x1
SD
Host X1
PCM x4
PCM
2.4 GHz
Ordering Information
Part Number Package
(Green/RoHS Compliant)
MT7628AN
MT7628KN
DR-QFN 156 pin
(12 mm x 12 mm)
DR-QFN 120 pin
(10 mm x 10 mm)
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© 2014 MediaTek Inc.
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Table of Contents
1. MAIN FEATURES
6
2. PINS
7
2.1 MT7628AN DR-QFN (12 MM X 12 MM) 156-PIN PACKAGE DIAGRAM
7
2.1.1 UP-LEFT SIDE
2.1.2 DOWN-LEFT SIDE
7
8
2.1.3 DOWN-RIGHT SIDE
9
2.1.4 UP-RIGHT SIDE
2.1.5 PIN DESCRIPTION
2.2 MT7628KN DR-QFN (10 MM X 10 MM) 120-PIN PACKAGE DIAGRAM
10
11
17
2.2.1 LEFT SIDE VIE
2.2.2 RIGHT SIDE VIEW
2.2.3 PIN DESCRIPTION
2.3 PIN SHARING SCHEMES
17
19
20
23
2.3.1 GPIO PIN SHARE SCHEME
2.3.2 UART1 PIN SHARE SCHEME
23
26
26
26
26
27
27
27
27
28
28
28
28
28
28
30
30
30
30
30
31
31
2.3.3 MT7628AN EPHY LED PIN SHARE SCHEME
2.3.4 MT7628AN WLAN LED PIN SHARE SCHEME
2.3.5 MT7628KN EPHY LED PIN SHARE SCHEME
2.3.6 MT7628KN WLAN LED PIN SHARE SCHEME
2.3.7 PERST_N PIN SHARE SCHEME
2.3.8 WDT_RST_N PIN SHARE SCHEME
2.3.9 REF_CLKO PIN SHARE SCHEME
2.3.10 UART0 PIN SHARE SCHEME
2.3.11 GPIO0 PIN SHARE SCHEME
2.3.12 SPI PIN SHARE SCHEME
2.3.13 SPI_CS1 PIN SHARE SCHEME
2.3.14 I2C PIN SHARE SCHEME
2.3.15 I2S PIN SHARE SCHEME
2.3.16 SD PIN SHARE SCHEME
2.3.17 UART2 PIN SHARE SCHEME
2.3.18 PWM_CH0 PIN SHARE SCHEME
2.3.19 PWM_CH1 PIN SHARE SCHEME
2.3.20 SPIS PIN SHARE SCHEME
2.3.21 PIN SHARE FUNCTION DESCRIPTION
2.4 BOOTSTRAPPING PINS DESCRIPTION
3. MAXIMUM RATINGS AND OPERATING CONDITIONS
3.1 ABSOLUTE MAXIMUM RATINGS
3.2 MAXIMUM TEMPERATURES
33
33
33
33
33
34
34
34
35
3.3 OPERATING CONDITIONS
3.4 THERMAL CHARACTERISTICS
3.5 STORAGE CONDITIONS
3.6 EXTERNAL XTAL SPECFICATION
3.7 DC ELECTRICAL CHARACTERISTICS
3.8 AC ELECTRICAL CHARACTERISTICS
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© 2014 MediaTek Inc.
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Confidential
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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3.8.1 DDR2 SDRAM INTERFACE
3.8.2 SPI INTERFACE
36
38
39
40
41
42
3.8.3 I2S INTERFACE
3.8.4 PCM INTERFACE
3.8.5 POWER ON SEQUENCE
3.9 PACKAGE PHYSICAL DIMENSIONS
3.9.1 DR-QFN (10 MM X 10 MM) 128 PINS
3.9.2 DR-QFN (12 MM X 12 MM) 156 PINS
3.9.3 MT7628 AN/KN MARKING
42
44
46
48
3.9.4 REFLOW PROFILE GUIDELINE
4. ABBREVIATIONS
49
52
5. REVISION HISTORY
Table of Figures
FIGURE 2-1 MT7628AN DR-QFN PIN DIAGRAM (UP-LEFT VIEW) ...................................................................................... 7
FIGURE 2-2 MT7628AN DR-QFN PIN DIAGRAM (DOWN-LEFT VIEW)................................................................................. 8
FIGURE 2-3 MT7628AN DR-QFN PIN DIAGRAM (DOWN-RIGHT VIEW)............................................................................... 9
FIGURE 2-4 MT7628AN DR-QFN PIN DIAGRAM (UP-RIGHT VIEW).................................................................................. 10
FIGURE 2-5 MT7628KN DR-QFN PIN DIAGRAM (LEFT VIEW) ......................................................................................... 18
FIGURE 2-6 MT7628KN DR-QFN PIN DIAGRAM (RIGHT SIDE VIEW)................................................................................. 19
FIGURE 3-1 DDR2 SDRAM COMMAND ....................................................................................................................... 36
FIGURE 3-2 DDR2 SDRAM WRITE DATA...................................................................................................................... 36
FIGURE 3-3 DDR2 SDRAM READ DATA ....................................................................................................................... 36
FIGURE 3-4 SPI INTERFACE ......................................................................................................................................... 38
FIGURE-3-5 I2S INTERFACE......................................................................................................................................... 39
FIGURE 3-6 PCM INTERFACE....................................................................................................................................... 40
FIGURE 3-7 POWER ON SEQUENCE .............................................................................................................................. 41
FIGURE 3-8 TOP VIEW................................................................................................................................................ 42
FIGURE 3-9 SIDE VIEW ............................................................................................................................................... 42
FIGURE 3-10 “B” EXPANDED....................................................................................................................................... 43
FIGURE 3-11 BOTTON VIEW ........................................................................................................................................ 43
FIGURE 3-12 TOP VIEW.............................................................................................................................................. 44
FIGURE 3-13 SIDE VIEW ............................................................................................................................................. 44
FIGURE 3-14 “B” EXPANDED....................................................................................................................................... 44
FIGURE 3-15 BOTTOM VIEW ....................................................................................................................................... 45
FIGURE 3-16 MT7620AN TOP MARKING...................................................................................................................... 47
FIGURE 3-17 MT7628KN TOP MARKING...................................................................................................................... 47
FIGURE 3-18 REFLOW PROFILE FOR MT7628 ................................................................................................................ 48
List of Tables
TABLE 1-1 MAIN FEATURES........................................................................................................................................... 6
TABLE 3-1 ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 33
TABLE 3-2 MAXIMUM TEMPERATURES.......................................................................................................................... 33
TABLE 3-3 OPERATING CONDITIONS ............................................................................................................................. 33
TABLE 3-4 THERMAL CHARACTERISTICS ......................................................................................................................... 34
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© 2014 MediaTek Inc.
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TABLE 3-5 EXTERNAL XTAL SPECIFICATIONS.................................................................................................................... 34
TABLE 3-6 DC ELECTRICAL CHARACTERISTICS.................................................................................................................. 34
TABLE 3-7 VDD 2.5V ELECTRICAL CHARACTERISTICS ........................................................................................................ 35
TABLE 3-8 VDD 1.8V ELECTRICAL CHARACTERISTICS ........................................................................................................ 35
TABLE 3-9 VDD 3.3V ELECTRICAL CHARACTERISTICS ........................................................................................................ 35
TABLE 3-10 DDR2 SDRAM INTERFACE DIAGRAM KEY.................................................................................................... 37
TABLE 3-11 SPI INTERFACE DIAGRAM KEY..................................................................................................................... 38
TABLE 3-12 I2S INTERFACE DIAGRAM KEY ..................................................................................................................... 39
TABLE 3-13 PCM INTERFACE DIAGRAM KEY .................................................................................................................. 40
TABLE 3-14 POWER ON SEQUENCE DIAGRAM KEY.......................................................................................................... 41
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This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT7628
Chip Name
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1. Main Features
The following table covers the main features offered by the MT7628KN and MT7628AN. Overall, the
MT7628KN supports the requirements of an entry-level AP/router, while the more advanced MT7628AN
supports a number of interfaces together with a large maximum RAM capacity.
Features
MT7628KN
MIPS24KEc (580 MHz)
580 x 1.6 DMIPs
64 KB, 32 KB
MT7628AN
MIPS24KEc (580 MHz)
580 x 1.6 DMIPs
64 KB, 32 KB
CPU
Total DMIPs
I-Cache, D-Cache
L2 Cache
n/a
n/a
Memory
DRAM Device width support 16 bits
16 bits
DDR1
DDR2
64 Mb (MCM), 193 MHz
2 Gb, 193 MHz
2 Gb, 193 MHz
n/a
SPI Flash
3B addr mode (max 128Mbit)
4B addr mode (max 512Mbit)
3B addr mode (max 128Mbit)
4B addr mode (max 512Mbit)
SD
n/a
SD-XC (class 10)
RF
2T2R 802.11n 2.4 GHz
2T2R 802.11n 2.4 GHz
PCIe
USB 2.0
Switch
1
1
1
1
5p FE SW
5p FE SW
I2S
1
1
PCM
I2C
1
1
1
1
UART
JTAG
Package
2 (Lite)
2 (Lite)
1
1
DR-QFN120- 10 mm x 10 mm
DR-QFN156- 12 mm x 12 mm
Table 1-1 Main Features
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2. Pins
2.1 MT7628AN DR-QFN (12 mm x 12 mm) 156-Pin Package Diagram
2.1.1 Up-left side
DR-QFN 12X12
156 pin
156
154
152
150
148
146
144
142
140
138
136
134
155
153
151
149
147
145
143
141
DIG
139
137
135
1
3
AVSS33_RF_1
AVSS33_RF_2
WF0_RFION_1
WF0_RFION_2
WF0_RFIOP_1
WF0_RFIOP_2
AVSS33_RF_3
AVDD33_WF0_TX
WF1_LNA_EXT
AVSS33_RF_4
WF1_RFION
WF1_RFIOP
AVSS33_RF_5
AVDD33_WF1_TX
AVDD33_WF1_TRX
I2S_SDI
I2S_SDO
I2S_WS
2
4
5
6 RF
8
7
9
10
11
13
15
17
19
12
14
16
18
I2S_CLK
Figure 2-1 MT7628AN DR-QFN Pin Diagram (up-left view)
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2.1.2 Down-left side
20
22
24
26
28
30
32
34
36
I2C_SCLK
I2C_SD
SOC_CO_V12D_1
SOC_IO_V33D_1
SPI_CS1
SPI_CLK
SPI_MISO
SPI_MOSI
SPI_CS0
21
23
25
27
29
31
33
35
37
39
DIG
GPIO0
UART_TXD0
UART_RXD0
AVDD33_TX_P0
MDI_RP_P0
MDI_RN_P0
MDI_TP_P0
MDI_TN_P0
NC1
38
AVDD33_COM
EPHY_VRT
EPHY
42
USB
41
43
45
47
49
51
53
55
57
59
61
40
44
46
48
50
52
54
56
58
60
62
Figure 2-2 MT7628AN DR-QFN Pin Diagram (down-left view)
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2.1.3 Down-right side
98
96
DDR_IO_1V8D_2
MA3
MA12
MA7
MA9
MA5
MA10
SOC_CO_V12D_4
DDR_IO_VREF_1
SOC_CO_V12D_3
MA1
MA2
MA6
MA11
MA8
MA13
MA4
MRAS
MA0
DDR_IO_1V8D_2
MBA1
MBA0
MCS
MRAS
MCAS
MWE
SOC_CO_V12D_4
DDR_IO_VREF_1
SOC_CO_V12D_3
MA13
MCKE
MA12
MA11
MA9
MA8
MA7
MA6
MA5
97
95
93
91
89
87
85
83
81
79
94
92
90
88
86
84
82
80
DDR_IO_1V8D_1
DDR_IO_1V8D_1
DDR
71
63
65
67
69
73
75
77
64
66
68
70
72
74
76
78
[ DDR2 ]
[ DDR1 ]
Figure 2-3 MT7628AN DR-QFN Pin Diagram (down-right view)
Note: DR-QFN support DDR1 and DDR2 pin shuffle depend on the bootstrap.
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2.1.4 Up-right side
[ DDR2 ]
[ DDR1 ]
132
130
128
126
124
122
120
118
133
131
129
127
125
123
121
119
PCIE
PMU
117
115
113
111
109
107
105
103
101
99
AVDD33_SMPS
DDR_IO_1V8D_3
DDR_IO_VSS_2
MD14
MDQS0
MD9
MD12
MD11
MD6
MDQM0
MD1
MD4
MD3
DDR_IO_VREF_2
MCKE
MWE
MBA2
MBA0
MBA1
116
114
112
110
108
106
104
102
100
DDR_IO_1V8D_3
DDR_IO_VSS_4
MD0
MDQS0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MDQM0
DDR_IO_VREF_2
MA3
MA2
MA1
MA0
MA10
DDR
Figure 2-4 MT7628AN DR-QFN Pin Diagram (up-right view)
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2.1.5 Pin Description
Pins
RF
Name
Type
Driv.
Description
3,4
WF0_RFION_1
WF0_RFION_2
A
A
WF0 main path RF I/O
WF0 main path RF I/O
5,6
WF0_RFIOP_1
WF0_RFIOP_2
11
WF1_RFION
A
A
A
A
I
WF1 main path RF I/O
12
WF1_RFIOP
WF1 main path RF I/O
9
WF1_LNA_EXT
WF0_LNA_EXT
XTALIN
WF1 aux. path LNA input
WF0 aux. path LNA input
Crystal oscillator input
156
151
153
152
150
8
CLKOUTP
O
P
G
P
P
P
P
P
P
G
XO reference clock output
3.3V XTAL Power Supply Pin
3.3V XTAL Ground Pin
AVDD33_XTAL
AVSS33_XTAL
AVDD33_WF0_TX
AVDD33_WF1_TX
AVDD33_WF1_TRX
AVDD33_WF_RFDIG
AVDD33_WF_SX
AVDD33_WF0_TRX
AVSS33_RF
3.3V RF Channel 0 Suppoly Power
3.3V RF Channel 1 Suppoly Power
14
15
1.65V to 3.3V RF Channel 1 Suppoly Power
1.65V to 3.3V RF DIG and AFE Suppoly Power
1.65V to 3.3V RF Supply Power
149
154
155
1.65V to 3.3V RF Channel 0 Suppoly Power
3.3V RF Shielding Ground Pin
1,2
7,13
WLAN LED
144
WLED_N
O
4 mA
WLAN Activity LED
UART0 Lite
31
30
RXD0
TXD0
I
4 mA
4 mA
UART0 Lite RXD
UART0 Lite TXD
O, IPD
UART1 Lite
147
148
I2S
16
TXD1
O, IPU
I
4 mA
4 mA
UART1 Lite TXD
UART1 Lite RXD
RXD1
I2S_SDI
I2S_SDO
I2S_WS
I2S_CLK
O
4 mA
I2S data input
I2S data output
I2S word select
I2S clock
17
I/O, IPD 4 mA
18
O
4 mA
4 mA
19
I/O
I2C
21
I2C_SD
4 mA
I2C Data
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Pins
20
Name
Type
I/O
Driv.
Description
I2C Clock
I2C_SCLK
4 mA
SPI
26
SPI_MISO
SPI_MOSI
SPI_CLK
SPI_CS0
SPI_CS1
I/O
4 mA
SPI Master input/Slave output
SPI Master output/Slave input
SPI clock
27
I/O, IPD 4 mA
25
O, IPU
O
4 mA
4 mA
4 mA
28
SPI chip select0
24
O, IPD
SPI chip select1
GPIO
29
GPIO0
I/O, IPD 4 mA
General Purpose I/O
5-Port EPHY
143
142
141
140
139
EPHY_LED0 _N_JTDO
I/O
I/O
I/O
I/O
I/O,
4 mA
4 mA
4 mA
4 mA
4 mA
10/100 PHY Port #0 activity LED, JTAG_TDO
10/100 PHY Port #1 activity LED, JTAG_TDI
10/100 PHY Port #2 activity LED, JTAG_TMS
10/100 PHY Port #3 activity LED, JTAG_CLK
10/100 PHY Port #4 activity LED, JTAG_TRST_N
EPHY_LED1 _N_JTDI
EPHY_LED2 _N_JTMS
EPHY_LED3 _N_JTCLK
EPHY_LED4
_N_JTRST_N
39
EPHY_VRT
A
Connect to an external resistor to provide accurate bias
current
33
34
35
36
40
42
43
44
45
46
47
48
49
50
51
52
54
55
56
MDI_RP_P0
MDI_RN_P0
MDI_TP_P0
MDI_TN_P0
MDI_TP_P1
MDI_TN_P1
MDI_RP_P1
MDI_RN_P1
MDI_RP_P2
MDI_RN_P2
MDI_TP_P2
MDI_TN_P2
MDI_TP_P3
MDI_TN_P3
MDI_RP_P3
MDI_RN_P3
MDI_RP_P4
MDI_RN_P4
MDI_TP_P4
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
10/100 PHY Port #0 RXN
10/100 PHY Port #0 RXP
10/100 PHY Port #0 TXN
10/100 PHY Port #0 TXP
10/100 PHY Port #1 RXN
10/100 PHY Port #1 RXP
10/100 PHY Port #1 TXN
10/100 PHY Port #1 TXP
10/100 PHY Port #2 RXN
10/100 PHY Port #2 RXP
10/100 PHY Port #2 TXN
10/100 PHY Port #2 TXP
10/100 PHY Port #3 RXN
10/100 PHY Port #3 RXP
10/100 PHY Port #3 TXN
10/100 PHY Port #3 TXP
10/100 PHY Port #4 RXN
10/100 PHY Port #4 RXP
10/100 PHY Port #4 TXN
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Pins
57
Name
Type
Driv.
Description
MDI_TN_P4
AVDD33_TX_P0
AVDD33_COM
A
P
P
P
10/100 PHY Port #4 TXP
3.3V Supply Power for P0
3.3V Supply Power for EPHY COM
3.3V Supply Power for P1 ~ P4
32
38
41
AVDD33_TX_P1234_1
AVDD33_TX_P1234_2
Misc.
136
REF_CLKO
PORST_N
O, IPD
I, IPU
O
4 mA
4 mA
4 mA
Reference Clock Ouptut
Power on reset
138
137
WDT_RST_N
Watchdog timeout reset
USB PHY
129
130
AVDD33_USB
P
3.3 V USB PHY analog power supply
USB _VRT
I/O
Connect to an external 5.1 kΩ resistor for band-gap
reference circuit
62
61
USB_DM
USB _DP
I/O
I/O
USB Port0 data pin Data-
USB Port0 data pin Data+
PCIe PHY
135
134
129
128
133
132
127
126
129
130
DDR2
65
PERST_N
O, IPD
P
4mA
PCIe device reset
AVDD12_PCIE
AVDD33_PCIE
PCIE_IO_VSS
PCIE_CKP0
PCIE_CKN0
PCIE_TXP0
1.2 V PCIE PHY digital power supply
3.3 V USB PHY analog power supply
PCIE PHY Ground Pin
P
P
I/O
I/O
I/O
I/O
I/O
I/O
External reference clock output (positive)
External reference clock output (negative)
PCIe0 differential transmit TX -
PCIe0 differential transmit TX -
PCIe0 differential receiver RX -
PCIe0 differential receiver RX -
PCIE_TXN0
PCIE_TXP0
PCIE_TXN0
MD15
MD14
MD13
MD12
MD11
MD10
MD9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
DDR2 Data bit #15
DDR2 Data bit #14
DDR2 Data bit #13
DDR2 Data bit #12
DDR2 Data bit #11
DDR2 Data bit #10
DDR2 Data bit #9
DDR2 Data bit #8
DDR2 Data bit #7
DDR2 Data bit #6
114
67
111
110
68
112
66
MD8
70
MD7
109
MD6
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MT7628
Chip Name
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Pins
73
Name
MD5
Type
I/O
I/O
I/O
I/O
I/O
I/O
O
Driv.
Description
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
DDR2 Data bit #5
DDR2 Data bit #4
DDR2 Data bit #3
DDR2 Data bit #2
DDR2 Data bit #1
DDR2 Data bit #0
DDR2 Address bit #13
DDR2 Address bit #12
DDR2 Address bit #11
DDR2 Address bit #10
DDR2 Address bit #9
DDR2 Address bit #8
DDR2 Address bit #7
DDR2 Address bit #6
DDR2 Address bit #5
DDR2 Address bit #4
DDR2 Address bit #3
DDR2 Address bit #2
DDR2 Address bit #1
DDR2 Address bit #0
DDR2 MBA #2
106
105
69
MD4
MD3
MD2
107
71
MD1
MD0
83
MA13
MA12
MA11
MA10
MA9
96
O
85
O
92
O
94
O
84
MA8
O
95
MA7
O
86
MA6
O
93
MA5
O
82
MA4
O
97
MA3
O
87
MA2
O
88
MA1
O
80
MA0
O
101
99
MBA2
MBA1
MBA0
MODT
MRAS
MCAS
MWE
MCK_P
MCK_N
MDQM1
MDQM0
MCS
O
O
DDR2 MBA #1
100
74
O
DDR2 MBA #0
O
DDR2 ODT
81
O
DDR2 MRAS_N
75
O
DDR2 MCAS_N
102
77
O
DDR2 MWE_N
O
DDR2 MCK_P
76
O
DDR2 MCK_N
64
O
DDR2 MDQM#1
DDR2 MDQM#0
DDR2 MCS
108
78
O
O
72
MDQS1
MDQS0
MCKE
I/O
I/O
O
DDR2 MDQS#1
113
103
DDR2 MDQS#0
DDR2 MCKE
63
115
DDR_IO_VSS_1
DDR_IO_VSS_2
G
DDR IO Ground pins
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MT7628
Chip Name
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Pins
Name
Type
P
Driv.
Description
79
98
116
DDR_IO_1V8D_1
DDR_IO_1V8D_2
DDR_IO_1V8D_3
DDR io Supply power
90
104
DDR_IO_VREF_1
DDR_IO_VREF_2
A
DDR reference voltage
DDR1
64
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MA13
MA12
MA11
MA10
MA9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
DDR1 Data bit #15
DDR1 Data bit #14
DDR1 Data bit #13
DDR1 Data bit #12
DDR1 Data bit #11
DDR1 Data bit #10
DDR1 Data bit #9
65
66
67
68
69
70
71
DDR1 Data bit #8
106
107
108
109
110
111
112
114
88
DDR1 Data bit #7
DDR1 Data bit #6
DDR1 Data bit #5
DDR1 Data bit #4
DDR1 Data bit #3
DDR1 Data bit #2
DDR1 Data bit #1
DDR1 Data bit #0
DDR1 Address bit #13
DDR1 Address bit #12
DDR1 Address bit #11
DDR1 Address bit #10
DDR1 Address bit #9
DDR1 Address bit #8
DDR1 Address bit #7
DDR1 Address bit #6
DDR1 Address bit #5
DDR1 Address bit #4
DDR1 Address bit #3
DDR1 Address bit #2
DDR1 Address bit #1
DDR1 Address bit #0
DDR1 MBA #1
86
O
85
O
99
O
84
O
83
MA8
O
82
MA7
O
81
MA6
O
80
MA5
O
74
MA4
O
103
102
101
100
97
MA3
O
MA2
O
MA1
O
MA0
O
MBA1
O
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MT7628
Chip Name
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Pins
96
Name
Type
O
Driv.
Description
MBA0
MRAS
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
DDR1 MBA #0
DDR1 MRAS_N
DDR1 MCAS_N
DDR1 MWE_N
DDR1 MCK_P
DDR1 MCK_N
DDR1 MDQM#1
DDR1 MDQM#0
DDR1 MCS
94
O
93
MCAS
O
92
MWE
O
77
MCK_P
MCK_N
MDQM1
MDQM0
MCS
O
76
O
73
O
105
95
O
O
72
MDQS1
MDQS0
MCKE
I/O
I/O
O
DDR1 MDQS#1
DDR1 MDQS#0
DDR1 MCKE
113
87
63
75
78
115
DDR_IO_VSS_1
DDR_IO_VSS_2
DDR_IO_VSS_3
DDR_IO_VSS_4
G
DDR IO Ground pins
79
98
116
DDR_IO_1V8D_1
DDR_IO_1V8D_2
DDR_IO_1V8D_3
P
DDR IO Supply power
DDR reference voltage
90
104
DDR_IO_VREF_1
DDR_IO_VREF_2
A
PMU
118
119
LXBK_1
LXBK_2
O
Buck Switching node
122
59
VOUT_FB
A
P
Buck vout feedback pin
Buck 3.3V Supply power
Buck Gound pin
AVDD33_SMPS
120
121
AVSS33_SMPS_1
AVSS33_SMPS_2
G
123
124
AVDD33_DDRLDO_1
AVDD33_DDRLDO_2
G
O
DDRLDO 3.3V Supply power
56
DDRLDO
DDRLDO 1.8V/2.5V output voltage
Power
23
146
SOC_IO_V33D_1
SOC_IO_V33D_2
P
P
3.3 V digital I/O power supply
1.2 V digital core power supply
22
58
89
91
145
SOC_CO _V12D_1
SOC_CO _V12D_2
SOC_CO _V12D_3
SOC_CO _V12D_4
SOC_CO _V12D_5
EPAD GND
G
Ground pin
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MT7628
Chip Name
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Pins
Name
Type
Driv.
Description
Total: 156 pins
Note:
IPD : Internal pull-down
IPU : Internal pull-up
I
: Input
O
: Output
IO : Bi-directional
P
: Power
G
: Ground
NC : Not connected
2.2 MT7628KN DR-QFN (10 mm x 10 mm) 120-Pin Package Diagram
2.2.1 Left side vie
DR-QFN 10X10
120 pin
120
118
116
114
112
110
108
106
107 105
119
117
115
113
111
109
DIG
1
WF0_LNA_EXT
WF0_RFION_1
WF0_RFION_2
WF0_RFIOP_1
WF0_RFIOP_2
AVDD33_WF0_TX
WF1_LNA_EXT
WF1_RFION_1
WF1_RFION_2
WF1_RFIOP_1
WF1_RFIOP_2
AVDD33_WF1_TX
AVDD33_WF1_TRX
I2S_SDI
2
3
4
5
6 RF
8
7
9
10
11
13
15
17
19
21
23
25
27
29
12
14
16
18
20
22
24
26
28
I2S_SDO
I2S_WS
I2S_CLK
I2C_SCLK
I2C_SD
SOC_CO_V12D_1
SOC_IO_V33D_1
SPI_CS1
SPI_CLK
SPI_MISO
SPI_MOSI
SPI_CS0
GPIO0
UART_TXD0
UART_RXD0
DIG
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Confidential
This document contains information that is proprietary to MediaTek Inc.
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MT7628
Chip Name
Confidential B
30
AVDD33_TX_P0
EPHY
43
32
34
36
38
40
42
44
46
45
31
33
35
37
39
41
Figure 2-5 MT7628KN DR-QFN Pin Diagram (left view)
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MT7628
Chip Name
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2.2.2 Right side view
104
102
100
98
96
94
92
103
101
99
97
95
93
91
PCIE
PMU
90
88
86
84
82
80
78
76
74
72
70
68
66
64
62
61
LXBK_2
LXBK_1
AVDD33_SMPS_2
AVDD33_SMPS_1
SOC_IO_V33D_2
WLED_N
PMU
DIG
89
87
85
83
81
79
77
75
73
71
69
EPHY_LED0_N_JTDO
EPHY_LED1_N_JTDI
EPHY_LED2_N_JTMS
EPHY_LED3_N_JTCLK
EPHY_LED4_N_JTRST_N
DDR_IO_1V8D_4
DDR_IO_1V8D_3
DDR_IO_VREF_3
DDR_IO_VREF_2
SOC_CO_V12D_7
SOC_CO_V12D_6
DDR_IO_VREF_1
SOC_CO_V12D_5
SOC_CO_V12D_4
NC5
DDR
NC4
NC3
67
DDR_IO_1V8D_2
DDR_IO_1V8D_1
NC2
NC1
DDR_IO_VSS_3
DDR_IO_VSS_2
65
63
DDR_IO_VSS_1
USB
59
48
50
52
54
56
58
47
49
51
53
55
57
60
Figure 2-6 MT7628KN DR-QFN Pin Diagram (right side view)
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MT7628
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2.2.3 Pin Description
Pins
Name
Type
Driv.
Description
RF
2
3
WF0_RFION_1
WF0_RFION_2
A
A
A
A
WF0 main path RF I/O
WF0 main path RF I/O
WF1 main path RF I/O
WF1 main path RF I/O
4
5
WF0_RFIOP_1
WF0_RFIOP_2
8
9
WF1_RFION_1
WF1_RFION_2
10
11
WF1_RFIOP_1
WF1_RFIOP_2
7
WF1_LNA_EXT
WF0_LNA_EXT
XTALIN
A
A
I
WF1 aux. path LNA input
WF0 aux. path LNA input
Crystal oscillator input
1
116
118
114
CLKOUTP
O
P
G
XO reference clock output
3.3V XTAL Power Supply Pin
3.3V XTAL Ground Pin
AVDD33_XTAL
115
117
AVS33_XTAL_1
AVS33_XTAL_2
6
AVDD33_WF0_TX
AVDD33_WF1_TX
AVDD33_WF1_TRX
AVDD33_WF_RFDIG
AVDD33_WF_SX
P
P
P
P
P
P
3.3V RF Channel 0 Suppoly Power
3.3V RF Channel 1 Suppoly Power
12
13
1.65V to 3.3V RF Channel 1 Suppoly Power
1.65V to 3.3V RF DIG and AFE Suppoly Power
1.65V to 3.3V RF Supply Power
113
119
120
AVDD33_WF0_TRX
1.65V to 3.3V RF Channel 0 Suppoly Power
WLAN LED
85
WLED_N
O
4 mA
4 mA
WLAN Activity LED
UART0 Lite
28
29
TXD0
RXD0
O, IPD
I
UART0 Lite TXD
UART0 Lite RXD
UART1 Lite
111
112
I2S
14
TXD1
O, IPU
I
4 mA
UART1 Lite TXD
UART1 Lite RXD
RXD1
I2S_SDI
I2S_SDO
I2S_WS
I2S_CLK
I/O
4 mA
4 mA
4 mA
4 mA
I2S data input
I2S data output
I2S word select
I2S clock
15
O, IPD
O
16
17
I/O
I2C
19
I2C_SD
I/O
4 mA
I2C Data
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Pins
18
Name
Type
I/O
Driv.
Description
I2C Clock
I2C_SCLK
4 mA
SPI
24
SPI_MISO
SPI_MOSI
SPI_CLK
SPI_CS0
SPI_CS1
I/O
4 mA
SPI Master input/Slave output
SPI Master output/Slave input
SPI clock
25
I/O, IPD 4 mA
22
O, IPU
O
4 mA
4 mA
4 mA
26
SPI chip select0
22
O, IPD
SPI chip select1
GPIO
27
GPIO0
I/O, IPD 4 mA
General Purpose I/O
5-Port EPHY
84
83
82
81
80
EPHY_LED0 _N_JTDO
I/O
I/O
I/O
I/O
I/O,
4 mA
4 mA
4 mA
4 mA
4 mA
10/100 PHY Port #0 activity LED, JTAG_TDO
10/100 PHY Port #1 activity LED, JTAG_TDI
10/100 PHY Port #2 activity LED, JTAG_TMS
10/100 PHY Port #3 activity LED, JTAG_CLK
10/100 PHY Port #4 activity LED, JTAG_TRST_N
EPHY_LED1 _N_JTDI
EPHY_LED2 _N_JTMS
EPHY_LED3 _N_JTCLK
EPHY_LED4
_N_JTRST_N
35
EPHY_VRT
A
Connect to an external resistor to provide accurate bias
current
31
32
33
34
37
39
40
41
42
43
44
45
46
47
48
49
51
52
53
MDI_RP_P0
MDI_RN_P0
MDI_TP_P0
MDI_TN_P0
MDI_TP_P1
MDI_TN_P1
MDI_RP_P1
MDI_RN_P1
MDI_RP_P2
MDI_RN_P2
MDI_TP_P2
MDI_TN_P2
MDI_TP_P3
MDI_TN_P3
MDI_RP_P3
MDI_RN_P3
MDI_RP_P4
MDI_RN_P4
MDI_TP_P4
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
10/100 PHY Port #0 RXN
10/100 PHY Port #0 RXP
10/100 PHY Port #0 TXN
10/100 PHY Port #0 TXP
10/100 PHY Port #1 RXN
10/100 PHY Port #1 RXP
10/100 PHY Port #1 TXN
10/100 PHY Port #1 TXP
10/100 PHY Port #2 RXN
10/100 PHY Port #2 RXP
10/100 PHY Port #2 TXN
10/100 PHY Port #2 TXP
10/100 PHY Port #3 RXN
10/100 PHY Port #3 RXP
10/100 PHY Port #3 TXN
10/100 PHY Port #3 TXP
10/100 PHY Port #4 RXN
10/100 PHY Port #4 RXP
10/100 PHY Port #4 TXN
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Pins
54
Name
Type
Driv.
Description
MDI_TN_P4
AVDD33_TX_P0
AVDD33_COM
A
P
P
P
10/100 PHY Port #4 TXP
3.3V Supply Power for P0
3.3V Supply Power for EPHY COM
3.3V Supply Power for P1 ~ P4
30
36
38
50
AVDD33_TX_P1234_1
AVDD33_TX_P1234_2
Misc.
106
REF_CLKO
PORST_N
O, IPD
4 mA
4 mA
Reference Clock Ouptut
Power on reset
108
I
107
WDT_RST_N
O
Watchdog Reset
USB PHY
58
57
AVDD33_USB
P
3.3 V USB PHY analog power supply
USB _VRT
A
Connect to an external 5.1 kΩ resistor for band-gap
reference circuit
60
59
USB_DM
USB _DP
I/O
I/O
USB Port0 data pin Data-
USB Port0 data pin Data+
PCIe PHY
105
98
PERST_N
O, IPD
G
4mA
PCIe device reset
PCIE_IO_VSS
AVDD12_PCIE
AVDD33_PCIE
PCIE_CKP0
PCIE_CKN0
PCIE_TXP0
PCIe Ground pin
101
104
103
102
97
P
1.2 V PCIE PHY digital power supply
3.3 V USB PHY analog power supply
External reference clock output (positive)
External reference clock output (negative)
PCIe0 differential transmit TX -
PCIe0 differential transmit TX -
PCIe0 differential receiver RX -
PCIe0 differential receiver RX -
P
O
O
I/O
I/O
I/O
I/O
96
PCIE_TXN0
PCIE_RXP0
PCIE_RXN0
99
100
PMU
89
90
LXBK_1
LXBK_2
O
Buck Switching node
93
VOUT_FB
A
P
Buck vout feedback pin
Buck 3.3V Supply power
87
88
AVDD33_SMPS_1
AVDD33_SMPS_2
91
92
AVSS33_SMPS_1
AVSS33_SMPS_2
G
Buck Gound pin
94
AVDD33_DDRLDO
DDRLDO
P
DDRLDO 3.3V Supply power
95
O
DDRLDO 1.8V/2.5V output voltage
Power
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Pins
Name
Type
P
Driv.
Description
21
86
110
SOC_IO_V33D_1
SOC_IO_V33D_2
SOC_IO_V33D_3
3.3 V digital I/O power supply
20
55
56
71
72
74
75
109
SOC_CO _V12D_1
SOC_CO _V12D_2
SOC_CO _V12D_3
SOC_CO _V12D_4
SOC_CO _V12D_5
SOC_CO _V12D_6
SOC_CO _V12D_7
SOC_CO _V12D_8
P
1.2 V digital core power supply
EPAD GND
G
Ground pin
Total: 120 pins
Note:
IPD : Internal pull-down
IPU : Internal pull-up
I
: Input
O
: Output
IO : Bi-directional
P
: Power
G
: Ground
NC : Not connected
2.3 Pin Sharing Schemes
Some pins are shared with GPIO to provide maximum flexibility for system designers. The MT7628 provides up
to 41 GPIO pins. Users can configure GPIO1_MODE and GPIO2_MODE registers in the System Control block to
specify the pin function, or they can use the registers specified below. For more information, see the
Programmer’s Guide. Unless specified explicitly, all the GPIO pins are in input mode after reset.
2.3.1 GPIO pin share scheme
I/O Pad Group
Normal Mode
GPIO Mode
GPIO#46
GPIO#45
GPIO#44
GPIO#43
GPIO#42
GPIO#41
GPIO#40
GPO#39
GPO#38
GPIO#37
UART1
UART_RXD1
UART_TXD1
WLED_AN
P0_LED_AN
P1_LED_AN
P2_LED_AN
P3_LED_AN
P4_LED_AN
WDT
WLED_N (7628AN)
EPHY_LED0_N_JTDO (7628AN)
EPHY_LED1_N_JTDI (7628AN)
EPHY_LED2_N_JTMS (7628AN)
EPHY_LED3_N_JTCLK (7628AN)
EPHY_LED4_N_JTRST_N (7628AN)
WDT_RST_N
REFCLK
REF_CLKO
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I/O Pad Group
PERST
Normal Mode
PERST_N
GPIO Mode
GPIO#36
GPIO#35
GPIO#34
GPIO#33
GPIO#32
GPIO#31
GPIO#30
GPIO#29
GPIO#28
GPIO#27
GPIO#26
GPIO#25
GPIO#24
GPIO#23
GPIO#22
GPIO#21
GPIO#20
GPO#19
GPO#18
GPIO#17
GPIO#16
GPO#15
GPIO#14
GPIO#13
GPIO#12
GPIO#11
GPIO#10
GPIO#9
WLED_KN
P0_LED_KN
P1_LED_KN
P2_LED_KN
P3_LED_KN
P4_LED_KN
SD
WLED_N (7628KN)
EPHY_LED0_N_JTDO (7628KN)
EPHY_LED1_N_JTDI (7628KN)
EPHY_LED2_N_JTMS (7628KN)
EPHY_LED3_N_JTCLK (7628KN)
EPHY_LED4_N_JTRST_N (7628KN)
MDI_TN_P4
MDI_TP_P4
MDI_RN_P4
MDI_RP_P4
MDI_RN_P3
MDI_RP_P3
MDI_TN_P3
MDI_TP_P3
UART2
MDI_TN_P2
MDI_TP_P2
PWM1
PWM0
SPIS
MDI_RN_P2
MDI_RP_P2
MDI_RN_P1
MDI_RP_P1
MDI_TN_P1
MDI_TP_P1
UART0
UART_RXD0
UART_TXD0
GPIO
SPI
GPIO0
SPI_CS0
SPI_MISO
SPI_MOSI
GPIO#8
SPI_CLK
GPIO#7
SPI_CS1
I2C
SPI_CS1
GPIO#6
I2C_SD
GPO#5
I2C_SCLK
GPO#4
I2S
I2S_CLK
GPIO#3
I2S_WS
GPIO#2
I2S_SDO
GPIO#1
I2S_SDI
GPO#0
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2.3.2 UART1 pin share scheme
Controlled by the UART1_MODE register.
Pin Name
2’b00
UART-Lite #1
2’b01
GPIO
2’b10
PWM
2’b11
TRX_SW
UART1_RXD
UART1_TXD
UART1_RXD
UART1_TXD
GPIO#46
GPIO#45
PWM_CH1
PWM_CH0
2.3.3 MT7628AN EPHY LED pin share scheme
Controlled by the P#_LED_AN_MODE registers
Pin Name
Bootstrapping
Bootstrapping
(DBG_JTAG_MODE=1)
(DBG_JTAG_MODE=0)
P4_LED_AN_MODE
=2’b00
P4_LED_AN_MODE
=2’b01
EPHY_LED4_N_JTRST_N JTAG_RST_N
EPHY_LED4_N
GPIO#39
P3_LED_AN_MODE
P3_LED_AN_MODE
=2’b00
=2’b01
EPHY_LED3_N_JTCLK
EPHY_LED2_N_JTMS
EPHY_LED1_N_JTDI
EPHY_LED0_N_JTDO
JTAG_CLK
JTAG_TMS
JTAG_TDI
JTAG_TDO
EPHY_LED3_N
GPIO#40
P2_LED_AN_MODE
=2’b00
P2_LED_AN_MODE
=2’b01
EPHY_LED2_N
GPIO#41
P1_LED_AN_MODE
=2’b00
P1_LED_AN_MODE
=2’b01
EPHY_LED1_N
GPIO#42
P0_LED_AN_MODE
=2’b00
P0_LED_AN_MODE
=2’b01
EPHY_LED0_N
GPIO#43
2.3.4 MT7628AN WLAN LED pin share scheme
Controlled by the WLED_AN_MODE registers
Pin Name
2’b00
2’b01
WLED_N
WLED_N
GPIO#44
2.3.5 MT7628KN EPHY LED pin share scheme
Controlled by the P#_LED_KN_MODE registers
Pin Name
Bootstrapping
Bootstrapping
(DBG_JTAG_MODE=1)
(DBG_JTAG_MODE=0)
P4_LED_KN_MODE
=2’b00
P4_LED_KN_MODE
=2’b01
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Pin Name
Bootstrapping
Bootstrapping
(DBG_JTAG_MODE=1)
(DBG_JTAG_MODE=0)
P4_LED_KN_MODE
=2’b00
P4_LED_KN_MODE
=2’b01
EPHY_LED4_N_JTRST_N JTAG_RST_N
EPHY_LED4_N
GPIO#30
P3_LED_KN_MODE
P3_LED_KN_MODE
=2’b00
=2’b01
EPHY_LED3_N_JTCLK
EPHY_LED2_N_JTMS
EPHY_LED1_N_JTDI
EPHY_LED0_N_JTDO
JTAG_CLK
JTAG_TMS
JTAG_TDI
JTAG_TDO
EPHY_LED3_N
GPIO#31
P2_LED_KN_MODE
=2’b00
P2_LED_KN_MODE
=2’b01
EPHY_LED2_N
GPIO#32
P1_LED_KN_MODE
=2’b00
P1_LED_KN_MODE
=2’b01
EPHY_LED1_N
GPIO#33
P0_LED_KN_MODE
=2’b00
P0_LED_KN_MODE
=2’b01
EPHY_LED0_N
GPIO#34
2.3.6 MT7628KN WLAN LED pin share scheme
Controlled by the WLED_KN_MODE registers
Pin Name
2’b00
2’b01
WLED_N
WLED_N
GPIO#35
2.3.7 PERST_N pin share scheme
Controlled by the PERST_ MODE register.
Pin Name
1’b0
1’b1
PERST_N
PERST_N
GPIO#36
2.3.8 WDT_RST_N pin share scheme
Controlled by the WDT _MODE register.
Pin Name
1’b0
1’b1
WDT_RST_N
WDT_RST_N
GPIO#37
2.3.9 REF_CLKO pin share scheme
Controlled by the REFCLK _MODE register.
Pin Name
1’b0
1’b1
REF_CLKO
REF_CLKO
GPIO#38
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2.3.10 UART0 pin share scheme
Controlled by the UART0 _MODE register.
Pin Name
1’b0
1’b1
UART_TXD0
UART_TXD0
UART_TXD0
UART_RXD0
GPIO#12
GPIO#13
2.3.11 GPIO0 pin share scheme
Controlled by GPIO_MODE register.
Pin Name
2’b00
2’b01
2’b10
REF_CLKO
2’b11
GPIO0
GPIO#11
GPIO#11
PERST_N
2.3.12 SPI pin share scheme
Controlled by SPI_ MODE register.
Pin Name
SPI_CLK
1’b0
1’b1
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_CS0
GPO#7
GPO#8
GPIO#9
GPIO#10
SPI_MOSI
SPI_MISO
SPI_CS0
2.3.13 SPI_CS1 pin share scheme
Controlled by SPI_CS1_MODE register.
Pin Name
2’b00
2’b01
2’b10
SPI_CS1
SPI_CS1
GPIO#6
REF_CLKO
2.3.14 I2C pin share scheme
Controlled by I2C_MODE register.
Pin Name
I2C_SCLK
I2C_SD
2’b00
2’b01
I2C_SCLK
I2C_SD
GPIO#4
GPIO#5
2.3.15 I2S pin share scheme
Controlled by I2S_MODE register.
Pin Name
I2S_SDI
2’b00
2’b01
2’b10
I2C_SCLK
I2C_SD
I2C_SCLK
I2C_SD
GPIO#0
GPIO#1
GPIO#2
GPIO#3
PCMDRX
PCMDTX
PCMCLK
PCMFS
I2S_SDO
I2S_WS
I2S_CLK
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2.3.16 SD pin share scheme
Controlled by the EPHY_APGIO_AIO_EN[4:1] and SD_MODE registers
EPHY_APGIO_AIO_EN[4:1]
=4’b0000
EPHY_APGIO_AIO_EN[4:1]
=4’b1111
Pin Name
SD_MODE
SD_MODE
=2’b00
=2’b01
MDI_TP_P3
MDI_TN_P3
MDI_RP_P3
MDI_RN_P3
MDI_RP_P4
MDI_TN_P4
MDI_RN_P4
MDI_TP_P4
MDI_TP_P3
MDI_TN_P3
MDI_RP_P3
MDI_RN_P3
MDI_RP_P4
MDI_TN_P4
MDI_RN_P4
MDI_TP_P4
SD_WP
SD_CD
SD_D1
SD_D0
SD_CLK
SD_D2
SD_CMD
SD_D3
GPIO#22
GPIO#23
GPIO#24
GPIO#25
GPIO#26
GPIO#27
GPIO#28
GPIO#29
2.3.17 UART2 pin share scheme
Controlled by the EPHY_APGIO_AIO_EN[4:1] and UART2_MODE registers
4’b0000
4’b1111
2’b00
Pin Name
2’b01
2’b10
2’b11
MDI_TP_P2
MDI_TN_P2
MDI_TP_P2
MDI_TN_P2
UART_TXD2
GPIO#20
PWM_CH2 SD_D5
PWM_CH3 SD_D4
UART_RXD2 GPIO#21
2.3.18 PWM_CH0 pin share scheme
Controlled by the EPHY_APGIO_AIO_EN[4:1] and PWM0_MODE registers
4’b0000
4’b1111
2’b00
Pin Name
2’b01
2’b10
2’b10
2’b10
2’b11
MDI_RP_P2
MDI_RP_P2
PWM_CH0
GPIO#18
SD_D7
2.3.19 PWM_CH1 pin share scheme
Controlled by the EPHY_APGIO_AIO_EN[4:1] and PWM1_MODE registers
4’b0000
4’b1111
2’b00
Pin Name
2’b01
2’b11
MDI_RN_P2
MDI_RN_P2
PWM_CH1
GPIO#19
SD_D6
2.3.20 SPIS pin share scheme
Controlled by the EPHY_APGIO_AIO_EN[4:1] and SPIS_MODE registers
4’b0000
4’b1111
2’b00
Pin Name
2’b01
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4’b0000
4’b1111
2’b00
Pin Name
2’b01
2’b10
2’b11
MDI_TP_P1
MDI_TN_P1
MDI_RP_P1
MDI_RN_P1
MDI_TP_P1
MDI_TN_P1
MDI_RP_P1
MDI_RN_P1
SPIS_CS
GPIO#14
GPIO#15
GPIO#16
GPIO#17
PWM_CH0
PWM_CH1
UART_TXD2
UART_RXD2
SPIS_CLK
SPIS_MISO
SPIS_MOSI
2.3.21 Pin share function description
Pin Share Name
I/O Pin Share Function description
PCMDTX
O
PCM Data Transmit
DATA signal sent from the PCM host to the external codec.
PCMDRX
PCMCLK
I
PCM Data Receive
DATA signal sent from the external codec to the PCM host.
I/O PCM Clock
The clock signal can be generated by the PCM host (Output direction), or
provided by an external clock (input direction). The clock frequency should match
the slot configuration of the PCM host.
e.g.
4 slots, PCM clock out/in should be 256 kHz.
8 slots, PCM clock out/in should be 512 kHz.
16 slots, PCM clock out/in should be 1.024 MHz.
32 slots, PCM clock out/in should be 2.048 MHz.
64 slots, PCM clock out/in should be 4.096 MHz.
128 slots, PCM clock out/in should be 8.192 MHz.
PCMFS
I/O PCM SYNC signal.
In our design, the direction of this signal is independent of the direction of
PCMCLK. Its direction and mode is configurable.
PWM_CH0
PWM_CH1
PWM_CH2
PWM_CH3
O
O
O
O
Pulse Width Modulation Channle 0
Pulse Width Modulation Channle 1
Pulse Width Modulation Channle 2
Pulse Width Modulation Channle 3
2.4 Bootstrapping Pins Description
Pin Name
Boot Strapping Signal
Name
Description
UART_TXD1 DBG_JTAG_MODE
0: JTAG_MODE
1: EPHY_LED (default)
PERST_N XTAL_FREQ_SEL
0: 25 MHz DIP
1: 40 MHz SMD
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Pin Name
Boot Strapping Signal
Name
Description
I2S_SDO
DRAM_TYPE
1: DDR1
0: DDR2
[note] This pin is valid for MT7628AN only. It needs to be pull-low for
7628KN which only supports DDR1.
{SPI_CS1
SPI_CLK,
SPI_MOSI}
CHIP_MODE[2:0]
A vector to set chip function/test/debug modes.
000: Boot from PLL (boot from SPI 3-Byte Addr)
001: Boot from PLL (boot from SPI 4-Byte Addr)
010: Boot from XTAL (boot from SPI 3-Byte Addr)
011: Boot from XTAL (boot from SPI 4-Byte Addr)
PAD_TXD0
EXT_BGCK
1: Test Mode
0: Normal (default)
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3. Maximum Ratings and Operating Conditions
3.1 Absolute Maximum Ratings
I/O supply voltage
3.63 V
Input, Output, or I/O Voltage
GND -0.3 V to Vcc +0.3 V
Table 3-1 Absolute Maximum Ratings
3.2 Maximum Temperatures
Maximum Junction Temperature (Plastic Package)
Maximum Lead Temperature (Soldering 10 s)
125 °C
260 °C
Table 3-2 Maximum Temperatures
3.3 Operating Conditions
I/O supply voltage
3.3 V +/- 10%
2.5 V +/- 5%
1.8 V +/- 5%
1.2 V +/- 10%
-20 to 55 °C
DDR1 supply voltage
DDR2 supply voltage
Core supply voltage
Ambient Temperature Range
Table 3-3 Operating Conditions
3.4 Thermal Characteristics
Thermal characteristics without an external heat sink in still air conditions.
MT7628KN:
Thermal Resistance θJA (°C /W) for JEDEC 2L system PCB
26.1°C/W
17.72°C/W
6.5°C/W
Thermal Resistance θJA (°C /W) for JEDEC 4L system PCB
Thermal Resistance θJC (°C /W) for JEDEC
Thermal Resistance ψJt (°C /W) for JEDEC 2L system PCB
Thermal Resistance ψJt (°C /W) for JEDEC 4L system PCB
1.81°C/W
1.18°C/W
MT7628AN:
Thermal Resistance θJA (°C /W) for JEDEC 2L system PCB
27.01°C/W
18.15°C/W
6.9°C/W
Thermal Resistance θJA (°C /W) for JEDEC 4L system PCB
Thermal Resistance θJC (°C /W) for JEDEC
Thermal Resistance ψJt (°C /W) for JEDEC 2L system PCB
Thermal Resistance ψJt (°C /W) for JEDEC 4L system PCB
2.41 °C/W
1.51 °C/W
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Table 3-4 Thermal Characteristics
3.5 Storage Conditions
The calculated shelf life in a sealed bag is 12 months if stored between 0 °C and 40 °C at less than 90% relative
humidity (RH). After the bag is opened, devices that are subjected to solder reflow or other high temperature
processes must be handled in the following manner:
.
.
.
Mounted within 168 hours of factory conditions, i.e. < 30 °C at 60% RH.
Storage humidity needs to maintained at < 10% RH.
Baking is necessary if the customer exposes the component to air for over 168 hrs, baking conditions: 125
°C for 8 hrs.
3.6 External Xtal Specfication
Frequency
Frequency offset
VIH/VIL
25 MHz/ 40 Mhz
+/-20 ppm
Vcc-0.3 V/0.3 V
45% to 55%
Duty cycle
Table 3-5 External Xtal Specifications
3.7 DC Electrical Characteristics
Parameters
Sym
Vddc33
Vdd25
Vdd18
Vdd12
Icc33
Conditions
Min
2.97
2.375
1.71
1.08
Typ
3.3
2.5
1.8
1.2
Max
3.63
2.625
1.89
1.32
Unit
V
3.3 V supply voltage (IO)
2.5V supply voltage (DDR1)
1.8 V supply voltage (DDR2)
1.2 V supply voltage
V
V
V
3.3 V current consumption
1.5 V current consumption
1.2 V current consumption
DDR2 Current
mA
mA
mA
mA
Icc15
Icc12
Icc18
Table 3-6 DC Electrical Characteristics
Vdd=2.5V
(DDR2)
Typ
2.5
Min
Max
Vdd
VIH
VIL
2.375
VREF+0.15
-0.3
2.625
Vdd25+0.3
VREF-0.15
VOH
VOL
0.8*Vdd25
0.2*Vdd25
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IOL
IOH
Table 3-7 Vdd 2.5V Electrical Characteristics
Vdd=1.8V
(DDR2)
Typ
1.8
Min
Max
Vdd
VIH
VIL
1.71
VREF+0.125
-0.3
1.89
Vdd18+0.3
VREF-0.125
VOH
VOL
IOL
1.42
0.28
IOH
Table 3-8 Vdd 1.8V Electrical Characteristics
Vdd=3.3V
Vdd
Min
Typ
Max
3.63V
2.97V 3.3V
2.0V
VIH
Vdd33+0.3
0.8V
VIL
-0.3
VOH
VOL
2.4V
0.4V
IOL
IOH
Table 3-9 Vdd 3.3V Electrical Characteristics
3.8 AC Electrical Characteristics
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3.8.1 DDR2 SDRAM Interface
The DDR2 SDRAM interface complies with 200 MHz timing requirements for standard DDR2 SDRAM. The
interface drivers are SSTL_18 drivers matching the EIA/JEDEC standard JESD8-15A.
tCH
tCL
CLK
CLK#
tIS
tIH
tIH
tIH
tIH
tIH
tIH
MCS_N
MRAS_N
tIS
tIS
tIS
tIS
tIS
MCAS_N
MWE_N
MA0 to MA13
MBA0, MBA1
Figure 3-1 DDR2 SDRAM Command
tWPRE
tWPST
tDQSH
tDQSL
MDQS
MD
tDS
D1
tDH
D2
tDS
D3
tDH
D4
MDQM
Figure 3-2 DDR2 SDRAM Write data
tRPRE
tRPST
D3
MDQS
MD
D1
D2
tQH
tDQSQ (max)
Figure 3-3 DDR2 SDRAM Read data
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Symbol
tCK(avg)
tAC
Description
Min
5
Max
Unit
Remark
Clock cycle time
-
ns
ns
DQ output access time from SDRAM CLK
DQS output access time from SDRAM CLK
SDRAM CLK high pulse width
SDRAM CLK low pulse width
SDRAM CLK half period
-0.6
0.6
tDQSCK
tCH
-0.5
0.5
ns
0.48
0.48
Min(tCH,tCL)
0.75
0.75
-
0.52
tCK(avg)
tCK(avg)
ns
tCL
0.52
tHP
-
tIS
Address and control input setup time
Address and control input hold time
Data skew of DQS and associated DQ
DQ/DQS output hold time from DQS
DQS read preamble
-
ns
tIH
-
ns
tDQSQ
tQH
0.4
ns
tHP-0.5
0.9
-
ns
tRPRE
tRPST
tDQSS
tDQSH
tDQSL
tDSS
1.1
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
DQS read postamble
0.4
0.6
DQS rising edge to CK rising edge
DQS input-high pulse width
DQS input-low pulse width
-0.25
0.35
0.35
0.2
0.25
-
-
DQS falling edge to SDRAM CLK setup time
DQS falling edge hold time from SDRAM CLK
DQS write preamble
-
tDSH
tWPRE
tWPST
tDS
0.2
-
-
0.35
0.4
DQS write postamble
0.6
-
DQ and DQM input setup time
DQ and DQM input hold time
*0.4
*0.4
tDH
-
ns
Table 3-10 DDR2 SDRAM Interface Diagram Key
NOTE: Depends on slew rate of DQS and DQ/DQM for single ended DQS.
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3.8.2 SPI Interface
Write operation (driven by clock rising edge)
SPI_CLK
SPI_CS
SPI_MOSI
t_SPI_OVLD (max)
T_SPI_OVLD (min)
Read operation (Driven by clock rising edge (slave-device) and latched by clock rising edge)
SPI_CLK
SPI_CS
SPI_MISO
t_SPI_IS
t_SPI_IH
NOTE: 1) SPI_CLK is a gated clock.
2) SPI_CS is controlled by software
Figure 3-4 SPI Interface
Symbol
Description
Min
6.0
Max
Unit Remark
t_SPI_IS
Setup time for SPI input
Hold time for SPI input
SPI_CLK to SPI output valid
-
-
ns
ns
t_SPI_IH
-1.0
-2.0
t_SPI_OVLD
3.0
ns
output load: 5 pF
Table 3-11 SPI Interface Diagram Key
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3.8.3 I2S Interface
Transmitter
SCK
WS & SD
t_I2S_OVLD (min)
t_I2S_OVLD (max)
Receiver
SCK
WS & SD
t_I2S_IS t_I2S_IH
Figure-3-5 I2S Interface
Symbol
t_I2S_IS
Description
Min
3.5
Max
Unit Remark
ns
Setup time for I2S input
(data & WS)
-
t_I2S_IH
Hold time for I2S input
(data & WS)
0.5
2.5
-
ns
t_I2S_OVLD
I2S_CLK to I2S output
(data & WS) valid
10.0
ns
output load: 5 pF
Table 3-12 I2S Interface Diagram Key
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3.8.4 PCM Interface
PCMCLK
DTX
t_PCM_OVLD
PCMCLK
DRX &
FSYNC
t_PCM_IS
t_PCM_IH
Figure 3-6 PCM Interface
Symbol
Description
Min
3.0
Max
Unit Remark
ns
t_PCM_IS
Setup time for PCM input to
PCM_CLK fall
-
t_PCM_IH
Hold time for PCM input to PCM_CLK
fall
1.0
-
ns
ns
t_PCM_OVLD
PCM_CLK rise to PCM output valid
10.0
35.0
output load: 5 pF
Table 3-13 PCM Interface Diagram Key
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3.8.5 Power On Sequence
Figure 3-7 Power ON Sequence
Table 3-14 Power ON Sequence Diagram Key
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3.9 Package Physical Dimensions
3.9.1 DR-QFN (10 mm x 10 mm) 128 pins
3.9.1.1 Top View
Figure 3-8 Top View
3.9.1.3 “B” Expanded
3.9.1.2 Side View
Figure 3-9 Side View
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Figure 3-10 “B” Expanded
3.9.1.5 Package Diagram Key
3.9.1.4 Bottom View
Figure 3-11 Botton view
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3.9.2 DR-QFN (12 mm x 12 mm) 156 pins
3.9.2.1 Top View
Figure 3-12 Top View
3.9.2.2 Side View
3.9.2.3 “B” Expanded
Figure 3-13 Side View
Figure 3-14 “B” Expanded
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3.9.2.4 Bottom View
Figure 3-15 Bottom View
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3.9.2.5 Package Diagram Key
3.9.3 MT7628 AN/KN marking
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MEDIATEK
MT7628AN
YYWW-XXXX
LLLLLLLLL
YYWW: Date code
LLLLLLLLL : Lot number
“.” : Pin #1 dot
Figure 3-16 MT7620AN top marking
MEDIATEK
MT7628KN
YYWW-XXXX
LLLLLLLLL
YYWW: Date code
LLLLLLLLLL : Lot number
“.”
: Pin #1 dot
Figure 3-17 MT7628KN top marking
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3.9.4 Reflow profile guideline
Figure 3-18 Reflow profile for MT7628
Notes;
1. Reflow profile guideline is designed for SnAgCulead-free solder paste.
2. Reflow temperature is defined at the solder ball of package/or the lead of package.
3. MTK would recommend customer following the solder paste vendor’s guideline to design a profile
appropriate your line and products.
4. Appropriate N2 atmosphere is recommended since it would widen the process window and mitigate the risk
for having solder open issues.
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4. Abbreviations
Abbrev.
AC
Description
Abbrev.
CPU
Description
Access Category
Central Processing Unit
Cyclic Redundancy Check
Control Status Register
Clear to Send
ACK
Acknowledge/ Acknowledgement
Adjacent Channel Power Ratio
CRC
ACPR
AD/DA
CSR
Analog to Digital/Digital to Analog
converter
CTS
CW
Contention Window
ADC
AES
Analog-to-Digital Converter
Advanced Encryption Standard
Auto Gain Control
CWmax
CWmin
DAC
Maximum Contention Window
Minimum Contention Window
Digital-To-Analog Converter
Distributed Coordination Function
DMA Done
AGC
AIFS
AIFSN
Arbitration Inter-Frame Space
DCF
Arbitration Inter-Frame Spacing
Number
DDONE
DDR
Double Data Rate
ALC
Asynchronous Layered Coding
DFT
Discrete Fourier Transform
DCF Inter-Frame Space
Direct Memory Access
Digital Signal Processor
DWORD
A-MPDU
A-MSDU
Aggregate MAC Protocol Data Unit
DIFS
Aggregation of MAC Service Data
Units
DMA
DSP
AP
Access Point
DW
ASIC
ASME
Application-Specific Integrated Circuit
EAP
Expert Antenna Processor
Enhanced Distributed Channel Access
EEPROM chip select
American Society of Mechanical
Engineers
EDCA
EECS
EEDI
ASYNC
BA
Asynchronous
EEPROM data input
Block Acknowledgement
Block Acknowledgement Control
Base Address Register
Baseband Processor
EEDO
EEPROM
EEPROM data output
BAC
BAR
BBP
Electrically Erasable Programmable
Read-Only Memory
eFUSE
EESK
EIFS
EIV
electrical Fuse
BGSEL
BIST
BSC
Band Gap Select
EEPROM source clock
Extended Inter-Frame Space
Extend Initialization Vector
Error Vector Magnitude
Frequency Domain Spreading
Front-End Module
Built-In Self-Test
Basic Spacing between Centers
BJT
EVM
FDS
BSSID
BW
Basic Service Set Identifier
Bandwidth
FEM
FEQ
FIFO
FSM
GF
CCA
Clear Channel Assessment
Complementary Code Keying
Frequency Equalization
First In First Out
CCK
CCMP
Counter Mode with Cipher Block
Chaining Message Authentication
Code Protocol
Finite-State Machine
Green Field
CCX
Cisco Compatible Extensions
Control Frame End
GND
GP
Ground
CF-END
CF-ACK
CLK
General Purpose
Control Frame Acknowledgement
Clock
GPO
GPIO
General Purpose Output
General Purpose Input/Output
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Abbrev.
HCCA
HCF
HT
Description
Abbrev.
NAV
Description
HCF Controlled Channel Access
Hybrid Coordination Function
High Throughput
Network Allocation Vector
Network-Attached Server
Network Address Translation
Null Data Packet
NAS
NAT
HTC
ICV
High Throughput Control
Integrity Check Value
Inter-Frame Space
NDP
NVM
ODT
Non-Volatile Memory
On-die Termination
IFS
iNIC
IV
Intelligent Network Interface Card
Initialization Vector
Oen
Output Enable
OFDM
Orthogonal Frequency-Division
Multiplexing
I2C
Inter-Integrated Circuit
Integrated Inter-Chip Sound
Input/Output
I2S
OSC
PA
Open Sound Control
Power Amplifier
I/O
PAPE
Provider Authentication Policy
Extension
IPI
Idle Power Indicator
IQ
In phase/Quadrature phase
PBC
PBF
Push Button Configuration
Packet Buffer
JEDEC
Joint Electron Devices Engineering
Council
PCB
PCF
Printed Circuit Board
JTAG
kbps
KB
Joint Test Action Group
kilo (1000) bits per second
Kilo (1024) Bytes
Point Coordination Function
Pulse-Code Modulation
Physical Layer
PCM
PHY
PIFS
PLCP
PLL
LDO
Low-Dropout Regulator
LDO for DIGital part output voltage
Light-Emitting Diode
Low Noise Amplifier
PCF Interframe Space
Physical Layer Convergence Protocol
Phase-Locked Loop
LDODIG
LED
LNA
PME
PMU
PN
Physical Medium Entities
Power Management Unit
Packet Number
LO
Local Oscillator
L-SIG
MAC
MCU
MCS
MDC
MDIO
MEM
MFB
MFS
Legacy Signal Field
Medium Access Control
Microcontroller Unit
Modulation and Coding Scheme
Management Data Clock
Management Data Input/Output
Memory
PROM
PSDU
PSI
Programmable Read-Only Memory
Physical layer Service Data Unit
Power supply Strength Indication
Power Save Mode
PSM
PTN
QoS
RDG
RAM
RF
Packet Transport Network
Quality of Service
MCS Feedback
Reverse Direction Grant
Random Access Memory
Radio Frequency
MFB Sequence
MIC
Message Integrity Code
Multiple-Input Multiple-Output
Monolithic Low Noise Amplifier
Mixed Mode
MIMO
MLNA
MM
RGMII
Reduced Gigabit Media Independent
Interface
RH
Relative Humidity
MOSFET
Metal Oxide Semiconductor Field
Effect Transistor
RoHS
ROM
Restriction on Hazardous Substances
Read-Only Memory
MPDU
MSB
MAC Protocol Data Units
Most Significant Bit
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Abbrev.
RSSI
Description
Abbrev.
TSSI
Description
Received Signal Strength Indication
(Indicator)
Transmit Signal Strength Indication
Transmit
Tx
RTS
Request to Send
TxBF
TXD
Transmit Beamforming
Transmitted Data
RvMII
Rx
Reverse Media Independent Interface
Receive
TXDAC
TXINFO
TXOP
TXWI
UART
USB
Transmit Digital-Analog Converter
Transmit Information
Opportunity to Transmit
Tx Wireless Information
Universal Asynchronous Rx/ Tx
Universal Serial Bus
RXD
Received Data
RXINFO
RXWI
S
Receive Information
Receive Wireless Information
Stream
SDXC
SDIO
SDRAM
Secure Digital eXtended Capacity
Secure Digital Input Output
UTIF
VGA
Universal Test Interface
Variable Gain Amplifier
Voltage Controlled Amplifier
High Level Input Voltage
Low Level Input Voltage
Voice over IP
Synchronous Dynamic Random Access
Memory
VCO
SEC
Security
VIH
SGI
Short Guard Interval
VIL
SIFS
SoC
Short Inter-Frame Space
System-on-a-Chip
VoIP
WCID
WEP
WI
Wireless Client Identification
Wired Equivalent
SPI
Serial Peripheral Interface
Static Random Access Memory
Spread Spectrum Clock Generator
Space–Time Block Code
Switch Regulator
SRAM
SSCG
STBC
SW
Wireless Information
Wireless Information Valid
Wi-Fi Multimedia
WIV
WMM
WPA
WPDMA
Wi-Fi Protected Access
TA
Transmitter Address
Wireless Polarization Division Multiple
Access
TBTT
TDLS
TKIP
TRSW
TSF
Target Beacon Transmission Time
Tunnel Direct Link Setup
Temporal Key Integrity Protocol
Tx/Rx Switch
WS
Word Select
Timing Synchronization Function
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5. Revision History
Rev
1.0
1.1
1.2
1.3
Date
Description
2012/07/09
2012/07/18
2012/08/20
2012/09/12
Initial Release
Update SPI_WP/SPI_HOLD GPO table
Fix DRQFN internal pad size typo
Add IR reflow guideline
This product is not designed for use in medical and/or life support applications. Do not use this product in these
types of equipment or applications. This document is subject to change without notice and Ralink assumes no
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responsibility for any inaccuracies that may be contained in this document. Ralink reserves the right to make
changes in its products to improve function, performance, reliability, and to attempt to supply the best product
possible.
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