MTV112A [ETC]
8051 Embedded CRT Monitor Controller MASK Version; 8051嵌入式CRT显示器控制器掩膜版
| 型号： | MTV112A |
| 厂家： | 
ETC |
| 描述： | 8051 Embedded CRT Monitor Controller MASK Version |
| 文件： | 总20页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
8051 Embedded CRT Monitor Controller
MASK Version
FEATURES
l
l
l
l
l
l
l
l
l
l
l
8051 core.
384-bytes internal RAM.
16K-bytes program Mask ROM.
14-channels 10V open-drain PWM DAC, 10 dedicated channels and 4 channels shared with I/O pin.
28 bi-direction I/O pin,12 dedicated pin,12 shared with DAC,4 shared with DDC/IIC interface.
5-output pin shared with H/V sync output and self test output pins.
SYNC processor for composite separation, polarity and frequency check, and polarity adjustment.
Built-in monitor self-test pattern generator.
Built-in low power reset circuit.
One slave mode IIC interface and one master mode IIC interface.
IIC interface for DDC1/DDC2B and EEPROM; only one EEPROM needed to store DDC1/DDC2B and
display mode information.
l
l
l
Dual 4-bit ADC or 4 channel 6-bit ADC.
Watchdog timer with programmable interval.
40-pin PDIP and 44-pin PLCC package.
GENERAL DESCRIPTION
The MTV112A micro-controller is an 8051 CPU core embedded device specially tailored to CRT monitor
applications. It includes an 8051 CPU core, 384-byte SRAM, 14 built-in PWM DACs, DDC1/DDC2B interface,
24Cxx series EEPROM interface, A/D converter and a 16K-bytes internal program Mask ROM.
BLOCK DIAGRAM
STOUT
HSYNC
P0.0-7
P0.0-7
RD
P1.0-7
X1
XFR
H / VSYNC VSYNC
RD
HBLANK
CONTROL
WR
WR
VBLANK
8051
CORE
X2
INT
1
WATCH-DOG
TIMER
14 CHANNEL DA0-9
RST
P2.0-3
RST
PWM DAC
DA10-13
P2.4-7
P3.0-P3.2 P3.4
AD0
AD1
ADC
ISCL
HSCL
HSDA
DDC 1/2 B & FIFO
INTERFACE
IIC INTERFACE
ISDA
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
MTV112A Revision 1.9 05/18/2001
1/20
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
1.0 PIN CONNECTION
P1.0
P1.1/HALFV
P1.2/HALFH
P1.3/HCLAMP
P1.4/AD2
VDD
P1.0
P1.1/HALFV
P1.2/HALFH
P1.3/HCLAMP
P1.4/AD2
VDD
DA0/P5.0
DA0/P5.0
DA1/P5.1
DA2/P5.2
DA3/P5.3
DA4/P5.4
DA5/P5.5
DA6/P5.6
DA7/P5.7
DA8
DA1/P5.1
DA2/P5.2
DA3/P5.3
DA4/P5.4
DA5/P5.5
DA6/P5.6
DA7/P5.7
DA8
P1.5/AD3
P1.5/AD3
P1.6/AD0
P1.6/AD0
P1.7/AD1
P1.7/AD1
RST
RST
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
ISDA/P3.2/INT0
HSYNC
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
ISDA/P3.2/INT0
HSYNC
MTV112A
DA9
MTV112A
DA9
STOUT/P4.2
DA10/P2.7
DA11/P2.6
DA12/P2.5
DA13/P2.4
P2.3
HALFH/P4.3
STOUT/P4.2
DA10/P2.7
DA11/P2.6
DA12/P2.5
DA13/P2.4
P2.3
ISCL/P3.4/T0
VSYNC
ISCL/P3.4/T0
VSYNC
HBLANK/P4.1
VBLANK/P4.0
X2
HCLAMP/P4.4
HBLANK/P4.1
VBLANK/P4.0
X2
P2.2
X1
P2.1
P2.2
VSS
P2.0/INT0
X1
P2.1
VSS
P2.0/INT0
NC
7
8
9
39 DA4/P5.4
P1.5/AD3
P1.6/AD0
38 DA5/P5.5
37 DA6/P5.6
36 DA7/P5.7
35 DA8
P1.7/AD1 10
RESET 11
HSCL/P3.0/Rxd 12
HSDA/P3.1/Txd 13
ISDA/P3.2/INT0 14
HSYNC 15
34 DA9
MTV112A
33 STOUT/P4.2
32 DA10/P2.7
31 DA11/P2.6
30 DA12/P2.5
29 NC
ISCL/P3.4/T0 16
VSYNC 17
MTV112A Revision 1.9 05/18/2001
2/20
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
2.0 PIN DESCRIPTIONS
Pin#
40 42 44
Name
Type
Description
P1.0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
2
3
4
5
6
8
9
General purpose I/O
P1.1/HALFV
P1.2/HALFH
P1.3/HCLAMP
P1.4/AD2
P1.5/AD3
P1.6/AD0
P1.7/AD1
RST
General purpose I/O / Vsync half frequency output.
General purpose I/O / Hsync half frequency output.
General purpose I/O / Hsync clamp pulse output.
General purpose I/O / ADC input.
General purpose I/O / ADC input.
General purpose I/O / ADC input
10 General purpose I/O / ADC input
11 Active high reset
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
ISDA/P3.2/INT0
HSYNC
ISCL/P3.4/T0
VSYNC
I/O
I/O
I/O
I
I/O
I
10 10 12 IIC clock / General purpose I/O / Rxd
11 11 13 IIC data / General purpose I/O / Txd
12 12 14 IIC data / General purpose I/O / INT0
13 13 15 Horizontal SYNC or Composite SYNC
14 14 16 IIC clock / General purpose I/O / T0
15 15 17 Vertical SYNC
HCLAMP/P4.4
HBLANK/P4.1
VBLANK/P4.0
X2
O
O
O
O
-
16
-
Hsync clamp pulse output / General purpose output
16 17 19 Horizontal blank / General purpose output
17 18 20 Vertical blank / General purpose output
18 19 21 Oscillator output
X1
I
19 20 22 Oscillator input
VSS
-
20 21 23 Ground
P2.0/INT0
P2.1
P2.2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
-
21 22 24 General purpose I/O / INT0
22 23 25 General purpose I/O
23 24 26 General purpose I/O
24 25 27 General purpose I/O
25 26 28 PWM DAC output / General purpose I/O (open-drain)
26 27 30 PWM DAC output / General purpose I/O (open-drain)
27 28 31 PWM DAC output / General purpose I/O (open-drain)
28 29 32 PWM DAC output / General purpose I/O (open-drain)
29 30 33 Self-test video output / General purpose output
P2.3
DA13/P2.4
DA12/P2.5
DA11/P2.6
DA10/P2.7
STOUT/P4.2
HALFH/P4.3
DA9
-
31
-
Hsync half frequency output / General purpose output
30 32 34 PWM DAC output / General purpose I/O (open-drain)
31 33 35 PWM DAC output / General purpose I/O (open-drain)
32 34 36 PWM DAC output / General purpose I/O (open-drain)
33 35 37 PWM DAC output / General purpose I/O (open-drain)
34 36 38 PWM DAC output / General purpose I/O (open-drain)
35 37 39 PWM DAC output / General purpose I/O (open-drain)
36 38 41 PWM DAC output / General purpose I/O (open-drain)
37 39 42 PWM DAC output / General purpose I/O (open-drain)
38 40 43 PWM DAC output / General purpose I/O (open-drain)
39 41 44 PWM DAC output / General purpose I/O (open-drain)
DA8
DA7/P5.7
DA6/P5.6
DA5/P5.5
DA4/P5.4
DA3/P5.3
DA2/P5.2
DA1/P5.1
DA0/P5.0
VDD
40 42
1
Positive power supply
MTV112A Revision 1.9 05/18/2001
3/20
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
3.0 FUNCTIONAL DESCRIPTION
1. 8051 CPU Core
MTV112A includes all 8051 functions with the following exceptions:
1.1 PSEN, ALE, RD and WR pins are disabled. The external RAM access is restricted to XFRs within
MTV112A.
1.2 Port 0, port 3.3, and ports 3.5 ~ 3.7 are not general-purpose I/O ports. They are dedicated to monitor
control or DAC pins.
1.3 INT1 and T1 input pins are not provided.
1.4 Ports 2.4 ~ 2.7 are shared with DAC pins; ports 3.0 ~ 3.2, and port3.4 are shared with monitor control
pins.
In addition, there are 2 timers, 5 interrupt sources and a serial interface compatible with the standard 8051.
The Txd/Rxd (P3.0/P3.1) pins are shared with DDC interface. INT0/T0 pins are shared with IIC interface. An
extra option can be used to switch the INT0 source from P3.2 to P2.0. This feature maintains an external
interrupt source when IIC interface is enabled.
Note: All registers listed in this document reside in the external RAM area (XFR). For the internal
RAM memory map please refer to the 8051 spec.
Reg name
addr
bit7
bit6
IICF
P56E
-
bit5
DDCE
P55E
-
bit4
IICE
P54E
-
bit3
bit2
bit1
bit0
PADMOD 30h (w) SINT0
PADMOD 31h (w) P57E
PADMOD 37h (w)
DA13E DA12E DA11E DA10E
P53E
-
P52E
-
P51E
-
P50E
MORE
-
SINT0 = 1
= 0
® INT0 source is pin #21.
® INT0 source is pin #12.
IICF
= 1
= 0
® Selects 400kHz master IIC speed.
® Selects 100kHz master IIC speed.
® Pin #10 is HSCL; pin #11 is HSDA.
® Pin #10 is P3.0/Rxd; pin #11 is P3.1/Txd.
® Pin #12 is ISDA; pin #14 is ISCL.
® Pin #12 is P3.2/(INT0*); pin #14 is P3.4/T0.
® Pin #25 is DA13.
DDCE = 1
= 0
IICE
= 1
= 0
DA13E = 1
= 0
® Pin #25 is P2.4.
DA12E = 1
= 0
® Pin #26 is DA12.
® Pin #26 is P2.5.
DA11E = 1
= 0
® Pin #27 is DA11.
® Pin #27 is P2.6.
DA10E = 1
= 0
® Pin #28 is DA10.
® Pin #28 is P2.7.
P57E = 1
= 0
® Pin #32 is P5.7.
® Pin #32 is DA7.
P56E = 1
= 0
® Pin #33 is P5.6.
® Pin #33 is DA6.
P55E = 1
= 0
® Pin #34 is P5.5.
® Pin #34 is DA5.
P54E = 1
= 0
® Pin #35 is P5.4.
® Pin #35 is DA4.
P53E = 1
= 0
® Pin #36 is P5.3.
® Pin #36 is DA3.
P52E = 1
= 0
® Pin #37 is P5.2.
® Pin #37 is DA2.
MTV112A Revision 1.9 05/18/2001
4/20
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
P51E = 1
= 0
P50E = 1
= 0
® Pin #38 is P5.1.
® Pin #38 is DA1.
® Pin #39 is P5.0.
® Pin #39 is DA0.
MORE = 1
® Bits P57E,P56E,P55E,P54E,P53E,P52E,P51E,P50E,DACK,EHALFV,
EHALFH,ENCLP,ADCMOD can be programmed,and master IIC speed is
controlled by (MCLK1,MCLK0) bits.
= 0
® above bits internal keep “0” by MTV112A, and master IIC speed is controlled by
IICF bit.
* SINT0 should be 0 in this case.
2. Memory Allocation
2.1 Internal Special Function Registers (SFR)
SFR is a group of registers that is the same as standard 8051.
2.2 Internal RAM
There is a 384 bytes RAM in MTV112A. The first portion of the RAM area contains 256 bytes, accessible by
setting PSW.1=0; the second portion of the RAM area contains 128 bytes, accessible by setting PSW.1=1.
2.3 External Special Function Registers (XFR)
XFR is a group of registers allocated in the 8051 external RAM area. Most of the registers are used for
monitor control or PWM DAC. The program can initialize Ri value and use "MOVX" instruction to access
these registers.
FFH
Accessible by indirect
addressing only.
The value of PSW.1 =
both 0 and 1.
(Using MOV A, @Ri
instruction)
SFR
Accessible by direct
addressing.
FFH
00H
XFR
Accessible by indirect
external RAM
addressing.
(Using MOVX A, @Ri
Instruction.)
80H
7FH
Accessible by direct
and indirect
Accessible by direct
and indirect
addressing.
addressing.
PSW.1=0
PSW.1 =1
00H
3. PWM DAC
Each D/A converter's output pulse width is controlled by an 8-bit register in XFR. The frequency of PWM clk
is X’tal or 2 * X’tal, selected by DACK. And the frequency of these DAC outputs is (PWM clk frequency)/253
or (PWM clk frequency)/256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to the DAC register
generates stable high output. If DIV253=0, the output will pulse low at least once even if the DAC register's
content is FFH. Writing 00H to the DAC register generates stable low output.
reg name
addr
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DA0
DA1
DA2
DA3
20h (r/w) DA0
21h (r/w) DA1
22h (r/w) DA2
23h (r/w) DA3
DA0
DA0
DA0
DA0
DA0
DA0
DA0
b7
b7
b7
b7
b6
b6
b6
b6
b5
b5
b5
b5
b4
b4
b4
b4
b3
b3
b3
b3
b2
b2
b2
b2
b1
b1
b1
b1
b0
b0
b0
b0
DA1
DA2
DA3
DA1
DA2
DA3
DA1
DA2
DA3
DA1
DA2
DA3
DA1
DA2
DA3
DA1
DA2
DA3
DA1
DA2
DA3
MTV112A Revision 1.9 05/18/2001
5/20
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
DA4
DA5
24h (r/w) DA4
25h (r/w) DA5
26h (r/w) DA6
27h (r/w) DA7
28h (r/w) DA8
29h (r/w) DA9
DA4
DA5
DA6
DA7
DA8
DA9
DA4
DA5
DA6
DA7
DA8
DA9
DA4
DA5
DA6
DA7
DA8
DA9
DA4
DA5
DA6
DA7
DA8
DA9
DA4
DA5
DA6
DA7
DA8
DA9
DA4
DA5
DA6
DA7
DA8
DA9
DA4
DA5
DA6
DA7
DA8
DA9
b7
b7
b7
b7
b7
b7
b6
b6
b6
b6
b6
b6
b5
b5
b5
b5
b5
b5
b4
b4
b4
b4
b4
b4
b3
b3
b3
b3
b3
b3
b2
b2
b2
b2
b2
b2
b1
b1
b1
b1
b1
b1
b0
b0
b0
b0
b0
b0
DA6
DA7
DA8
DA9
2Ah (r/w)
2Bh (r/w)
2Ch (r/w)
2Dh (r/w)
80h
DA10
DA11
DA12
DA13
WDT
DA10
DA10
DA11
DA12
DA13
DA10
DA11
DA12
DA13
DA10
DA11
DA12
DA13
DA10
DA11
DA12
DA13
DA10
DA11
DA12
DA13
DA10
DA11
DA12
DA13
DA10
DA11
DA12
DA13
b7
b7
b7
b7
b6
b6
b6
b6
b5
b5
b5
b5
b4
b4
b4
b4
b3
b3
b3
b3
b2
b2
b2
b2
b1
b1
b1
b1
b0
b0
b0
b0
DA11
DA12
DA13
CLRDDC
WEN
WCLR
DIV253 DACK
WDT2 WDT1 WDT0
DA0 (r/w) :
The output pulse width control for DA0.
The output pulse width control for DA1.
The output pulse width control for DA2.
The output pulse width control for DA3.
The output pulse width control for DA4.
The output pulse width control for DA5.
The output pulse width control for DA6.
The output pulse width control for DA7.
The output pulse width control for DA8.
The output pulse width control for DA9.
The output pulse width control for DA10.
The output pulse width control for DA11.
The output pulse width control for DA12.
The output pulse width control for DA13.
Watchdog timer & special control bit.
DA1 (r/w) :
DA2 (r/w) :
DA3 (r/w) :
DA4 (r/w) :
DA5 (r/w) :
DA6 (r/w) :
DA7 (r/w) :
DA8 (r/w) :
DA9 (r/w) :
DA10 (r/w) :
DA11 (r/w) :
DA12 (r/w) :
DA13 (r/w) :
WDT (w) :
DIV253 = 1
® The PWM DAC outputs frequency is (PWM clk frequency)/253.
® The PWM DAC output frequency is Xtal frequency/256.
® The PWM clk frequency is 2 x (X’tal frequency).
® The PWM clk frequency is (X’tal frequency).
= 0
DACK = 1
= 0
*1. All D/A converters are centered with value 80h after power-on.
4. H/V SYNC Processing
The H/V SYNC processing block performs the functions of composite signal separation, SYNC input
presence check, frequency counting, and polarity detection and control, as well as the protection of VBLANK
output while VSYNC speeds up to a high DDC communication clock rate. The present and frequency
function block treat any pulse less than one OSC period as noise.
4.1 Composite SYNC Separation
MTV112A continuously monitors the input HSYNC. If the vertical SYNC pulse can be extracted from the
input, a CVpre flag is set and the user can select the extracted "CVSYNC" for the source of polarity check,
frequency count and VBLANK. The CVSYNC will have a 10-16 us delay compared to the original signal. The
delay depends on the OSC frequency and composite mix method.
4.2 H/V Frequency Counter
MTV112A can discriminate HSYNC/VSYNC frequency and saves the information in XFRs. The 15-bit
Hcounter counts the time of the 64xHSYNC period, but only 11 upper bits are loaded into the
HCNTH/HCNTL latch. The 11-bit output value is {2/H-Freq} / {1/OSC-Freq}, updated once per
VSYNC/CVSYNC period when VSYNC/CVSYNC is present or continuously updated when VSYNC/CVSYNC
is not present. The 14-bit Vcounter counts the time between 2 VSYNC pulses, but only 9 upper bits are
MTV112A Revision 1.9 05/18/2001
6/20
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
loaded into the VCNTH/VCNTL latch. The 9-bit output value is {1/V-Freq} / {512/OSC-Freq}, updated every
VSYNC/CVSYNC period. An extra overflow bit indicates the condition of the H/V counter overflow. The
VFchg/HFchg interrupt is active when VCNT/HCNT value changes or overflows. Tables 4.2.1 and 4.2.2
shows the HCNT/VCNT value under the operations of 8MHz and 12MHz.
4.2.1 H-Freq Table
Output Value (11 bits)
H-Freq(KHZ)
8MHz OSC (hex / dec)
215h / 533
12MHz OSC (hex / dec)
320h / 800
1
2
3
4
5
30
31.5
33.5
35.5
36.8
38
1FBh / 507
1DDh /477
1C2h / 450
1B2h / 434
1A5h / 421
190h / 400
2F9h / 761
2CCh / 716
2A4h / 676
28Ch / 652
277h / 631
6
7
40
258h / 600
8
9
10
11
12
13
48
50
57
60
64
100
14Dh / 333
140h / 320
118h / 280
10Ah / 266
0FAh / 250
0A0h / 160
1F4h / 500
1E0h / 480
1A5h / 421
190h / 400
177h / 375
0F0h / 240
*1. The H-Freq output (HF10 - HF0) is valid.
*2. The tolerance deviation is + 1 LSB.
4.2.2 V-Freq Table
Output Value (9 bits)
V-Freq(Hz)
8MHz OSC (hex / dec)
115h / 277
12MHz OSC (hex / dec)
1A0h / 416
187h / 391
1
2
3
4
5
6
7
8
9
56.25
59.94
60
60.32
60.53
66.67
70.069
70.08
72
104h / 260
104h / 260
103h / 259
102h / 258
0EAh / 234
0DEh / 222
0DEh / 222
0D9h /217
0D7h / 215
0D6h / 214
0B3h / 179
186h / 390
184h / 388
183h / 387
15Fh / 351
14Eh / 334
14Eh / 334
145h / 325
10
11
12
72.378
72.7
87
143h / 323
142h / 322
10Dh / 269
*1. The V-Freq output (VF8 - VF0) is valid.
*2. The tolerance deviation is + 1 LSB.
4.3 H/V Presence Check
The Hpresent function checks the input HSYNC pulse. The Hpre flag is set when HSYNC is over 10KHz or
cleared when HSYNC is under 10Hz. The Vpresent function checks the input VSYNC pulse. The Vpre flag
is set when VSYNC is over 40Hz or cleared when VSYNC is under 10Hz. A control bit "PREFS" selects the
time base for these functions. The HPRchg interrupt is set when the Hpre value changes. The VPRchg
interrupt is set when the Vpre/CVpre value changes. However, the CVpre flag interrupt may be disabled
when S/W disables the composite function.
MTV112A Revision 1.9 05/18/2001
7/20
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
4.4 H/V Polarity Detection
The polarity functions detect the input HSYNC/VSYNC high and low pulse duty cycle. If the high pulse
duration is longer than that of the low pulse, the negative polarity is asserted; otherwise, positive polarity is
asserted. The HPLchg interrupt is set when the Hpol value changes. The VPLchg interrupt is set when the
Vpol value changes.
4.5 Output HBLANK/VBLANK Control and Polarity Adjustment
The HBLANK is the mux output of HSYNC and self-test horizontal pattern. The VBLANK is the mux output of
VSYNC, CVSYNC and the self-test vertical pattern. The mux selection and output polarity are S/W
controllable. The VBLANK output is cut off when VSYNC frequency is over 200Hz or 133Hz depends on
8MHz/12MHz OSC selection. The HBLANK/VBLANK shares the output pin with P4.1/ P4.0.
4.6 Self-Test Pattern Generator
This generator can generate 4 display patterns for testing purposes: positive cross-hatch, negative cross-
hatch, full white, and full black (shown in the following figure). It was originally designed to support the
monitor manufacturer in performing a burn-in test, or to offer the end-user a reference to check the monitor.
The generator's output STOUT shares the output pin with P4.2.
Display Region
Positive Cross-Hatch
Negative Cross-Hatch
Full White
Full Black
MTV112A Revision 1.9 05/18/2001
8/20
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
D
A
R
O
C
E
Hor.
B
Q
S
Vert.
P
MTV112A Self-Test Pattern Timing (8MHz)
63.5KHz, 60Hz
Absolute time
31.7KHz, 60Hz
H dots
1280
Absolute time
Us(A)=31.5
Us(D)=24.05
Us(E)=0.45
Us(B)=3
H dots
Hor. Total Time
Hor. Acitve Time
Hor. F. P.
SYNC Pulse Width
Hor. B. P.
Us(A)=15.75
Us(D)=12.05
Us(E)=0.2
Us(B)=1.5
Us(C)=2
640
488.6
9
979.3
16.25
122
61
162.54
Us(C)=4
81.27
V lines
V lines
Hor. Total Time
Hor. Active Time
Hor. F. P.
SYNC Pulse Width
Hor. B. P.
Us(O)=16.6635
Us(R)=15.6555
Us(S)=0.063
Us(P)=0.063
Us(Q)=0.882
1024
962
3.87
3.87
54.2
Us(O)=16.6635
Us(R)=15.6555
Us(S)=0.063
Us(P)=0.063
Us(Q)=0.882
480
451
1.82
1.82
25.4
* 8 x 8 blocks of cross-hatch pattern in display region.
4.7 VSYNC Interrupt
MTV112A checks the VSYNC input pulse and generates an interrupt at its leading edge. The VSYNC1 flag
is set each time MTV112A detects a VSYNC pulse.
4.8 H/V SYNC Processor Register
reg name
addr
40h (r)
bit7
CVpre
Hovf
HF7
Vovf
VF7
C1
bit6
X
X
HF6
X
VF6
C0
X
bit5
Hpol
X
HF5
X
bit4
Vpol
X
HF4
X
bit3
Hpre
X
HF3
X
bit2
Vpre
HF10
HF2
X
bit1
Hoff
HF9
HF1
X
VF1
HBpl
Rt0
bit0
Voff
HF8
HF0
VF8
VF0
VBpl
STF
PSTUS
HCNTH 41h (r)
HCNTL
42h (r)
VCNTH 43h (r)
VCNTL
44h (r)
PCTR0 40h (w)
PCTR2 42h (w)
VF5
VF4
VF3
VF2
HVsel STOsel PREFS HALFV
ST
X
X
Selft
Rt1
bsh
PCTR3 43h (w) ENCLP CLPEG CLPPO CLPW2 CLPW1 CLPW0 EHALFV EHALFH
P4OUT 44h (w)
P44 P43 P42 P41 P40
X
X
X
MTV112A Revision 1.9 05/18/2001
9/20
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
P5OUT 45h (r/w)
PCTR6 46h (w)
P57
X
P56
X
P55
X
P54
X
P53
X
P52
X
P51
P50
CLPsel HALFHsel
INTFLG 50h (r/w) HPRchg VPRchg HPLchg VPLchg HFchg VFchg
FIFOI
EFIFO
X
MI
EMI
VSYNC
EVSI
INTEN
INTFLG 51h(r/w)
INTEN
61h(w)
60h (w) EHPR
EVPR
EHPL
X
X
EVPL
X
X
EHF
X
X
EVF
X
X
X
X
X
X
X
Present
Check
Vpre
Vfreq
Vpol
Digital Filter
Frequency
Count
Polarity
Check
VBpl
VSYNC
High
Frequency
Mask
VBLANK
HBLANK
Vself
CVSYNC
Present
Check
CVpre
HBpl
Polarity Check &
Sync Seperator
Hpol
Hself
HSYNC
Hpre
Present Check &
Frequency Count
Digital Filter
Hfreq
H/V SYNC Processor Block Diagram
The status of polarity, presence and static level for HSYNC and VSYNC.
PSTUS (r) :
CVpre = 1
= 0
® The extracted CVSYNC is present.
® The extracted CVSYNC is not present.
® HSYNC input is positive polarity.
® HSYNC input is negative polarity.
® VSYNC (CVSYNC) is positive polarity.
® VSYNC (CVSYNC) is negative polarity.
® HSYNC input is present.
® HSYNC input is not present.
® VSYNC input is present.
® VSYNC input is not present.
H
= 1
= 0
= 1
= 0
= 1
= 0
= 1
= 0
= 1
= 0
= 1
= 0
pol
V
pol
H
pre
V
pre
H
® HSYNC input's off-level is high.
® HSYNC input's off-level is low.
® VSYNC input's off-level is high.
® VSYNC input's off-level is low.
off*
V
off*
*H and V are valid when H
or V
off off pre=0
pre=0.
HCNTH (r) :
Hovf
HF10 - HF8 : 3 high bits of H-Freq counter.
H-Freq counter's high bits.
= 1 ® H-Freq counter overflows; this bit is cleared by H/W when condition removed.
HCNTL (r) :
H-Freq counter's low bits.
MTV112A Revision 1.9 05/18/2001
10/20
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
VCNTH (r) :
V-Freq counter's high bits.
Vovf
= 1
® V-Freq counter overflows; this bit is cleared by H/W when condition removed.
VF8 : High bit of V-Freq counter.
VCNTL (r) :
V-Freq counter's low bits.
PCTR0 (w) :
SYNC processor control register 0.
C1, C0 = 1,1 ® Selects CVSYNC as the polarity, Freq and VBLANK source.
= 1,0 ® Selects VSYNC as the polarity, Freq and VBLANK source.
= 0,0 ® Disables composite function (MTV012 compatible mode).
= 0,1 ® H/W auto switches to CVSYNC when CVpre=1 and VSpre=0.
HVsel = 1
= 0
STOsel = 1
= 0
® Pin #16 is P4.1, pin #17 is P4.0.
® Pin #16 is HBLANK, pin #17 is VBLANK.
® Pin #29 is P4.2.
® Pin #29 is STOUT.
PREFS = 0
= 1
HALFV = 1
® Selects 8MHz OSC as H/V presence check and self-test pattern time base.
® Selects 12MHz OSC as H/V presence check and self-test pattern time base.
® VBLANK is half frequency output of VSYNC.
® Negative polarity HBLANK output.
® Positive polarity HBLANK output.
® Negative polarity VBLANK output.
HB
= 1
= 0
= 1
= 0
pl
VB
pl
® Positive polarity VBLANK output.
PCTR2 (w) :
Self-test pattern generator control.
S
= 1
= 0
= 1
= 0
® Enables generator.
® Disables generator.
® 63.5KHz (horizontal) output selected.
® 31.75KHz (horizontal) output selected.
elft
ST
bsh
Rt1, Rt0= 0,0 ® Positive cross-hatch pattern output.
= 0,1 ® Negative cross-hatch pattern output.
= 1,0 ® Full white pattern output.
= 1,1 ® Full black pattern output.
STF
= 1
® Enables STOUT output.
= 0
® Disables STOUT output.
PCTR3 (w) :
HSYNC clamp pulse control register.
ENCLP = 1
= 0
® pin #4 is HCLAMP.
® pin #4 is P1.3.
CLPEG = 1
= 0
CLPPO= 1
® Clamp pulse follows HSYNC leading edge.
® Clamp pulse follows HSYNC trailing edge.
® Positive polarity clamp pulse output.
® Negative polarity clamp pulse output.
= 0
CLPW2 : CLPW0 : Pulse width of clamp pulse is
[(CLPW2:CLPW0) + 1] X 0.25 µs for 8MHz X’tal selection,or
[(CLPW2:CLPW0) + 1] X 0.167 µs for 12MHz X’tal selection.
EHALFV= 1
= 0
EHALFV= 1
= 0
® pin #2 is HALFV.
® pin #2 is P1.1.
® pin #3 is HALFH.
® pin #3 is P1.2.
P4OUT (w) :
Port 4 data output value.
P5OUT (r/w) : Port 5 data input/output value.
MTV112A Revision 1.9 05/18/2001
11/20
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
PCTR6 (w) :
Sync processor control register 6.
CLPsel = 1
= 0
® pin HCLAMP/P4.4 is P4.4.
® pin HCLAMP/P4.4 is HCLAMP.
HALFHsel = 1 ® pin HALFH/P4.3 is P4.3.
= 0 ® pin HALFH/P4.3 is HALFH.
INTFLG (w) : Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt
enabler bit is set, the 8051 core's INT1 source will be driven by a zero level. Software MUST
clear this register while serving the interrupt routine.
HPRchg= 1
= 0
VPRchg= 1
= 0
HPLchg= 1
= 0
VPLchg= 1
= 0
HFchg = 1
= 0
VFchg = 1
= 0
VSYNCi= 1
= 0
® No action.
® Clears HSYNC presence change flag.
® No action.
® Clears VSYNC presence change flag.
® No action.
® Clears HSYNC polarity change flag.
® No action.
® Clears VSYNC polarity change flag.
® No action.
® Clears HSYNC frequency change flag.
® No action.
® Clears VSYNC frequency change flag.
® No action.
® Clears VSYNC interrupt flag.
INTFLG (r) :
Interrupt flag.
HPRchg= 1
VPRchg= 1
HPLchg= 1
VPLchg= 1
HFchg = 1
VFchg = 1
VSYNCi= 1
® Indicates an HSYNC presence change.
® Indicates a VSYNC presence change.
® Indicates a HSYNC polarity change.
® Indicates a VSYNC polarity change.
® Indicates an HSYNC frequency change or counter overflow.
® Indicates a VSYNC frequency change or counter overflow.
® Indicates a VSYNC interrupt.
INTEN (w) :
Interrupt enabler.
EHPR = 1
EVPR = 1
EHPL = 1
EVPL = 1
® Enables HSYNC presence change interrupt.
® Enables VSYNC presence change interrupt.
® Enables HSYNC polarity change interrupt.
® Enables VSYNC polarity change interrupt.
® Enables HSYNC frequency change / counter overflow interrupt.
® Enables VSYNC frequency change / counter overflow interrupt.
® Enables VSYNC interrupt.
EHF
EVF
= 1
= 1
EVSI = 1
5. DDC & IIC Interface
5.1 DDC1 Mode
MTV112A enters DDC1 mode after Reset. In this mode, VSYNC is used as a data clock. The HSCL pin
should remain at high. The data output to the HSDA pin is taken from 8 bytes f FIFO in MTV112A. MTV112A
fetches the data byte from FIFO, then sends it in a 9-bit packet format which includes a null bit (=1) as
packet separator. The software program should load EDID data (original stored in EEPROM) into FIFO and
take care of the FIFO depth. FIFO sets the FIFOI (FIFO low interrupt) flag when there are fewer than N
(N=2,3,4 or 5 controlled by LS1, LS0) bytes to be output to the HSDA pin. To prevent FIFO from emptying,
software needs to write EDID data to FIFO as soon as FIFOI is set. On the other hand, FIFO sets the FIFOH
flag when its capacity is full. Software should not write additional data to FIFO in such instance. The FIFOI
interrupt can be masked or enabled by an EFIFO control bit. A simple way to control FIFO is to set (LS1,
MTV112A Revision 1.9 05/18/2001
12/20
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
LS0=1,0) and enable FIFOI interrupt, then software may load 4 bytes into FIFO each time a FIFOI interrupt
arises. A special control bit "LDFIFO" can reduce the software effort when EDID data is stored in EEPROM.
If LDFIFO=1, FIFO will be automatically loaded with MBUF data when software reads MBUF XFR.
5.2 DDC2B Mode
MTV112A switches to DDC2B mode when it detects a high to low transition on the HSCL pin. Once
MTV112A enters DDC2B mode, the host can access the EEPROM using IIC bus protocol as if the HSDA
and HSCL are directly bypassed to ISDA and ISCL pins. MTV112A will return to DDC1 mode if HSCL is
kept high for a 128 VSYNC clock period. However, it will lock in DDC2B mode if a valid IIC access has been
detected on HSCL/HSDA bus. The DDC2 flag reflects the current DDC status. S/W may clear it by setting
CLRDDC. Control bits M128/M256 are used to block the EEPROM write operation from the host if the
address is over 128/256.
5.3 Master Mode IIC Function Block
The master mode IIC block is connected to the ISDA and ISCL pins. Its speed can be selected to 100kHz or
400kHz by s/w set IICF control bit while MORE=0, or to 50KHz,100KHz,200KHz or 400KHz by s/w set
(MCLK1,MCLK0) bits while MORE=1. The software program can access the external EEPROM through this
interface. Since the EDID/VDIF data and display information share the common EEPROM, precaution must
be taken to avoid bus conflict. In DDC1 mode, the IIC interface is controlled by MTV112A only. In DDC2B
mode, the host may access the EEPROM directly. Software can test the HSCL condition by reading the
BUSY flag, which is set in case HSCL=0. A summary of master IIC access is illustrated as follows:
5.3.1. To Write EEPROM
1. Write the EEPROM slave address to MBUF (bit 0 = 0).
2. Set the S bit to Start.
3. After MTV112A transmits this byte, an MI interrupt will be triggered.
4. The program can write MBUF to transfer the next byte or set the P bit to Stop.
* Please see the attachments about "Master IIC Transmission Timing".
5.3.2. To Read EEPROM
1. Write the slave address to MBUF (bit 0 = 1).
2. Set the S bit to Start.
3. After MTV112A transmits this byte, a MI interrupt will be triggered.
4. Set or reset the ACK flag according to the IIC protocol.
5. Read out the useless byte to MBUF to continue the data transfer.
6. After MTV112A receives a new byte, the MI interrupt is triggered again.
7. Reading MBUF also triggers the next receiving operation, but setting the P bit before reading can
terminate the operation.
* Please see the attachments about "Master IIC Timing Receiving".
5.4 Slave Mode IIC Function Block
The slave mode IIC block can be connected to HSDA/HSCL or ISDA/ISCL pins, and selected by the SLVsel
control bit. This block can receive/transmit data using the IIC protocol. S/W may set the SLVADR register to
determine which slave address the block should respond to.
In receiving mode, the block first detects an IIC slave address match condition then issues a SLVMI interrupt.
The data received from SDA is shifted into a shift register and written to the RCBUF latch. The first byte
loaded is the word address (slave address is dropped). This block also generates an RCBI (Receive Buffer
full Interrupt) each time the RCBUF is loaded. If S/W can't read out the RCBUF in time, the next byte will not
be written to RCBUF and the slave block will return NACK to the master. This feature guarantees the data
integrity of communication. A WADR flag can tell S/W if the data in RCBUF is a word address.
In transmission mode, the block first detects an IIC slave address match condition then issues a SLVMI. In
the meantime, the data pre-stored in the TXBUF is loaded into the shift register, results in TXBUF emptying
and generates a TXBI (Transmission Buffer Interrupt). S/W should write the TXBUF a new byte for the next
transfer before the shift register empties. Failure to do this will cause data corruption. The TXBI occurs each
time the shift register receives new data from TXBUF. The SLVMI is cleared by writing the SLVSTUS
register. The RCBI is cleared by reading the RCBUF. The TXBI is cleared by writing the TXBUF.
MTV112A Revision 1.9 05/18/2001
13/20
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
If the control bit ENSCL is set, the block will hold SCL low until the RCBI/TXBI is cleared.
*Please see the attachments about "Slave IIC Block Timing".
Reg name
addr
bit7
LS1
X
bit6
LS0
bit5
bit4
bit3
bit2
bit1
bit0
S
BUSY
MCTR
00h (w)
LDFIFO M256
M128
ACK
P
SCLERR
MSTUS 00h (r)
MCTR
01h (w)
DDC2
X
BERR HFREQ FIFOH FIFOL
X
X
X
X
X
MCLK1 MCLK0
MBUF 10h (r/w) MBUF7 MBUF6 MBUF5 MBUF4 MBUF3 MBUF2 MBUF1 MBUF0
INTFLG 50h (r/w) HPRchg VPRchg HPLchg VPLchg HFchg VFchg
FIFOI
MI
INTEN
FIFO
60h (w) EHPR
EVPR
EHPL
EVPL
EHF
EVF
EFIFO
EMI
70h (w) FIFO7 FIFO6 FIFO5 FIFO4 FIFO3 FIFO2 FIFO1 FIFO0
SLVCTR 90h (w) ENSLV SLVsel ERCBI ESLVMI ETXBI ENSCL
X
X
X
SLVSTUS 91h (r) WADR SLVS
SLVSTUS 91h (w)
RCBI
SLVMI
Write to clear SLVMI
TXBI
RWB
ACKIN
RCBUF 92h (r) RCbuf7 RCbuf6 RCbuf5 RCbuf4 RCbuf3 RCbuf2 RCbuf1 RCbuf0
TXBUF 92h (w) TXbuf7 TXbuf6 TXbuf5 TXbuf4 TXbuf3 TXbuf2 TXbuf1 TXbuf0
SLVADR 93h (w) SLVadr7 SLVadr6 SLVadr5 SLVadr4 SLVadr3 SLVadr2 SLVadr1
X
MCTR (w) :
Master IIC interface control register.
LS1, LS0
= 11
= 10
= 01
= 00
= 1
® FIFOL is the status in which FIFO depth < 5.
® FIFOL is the status in which FIFO depth < 4.
® FIFOL is the status in which FIFO depth < 3.
® FIFOL is the status in which FIFO depth < 2.
® FIFO will be written while S/W reads MBUF.
LDFIFO
M256
M128
ACK
= 1
= 1
= 1
= 0
® Disables host writing EEPROM when address is over 256.
® Disables host writing EEPROM when address is over 128.
® In receiving mode, no acknowledgment is given by MTV112A.
® In receiving mode, ACK is returned by MTV112A.
S, P
= • , 0 ® Start condition when Master IIC is not transferring.
= X, • ® Stop condition when Master IIC is not transferring.
= 1, X ® Will resume transfer after a read/write MBUF operation.
= X, 0 ® Forces HSCL low and occupies the IIC bus.
MCLK1 : MCLK0 : Master IIC speed select,
= 0
= 1
= 2
= 3
® 50KHz for 8MHz X’tal, 75KHz for 12MHz X’tal.
® 100KHz for 8MHz X’tal, 150KHz for 12MHz X’tal.
® 200KHz for 8MHz X’tal, 300KHz for 12MHz X’tal .
® 400KHz for 8MHz X’tal, 600KHz for 12MHz X’tal.
* MTV112A uses a 100KHz clock to sample the S/P bit; any pulse should sustain at least 20us.
* A write/read MBUF operation can be recognized only after 10us of the MI flag's rising edge.
MSTUS (r) :
Master IIC interface status register.
SCLERR
= 1
® The ISCL pin has been pulled low by other devices during the transfer,
cleared when S=0.
DDC2
= 1
= 0
= 1
® DDC2B is active.
® MTV112A remains in DDC1 mode.
® IIC bus error, no ACK received from the slave, updated each time the
slave sends ACK on the ISDA pin.
® MTV112A has detected a higher than 200Hz clock on the VSYNC pin.
® FIFO high indicated.
BERR
HFREQ
FIFOH
FIFOL
BUSY
= 1
= 1
= 1
= 1
® FIFO low indicated.
® Host drives the HSCL pin to low.
MTV112A Revision 1.9 05/18/2001
14/20
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
* While writing FIFO, the FIFOH/FIFOL flag will reflect the FIFO condition after 30us.
MBUF (w) :
MBUF (r) :
Master IIC data shift register, after START and before STOP condition, write this register will
resume MTV112A's transmission to the IIC bus.
Master IIC data shift register, after START and before STOP condition, read this register will
resume MTV112A's receiving from the IIC bus.
INTFLG (w) : Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt
enabler bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear
this register while serving the interrupt routine.
FIFOI = 1
= 0
® No action.
® Clears FIFOI flag.
® No action.
MI
= 1
= 0
® Clears Master IIC bus interrupt flag (MI).
INTFLG (r) :
Interrupt flag.
® Indicates the FIFO low condition; when EFIFO is set, MTV112A will be interrupted
FIFOI = 1
by INT1.
MI
= 1
® Indicates when a byte is sent/received to/from the IIC bus; when EME is active,
MTV112A will be interrupted by INT1.
INTEN (w) :
Interrupt enabler.
® Enables FIFO interrupt.
® Enables Master IIC bus interrupt.
EFIFO = 1
EMI = 1
FIFO (w) :
Writes FIFO contents.
SLVCTR (w) : Slave IIC block control.
ENSLV
SLVsel
= 1
= 0
= 1
= 0
= 1
= 1
= 1
= 1
® Enables slave IIC block.
® Disables slave IIC block.
® Slave IIC connects to ISDA/ISCL.
® Slave IIC connects to HSDA/HSCL.
® Enables slave receiving buffer interrupt.
® Enables slave address match interrupt.
® Enables slave transmission buffer interrupt.
® Enables slave block to hold SCL pin low.
ERCBI
ESLVMI
ETXBI
ENSCL
SLVSTUS (r) : Slave IIC block status.
WADR
SLVS
RCBI
= 1
= 1
= 1
= 1
® The data in SLVBUF is a word address.
® The slave block has detected a START; cleared when STOP detected.
® RCBUF has loaded a new data byte; reset by S/W reading RCBUF.
® The slave block has detected the slave address match condition; cleared
by S/W writing SLVSTUS.
SLVMI
TXBI
RWB
= 1
= 1
= 0
= 1
® TXBUF is empty; reset by S/W writing TXBUF.
® Current transfer is slave transmitting.
® Current transfer is slave receiving.
ACKIN
® Master responds to NACK.
SLVSTUS (w) : Clears SLVMI flag.
RCBUF (r) :
TXBUF (w) :
Slave IIC receives data buffer.
Slave IIC transmits data buffer.
MTV112A Revision 1.9 05/18/2001
15/20
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
SLVADR (w) : Slave IIC address to which the slave block should respond.
6. Low Power Reset (LVR) & Watchdog Timer
When the voltage level of the power supply is below 4.0V for a specific time, the LVR will generate a chip
resetting signal. After the power supply is above 4.0V, LVR maintains the reset state for 144 Xtal cycles to
guarantee the chip exit reset condition has a stable Xtal oscillation. The specific time of power supply in a
low level is 3us and is adjustable by an external capacitor connected to the RST pin.
The watchdog timer automatically generates a device reset when it overflows. The interval of overflow is
0.25 sec x N, in which N is a number from 1 to 8, and can be programmed via register WDT (2:0). The timer
function is disabled after power-on reset. The user can activate this function by setting WEN and clear the
timer by setting WCLR.
7. A/D Converter
The MTV112 is equipped with two 4-bit or four 6-bit A/D converters. Each one can be enabled/disabled by
S/W control. The refresh rate for the ADC is OSC freq./6144(4-bit) or OSC freq./12288(6-bit). The ADC
compare the input pin voltage with the internal VDD*N/16(4-bit) or VDD*N/64(6-bit) voltage (where N = 0 -15
or N = 0 - 63). The ADC output value is N when pin voltage is greater than VDD*N/16 or VDD *N/64 and
smaller than VDD*(N+1)/16 or VDD*(N+1)/64.
Reg name addr
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ADC
ADC
ADC
WDT
A0h (w) ENADC
X
X
X
X
X
EADC1 EADC0
A0h (r) AD1b3 AD1b2 AD1b1 AD1b0 AD0b3 AD0b2 AD0b1 AD0b0
A0h (r)
X
X
ADb5
CLRDDC
ADb4
DIV253 DACK
ADb3
ADb2
ADb1
ADb0
80h (w) WEN
WCLR
WDT2 WDT1 WDT0
WDT (w) :
Watchdog timer control register.
WEN
WCLR
CLRDDC
= 1
= 1
= 1
® Enables watchdog timer.
® Clears watchdog timer.
® Clears DDC2 flag.
WDT2: WDT0 = 0
® Overflow interval = 8 x 0.25 sec.
® Overflow interval = 1 x 0.25 sec.
® Overflow interval = 2 x 0.25 sec.
® Overflow interval = 3 x 0.25 sec.
® Overflow interval = 4 x 0.25 sec.
® Overflow interval = 5 x 0.25 sec.
® Overflow interval = 6 x 0.25 sec.
® Overflow interval = 7 x 0.25 sec.
= 1
= 2
= 3
= 4
= 5
= 6
= 7
ADC (w) :
ENADC
ADC control.
= 1
® Enables ADC.
ADCMOD
= 1
® 4 channels 6 bits ADC are selected.
Note: Only one ADC input can be enabled at the same time.
® Dual 4 bits ADC are selected.(ADC1 and ADC0)
® Enables ADC3 pin input.
® Enables ADC2 pin input.
® Enables ADC1 pin input.
= 0
= 1
= 1
= 1
= 1
EADC3
EADC2
EADC1
EADC0
® Enables ADC0 pin input.
ADC (r) :
ADC conversion result.
AD1b3: AD1b0 4-bit ADC1 convert result.
AD0b3: AD0b0 4-bit ADC0 convert result.
MTV112A Revision 1.9 05/18/2001
16/20
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
ADb5: ADb0
6-bit ADC convert result.
4.0 Test Mode Condition
In normal applications, users should avoid the MTV012 entering its test/program mode, outlined as follow:
Test Mode A: RESET=1 & DA9=0 & DA8=1 & DA7=1 &DA6=0
Test Mode B: RESET falling edge & DA9=1 & DA8=0 & DA7=1 & DA6=0
5.0 ELECTRICAL PARAMETERS
5.1 Absolute Maximum Ratings
o
at: Ta= 0 to 70 C, VSS=0V
Name
Symbol
VDD
Vin
Vout
Topg
Range
-0.3 to +6.0
-0.3 to VDD+0.3
-0.3 to VDD+0.3
0 to +70
Unit
V
V
Maximum Supply Voltage
Maximum Input Voltage
Maximum Output Voltage
Maximum Operating Temperature
V
o
C
Maximum Storage Temperature
Tstg
-25 to +125
o
C
5.2 Allowable Operating Conditions
o
at: Ta= 0 to 70 C, VSS=0V
Name
Supply Voltage
Input "H" Voltage
Input "L" Voltage
Operating Freq.
Symbol
VDD
Vih1
Vil1
Fopg
Min.
4.0
0.4 x VDD
Max.
Unit
V
V
V
MHz
6.0
VDD +0.3
0.15 x VDD
15
-0.3
-
5.3 DC Characteristics
o
at: Ta=0 to 70 C, VDD=4.0V ~ 6.0V, VSS=0V
Name
Symbol
Condition
Min.
Typ.
Max.
Unit
Output "H" Voltage, except open-
drain pins: pin #s 16, 17, 29
Output "H" Voltage, pin #s 16, 17, 29
Output "L" Voltage
Voh1 Ioh=-50uA
4
V
Voh2 Ioh=-1mA
4
V
V
mA
mA
uA
Vol
Idd
Iol=8mA
Active
Idle
0.45
24
4.0
80
18
1.3
50
Power Supply Current
Power-Down
RST Pull-Down Resistor
Pin Capacitance
Rrst VDD=5V
Cio
50
150
15
Kohm
pF
5.4 AC Characteristics
o
at: Ta=0 to 70 C, VDD=4.0V ~ 6.0V, VSS=0V
Name
Crystal Frequency
PWM DAC Frequency
PWM DAC Frequency
HS Input Pulse Width
Symbol
fXtal
fDA
Condition
Min.
Typ.
8
Max.
Unit
MHz
KHz
KHz
uS
fXtal=8MHz
fXtal=12MHz
31.25
46.875
0.3
31.62
47.43
12
fDA
tHIPW fXtal=8MHz
MTV112A Revision 1.9 05/18/2001
17/20
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
VS Input Pulse Width
HS Input Pulse Width
VS Input Pulse Width
HSYNC to HBLANK Output Jitter
H+V to VBLANK Output Delay
H+V to VBLANK Output Delay
VS Pulse Width in H+V Signal
VS Pulse Width in H+V Signal
tVIPW fXtal=8MHz
tHIPW fXtal=12MHz
tVIPW fXtal=12MHz
tHHBJ
tVVBD fXtal=8MHz
tVVBD fXtal=12MHz
tVCPW fXtal=8MHz
tVCPW FXtal=12MHz
3
0.2
2
US
8
5
US
US
NS
uS
uS
uS
uS
16
10
32
20
6.0 PACKAGE DIMENSION
6.1 40 pin PDIP 600 mil
52.197mm +/-
0.127
1.981m
m
+/-0.254
2.540m
m
1.270mm +/-
0.254
0.457mm +/-
0.127
15.494mm +/-
0.254
13.868mm +/-
0.102
0.254m
m
1.778m
m
+/-0.102
3.81mm
+/-0.127
+/-0.127
0.254m
m
(min.)
5o~7
3.302m
m
0
+/-0.254
6o +/-
3o
16.256mm +/-
0.508
6.2 42 pin SDIP 600 mil
36.83mm +/-0.05
MTV 112A
1.981mm
+/-0.254
0.457mm +/-0.127
1.270mm +/-0.254
70TYP.
15.494mm +/-0.254
13.868mm +/-0.102
0.254mm
+/-0.102
1.778mm
3.81mm
+/-0.127
+/-0.127
0.254mm
(min.)
5o~70
3.302mm
+/-0.254
6o +/-3o
16.256mm +/-0.508
MTV112A Revision 1.9 05/18/2001
18/20
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
6.3 44 pin PLCC Unit: inch
PIN #1 HOLE
0.045*450
0.180 MAX.
0.020 MIN.
0.013~0.021 TYP.
0.690 +/-0.005
0.610 +/-0.02
0.653 +/-0.003
0.500
70TYP.
0.070
0.010
0.050 TYP.
0.026~0.032 TYP.
0.070
0.653 +/-0.003
0.690 +/-0.005
MTV112A Revision 1.9 05/18/2001
19/20
MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
7.0 Ordering Information
Standard configurations:
Prefix
Part Type
Package Type
N: PDIP
Other Information
MTV
112A
V: PLCC
Part Numbers:
MTV112A N -999
Prefix
Part Type
Package Type
Code Number
MTV112A Revision 1.9 05/18/2001
20/20
相关型号：
©2020 ICPDF网 联系我们和版权申明