NB100LVEP56/D [ETC]
2.5 V / 3.3 V 5 V ECL Dual Differential 2:1 Multiplexer ; 2.5 V / 3.3 V，5 V ECL双差分2 ： 1多路复用器\n
| 型号： | NB100LVEP56/D |
| 厂家： | 
ETC |
| 描述： | 2.5 V / 3.3 V 5 V ECL Dual Differential 2:1 Multiplexer
|
| 文件： | 总12页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB100LVEP56
2.5V / 3.3V / 5VꢀECL Dual
Differential 2:1 Multiplexer
The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The
differential data path makes the device ideal for multiplexing low
skew clock or differential data signals. The device features both
individual and common select inputs to address both data path and
random logic applications. Common and individual selects can accept
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MARKING
both ECL and CMOS input voltage levels. Multiple V pins are
BB
DIAGRAMS*
provided.
The V pin, an internally generated voltage supply, is available to
this device only. For single-ended input operation, the unused
BB
20
20
differential input is connected to V as a switching reference voltage.
BB
1
N100
LP56
ALYW
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
TSSOP-20
DT SUFFIX
CASE 948E
and V via a 0.01 mF capacitor and limit current sourcing or sinking
CC
to 0.5 mA. When not used, V should be left open.
BB
1
• Maximum Input Clock Frequency > 2.5 GHz Typical
• Maximum Input Data Rate > 2.5 Gb/s Typical
24
1
• 525 ps Typical Propagation Delays
• Low Profile QFN Package
N100
LP56
ALYW
24
1
24 PIN QFN
MN SUFFIX
CASE 485L
• PECL Mode Operating Range: V = 2.375 V to 5.5 V
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
A
L
Y
= Assembly Location
= Wafer Lot
= Year
with V = -2.375 V to -5.5 V
EE
• Separate, Common Select, and Individual Select
W = Work Week
(Compatible with ECL and CMOS Input Voltage Levels)
• Q Output Will Default LOW with Inputs Open or at V
EE
*For additional information, see Application Note
AND8002/D
• Multiple V Outputs
BB
ORDERING INFORMATION
Device
Package
Shipping
NB100LVEP56DT
TSSOP-20
75 Units/Rail
NB100LVEP56DTR2 TSSOP-20 2500 Tape & Reel
NB100LVEP56MN QFN-24 92 Units/Rail
NB100LVEP56MNR2 QFN-24 3000 Tape & Reel
Semiconductor Components Industries, LLC, 2003
1
Publication Order Number:
April, 2003 - Rev. 3
NB100LVEP56/D
NB100LVEP56
Table 1. PIN DESCRIPTION
Pin No.
Default
State
TSSOP
QFN
Name
I/O
Description
14,20
3,9,18,19,
20
V
CC
-
-
Positive Supply Voltage. All VCC Pins must be Externally Con-
nected to Power Supply to Guarantee Proper Operation.
11
3,8
1
15,24
6,12
4
V
-
-
Negative Supply Voltage. All VEE Pins must be Externally Con-
nected to Power Supply to Guarantee Proper Operation.
EE
V
BB0
,
-
-
ECL Reference Voltage Output
V
BB1
D0a
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
ECL Output
ECL Output
ECL Output
ECL Output
Low
High
Low
High
Low
High
Low
High
-
Noninverted Differential Data a Input to MUX 0. Internal 75 kW to
V
EE
.
2
5
D0a
Inverted Differential Data a Input to MUX 0. Internal 75 kW to V
EE
and 37 kW to V
.
CC
4
7
D0b
Noninverted Differential Data b Input to MUX 0. Internal 75 kW to
V
EE
.
5
8
D0b
Inverted Differential Data b Input to MUX 0. Internal 75 kW to V
EE
and 37 kW to V
.
CC
6
10
11
13
14
2
D1a
Noninverted Differential Data a Input to MUX 1. Internal 75 kW to
V
EE
.
7
D1a
Inverted Differential Data a Input to MUX 1. Internal 75 kW to V
EE
and 37 kW to V
.
CC
9
D1b
Noninverted Differential Data b Input to MUX 1. Internal 75 kW to
V
EE
.
10
19
18
13
12
17
16
15
N/A
D1b
Inverted Differential Data b Input to MUX 1. Internal 75 kW to V
EE
and 37 kW to V
.
CC
Q0
Noninverted Differential Output MUX 0. Typically Terminated with
50 W to V = V - 2 V.
TT
CC
1
Q0
-
Inverted Differential Output MUX 0. Typically Terminated with
50 W to V = V - 2 V.
TT
CC
17
16
23
22
21
-
Q1
-
Noninverted Differential Output MUX 1. Typically Terminated with
50 W to V = V - 2 V.
TT
CC
Q1
-
Inverted Differential Output MUX 1. Typically Terminated with
50 W to V = V - 2 V.
TT
CC
SEL0
COM_SEL
SEL1
EP
ECL, CMOS
Input
Low
Low
Low
Noninverted Differential Select Input to MUX 0. Internal 75 W to
V
EE
.
ECL, CMOS
Input
Noninverted Differential Common Select Input to Both MUX. In-
ternal 75 W to V
.
EE
ECL, CMOS
Input
Noninverted Differential Select Input to MUX 1. Internal 75 W to
V
EE
.
-
Exposed Pad. (Note 1)
1. The thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heat sinking conduit.
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2
NB100LVEP56
D0a
R
1
1
1
R
R
2
2
Q0
Q0
D0a
R
D0b
0
Table 2. TRUTH TABLE
R
1
1
SEL0
SEL0
SEL1
COM_SEL Q0, Q0
Q1, Q1
R
R
R
1
1
1
D0b
R
X
L
L
H
H
X
L
H
H
L
H
L
L
L
L
a
b
b
a
a
a
b
a
a
b
COM_SEL
SEL1
D1a
R
1
1
1
R
R
2
2
D1a
Q1
Q1
R
D1b
0
R
1
1
V
CC
V
EE
D1b
R
Exposed Pad
(EP)
COM
SEL
Figure 1. Logic Diagram
V
EE
SEL0
SEL1 V
V
CC CC
24
23
22
21
20
19
Q0
Q0
1
2
3
4
5
6
18
V
CC
20 19 18 17 16 15 14 13 12
11
17 Q1
16
15
14
13
V
CC
Q1
NB100LVEP56
NB100LVEP56
D0a
V
EE
D1b
D1b
D0a
1
2
3
4
5
6
7
8
9
10
V
BB0
7
8
9
10
11
12
D0b D0b V
D1a D1a V
CC
BB1
Figure 1. TSSOP-20 Lead Pinout (Top View)
Figure 2. QFN-24 Lead Pinout (Top View)
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
(R1)
(R2)
75 kW
37 kW
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 150 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Level 1
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
354 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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NB100LVEP56
Table 4. MAXIMUM RATINGS (Note 2)
Symbol Parameter
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
CC
V
EE
V
I
Positive Mode Power Supply
Negative Mode Power Supply
V
V
6
EE
= 0 V
-6
V
CC
Positive Mode Input Voltage
Negative Mode Input Voltage
V
EE
V
CC
= 0 V
= 0 V
V v V
6
-6
V
V
I
CC
EE
V w V
I
I
Output Current
Continuous
Surge
50
100
mA
mA
out
I
V
Sink/Source
"0.5
mA
°C
BB
BB
T
Operating Temperature Range
Storage Temperature Range
-40 to +85
-65 to +150
A
T
°C
stg
q
Thermal Resistance (Junction-to-Ambient)
JEDEC 51-3 (1S - Single Layer Test Board)
0 LFPM
500 LFPM
20 TSSOP
20 TSSOP
140
50
°C/W
°C/W
JA
q
Thermal Resistance (Junction-to-Ambient)
JEDEC 51-6 (2S2P-Multi Layer Test Board) with Filled Thermal
Vias
0 LFPM
500 LFPM
24 QFN
24 QFN
37
32
°C/W
°C/W
JA
q
Thermal Resistance (Junction-to-Case)
Standard Board
20 TSSOP
24 QFN
23 to 41
11
°C/W
°C
JC
T
sol
Wave Solder
<2 to 3 sec @ 248°C
265
2. Maximum Ratings are those values beyond which device damage may occur.
Table 5. DC CHARACTERISTICS, PECL V = 2.5 V, V = 0 V (Note 3)
CC
EE
-40 °C
Typ
45
25°C
85°C
Min
Max
Min
Typ
Max
55
Min
Typ
Max
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 4)
Output LOW Voltage (Note 4)
Unit
mA
mV
mV
mV
I
EE
35
55
35
45
35
48
58
V
OH
V
OL
V
IH
1355 1480 1605 1355 1480 1605 1355 1480 1605
555
775
900
555
775
900
555
775
900
Input HIGH Voltage (SEL0, SEL1, COM_SEL) 1335
V
CC
1335
V
CC
1275
V
CC
1335
1620 1335
1620 1275
1620
Input HIGH Voltage (D Inputs) (Note 5)
V
V
Input LOW Voltage (SEL0, SEL1, COM_SEL)
Input LOW Voltage (D Inputs) (Note 5)
V
555
875
875
V
555
875
875
V
EE
555
875
875
mV
V
IL
EE
EE
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 6)
1.2
2.5
1.2
2.5
1.2
2.5
IHCMR
I
I
Input HIGH Current (@V
)
150
150
150
mA
mA
IH
IH
Input LOW Current (@V )
D
D
SEL
0.5
-150
-150
0.5
-150
-150
0.5
-150
-150
IL
IL
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with V . V can vary +0.125 V to -1.3 V.
CC
EE
4. All loading with 50 W to V -2.0 V.
CC
5. Do not use V at V < 3.0 V.
BB
CC
6. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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4
NB100LVEP56
Table 6. DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 7)
CC
EE
-40 °C
Typ
45
25°C
Typ
45
85°C
Typ
Min
Max
Min
Max
Min
Max
58
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 8)
Output LOW Voltage (Note 8)
Unit
mA
mV
mV
mV
I
EE
35
55
35
55
35
48
V
OH
V
OL
V
IH
2155 2280 2405 2155 2280 2405 2155
1355 1575 1700 1355 1575 1700 1355
2280
1575
2405
1700
Input HIGH Voltage (SEL0, SEL1, COM_SEL)
Input HIGH Voltage (D Inputs)
2135
2135
V
CC
2135
V
CC
2135
V
CC
2420
2420 2135
2420 2135
V
IL
Input LOW Voltage (SEL0, SEL1, COM_SEL)
Input LOW Voltage (D Inputs)
V
1355
1675
1675 1355
V
1675
1675 1355
V
1675
1675
mV
EE
EE
EE
V
V
Output Reference Voltage (Note 9)
1775 1875 1975 1775 1875 1975 1775
1875
1975
3.3
mV
V
BB
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 10)
1.2
3.3
1.2
3.3
1.2
IHCMR
I
I
Input HIGH Current (@V
)
150
150
150
mA
mA
IH
IH
Input LOW Current (@V )
D
D
SEL
0.5
-150
-150
0.5
-150
-150
0.5
-150
-150
IL
IL
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
7. Input and output parameters vary 1:1 with V . V can vary +0.925 V to -0.5 V.
CC
EE
8. All loading with 50 W to V -2.0 V.
CC
9. Single-Ended input operation is limited to V ꢀ 3.0 V in PECL mode.
CC
10.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 7. DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 11)
CC
EE
-40 °C
Typ
50
25°C
Typ
50
85°C
Typ
Min
Max
Min
Max
Min
Max
65
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 12)
Output LOW Voltage (Note 12)
Unit
mA
mV
mV
mV
I
EE
40
60
40
60
45
55
V
OH
V
OL
V
IH
3855 3980 4105 3855 3980 4105 3855
3055 3275 3400 3055 3275 3400 3055
3980
3275
4105
3400
Input HIGH Voltage (SEL0, SEL1, COM_SEL)
Input HIGH Voltage (D Inputs)
3775
3775
V
CC
3775
V
CC
3775
V
CC
4120
4120 3775
4120 3775
V
IL
Input LOW Voltage (SEL0, SEL1, COM_SEL)
Input LOW Voltage (D Inputs)
V
3055
3375
3375 3055
V
3375
3375 3055
V
3375
3375
mV
EE
EE
EE
V
V
Output Voltage Reference
3475 3575 3675 3475 3575 3675 3475
3575
3675
5.0
mV
V
BB
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 13)
1.2
5.0
1.2
5.0
1.2
IHCMR
I
I
Input HIGH Current (@V
)
150
150
150
mA
mA
IH
IH
Input LOW Current (@V )
D
D
SEL
0.5
-150
-150
0.5
-150
-150
0.5
-150
-150
IL
IL
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
11. Input and output parameters vary 1:1 with V . V can vary +2.0 V to -0.5 V.
CC
EE
12.All loading with 50 ohms to V -2.0 V.
CC
13.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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NB100LVEP56
Table 8. DC CHARACTERISTICS, NECL V = 0 V, V = -3.8 V to -2.375 V (Note 14)
CC
EE
-40 °C
25°C
Typ
45
85°C
Typ
48
Min
Typ
Max
55
Min
Max
55
Min
Max
58
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 15)
Output LOW Voltage (Note 15)
Input HIGH Voltage
Unit
mA
mV
mV
mV
I
EE
35
45
35
35
V
OH
V
OL
V
IH
-1145 -1020
-895
-1145 -1020
-895
-1145 -1020
-895
-1945 -1725 -1600 -1945 -1725 -1600 -1945 -1725 -1600
-1165
-1165
V
CC
-1165
-1165
V
CC
-1165
-1165
V
CC
(SEL0, SEL1, COM_SEL)
Input HIGH Voltage
-880
-880
-880
(D Inputs)
V
IL
Input LOW Voltage
(SEL0, SEL1, COM_SEL)
Input LOW Voltage
mV
V
-1600
V
-1600
V
-1600
-1600
EE
EE
EE
-1945
-1600 -1945
-1600 -1945
(D Inputs)
V
V
Output Reference Voltage (Note 16)
-1525 -1425 -1325 -1525 -1425 -1325 -1525 -1425 -1325
mV
V
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 17)
V
EE
+1.2
0.0
V
EE
+1.2
0.0
V
EE
+1.2
0.0
IHCMR
I
I
Input HIGH Current (@V
)
150
150
150
mA
mA
IH
IH
Input LOW Current (@V )
D
D
0.5
-150
0.5
-150
-150
0.5
-150
-150
IL
IL
SEL -150
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
14.Input and output parameters vary 1:1 with V
.
CC
15.All loading with 50 W to V -2.0 V.
CC
16.Single-Ended input operation is limited to V from -3.0 V to -5.5 V in NECL mode.
EE
17.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 9. DC CHARACTERISTICS, NECL V = 0 V, V = -3.8 V to -5.5 V (Note 18)
CC
EE
-40 °C
25°C
Typ
50
85°C
Typ
55
Min
Typ
Max
60
Min
Max
60
Min
Max
65
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 19)
Output LOW Voltage (Note 19)
Input HIGH Voltage
Unit
mA
mV
mV
mV
I
EE
40
50
40
45
V
OH
V
OL
V
IH
-1145 -1020
-895
-1145 -1020
-895
-1145 -1020
-895
-1945 -1725 -1600 -1945 -1725 -1600 -1945 -1725 -1600
-1165
-1165
V
CC
-1165
-1165
V
CC
-1165
-1165
V
CC
(SEL0, SEL1, COM_SEL)
Input HIGH Voltage
-880
-880
-880
(D Inputs)
V
IL
Input LOW Voltage
(SEL0, SEL1, COM_SEL)
Input LOW Voltage
mV
V
-1600
V
-1600
V
-1600
-1625
EE
EE
EE
-1945
-1625 -1945
-1625 -1945
(D Inputs)
V
V
Output Reference Voltage (Note 20)
-1525 -1425 -1325 -1525 -1425 -1325 -1525 -1425 -1325
mV
V
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 21)
V
EE
+1.2
0.0
V
EE
+1.2
0.0
V
EE
+1.2
0.0
IHCMR
I
I
Input HIGH Current (@V
)
150
150
150
mA
mA
IH
IH
Input LOW Current (@V )
D
D
0.5
-150
0.5
-150
-150
0.5
-150
-150
IL
IL
SEL -150
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18.Input and output parameters vary 1:1 with V
.
CC
19.All loading with 50 W to V -2.0 V.
CC
20.Single-Ended input operation is limited to V from -3.0 V to -5.5 V in NECL mode.
EE
21.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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NB100LVEP56
Table 10. AC CHARACTERISTICS V = 0 V; V = -2.375 V to -3.8 V or V = 2.375 V to 3.8 V; V = 0 V (Note 22)
CC
EE
CC
EE
-40 °C
25°C
85°C
Min Typ Max Min Typ Max Min
Typ
Max
Symbol
Characteristic
Unit
V
Output Voltage Amplitude
(See Figure 2)
f
v 1 GHz 525 700
in
550 700
500 600
350 450
500
400
200
700
500
300
mV
OUTPP
f = 2 GHz 500 600
in
f
= 2.5 GHz 400 500
in
t
t
,
Propagation Delay to Output Differential
ps
ps
ps
PLH
PHL
D to Q, Q 375 500
SEL to Q, Q 575 775
625 400 525
975 625 825 1025 700
950 600 800 1000 700
650 450
575
900
900
700
1100
1100
COM_SEL to Q, Q 550 750
t
Pulse Skew (Note 23)
Within Device Input Skew (Note 24)
Within Device Output Skew (Note 25)
Device-to-Device Skew (Note 26)
10
5
15
50
50
30
50
10
5
15
50
10
5
15
50
50
30
50
Skew
200
200
t
RMS Random Clock Jitter
(Note 27)
f
in
= 2.5 GHz
1
1
1
JITTER
Peak-to-Peak Data Dependent Jitter
(Note 28)
f
in
=1.5 Gb/s
= 2.5 Gb/s
5
15
10
25
10
25
in
f
V
INPP
Input Voltage Swing (Differential Configuration)
(Note 29)
150 800 1200 150 800 1200 150
800
1200 mV
t
r
t
f
Output Rise/Fall Times @ 50 MHz
(20% - 80%)
Q, Q
ps
60
110
150
60
120
170
90
140
230
22.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V -2.0 V. Input edge rates 150 ps (20% - 80%).
CC
23.Pulse Skew |t
- t
|
PLH
PHL
24.Worst case difference between D0a and D0b (or between D1a or D1b), when both output come from same input.
25.Worst case difference between Q0 and Q1 outputs.
26.Skew is measured between outputs under identical transitions.
27.Additive RMS jitter with 50% Duty Cycle Clock Signal at f = 2.5 GHz.
in
31
28.Additive Peak-to-Peak jitter with input NRZ data at PRBS 2 -1 at f = 2.5 Gb/s.
in
29.Input voltage swing is a single-ended measurement operating in differential mode.
Table 11. AC CHARACTERISTICS V = 0 V; V = -4.2 V to -5.5 V or V = 4.2 V to 5.5 V; V = 0 V (Note 30)
CC
EE
CC
EE
-40 °C
25°C
85°C
Min Typ Max Min Typ Max Min
Typ
Max
Symbol
Characteristic
Unit
V
Output Voltage Amplitude
(See Figure 3)
f
v 1 GHz 600 750
in
600 750
500 600
350 450
600
400
200
750
500
300
mV
OUTPP
f = 2 GHz 550 650
in
f
= 2.5 GHz 400 550
in
t
t
,
Propagation Delay to Output Differential
ps
ps
ps
PLH
PHL
D to Q, Q 375 500
SEL to Q, Q 575 775
625 400 525
975 625 825 1025 700
950 600 800 1000 700
650 450
575
900
900
700
1100
1100
COM_SEL to Q, Q 550 750
t
Pulse Skew (Note 31)
Within Device Input Skew (Note 32)
Within Device Output Skew (Note 33)
Device-to-Device Skew (Note 34)
5
15
20
50
50
30
50
5
50
30
50
5
50
30
50
Skew
15
20
50
15
20
50
200
200
200
t
RMS Random Clock Jitter
(Note 35)
f
in
= 2.5 GHz
1
1
1
JITTER
Peak-to-Peak Data Dependent Jitter
(Note 36)
f
in
=1.5 Gb/s
= 2.5 Gb/s
5
15
10
25
10
20
in
f
V
INPP
Input Voltage Swing (Differential Configuration)
(Note 37)
150 800 1200 150 800 1200 150
800
1200 mV
t
r
t
f
Output Rise/Fall Times @ 50 MHz
(20% - 80%)
Q, Q
ps
60
110
150
60
120
170
90
140
230
30.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V -2.0 V. Input edge rates 150 ps (20% - 80%).
CC
31.Pulse Skew |t
- t
|
PLH
PHL
32.Worst case difference between D0a and D0b (or between D1a or D1b), when both output come from same input.
33.Worst case difference between Q0 and Q1 outputs.
34.Skew is measured between outputs under identical transitions.
35.Additive RMS jitter with 50% Duty Cycle Clock Signal at f = 2.5 GHz.
in
31
36.Additive Peak-to-Peak jitter with input NRZ data at PRBS 2 -1 at f = 2.5 Gb/s.
in
37.Input voltage swing is a single-ended measurement operating in differential mode.
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7
NB100LVEP56
850
750
650
550
450
350
250
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
Q AMP (mV)
JITTER (ps)
1.0
0.5
1.5
2.0
2.5
INPUT FREQUENCY (GHz)
Figure 2. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at VCC = 2.5 V, 255C
850
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
Q AMP (mV)
750
650
550
450
350
JITTER (ps)
250
0.5
1.0
1.5
2.0
2.5
INPUT FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at VCC = 5.0 V, 255C
D
V
INPP
= V (D) - V (D)
IH IL
D
Q
V
= V (Q) - V (Q)
OUTPP
OH
OL
Q
t
PHL
t
PLH
Figure 4. AC Reference Measurement
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8
NB100LVEP56
Q
Q
D
Receiver
Device
Driver
Device
D
50
TT
50
W
W
V
TT
V
V
=
- 2.0 V
CC
Figure 5. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
AN1405
AN1406
AN1504
AN1568
AN1672
AND8002
AND8009
AND8020
-
-
-
-
-
-
-
-
-
ECLinPS Circuit Performance at Non-Standard V Levels
IH
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Marking and Date Codes
ECLinPS Plus Spice I/O Model Kit
Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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9
NB100LVEP56
PACKAGE DIMENSIONS
TSSOP-20
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E-02
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20X K REF
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2. ICONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
K
K1
20
11
2X L/2
J J1
B
L
-U-
PIN 1
IDENT
SECTION N-N
1
10
0.25 (0.010)
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
N
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
0.15 (0.006) T U
M
A
-V-
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
A
B
6.40
4.30
−−−
6.60 0.252
4.50 0.169
N
C
1.20
−−−
D
0.05
0.50
0.15 0.002
0.75 0.020
F
F
G
H
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
J
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
-W-
J1
K
C
K1
L
6.40 BSC
0 8 0 8
0.252 BSC
G
D
M
_
_
_
_
H
DETAIL E
0.100 (0.004)
-T- SEATING
PLANE
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10
NB100LVEP56
PACKAGE DIMENSIONS
QFN 24
MN SUFFIX
24 PIN QFN, 4x4
CASE 485L-01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
D
A
B
E
PIN 1
IDENTIFICATION
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
MILLIMETERS
DIM MIN
MAX
1.00
0.05
0.80
2X
A
A1
A2
A3
b
0.80
0.00
0.60
0.15
C
0.20 REF
2X
0.15
C
0.23
0.28
D
4.00 BSC
A2
D2
E
2.70
2.70
2.90
0.10
C
4.00 BSC
E2
e
2.90
A
0.50 BSC
0.08
C
L
0.35
0.45
A3
SEATING
PLANE
REF
A1
C
D2
e
L
7
12
6
1
13
E2
24X
b
18
24
19
e
0.10 C A B
0.05 C
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11
NB100LVEP56
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NB100LVEP56/D
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