NBSG16VS/D [ETC]
2.5V / 3.3V SiGe Differential Receiver/Driver with Variable Output Swing ; 2.5V / 3.3V的SiGe差分接收器/驱动器,带有可变输出摆幅\n![NBSG16VS/D](http://pdffile.icpdf.com/pdf1/p00005/img/icpdf/NBSG1_22369_icpdf.jpg)
型号: | NBSG16VS/D |
厂家: | ![]() |
描述: | 2.5V / 3.3V SiGe Differential Receiver/Driver with Variable Output Swing
|
文件: | 总14页 (文件大小:113K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NBSG16VS
2.5V/3.3VꢀSiGe Differential
Receiver/Driver with
Variable Output Swing
The NBSG16VS is a differential receiver/driver targeted for high
frequency applications that require variable output swing. The device
is functionally equivalent to the EP16VS device with much higher
bandwidth and lower EMI capabilities. This device may be used for
applications driving VCSEL lasers.
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MARKING
DIAGRAM*
Inputs incorporate internal 50 W termination resistors and accept
NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS,
CML, or LVDS. The output amplitude is varied by applying a voltage
SGS
16
LYW
to the V
input pin. Outputs are variable swing ECL from 100 mV
CTRL
FCBGA-16
BA SUFFIX
CASE 489
to 750 mV amplitude, optimized for operation from V - V = 3.0
CC
EE
V to 3.465 V.
The V and V
pins are internally generated voltage supplies
MM
BB
available to this device only. The V is used as a reference voltage
BB
for single-ended NECL or PECL inputs and the V
pin is used as a
MM
SG16VS
ALYW
reference voltage for LVCMOS inputs. For single-ended input
operation, the unused complementary differential input is connected to
V
or V
as a switching reference voltage. V or V
may also
BB
MM
BB
MM
QFN-16
MN SUFFIX
CASE 485G
rebias AC coupled inputs. When used, decouple V and V
0.01 m F capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V and V outputs should be left open.
via a
A = Assembly Location
L = Wafer Lot
Y = Year
BB
MM
BB
MM
W = Work Week
• Maximum Input Clock Frequency up to 12 GHz Typical
• Maximum Input Data Rate up to 12 Gb/s Typical
*For additional information, refer to Application Note
AND8002/D
• 40 ps Typical Rise and Fall Times (V
• 120 ps Typical Propagation Delay (V
= V - 1 V)
CTRL
CC
= V - 1 V)
CTRL
CC
ORDERING INFORMATION
• Variable Swing PECL Output with Operating Range: V = 2.375 V
CC
to 3.465 V with V = 0 V
EE
Device
Package
Shipping
• Variable Swing NECL Output with NECL Inputs with
NBSG16VSBA
4x4 mm
FCBGA-16
100 Units/Tray
Operating Range: V = 0 V with V = -2.375 V to -3.465 V
CC
EE
• Output Level (100 mV to 750 mV Peak-to-Peak Output;
- V = 3.0 V to 3.465 V), Differential Output Only
NBSG16VSBAR2
NBSG16VSMN
4x4 mm
FCBGA-16
500/Tape & Reel
123 Units/Rail
V
CC
EE
• 50 W Internal Input Termination Resistors
• Compatible with Existing 2.5 V/3.3 V EP Devices
3x3 mm
QFN-16
• V and V
Reference Voltage Output
BB
MM
NBSG16VSMNR2
3x3 mm
QFN-16
3000/Tape & Reel
Board
Description
NBSG16VSBAEVB
NBSG16VSBA
Evaluation Board
Semiconductor Components Industries, LLC, 2003
1
Publication Order Number:
April, 2003 - Rev. 5
NBSG16VS/D
NBSG16VS
1
2
3
4
V
EE
V
BB
V
MM
V
EE
Exposed Pad (EP)
16
15
14
13
A
B
V
NC
V
V
EE
EE
CTRL
VTD
D
V
CC
1
2
3
4
12
11
10
9
D
D
VTD
VTD
V
Q
Q
CC
CC
MM
Q
Q
V
NBSG16VS
D
V
C
D
VTD
CC
V
EE
V
BB
V
V
EE
5
6
7
8
V
EE
NC V
V
CTRL EE
Figure 1. BGA-16 Pinout (Top View)
Figure 2. QFN-16 Pinout (Top View)
Table 1. Pin Description
Pin
BGA
C2
QFN
Name
VTD
D
I/O
Description
1
2
-
Internal 50 W Termination Pin. See Table 2.
C1
ECL, CML, Inverted Differential Input. Internal 75 kW to V and 36.5 kW to V
.
EE
CC
LVCMOS,
LVDS,
LVTTL
Input
B1
B2
3
D
ECL, CML, Noninverted Differential Input. Internal 75 kW to V
LVCMOS,
LVDS,
LVTTL
Input
.
EE
4
VTD
-
-
Internal 50 W Termination Pin. See Table 2.
A1,D1,A4,
D4
5,8,13,16
V
EE
Negative Supply Voltage
A2
A3
6
7
NC
-
No Connect
V
Output Amplitude Swing Control. Bypass Pin to V through 0.1 m F Capacitor.
CTRL
CC
B3,C3
B4
9,12
10
V
-
Positive Supply Voltage
CC
Q
RSECL
Output
Noninverted Differential Output. Typically Terminated with 50 W to
V
TT
= V
- 2 V
CC
C4
11
Q
RSECL
Output
Inverted Differential Output. Typically Terminated with 50 W to V = V
- 2 V
TT
CC
D3
D2
14
15
-
V
-
-
-
LVCMOS Reference Voltage Output. (V
ECL Reference Voltage Output
Exposed Pad. (Note 2)
- V )/2
CC EE
MM
V
BB
N/A
EP
1. The NC pin is electrically connected to the die and must be left open.
2. All V and V pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package
CC
EE
bottom (see case drawing) must be attached to a heat-sinking conduit.
3. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage, and if no signal
is applied then the device will be susceptible to self-oscillation.
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2
NBSG16VS
+3.3 V
V
CC
+
V
CTRL
0.1 mF
V
V
CTRL CC
R
VAR
V
CTRL
V
CC
V
MM
36.5
VTD
V
MM
VTD
36.5
KW
50
50
W
W
K
W
Q
50
50
W
W
D
D
Q OUT
Q OUT
Q
Q
D
D
Q OUT
Q OUT
Q
V
75
KW
75
KW
140
W
140 W
75
KW
75
50
W
50
W
BB
KW
VTD
V
BB
VTD
V
CC
- 2 V
V
EE
V
EE
Figure 3. Logic Diagram/
Voltage Source Implementation
Figure 4. Alternative Voltage Source Implementation
Table 2. INTERFACING OPTIONS
INTERFACING OPTIONS
CONNECTIONS
Connect VTD and VTD to V
CML
LVDS
CC
Connect VTD and VTD Together
Bias VTD and VTD Inputs within
AC-COUPLED
Common Mode Range (V
)
IHCMR
RSECL, PECL, NECL
LVTTL
Standard ECL Termination Techniques
An external voltage should be applied to the unused
complementary differential input. Nominal voltage is
1.5 V for LVTTL.
LVCMOS
V
MM
should be connected to the unused
complementary differential input.
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3
NBSG16VS
Table 3. ATTRIBUTES
Characteristics
Value
75 k
36.5 k
Internal Input Pulldown Resistor (D, D)
Internal Input Pullup Resistor (D)
ESD Protection
W
W
Human Body Model
> 2 kV
Machine Model
> 100 V
Moisture Sensitivity (Note 1)
FCBGA-16
QFN-16
Level 3
Level 1
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
192
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS (Note 2)
Symbol Parameter
Positive Power Supply
Condition 1
= 0 V
Condition 2
Rating
Units
V
CC
V
EE
V
I
V
V
3.6
V
V
EE
Negative Power Supply
= 0 V
-3.6
CC
Positive Input
Negative Input
V
EE
V
CC
= 0 V
= 0 V
V v V
3.6
-3.6
V
V
I
I
CC
EE
V w V
V
INPP
Differential Input Voltage
|D - D|
V
CC
V
CC
- V w 2.8 V
2.8
V
V
EE
- V t 2.8 V
|V
- V
|
EE
CC
EE
I
I
Output Current
Continuous
Surge
25
50
mA
mA
OUT
Input Current Through R (50 WResistor)
Static
Surge
45
80
mA
mA
IN
T
I
I
V
V
Sink/Source
Sink/Source
1
1
mA
mA
°C
BB
BB
MM
MM
TA
Operating Temperature Range
Storage Temperature Range
-40 to +85
-65 to +150
108
T
°C
stg
q
Thermal Resistance (Junction-to-Ambient) 0 LFPM
(Note 3)
16 FCBGA
16 FCBGA
16 QFN
°C/W
JA
500 LFPM
0 LFPM
500 LFPM
86
41.6
35.2
°C/W
°C/W
°C/W
16 QFN
q
Thermal Resistance (Junction-to-Case)
Wave Solder
2S2P (Note 3)
2S2P (Note 4)
16 FCBGA
16 QFN
5.0
4.0
°C/W
°C/W
JC
T
sol
< 15 sec.
225
°C
2. Maximum Ratings are those values beyond which device damage may occur.
3. JEDEC standard 51-6 multilayer board - 2S2P (2 signal, 2 power).
4. JEDEC standards multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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4
NBSG16VS
Table 5. DC CHARACTERISTICS, INPUT WITH VARIABLE PECL OUTPUT V = 2.5 V; V = 0 V (Note 5)
CC
EE
-40 °C
Typ
25°C
85°C
Typ
25
Min
18
Max
32
Min
18
Typ
25
Max
Min
18
Max
32
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 6)
Unit
mA
mV
mV
I
EE
25
32
V
1315
1440
1565
1305
1430
1555
1305
1430
1555
OH
OL
V
(Max Swing)
645
765
885
605
725
845
600
720
840
(V
CTRL
= V
- 600 mV) 1090
1210
1330
1035
1155
1275
1010
1130
1250
CC
V
V
Input HIGH Voltage
(Single-Ended) (Notes 8 and 9)
V
V
-
V
V
V
-
V
V
V
-
V
CC
mV
mV
IH
THR
CC
CC
THR
CC
CC
THR
CC
+ 75 1000*
+ 75 1000*
+ 75 1000*
Input LOW Voltage
V
-
V
CC
-
V
THR
V
-
V
CC
-
V
THR
V
-
V
CC
-
V
THR
IL
IH
IH
IH
(Single-Ended) (Notes 8 and 10)
2500 1400* - 75
2500 1400* - 75
2500 1400* - 75
V
V
PECL Output Voltage Reference
1080
1.2
1140
1200
2.5
1080
1.2
1140
1200
2.5
1080
1.2
1140
1200
2.5
mV
V
BB
Input HIGH Voltage Common Mode
Range (Note 7)
IHCMR
(Differential Configuration)
V
MM
CMOS Output Voltage Reference
mV
(V
- V )/2 1100
1250
50
1400
55
1100
45
1250
50
1400
55
1100
45
1250
50
1400
55
CC
EE
R
TIN
Internal Input Termination Resistor
Input HIGH Current (@ V
45
W
I
)
IH
30
100
50
30
100
50
30
100
50
m A
m A
IH
IL
I
Input LOW Current (@ V )
25
25
25
IL
Table 6. DC CHARACTERISTICS, INPUT WITH VARIABLE PECL OUTPUT V = 3.3 V; V = 0 V (Note 11)
CC
EE
-40 °C
Typ
25°C
85°C
Typ
27
Min
20
Max
34
Min
20
Typ
27
Max
Min
20
Max
34
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 6)
Unit
mA
mV
mV
I
EE
27
34
V
V
2095
2220
2345
2085
2210
2335
2075
2200
2325
OH
OL
(Max Swing) 1275
= V - 600 mV) 1750
CC
1395
1870
1515
1990
1285
1730
1405
1850
1525
1970
1295
1715
1415
1835
1535
1955
(V
CTRL
V
V
Input HIGH Voltage
(Single-Ended) (Notes 8 and 9)
V
V
-
V
V
V
-
V
V
V
-
V
CC
mV
mV
IH
THR
CC
CC
THR
CC
CC
THR
CC
+ 75 1000*
+ 75 1000*
+ 75 1000*
Input LOW Voltage
(Single-Ended) (Notes 8 and 10)
V
-
V
CC
-
V
THR
V
-
V
CC
-
V
THR
V
-
V
CC
-
V
THR
IL
IH
IH
IH
2500 1400* - 75
2500 1400* - 75
2500 1400* - 75
V
V
PECL Output Voltage Reference
1880
1.2
1940
2000
3.3
1880
1.2
1940
2000
3.3
1880
1.2
1940
2000
3.3
mV
V
BB
Input HIGH Voltage Common Mode
Range (Note 7)
IHCMR
(Differential Configuration)
V
MM
CMOS Output Voltage Reference
mV
(V
- V )/2 1500
1650
50
1800
55
1500
45
1650
50
1800
55
1500
45
1650
50
1800
55
CC
EE
R
TIN
Internal Input Termination Resistor
Input HIGH Current (@ V
45
W
I
IH
I
IL
)
IH
30
100
50
30
100
50
30
100
50
m A
m A
Input LOW Current (@ V )
25
25
25
IL
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above tables after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
5. Input and output parameters vary 1:1 with V . V can vary +0.125 V to -0.965 V.
CC
EE
6. All loading with 50 W to V -2.0 volts. V /V measured at V /V .
CC
OH OL
IH IL
7. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
8. V is the voltage applied to the complementary input, typically V or V . V
= V
+ 75 mV. V
= V
- 75 mV.
THR
BB
MM THR(MIN)
IHCMR
THR(MAX)
IHCMR
9. V cannot exceed V
.
IH
CC
10.V always w V
.
IL
EE
11. Input and output parameters vary 1:1 with V . V can vary +0.925 V to -0.165 V.
CC
EE
*Typicals used for testing purposes.
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5
NBSG16VS
Table 7. DC CHARACTERISTICS, NECL INPUT WITH VARIABLE NECL OUTPUT
V
CC
= 0 V; V = -3.465 V to -2.375 V (Note 12)
EE
-40 °C
Typ
27
25°C
Typ
27
85°C
Typ
27
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Unit
mA
mV
I
EE
Negative Power Supply Current
Output HIGH Voltage (Note 13)
20
34
20
34
20
34
VOH
-1205
-1185 -1060
-1080
-955
-935
-1215 -1090
-1195 -1070
-965
-945
-1225
-1195 -1070
-1100
-975
-945
-3.465 V v V v -3.0 V
EE
-3.0 V t V v -2.375 V
EE
V
OL
Output LOW Voltage (Note 13)
-3.465 V v V v -3.0 V
mV
mV
EE
(Max Swing) -2000
-1910
-1440
-1820
-1320
-1990 -1900 -1810
-1580 -1460 -1340
-1980
-1595
-1890
-1475
-1800
-1355
(V
CTRL
= V
- 600 mV) -1560
CC
-3.0 V t V v -2.375 V
EE
(Max Swing) -1855
-1620
-1215
-1290
-1000
-1895 -1705 -1425
-1460 -1290 -1100 -1490
-1900
-1730
-1330
-1470
-1150
(V
CTRL
= V
- 600 mV) -1410
CC
V
V
Input HIGH Voltage
(Single-Ended) (Notes 15 and 16)
V
+ 75
V
1000*
-
V
V
+ 75
V
1000*
-
V
V
+ 75
V
1000*
-
V
CC
mV
mV
IH
THR
CC
CC
THR
CC
CC
THR
CC
Input LOW Voltage
V
-
V
CC
-
V
THR
V
-
V
CC
-
V
THR
V
-
V
CC
-
V
THR
IL
IH
IH
IH
(Single-Ended) (Notes 15 and 17)
2500
1400*
- 75
-1300
0.0
2500
1400*
- 75
2500
1400*
- 75
-1300
0.0
V
V
NECL Output Voltage Reference
-1420
-1360
-1420 -1360 -1300
+1.2 0.0
-1420
-1360
mV
V
BB
Input HIGH Voltage Common Mode
Range (Note 14)
V
EE
+1.2
V
EE
V
EE
+1.2
IHCMR
(Differential Configuration)
V
MM
CMOS Output Voltage Reference
(Note 18)
V
- 150
V
MMT
V
+ 150
V
- 150
V
MMT
V
+ 150
V
- 150
V
MMT
V
MMT
+ 150
mV
MMT
MMT
MMT
MMT
MMT
R
Internal Input Termination Resistor
45
50
30
25
55
45
50
30
25
55
100
50
45
50
30
25
55
W
TIN
I
IH
I
IL
Input HIGH Current (@ V
)
100
50
100
50
m A
m A
IH
Input LOW Current (@ V )
IL
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12.Input and output parameters vary 1:1 with V
.
CC
13.All loading with 50 W to V -2.0 volts. V /V measured at V /V .
CC
OH OL
IH IL
14.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
15.V
is the voltage applied to the complementary input, typically V or V . V
= V
+ 75 mV. V
= V
- 75 mV.
THR
BB
MM THR(MIN)
IHCMR
THR(MAX)
IHCMR
16.V cannot exceed V
.
IH
CC
17.V always w V
.
IL
EE
18.V
typical = |V -V | / 2 + V = V
.
MM
CC
EE
EE
MMT
*Typicals used for testing purposes.
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6
NBSG16VS
Table 8. AC CHARACTERISTICS for FCBGA-16 V = 0 V; V = -3.465 V to -3.0 V or V = 3.0 V to 3.465 V; V = 0 V
CC
EE
CC
EE
-40 °C
25°C
85°C
Min
Typ Max
Min
Typ Max
Min
Typ Max
Symbol
Characteristic
Maximum Frequency
Unit
f
10.7
12
10.7
12
10.7
12
GHz
max
(See Figure 8) (Note 19)
(Note 22)
(Note 22)
(Note 22)
t
t
,
Propagation Delay to Output Differen-
tial
ps
PLH
PHL
(V
CTRL
(V
CTRL
= V - 2 V) D → Q, Q
100
100
125
120
145
140
100
100
125
120
145
140
100
100
125
120
145
140
CC
= V - 1 V) D → Q, Q
CC
t
t
Duty Cycle Skew (Note 20)
RMS Random Clock Jitter
3
10
3
10
3
10
ps
ps
SKEW
JITTER
f
in
< 10 GHz
0.8
2
0.8
2
0.8
2
Peak-to-Peak Data Dependent Jitter
< 10 Gb/s
f
in
TBD
TBD
TBD
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 21)
75
2600
75
2600
75
2600 mV
ps
INPP
t
r
t
f
Output Rise/Fall Times (20% - 80%)
@ 1 GHz
(V
CTRL
(V
CTRL
= V - 2 V) Q, Q
30
30
45
40
55
50
30
30
45
40
55
50
30
30
45
40
55
50
CC
= V - 1 V) Q, Q
CC
19.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 Wto V -2.0 V. Input edge rates 40 ps (20% - 80%).
CC
20.t
= |t
-t
| for a nominal 50% differential clock input waveform. See Figure 10.
SKEW
PLH PHL
21.V
cannot exceed V
- V (applicable only when V
- V t 2600 mV).
- 2 V. Minimum output amplitude guarantee of 100 mV (see Output P-P
CC
INPP(MAX)
CC
EE
CC
EE
22.Conditions include input amplitude of 500 mV and V
= V
CTRL
Spec in Figure 8).
Table 9. AC CHARACTERISTICS for FCBGA-16 V = 0 V; -3.0 V tV v -2.375 V or 2.375 V v V t 3.0 V; V = 0 V
CC
EE
CC
EE
-40 °C
Typ
25°C
85°C
Min
Max
Min
Typ Max
Min
Typ Max
Symbol
Characteristic
Maximum Frequency
Unit
f
10.7
12
10.7
12
10.7
12
GHz
max
(See Figure 9) (Note 23)
(Note 26)
(Note 26)
(Note 26)
t
t
,
Propagation Delay to Output Differen-
tial
ps
PLH
PHL
(V
CTRL
(V
CTRL
= V - 2 V) D → Q, Q
100
100
125
120
145
140
100
100
125
120
145
140
100
100
125
120
145
140
CC
= V - 1 V) D → Q, Q
CC
t
t
Duty Cycle Skew (Note 24)
3
10
3
10
3
10
ps
ps
SKEW
RMS Random Clock Jitter
f
JITTER
< 10 GHz
0.9
3
0.9
3
0.9
3
in
Peak-to-Peak Data Dependent Jitter
< 10 Gb/s
f
in
TBD
TBD
TBD
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 25)
75
2600
75
2600
75
2600 mV
ps
INPP
t
r
t
f
Output Rise/Fall Times (20% - 80%)
@ 1 GHz
(V
CTRL
(V
CTRL
= V - 2 V) Q, Q
25
22
50
45
70
60
25
22
50
45
70
60
25
22
50
45
70
60
CC
= V - 1 V) Q, Q
CC
23.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 Wto V -2.0 V. Input edge rates 40 ps (20% - 80%).
CC
24.t
= |t
-t
| for a nominal 50% differential clock input waveform. See Figure 10.
SKEW
PLH PHL
25.V
cannot exceed V
- V (applicable only when V
- V t 2600 mV).
- 2 V. Minimum output amplitude guarantee of 100 mV (see Output P-P
CC
INPP(MAX)
CC
EE
CC
EE
26.Conditions include input amplitude of 500 mV and V
Spec in Figure 9).
= V
CTRL
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7
NBSG16VS
Table 10. AC CHARACTERISTICS for QFN-16 V = 0 V; V = -3.465 V to -3.0 V or V = 3.0 V to 3.465 V; V = 0 V
CC
EE
CC
EE
-40 °C
Typ
12
25°C
85°C
Min
Max
Min
Typ Max
Min
Typ Max
Symbol
Characteristic
Maximum Frequency
Unit
f
10
10
(Note 30)
12
10
(Note 30)
12
GHz
max
(See Figure 8) (Note 27)
(Note 30)
t
t
,
Propagation Delay to
Output Differential
ps
PLH
PHL
(V
CTRL
(V
CTRL
= V - 2 V) D → Q, Q
100
100
140
135
180
180
100
100
140
135
180
180
100
80
140
135
180
220
CC
= V - 1 V) D → Q, Q
CC
t
t
Duty Cycle Skew (Note 28)
RMS Random Clock Jitter
3
20
3
15
3
10
ps
ps
SKEW
JITTER
f
< 10 GHz
0.5
2
0.5
2
0.5
2
in
Peak-to-Peak Data Dependent Jitter
< 10 Gb/s
f
in
TBD
TBD
TBD
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 29)
75
2600
75
2600
75
2600 mV
ps
INPP
t
r
t
f
Output Rise/Fall Times (20% - 80%)
@ 1 GHz
(V
CTRL
(V
CTRL
= V - 2 V) Q, Q
30
30
45
40
55
50
30
30
45
40
55
50
30
30
45
40
55
50
CC
= V - 1 V) Q, Q
CC
27.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 Wto V -2.0 V. Input edge rates 40 ps (20% - 80%).
CC
28.t
= |t
-t
| for a nominal 50% differential clock input waveform. See Figure 10.
SKEW
PLH PHL
29.V
cannot exceed V
- V (applicable only when V
- V t 2600 mV).
- 2 V. Minimum output amplitude guarantee of 100 mV (see Output P-P
CC
INPP(MAX)
CC
EE
CC
EE
30.Conditions include input amplitude of 500 mV and V
= V
CTRL
Spec in Figure 8).
Table 11. AC CHARACTERISTICS for QFN-16 V = 0 V; -3.0 V tV v -2.375 V or 2.375 V v V t 3.0 V; V = 0 V
CC
EE
CC
EE
-40 °C
25°C
85°C
Min
Typ
Max
Min
Typ Max
Min
Typ Max
Symbol
Characteristic
Maximum Frequency
Unit
f
10
12
10
12
10
12
GHz
max
(See Figure 9) (Note 31)
(Note 34)
(Note 34)
(Note 34)
t
t
,
Propagation Delay to
Output Differential
ps
PLH
PHL
(V
CTRL
(V
CTRL
= V - 2 V) D → Q, Q
100
100
140
135
180
180
100
100
140
135
180
180
80
100
140
135
180
220
CC
= V - 1 V) D → Q, Q
CC
t
t
Duty Cycle Skew (Note 32)
3
20
3
15
3
10
ps
ps
SKEW
RMS Random Clock Jitter
f
JITTER
< 10 GHz
0.5
3
0.5
3
0.5
3
in
Peak-to-Peak Data Dependent Jitter
< 10 Gb/s
f
in
TBD
TBD
TBD
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 33)
75
2600
75
2600
75
2600 mV
ps
INPP
t
r
t
f
Output Rise/Fall Times (20% - 80%)
@ 1 GHz
(V
CTRL
(V
CTRL
= V - 2 V) Q, Q
25
22
50
45
70
60
25
22
50
45
70
60
25
22
50
45
70
60
CC
= V - 1 V) Q, Q
CC
31.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 Wto V -2.0 V. Input edge rates 40 ps (20% - 80%).
CC
32.t
= |t
-t
| for a nominal 50% differential clock input waveform. See Figure 10.
SKEW
PLH PHL
33.V
cannot exceed V
- V (applicable only when V
- V t 2600 mV).
- 2 V. Minimum output amplitude guarantee of 100 mV (see Output P-P
CC
INPP(MAX)
CC
EE
CC
EE
34.Conditions include input amplitude of 500 mV and V
Spec in Figure 9).
= V
CTRL
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8
NBSG16VS
100
90
80
70
60
50
40
30
20
10
0
V
CC
- 0.0
V
CC
- 0.5
V
CC
- 1.0
V
CC
- 1.5
V
CC
- 2.0
V
CTRL
(V)
Figure 5. Output Amplitude % vs. VCTRL (pin #A3)
V
OH
AMPLITUDE DECREASES
MAX. AMPLITUDE REGION
MIN. AMPLITUDE REGION
V
OL
2.375 V v V
- V < 3.0 V
EE
CC
3.0 V v V
- V v 3.465 V
CC
EE
V
CC
- 1.3
V
CC
- 0.0
V
CC
- 0.5
V
CC
- 1.0
V
CC
- 1.5
V
CC
- 2.0
V
CTRL
(V)
Figure 6. Output Amplitude vs. VCTRL (pin #A3)
3.40
3.20
3.00
2.80
2.60
V
CTRL
2.40
2.20
2.00
1.80
Q/Q
1.60
0
2
4
6
8
10
12
14
16
18
20
TIME (ns)
Figure 7. Output Response Under Amplitude Modulation of VCTRL
(Conditions Include VCC - VEE = 3.3 V at 255C, fIN (VCTRL) = 200 MHz, and fIN (D, D) = 2 GHz)
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9
NBSG16VS
900
800
700
600
500
400
300
200
100
9
8
7
6
5
4
3
2
1
V
= V - 2 V
CC
CTRL
V
CTRL
= V - 1 V
CC
V
CTRL
= V - 0 V
CC
OUTPUT P-P SPEC
(AMPLITUDE GUARANTEE)
RMS JITTER
0
0
1
2
3
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 8. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at Ambient Temperature (Typical)
800
9
8
7
V
CTRL
= V - 2 V
CC
700
600
500
400
V
CTRL
= V - 1 V
CC
6
5
4
3
2
1
V
CTRL
= V - 0 V
CC
OUTPUT P-P SPEC
(AMPLITUDE GUARANTEE)
300
200
100
RMS JITTER
0
0
1
2
3
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 9. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at Ambient Temperature (Typical)
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10
NBSG16VS
D
V
V
= V (D) - V (D)
IH IL
INPP
D
Q
= V (Q) - V (Q)
OUTPP
OH
OL
Q
t
PHL
t
PLH
Figure 10. AC Reference Measurement
Q
Q
D
D
Receiver
Device
Driver
Device
50
50
W
W
V
TT
V
V
=
- 2.0 V
CC
TT
Figure 11. Typical Termination for Output Driver
and Device Evaluation (Refer to Application Note
AND8020 - Termination of ECL Logic Devices)
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11
NBSG16VS
PACKAGE DIMENSIONS
FCBGA-16
BA SUFFIX
PLASTIC 4X4 (mm) BGA FLIP CHIP PACKAGE
CASE 489-01
ISSUE O
LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA
-X-
D
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO DATUM
PLANE Z.
M
-Y-
K
E
4. DATUM Z (SEATING PLANE) IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE
ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
M
MILLIMETERS
0.20
DIM MIN
MAX
FEDUCIAL FOR PIN A1
IDENTIFICATION IN THIS AREA
A
A1
A2
b
1.40 MAX
0.25
0.35
3 X e
4
3
2
1
1.20 REF
0.30
0.50
A
D
4.00 BSC
3
B
E
4.00 BSC
1.00 BSC
0.50 BSC
e
16 X
b
C
D
S
M
M
0.15
0.08
Z X
Z
Y
S
VIEW M-M
5
0.15
Z
A2
A
-Z-
16 X
A1
0.10
Z
4
DETAIL K
ROTATED 90 CLOCKWISE
_
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12
NBSG16VS
PACKAGE DIMENSIONS
16 PIN QFN
MN SUFFIX
CASE 485G-01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
-X-
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
A
M
-Y-
MILLIMETERS
DIM MIN MAX
3.00 BSC
3.00 BSC
0.80
INCHES
MIN MAX
A
B
C
D
E
F
0.118 BSC
0.118 BSC
B
1.00 0.031
0.039
0.011
0.073
0.073
0.23
1.75
1.75
0.28 0.009
1.85 0.069
1.85 0.069
N
G
H
J
0.50 BSC
0.875 0.925
0.20 REF
0.020 BSC
0.034
0.036
0.25 (0.010) T
0.25 (0.010) T
0.008 REF
K
L
0.00
0.35
0.05 0.000
0.45 0.014
0.002
0.018
M
N
P
R
1.50 BSC
1.50 BSC
0.875 0.925
0.60 0.80 0.024
0.059 BSC
0.059 BSC
0.034
0.036
0.031
J
R
C
SEATING
PLANE
-T-
0.08 (0.003) T
K
E
H
G
L
5
8
4
9
F
12
1
16
13
P
D NOTE 3
M
0.10 (0.004)
T
X Y
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13
NBSG16VS
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