NLAST4052/D [ETC]
Analog Multiplexer/ Demultiplexer ; 模拟多路复用器/多路解复用器\n
| 型号： | NLAST4052/D |
| 厂家： | 
ETC |
| 描述： | Analog Multiplexer/ Demultiplexer
|
| 文件： | 总16页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NLAST4052
Analog Multiplexer/
Demultiplexer
TTL Compatible, Double–Pole, 4–Position
Plus Common Off
http://onsemi.com
MARKING DIAGRAMS
The NLAST4052 is an improved version of the MC14052 and
MC74HC4052 fabricated in sub–micron Silicon Gate CMOS
technology for lower R
resistance and improved linearity with
DS(on)
low current. This device may be operated either with a single supply or
16
dual supply up to ±3 V to pass a 6 V signal without coupling
9
PP
capacitors.
NLAST4052
AWLYWW
When operating in single supply mode, it is only necessary to tie
SO–16
D SUFFIX
CASE 751B
1
8
V , pin 7 to ground. For dual supply operation, V is tied to a
EE
EE
negative voltage, not to exceed maximum ratings. Translation is
provided in the device, the Address and Inhibit pins are standard TTL
level compatible. For CMOS compatibility see NLAS4052. Pin for
pin compatible with all industry standard versions of ‘4052.’
16
9
NLAST
ALYW
• Improved R
Specifications
DS(on)
TSSOP–16
DT SUFFIX
CASE 948F
• Pin for Pin Replacement for MAX4052 and MAX4052A
1
8
9
– One Half the Resistance Operating at 5.0 Volts
• Single or Dual Supply Operation
16
– Single 3–5 Volt Operation, or Dual ±3 Volt Operation
– With V of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic,
– No Translators Needed
– Address and Inhibit pins are Logic is Over–Voltage Tolerant and –
CC
NLAST
4052
ALYW
QSOP–16
QS SUFFIX
CASE 492
– May Be Driven Up +6 V Regardless of V
CC
1
8
• Address and Inhibit pins are Standard TTL Compatible
– Greatly Improved Noise Margin Over MAX4052 and MAX4052A
A
L, WL
Y
= Assembly Location
= Wafer Lot
– True TTL Compatibility V = 0.8 V, V = 2.0 V
IL
IH
= Year
• Improved Linearity Over Standard HC4052 Devices
W
= Work Week
• Popular SOIC, and Space Saving TSSOP, and QSOP 16 Pin
Packages
ORDERING INFORMATION
Device
Package
Shipping
NLAST4052D
SO–16
SO–16
48 Units/Rail
NLAST4052DR2
2500 Units/Reel
NLAST4052DT
NLAST4052DTR2
NLAST4052QS
NLAST4052QSR
TSSOP–16
96 Units/Rail
TSSOP–16 2500 Units/Reel
QSOP–16
QSOP–16
98 Units/Rail
2500 Units/Reel
Semiconductor Components Industries, LLC, 2002
1
Publication Order Number:
June, 2002 – Rev. 2
NLAST4052/D
NLAST4052
V
CC
NO
NO
COM NO
NO
ADD ADD
3A B A
1A
2A
A
0A
16
15
14
13
12
11
10
9
NO
NO
0B
1B
NO
NO
1A
2A
COM
B
COM
NO
NO
A
3B
2B
1
2
NO
3
4
5
6
7
8
NO
COM NO
NO
Inhibit
V
GND
NO
0B
1B
B
3B
2B
EE
0A
3A
ADD
B
NO
Figure 1. Pin Connection
(Top View)
Inhibit
LOGIC
ADD
A
Figure 2. Logic Diagram
TRUTH TABLE
Address
B
A
Inhibit
ON SWITCHES*
1
X
X
All switches open
don’t care
don’t care
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
COM –NO ,
A 0A
COM –NO
B
0B
0
1
1
0
0
1
1
COM –NO ,
A 1A
COM –NO
B
1B
COM –NO
,
A
2A
COM –NO
B
2B
COM –NO
,
A
3A
COM –NO
B
3B
COM –NO
,
A
0A
COM –NO
B
0B
COM –NO
,
A
1A
COM –NO
B
1B
COM –NO
,
A
2A
COM –NO
B
2B
COM –NO
,
A
3A
COM –NO
B
3B
*N/C, NO, and COM pins are identical and interchangeable. Either may be
considered an input or output; signals pass equally well in either direction.
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2
NLAST4052
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
Unit
V
V
EE
V
CC
Negative DC Supply Voltage
(Referenced to GND)
(Referenced to GND)
–7.0 to )0.5
Positive DC Supply Voltage (Note 2)
–0.5 to )7.0
–0.5 to )7.0
V
(Referenced to V
)
EE
V
V
I
Analog Input Voltage
V
EE
–0.5 to V )0.5
V
V
IS
CC
Digital Input Voltage
(Referenced to GND)
–0.5 to 7.0
$50
IN
DC Current, Into or Out of Any Pin
Storage Temperature Range
mA
°C
T
T
T
–65 to )150
260
STG
L
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
°C
)150
°C
J
q
SOIC
TSSOP
QSOP
143
164
164
°C/W
JA
P
D
Power Dissipation in Still Air,
SOIC
TSSOP
QSOP
500
450
450
mW
MSL
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Level 1
F
R
Oxygen Index: 30% – 35%
UL 94 V–0 @ 0.125 in
V
ESD
Human Body Model (Note 3)
Machine Model (Note 4)
u2000
u200
V
Charged Device Model (Note 5)
u1000
I
Latch–Up Performance
Above V and Below GND at 125°C (Note 6)
$300
mA
LATCH–UP
CC
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated
conditions is not implied.
2. The absolute value of V $|V | ≤ 7.0.
CC
EE
3. Tested to EIA/JESD22–A114–A.
4. Tested to EIA/JESD22–A115–A.
5. Tested to JESD22–C101–A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
V
EE
CC
Negative DC Supply Voltage
Positive DC Supply Voltage
(Referenced to GND)
(Referenced to GND)
–5.5
GND
V
2.5
2.5
5.5
6.6
V
(Referenced to V
)
EE
V
V
Analog Input Voltage
V
V
CC
V
V
IS
EE
Digital Input Voltage
(Note 7) (Referenced to GND)
0
5.5
IN
T
A
Operating Temperature Range, All Package Types
–55
125
°C
t , t
Input Rise/Fall Time
(Channel Select or Enable Inputs)
V
V
= 3.0 V $ 0.3 V
= 5.0 V $ 0.5 V
0
0
100
20
ns/V
r
f
CC
CC
7. Unused digital inputs may not be left open. All digital inputs must be tied to a high–logic voltage level or a low–logic input voltage level.
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3
NLAST4052
DC CHARACTERISTICS – Digital Section (Voltages Referenced to GND)
Guaranteed Limit
V
CC
–55 to 25°C v85°C v125°C
V
Symbol
Parameter
Condition
Unit
V
IH
Minimum High–Level Input Voltage,
Address or Inhibit Inputs
3.0
4.5
5.5
1.6
2.0
2.0
1.6
2.0
2.0
1.6
2.0
2.0
V
V
IL
Maximum Low–Level Input Voltage,
Address or Inhibit Inputs
3.0
4.5
5.5
0.5
0.8
0.8
0.5
0.8
0.8
0.5
0.8
0.8
V
I
I
Maximum Input Leakage Current,
Address or Inhibit Inputs
V
= 6.0 or GND
0 V to 6.0 V
$0.1
$1.0
$1.0
m A
m A
IN
IN
Maximum Quiescent Supply
Current (per Package)
Address, Inhibit, and
= V or GND
6.0
4.0
40
80
CC
V
IS
CC
DC ELECTRICAL CHARACTERISTICS – Analog Section
Guaranteed Limit
V
CC
V
EE
–55 to 25°C v85°C v125°C
V
V
Symbol
Parameter
Test Conditions
= V or V
Unit
R
Maximum “ON” Resistance
V
V
S
3.0
4.5
3.0
0
0
–3.0
86
37
26
108
46
120
55
W
ON
IN
IS
IL
IH
= V to V
EE
CC
|I | = 10 mA
(Figures 4 thru 9)
33
37
D
R
Maximum Difference in “ON”
Resistance Between Any
Two Channels in the Same
Package
V
= V or V
V
IS
V
IS
V
IS
= 2.0 V
= 3.5 V
= 2.0 V
3.0
4.5
3.0
0
0
–3.0
15
13
10
20
18
15
20
18
15
W
ON
IN
IL
IH,
|I | = 10 mA,
S
R
flat(ON)
ON Resistance Flatness
V
com
V
com
1, 2, 3.5 V
–2, 0, 2 V
4.5
3.0
4
2
4
2
5
3
W
–3.0
I
I
Maximum Off–Channel
Leakage Current
Switch Off
6.0
3.0
0
–3.0
0.1
0.1
5.0
5.0
100
100
nA
NC(OFF)
V
V
= V or V
IN
IL IH
NO(OFF)
= V –1.0 V or V +1.0 V
IO
CC
EE
(Figure 17)
I
Maximum On–Channel
Leakage Current, Channel–
to–Channel
Switch On
6.0
3.0
0
–3.0
0.1
0.1
5.0
5.0
100
100
nA
COM(ON)
V
IO
= V –1.0 V or V +1.0 V
CC EE
(Figure 17)
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4
NLAST4052
AC CHARACTERISTICS (Input t = t = 3 ns)
r
f
Guaranteed Limit
–55 to 25°C
V
CC
V
EE
Min
Typ*
V
V
Symbol
Parameter
Test Conditions
v85°C v125°C Unit
t
Minimum Break–Before–Make
Time
V
V
= V or V
3.0
4.5
3.0
0.0
0.0
–3.0
1.0
1.0
1.0
6.5
5.0
3.5
–
–
–
–
–
–
ns
BBM
IN
IS
IL
IH
= V
CC
R = 300 WC, = 35 pF
L
L
(Figure 19)
*Typical Characteristics are at 25°C.
AC CHARACTERISTICS (C = 50 pF, Input t = t = 3 ns)
L
r
f
Guaranteed Limit
–55 to 25°C
v85°C
v125°C
V
V
V
EE
V
CC
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Transition Time
(Address Selection Time)
(Figure 18)
Unit
t
t
t
2.5
3.0
4.5
3.0
0
0
0
40
28
23
23
45
30
25
25
50
35
30
28
ns
TRANS
–3.0
Turn–on Time
(Figures 14, 15, 20, and 21)
2.5
3.0
4.5
3.0
0
0
0
40
28
23
23
45
30
25
25
50
35
30
28
ns
ns
ON
Enable to N or N
O
C
–3.0
Turn–off Time
2.5
3.0
4.5
3.0
0
0
0
40
28
23
23
45
30
25
25
50
35
30
28
OFF
(Figures 14, 15, 20, and 21)
Enable to N or N
O
C
–3.0
Typical @ 25°C, V = 5.0 V
CC
pF
C
C
C
C
Maximum Input Capacitance,Select Inputs
8
IN
or C
Analog I/O
10
10
1.0
NO
NC
Common I/O
Feedthrough
COM
(ON)
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5
NLAST4052
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Typ
V
CC
V
EE
V
V
25°C
Symbol
Parameter
Condition
Unit
BW
Maximum On–Channel
Bandwidth or Minimum
Frequency Response
V
= ½ (V – V )
EE
3.0
4.5
6.0
3.0
0.0
0.0
0.0
110
130
140
140
MHz
IS
CC
Source Amplitude = 0 dBm
(Figures 10 and 22)
–3.0
V
Off–Channel Feedthrough
Isolation
f = 100 kHz; V = ½ (V – V
Source = 0 dBm
(Figures 12 and 22)
)
3.0
4.5
6.0
3.0
0.0
0.0
0.0
–93
–93
–93
–93
dB
dB
ISO
IS
CC
EE
–3.0
V
ONL
Maximum Feedthrough
On Loss
V
IS
= ½ (V – V )
EE
3.0
4.5
6.0
3.0
0.0
0.0
0.0
–2
–2
–2
–2
CC
Source = 0 dBm
(Figures 10 and 22)
–3.0
Q
Charge Injection
V
R
= V to V
f
= 1 kHz, t = t = 3 ns
5.0
3.0
0.0
–3.0
9.0
12
pC
%
IN
CC
EE, IS
r
f
= 0 W, C = 1000 pF, Q = C * D V
OUT
IS
L
L
(Figures 16 and 23)
f = 1 MHz, R = 10 KW, C = 50 pF,
IS
THD
Total Harmonic Distortion
THD + Noise
L
L
V
V
= 5.0 V sine wave
6.0
3.0
0.0
–3.0
0.10
0.05
IS
PP
= 6.0 V sine wave
IS
PP
(Figure 13)
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6
NLAST4052
100
10
100
80
60
2.0 V
1
0.1
0.01
40
20
0
V
= 3.0 V
CC
3.0 V
4.5 V
5.5 V
0.001
0.0001
$3.3 V
V
CC
= 5.0 V
0.00001
–40
–20
0
20
60
80
100
120
–4.0
–2.0
0
2.0
(VDC)
4.0
6.0
Temperature (°C)
V
IS
Figure 3. ICC versus Temp, VCC = 3 V and 5 V
Figure 4. RON versus VCC, Temp = 255C
50
100
90
80
70
60
50
40
30
20
10
125°C
85°C
125°C
25°C
40
30
25°C
85°C
20
10
–55°C
–55°C
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
VCom (V)
VCom (V)
Figure 5. Typical On Resistance
VCC = 2.0 V, VEE = 0 V
Figure 6. Typical On Resistance
VCC = 3.0 V, VEE = 0 V
25
20
15
10
25
125°C
125°C
85°C
85°C
20
15
25°C
10
5
25°C
–55°C
–55°C
5
0
0
0
0
0.5 1.0 1.5 2.0 2.5 3.0
VCom (V)
3.5 4.0 4.5
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCom (V)
Figure 7. Typical On Resistance
CC = 4.5 V, VEE = 0 V
Figure 8. Typical On Resistance
VCC = 5.5 V, VEE = 0 V
V
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7
NLAST4052
25
20
15
10
5
125°C
85°C
–55°C
25°C
0
–4
–2
0
2
4
VCom (V)
Figure 9. Typical On Resistance
VCC = 3.3 V, VEE = –3.3 V
90
72
54
36
50
40
30
20
10
0
18
0
PHASE SHIFT
BANDWIDTH (ON–RESPONSE)
–18
–36
–54
–10
–20
–30
–40
–50
–72
–90
0.1
1.0
10
100
0.1
1.0
10
100
FREQUENCY (mHz)
FREQUENCY (mHz)
Figure 10. Bandwidth
Figure 11. Phase Shift
0
0
–10
–20
3.0
–30
–40
–50
–60
–70
–80
–90
–100
5.5
4.5
0.1
$3.3
0.01
0.1
1.0
10
100
10
100
1000
10000
10000
FREQUENCY (mHz)
FREQUENCY (mHz)
Figure 12. Off Isolation
Figure 13. Total Harmonic Distortion
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8
NLAST4052
30
25
20
15
10
30
25
20
15
10
5
T
A
= 25°C
V
CC
= 4.5 V
t
(ns)
ON
t
ON
t
t
(ns)
3.5
OFF
5
0
OFF
0
–55
2.5
3
4
4.5
5
–40
25
Temperature (°C)
85
125
V
CC
(VOLTS)
Figure 14. tON and tOFF versus VCC
Figure 15. tON and tOFF versus Temp
3.0
2.5
2.0
1.5
1.0
0.5
100
10
1
V
= 5 V
CC
I
COM(ON)
0.1
I
COM(OFF)
V
CC
= 3 V
0.01
0
V
CC
= 5.0 V
85
I
NO(OFF)
–0.5
0.001
0
1
2
3
4
5
–55
–20
25
70
125
TEMPERATURE (°C)
V
COM
(V)
Figure 16. Charge Injection versus COM Voltage
Figure 17. Switch Leakage versus Temperature
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9
NLAST4052
V
CC
V
Output
CC
Input
50%
50%
V
OUT
0.1 m F
0 V
V
EE
300 W
35 pF
V
CC
90%
Output
Address Select Pin
10%
V
EE
t
t
trans
trans
Figure 18. Channel Selection Propagation Delay
V
CC
DUT
Input
GND
V
CC
Output
V
OUT
0.1 m F
t
BMM
300 W
35 pF
90%
90% of V
OH
Output
Address Select Pin
GND
Figure 19. tBBM (Time Break–Before–Make)
V
CC
DUT
Input
50%
50%
V
CC
0 V
Output
V
OUT
0.1 m F
V
OH
Open
300 W
35 pF
90%
90%
Output
GND
Enable
Input
t
t
OFF
ON
Figure 20. tON/tOFF
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10
NLAST4052
V
CC
V
CC
Input
0 V
50%
50%
DUT
300 W
Output
V
OUT
V
CC
Open
35 pF
Output
V
10%
10%
OL
Enable
Input
t
t
ON
OFF
Figure 21. tON/tOFF
50 W
DUT
Reference
Input
50 W Generator
Transmitted
Output
50 W
Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is
the bandwidth of an On switch. V , Bandwidth and V are independent of the input signal direction.
ISO
ONL
V
V
OUT
IN
= Off Channel Isolation = 20 Log ǒ Ǔ for V
V
V
at 100 kHz
IN
ISO
V
OUT
= On Channel Loss = 20 Log ǒ Ǔ for V
at 100 kHz to 50 MHz
ONL
IN
V
IN
Bandwidth (BW) = the frequency 3 dB below V
ONL
Figure 22. Off Channel Isolation/On Channel Loss (BW)/Crosstalk
(On Channel to Off Channel)/VONL
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11
NLAST4052
DUT
V
CC
V
IN
Output
Open
GND
C
L
Output
Off
D V
OUT
Off
On
V
IN
Figure 23. Charge Injection: (Q)
TYPICAL OPERATION
+5.0 V
+3.0 V
V
CC
V
CC
16
16
V
V
EE
EE
7
7
8
GND
GND
8
–3.0 V
Figure 24. 5.0 Volts Single Supply
CC = 5.0 V, VEE = 0
Figure 25. Dual Supply
VCC = 3.0 V, VEE = –3.0 V
V
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NLAST4052
PACKAGE DIMENSIONS
SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
B
0.25 (0.010)
1
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
R X 45
K
_
C
G
J
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
K
M
P
R
D
16 PL
_
_
_
_
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
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NLAST4052
PACKAGE DIMENSIONS
TSSOP–16
DT SUFFIX
CASE 948F–01
ISSUE O
16X KREF
M
S
S
0.10 (0.004)
T U
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
S
0.15 (0.006) T U
K
K1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
16
9
2X L/2
J1
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
B
–U–
SECTION N–N
L
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE -W-.
S
0.15 (0.006) T U
A
M
MILLIMETERS
INCHES
MIN
–V–
DIM MIN
MAX
5.10
4.50
1.20
0.15
0.75
MAX
0.200
0.177
0.047
0.006
0.030
N
A
B
4.90
4.30
---
0.193
0.169
---
F
C
D
0.05
0.50
0.002
0.020
F
DETAIL E
G
H
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28
0.20
0.16
0.30
0.25
0.007
0.004
0.004
0.007
0.007
0.011
0.008
0.006
0.012
0.010
J
J1
K
–W–
C
K1
L
6.40 BSC
0.252 BSC
0
0.10 (0.004)
M
0
8
8
_
_
_
_
H
DETAIL E
SEATING
PLANE
–T–
D
G
http://onsemi.com
14
NLAST4052
PACKAGE DIMENSIONS
QSOP–16
QS SUFFIX
CASE 492–01
ISSUE O
–A–
Q
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
R
2. CONTROLLING DIMENSION: INCH.
3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN
THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE
ONLY). BOTTOM PACKAGE DIMENSION SHALL
FOLLOW THE DIMENSION STATED IN THIS
DRAWING.
4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD
FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 6 MILS PER
SIDE.
H x 45
_
U
RAD.
0.013 X 0.005
DP. MAX
–B–
5. BOTTOM EJECTOR PIN WILL INCLUDE THE
COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D.
MOLD PIN
MARK
INCHES
MIN
MILLIMETERS
DIM
A
B
C
D
F
MAX
0.196
0.157
0.068
0.012
0.035
MIN
4.80
3.81
1.55
0.20
0.41
MAX
4.98
3.99
1.73
0.31
0.89
0.189
0.150
0.061
0.008
0.016
RAD.
0.005–0.010
TYP
G
G
H
J
0.025 BSC
0.64 BSC
L
0.008 0.018
0.0098 0.0075
0.20
0.249
0.10
5.84
0
0.46
0.191
0.25
6.20
8
P
DETAIL E
M
0.25 (0.010)
T
K
L
0.004
0.230
0
0.010
0.244
8
M
N
P
_
_
_
_
0
0.007
7
0.011
0
0.18
7
0.28
_
_
_
_
Q
R
U
V
0.020 DIA
0.51 DIA
V
K
0.025
0.025
0
0.035
0.035
8
0.64
0.64
0
0.89
0.89
8
C
N 8 PL
_
_
_
_
–T–
D16 PL
0.25 (0.010)
SEATING
PLANE
M
S
S
A
T
B
J
M
F
DETAIL E
http://onsemi.com
15
NLAST4052
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NLAST4052/D
相关型号：
NLAST4052DTR2
IC 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, PDSO16, TSSOP-16, Multiplexer or Switch
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