NLAST4053 [ONSEMI]
Analog Multiplexer/ Demultiplexer; 模拟多路复用器/多路解复用器
| 型号： | NLAST4053 |
| 厂家： | 
ONSEMI |
| 描述： | Analog Multiplexer/ Demultiplexer |
| 文件： | 总14页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NLAST4053
Analog Multiplexer/
Demultiplexer
TTL Compatible, Triple 2:1 Analog
Switch-Multiplexer Improved Process,
Sub-Micron Silicon Gate CMOS
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The NLAST4053 is an improved version of the MC14053 and
MC74HC4053 fabricated in sub-micron Silicon Gate CMOS
MARKING
DIAGRAM
technology for lower R
resistance and improved linearity with
low current. This device may be operated either with a single supply or
DS(on)
16
AST
4053
ALYW
TSSOP-16
DT SUFFIX
CASE 948F
dual supply up to 3 V to pass a 6 V signal without coupling
PP
capacitors.
When operating in single supply mode, it is only necessary to tie
1
V , pin 7 to ground. For dual supply operation, V is tied to a
EE EE
negative voltage, not to exceed maximum ratings. Translation is
provided in the device, the Address and Inhibit pins are standard TTL
level compatible. For CMOS compatibility see NLAS4053. Pin for
pin compatible with all industry standard versions of `4053.'
A
L
Y
W
=
=
=
=
Assembly Location
Wafer Lot
Year
Work Week
•ꢀImproved R
Specifications
DS(on)
ORDERING INFORMATION
•ꢀPin for Pin Replacement for MAX4053 and MAX4053A
†
- One Half the Resistance Operating at 5.0 Volts
Device
Package
Shipping
•ꢀSingle or Dual Supply Operation
NLAST4053DTR2G TSSOP-16 2500 / Tape &
(Pb-Free) Reel
- Single 3-5 Volt Operation, or Dual 3 Volt Operation
- With V of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic,
CC
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
- No Translators Needed
- Address and Inhibit Pins are Over-Voltage Tolerant and May Be
- Driven Up +6ꢁV Regardless of V
CC
•ꢀAddress and Inhibit Pins are Standard TTL Compatible
- Greatly Improved Noise Margin Over MAX4053 and MAX4053A
- True TTL Compatibility V = 0.8 V, V = 2.0 V
IL IH
•ꢀImproved Linearity Over Standard HC4053 Devices
•ꢀPopular SOIC, and Space Saving TSSOP, and QSOP 16 Pin
Packages
•ꢀThis is a Pb-Free Device
©ꢀ Semiconductor Components Industries, LLC, 2008
February, 2008 - Rev. 1
1
Publication Order Number:
NLAST4053/D
NLAST4053
NO
B
NC
NO
V
COM COM
NO
13
NC
Add
11
Add
10
Add
9
COM
COM
B
CC
B
C
C
C
C
B
A
B
16
15
14
12
C
A
COM
NC
NO
A
C
C
NC
A
1
2
NC
3
NO
4
5
6
7
8
NO
COM NC Inhibit
V
EE
GND
B
B
A
A
A
Enable
C
B
A
Figure 1. Pin Connection
(Top View)
Figure 2. Logic Diagram
TRUTH TABLE
Address
B
Inhibit
ON SWITCHES*
C
A
1
0
X
X
X
All switches open
don't care
don't care
don't care
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
COM -NC ,
A A
COM -NC ,
B
B
COM -NC
C
C
0
0
0
0
0
0
0
0
0
0
1
1
1
1
COM -NO ,
A A
COM -NC ,
B
B
COM -NC
C
C
COM -NC ,
A
A
COM -NO ,
B
B
COM -NC
C
C
COM -NO ,
A
A
COM -NO ,
B
B
COM -NC
C
C
COM -NC ,
A
A
COM -NC ,
B
B
COM -NO
C
C
COM -NO ,
A
A
COM -NC ,
B
B
COM -NO
C
C
COM -NC ,
A
A
COM -NO ,
B
B
COM -NO
C
C
COM -NO ,
A
A
COM -NO ,
B
B
COM -NO
C
C
*NO, NC, and COM pins are identical and interchangeable. Either may be
considered an input or output; signals pass equally well in either direction.
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2
NLAST4053
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
EE
V
CC
Negative DC Supply Voltage
(Referenced to GND)
(Referenced to GND)
-7.0 to )0.5
Positive DC Supply Voltage (Note 1)
-0.5 to )7.0
-0.5 to )7.0
V
(Referenced to V
)
EE
V
V
I
Analog Input Voltage
V
EE
-0.5 to V )0.5
V
V
IS
CC
Digital Input Voltage
(Referenced to GND)
-0.5 to 7.0
$50
IN
DC Current, Into or Out of Any Pin
Storage Temperature Range
mA
°C
T
STG
-65 to )150
260
T
T
ꢀ
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
°C
L
J
)150
°C
SOIC
TSSOP
QSOP
143
164
164
°C/W
JA
P
D
Power Dissipation in Still Air,
SOIC
TSSOP
QSOP
500
450
450
mW
MSL
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Level 1
F
R
Oxygen Index: 30% - 35%
UL 94 V-0 @ 0.125 in
V
ESD
Human Body Model (Note 2)
Machine Model (Note 3)
u2000
u200
V
Charged Device Model (Note 4)
u1000
I
Latch-Up Performance
Above V and Below GND at 125°C (Note 5)
$300
mA
LATCH-UP
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The absolute value of V $|V | ≤ 7.0.
CC
EE
2. Tested to EIA/JESD22-A114-A.
3. Tested to EIA/JESD22-A115-A.
4. Tested to JESD22-C101-A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
V
EE
Negative DC Supply Voltage
Positive DC Supply Voltage
(Referenced to GND)
(Referenced to GND)
-5.5
GND
V
CC
2.5
2.5
5.5
6.6
V
(Referenced to V
)
EE
V
V
T
Analog Input Voltage
V
V
CC
V
V
IS
EE
Digital Input Voltage
(Note 6) (Referenced to GND)
0
5.5
IN
Operating Temperature Range, All Package Types
-55
125
°C
A
t , t
Input Rise/Fall Time
(Channel Select or Enable Inputs)
V
CC
V
CC
= 3.0 V $ 0.3 V
= 5.0 V $ 0.5 V
0
0
100
20
ns/V
r
f
6. Unused digital inputs may not be left open. All digital inputs must be tied to a high-logic voltage level or a low-logic input voltage level.
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3
NLAST4053
DC CHARACTERISTICS - Digital Section (Voltages Referenced to GND)
Guaranteed Limit
V
CC
-55 to 25°C v85°C v125°C
V
Symbol
Parameter
Condition
Unit
V
V
I
Minimum High-Level Input Voltage,
Address and Inhibit Inputs
3.0
4.5
5.5
1.6
2.0
2.0
1.6
2.0
2.0
1.6
2.0
2.0
V
IH
Maximum Low-Level Input Voltage,
Address and Inhibit Inputs
3.0
4.5
5.5
0.5
0.8
0.8
0.5
0.8
0.8
0.5
0.8
0.8
V
IL
Maximum Input Leakage Current,
Address and Inhibit Inputs
V
= 6.0 or GND
0 V to 6.0 V
$0.1
$1.0
$1.0
ꢁ A
ꢁ A
IN
IN
I
Maximum Quiescent Supply
Current (per Package)
Address and Inhibit, and
= V or GND
6.0
4.0
40
80
CC
V
IS
CC
DC ELECTRICAL CHARACTERISTICS - Analog Section
Guaranteed Limit
V
CC
V
EE
-55 to 25°C v85°C v125°C
V
V
Symbol
Parameter
Test Conditions
= V or V
Unit
R
Maximum “ON” Resistance
V
V
3.0
4.5
3.0
0
0
-3.0
86
37
26
108
46
120
55
ꢂ
ON
IN
IL
IH,
= V to V
IS
EE
CC
|I | = 10 mA
(Figures 4 thru 9)
S
33
37
ꢃ
R
Maximum Difference in “ON”
Resistance Between Any
Two Channels in the Same
Package
V
= V or V
V
IS
V
IS
V
IS
= 2.0 V
= 3.0 V
= 2.0 V
3.0
4.5
3.0
0
0
-3.0
15
2.0
10
20
2.0
15
20
2.0
15
ꢂ
ON
IN
IL
IH,
|I | = 10 mA,
S
R
flat(ON)
COM-NO On-Resistance
Flatness
V
com
V
com
= 1, 2, 3.5 V
= -2, 0, 2 V
4.5
3.0
0
-3.0
24
2.0
24
2.0
35
3.0
ꢂ
I
I
Maximum Off-Channel
Leakage Current
Switch Off
6.0
3.0
0
-3.0
0.1
0.1
5.0
5.0
100
100
nA
NC(OFF)
V
V
= V or V
IN
IL IH
NO(OFF)
= V -1.0 V or V +1.0 V
IO
CC
EE
(Figure 17)
I
Maximum On-Channel
Leakage Current, Channel-
to-Channel
Switch On
6.0
3.0
0
-3.0
0.1
0.1
5.0
5.0
100
100
nA
COM(ON)
V
IO
= V -1.0 V or V +1.0 V
CC EE
(Figure 17)
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4
NLAST4053
AC CHARACTERISTICS (Input t = t = 3 ns)
r
f
Guaranteed Limit
-55 to 25°C
V
CC
V
EE
Min
Typ*
V
V
Symbol
Parameter
Test Conditions
v85°C v125°C Unit
t
Minimum Break-Before-Make
Time
V
V
= V or V
3.0
4.5
3.0
0.0
0.0
-3.0
1.0
1.0
1.0
6.5
5.0
3.5
-
-
-
-
-
-
ns
BBM
IN
IL
IH
= V
IS
CC
R = 300
ꢂ ꢄ C = 35 pF
L
L
(Figure 19)
*Typical Characteristics are at 25°C.
AC CHARACTERISTICS (C = 50 pF, Input t = t = 3 ns)
L
r
f
Guaranteed Limit
-55 to 25°C
v85°C
v125°C
V
V
EE
V
CC
Min
Typ
Max
Min
Max
Min
Max
V
Symbol
Parameter
Transition Time
(Address Selection Time)
(Figure 18)
Unit
t
t
t
2.5
3.0
4.5
3.0
0
0
0
40
28
23
23
45
30
25
25
50
35
30
28
ns
TRANS
-3.0
Turn-on Time
(Figures 14, 15, 20, and 21)
2.5
3.0
4.5
3.0
0
0
0
40
28
23
23
45
30
25
25
50
35
30
28
ns
ns
ON
Enable to N or N
O
C
-3.0
Turn-off Time
2.5
3.0
4.5
3.0
0
0
0
40
28
23
23
45
30
25
25
50
35
30
28
OFF
(Figures 14, 15, 20, and 21)
Enable to N or N
O
C
-3.0
Typical @ 25°C, V = 5.0 V
CC
pF
C
C
C
C
Maximum Input Capacitance,Select Inputs
8
IN
or C
Analog I/O
10
10
1.0
NO
NC
Common I/O
Feedthrough
COM
(ON)
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5
NLAST4053
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Typ
V
CC
V
EE
V
V
25°C
Symbol
Parameter
Condition
Unit
BW
Maximum On-Channel
Bandwidth or Minimum
Frequency Response
V
= ½ (V - V )
EE
3.0
4.5
6.0
3.0
0.0
0.0
0.0
145
165
180
180
MHz
IS
CC
Source Amplitude = 0 dBm
(Figures 10 and 22)
-3.0
V
V
Off-Channel Feedthrough
Isolation
f = 100 kHz; V = ½ (V - V
Source = 0 dBm
(Figures 12 and 22)
)
3.0
4.5
6.0
3.0
0.0
0.0
0.0
-93
-93
-93
-93
dB
dB
ISO
IS
CC
EE
-3.0
Maximum Feedthrough
On Loss
V
IS
= ½ (V - V )
EE
3.0
4.5
6.0
3.0
0.0
0.0
0.0
-2
-2
-2
-2
ONL
CC
Source = 0 dBm
(Figures 10 and 22)
-3.0
Q
Charge Injection
V
R
= V to V
f
= 1 kHz, t = t = 3 ns
5.0
3.0
0.0
-3.0
9.0
12
pC
%
IN
CC
EE, IS
r
f
= 0 ꢂ, C = 1000 pF, Q = C * ꢃ V
OUT
IS
L
L
(Figures 16 and 23)
f = 1 MHz, R = 10 Kꢂ, C = 50 pF,
IS
THD
Total Harmonic Distortion
THD + Noise
L
L
V
V
= 5.0 V sine wave
6.0
3.0
0.0
-3.0
0.10
0.05
IS
PP
= 6.0 V sine wave
IS
PP
(Figure 13)
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6
NLAST4053
100
10
100
80
60
2.0 V
1
0.1
0.01
40
20
0
V
CC
= 3.0 V
3.0 V
4.5 V
5.5 V
0.001
0.0001
$3.3 V
V
CC
= 5.0 V
0.00001
-40
-20
0
20
60
80
100
120
-4.0
-2.0
0
2.0
(VDC)
4.0
6.0
Temperature (°C)
V
IS
Figure 3. ICC versus Temp, VCC = 3 V and 5 V
Figure 4. RON versus VCC, Temp = 255C
50
100
90
80
70
60
50
40
30
20
10
125°C
85°C
125°C
25°C
40
30
25°C
85°C
20
10
-55°C
-55°C
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
VCom (V)
VCom (V)
Figure 5. Typical On Resistance
CC = 2.0 V, VEE = 0 V
Figure 6. Typical On Resistance
VCC = 3.0 V, VEE = 0 V
V
25
20
15
10
25
125°C
125°C
85°C
85°C
20
15
25°C
10
5
25°C
-55°C
-55°C
5
0
0
0
0
0.5 1.0 1.5 2.0 2.5 3.0
VCom (V)
3.5 4.0 4.5
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCom (V)
Figure 7. Typical On Resistance
CC = 4.5 V, VEE = 0 V
Figure 8. Typical On Resistance
VCC = 5.5 V, VEE = 0 V
V
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7
NLAST4053
25
20
15
10
5
125°C
85°C
-55°C
25°C
0
-4
-2
0
2
4
VCom (V)
Figure 9. Typical On Resistance
VCC = 3.0 V, VEE = -3.0 V
50
40
30
20
90
72
54
36
18
0
10
0
PHASE SHIFT
BANDWIDTH (ON-RESPONSE)
-10
-20
-18
-36
-54
-72
-30
-40
-50
-90
0.1
1.0
10
100
0.1
1.0
10
100
FREQUENCY (mHz)
FREQUENCY (mHz)
Figure 10. Bandwidth
Figure 11. Phase Shift
0
0
-10
-20
3.0
-30
-40
-50
-60
-70
-80
-90
-100
5.5
4.5
0.1
$3.3
0.01
0.1
1.0
10
100
10
100
1000
10000
10000
FREQUENCY (mHz)
FREQUENCY (mHz)
Figure 13. Total Harmonic Distortion
Figure 12. Off Isolation
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8
NLAST4053
30
25
20
15
10
30
25
20
15
10
5
T = 25°C
V
CC
= 4.5 V
A
t
(ns)
ON
t
ON
t
t
(ns)
OFF
5
0
OFF
0
-55
2.5
3
3.5
V
4
4.5
5
-40
25
Temperature (°C)
85
125
(VOLTS)
CC
Figure 14. tON and tOFF versus VCC
Figure 15. tON and tOFF versus Temp
3.0
2.5
2.0
1.5
1.0
0.5
100
10
1
V
= 5 V
CC
I
COM(ON)
0.1
I
COM(OFF)
V
CC
= 3 V
0.01
0
V
CC
= 5.0 V
85
I
NO(OFF)
-0.5
0.001
0
1
2
3
4
5
-55
-20
25
70
125
TEMPERATURE (°C)
V
COM
(V)
Figure 16. Charge Injection versus COM Voltage
Figure 17. Switch Leakage versus Temperature
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9
NLAST4053
V
CC
V
Output
CC
Input
50%
50%
V
OUT
0.1 ꢁ F
0 V
V
EE
300
ꢂ
35 pF
V
CC
90%
Output
Address Select Pin
10%
V
EE
t
t
trans
trans
Figure 18. Channel Selection Propagation Delay
V
CC
DUT
Input
GND
V
Output
CC
V
OUT
0.1 ꢁ F
t
BMM
300
ꢂ
35 pF
90%
90% of V
OH
Output
Address Select Pin
GND
Figure 19. tBBM (Time Break-Before-Make)
V
CC
DUT
Input
50%
50%
V
CC
0 V
Output
V
OUT
0.1 ꢁ F
V
OH
Open
300
ꢂ
35 pF
90%
90%
Output
GND
Enable
Input
t
t
OFF
ON
Figure 20. tON/tOFF
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10
NLAST4053
V
CC
V
CC
Input
0 V
50%
50%
DUT
300
ꢂ
Output
V
OUT
V
CC
Open
35 pF
Output
V
10%
10%
OL
Enable
Input
t
t
ON
OFF
Figure 21. tON/tOFF
50
ꢂ
DUT
Reference
Input
50 ꢂ Generator
Transmitted
Output
50
ꢂ
Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is
the bandwidth of an On switch. V , Bandwidth and V are independent of the input signal direction.
ISO
ONL
V
OUT
= Off Channel Isolation = 20 Log ǒ Ǔ for V
V
V
at 100 kHz
IN
ISO
V
IN
V
OUT
= On Channel Loss = 20 Log ǒ Ǔ for V
at 100 kHz to 50 MHz
ONL
IN
V
IN
Bandwidth (BW) = the frequency 3 dB below V
ONL
Figure 22. Off Channel Isolation/On Channel Loss (BW)/Crosstalk
(On Channel to Off Channel)/VONL
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11
NLAST4053
DUT
V
CC
V
IN
Output
Open
GND
C
L
Output
Off
ꢃ V
OUT
Off
On
V
IN
Figure 23. Charge Injection: (Q)
TYPICAL OPERATION
+5.0 V
+3.0 V
V
CC
V
CC
16
16
V
V
EE
EE
7
7
8
GND
GND
8
-3.0 V
Figure 24. 5.0 Volts Single Supply
CC = 5.0 V, VEE = 0
Figure 25. Dual Supply
VCC = 3.0 V, VEE = -3.0 V
V
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12
NLAST4053
PACKAGE DIMENSIONS
TSSOP-16
CASE 948F-01
ISSUE B
NOTES:
16X KREF
ꢁꢂ1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T
U
ꢁꢂ2. CONTROLLING DIMENSION: MILLIMETER.
ꢁꢂ3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
U
0.15 (0.006) T
K
K1
ꢁꢂ4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
ꢁꢂ5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
-U-
SECTION N-N
L
J
PIN 1
IDENT.
ꢁꢂ6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
ꢁꢂ7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T
U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
M
-V-
A
B
4.90
4.30
---
5.10 0.193 0.200
4.50 0.169 0.177
N
C
1.20
--- 0.047
D
F
G
H
J
J1
K
K1
L
0.05
0.50
0.65 BSC
0.18
0.09
0.09
0.19
0.19
0.15 0.002 0.006
0.75 0.020 0.030
0.026 BSC
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
F
DETAIL E
-W-
C
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
0.10 (0.004)
DETAIL E
H
SEATING
PLANE
-T-
D
G
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
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