NT256D64S88A2GM-7K_技术文档

NT256D64S88A2GM

256MB : 32M x 64

PC2100 / PC1600 Unbuffered DDR SO-DIMM

200pin One Bank Unbuffered DDR SO-DIMM Based on DDR266/200 32Mx8 SDRAM

Features

• JEDEC Standard 200-Pin Small Outline Dual In-Line Memory

• Data is read or written on both clock edges

• DRAM DLL aligns DQ and DQS transitions with clock

transitions.

Module (SO-DIMM)

• 32Mx64 Double Unbuffered DDR SO-DIMM based on 32Mx8

DDR SDRAM.

• Address and control signals are fully synchronous to positive

clock edge

• Performance :

• Programmable Operation:

PC1600

- 8B

2

PC2100

- DIMM

Latency: 2, 2.5

CAS

Unit

Speed Sort

- 75B

- 7K

2

- Burst Type: Sequential or Interleave

- Burst Length: 2, 4, 8

DIMM

Latency

2.5

133

7.5

CAS

f CK Clock Frequency

t CK Clock Cycle

100

10

133

7.5

266

MHz

ns

- Operation: Burst Read and Write

• Auto Refresh (CBR) and Self Refresh Modes

• Automatic and controlled precharge commands

• 13/10/2 Addressing (row/column/bank)

• 7.8 ms Max. Average Periodic Refresh Interval

• Serial Presence Detect

f DQ DQ Burst Frequency

200

266

MHz

• Intended for 100 MHz and 133 MHz applications

• Inputs and outputs are SSTL-2 compatible

• VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2

• Single Pulsed

interface

RAS

• Gold contacts

• SDRAMs have 4 internal banks for concurrent operation

• Module has one physical bank

• SDRAMs in 66-pin TSOP Type II Package

• Differential clock inputs

Description

NT256D64S88A2GM is an unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),

organized as a one-bank high-speed memory array. The 32Mx64 module is a single-bank DIMM that uses eight 32Mx8 DDR

SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use

in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 controls all

devices on the DIMM.

Prior to any access operation, the device

latency and burst type/ length/operation type must be programmed into the DIMM by

CAS

address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.

These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common

design files minimizes electrical variation between suppliers.

The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD

data are programmed and locked during module assembly. The last 128 bytes are available to the customer.

All NANYA 200pin DDR SO-DIMMs provide a high-performance, flexible 8-byte interface in a 2.66” long space-saving footprint.

Ordering Information

Part Number

Speed

143MHz (7ns @ CL = 2.5 )

133MHz (7.5ns @ CL= 2 )

133MHz (7.5ns @ CL= 2.5 )

100MHz (10ns @ CL = 2 )

125MHz (8ns @ CL = 2.5 )

100MHz (10ns @ CL = 2 )

Organization

32Mx64

Leads

Gold

Power

2.5V

NT256D64S88A2GM-7K

PC2100

PC1600

NT256D64S88A2GM-75B

NT256D64S88A2GM-8B

Preliminary 01 / 2002

1

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88A2GM

256MB : 32M x 64

PC2100 / PC1600 Unbuffered DDR SO-DIMM

Pin Description

CK0, CK1,

Differential Clock Inputs

DQ0-DQ63

Data input/output

,

CK0 CK1

CKE0,CKE1

RAS

Clock Enable

Row Address Strobe

Column Address Strobe

Write Enable

DQS0-DQS7

DM0-DM7

Bidirectional data strobes

Data Masks

VDD

VDDQ

VSS

Power (2.5V)

Supply voltage for DQs(2.5V)

Ground

CAS

WE

Chip Selects

S0

A0-A9, A11,A12

A10/AP

BA0, BA1

VREF

Address Inputs

NC

No Connect

Address Input/Autoprecharge

SDRAM Bank Address Inputs

Ref. Voltage for SSTL_2 inputs

VDD Identification flag.

SCL

Serial Presence Detect Clock Input

Serial Presence Detect Data input/output

Serial Presence Detect Address Inputs

Serial EEPROM positive power supply(2.5V)

SDA

SA0-2

VDDSPD

VDDID

Pinout

1

Front

VREF

VSS

2

Back

VREF

VSS

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

99

Front

VSS

DQ19

DQ24

VDD

DQ25

DQS3

VSS

DQ26

DQ27

VDD

NC

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

92

94

96

98

100

Back

VSS

DQ23

DQ28

VDD

DQ29

DM3

VSS

DQ30

DQ31

VDD

NC

Front

A9

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

Back

A8

151

153

155

157

159

161

163

165

167

169

171

173

175

Front

DQ42

DQ43

VDD

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

182

184

186

188

190

192

194

196

198

200

Back

DQ46

DQ47

VDD

101

103

105

107

109

111

113

3

4

VSS

A7

VSS

A6

5

DQ0

DQ1

VDD

6

DQ4

DQ5

VDD

7

8

A5

A4

VDD

CK1

9

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

A3

A2

VSS

CK1

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

DQS0

DQ2

VSS

DM0

DQ6

VSS

A1

A0

VSS

VDD

BA1

RAS

CAS

DU

DQ48

DQ49

VDD

DQ52

DQ53

VDD

115 A10/AP

DQ3

DQ8

VDD

DQ7

DQ12

VDD

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

VDD

WE

DQS6

DQ50

VSS

DM6

DQ54

VSS

S0

DQ9

DQS1

VSS

DQ13

DM1

VSS

NC

DU

VSS

NC

VSS

NC

VSS

DQ51

DQ56

VDD

DQ55

DQ60

VDD

DQ32

DQ33

VDD

DQ36 177

DQ37 179

DQ10

DQ11

VDD

DQ14

DQ15

VDD

NC

VDD

NC

VDD

NC

VDD

181

183

DQ57

DQS7

VSS

DQ61

DM7

VSS

DQS4

DQ34

VSS

DM4

CK0

VDD

DU

DQ38 185

VSS 187

VSS

NC

VSS

VDD

CKE0

DU

DQ58

DQ59

VDD

DQ62

DQ63

VDD

CK0

VSS

DQ35

DQ40

VDD

DQ39 189

DQ44 191

DQ16

DQ17

VDD

DQ20

DQ21

VDD

NC

VDD

CKE1

NC

VDD

193

SDA

SA0

DQ41

DQS5

VSS

DQ45 195

SCL

SA1

DQS2

DQ18

DM2

DQ22

DM5

VSS

197 VDDSPD

199 VDDID

SA2

NC

A11

DU

Note: All pin assignments are consistent for all 8-byte unbuffered versions.

Preliminary 01 / 2002

2

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88A2GM

256MB : 32M x 64

PC2100 / PC1600 Unbuffered DDR SO-DIMM

Input/Output Functional Description

Function

Symbol

Type

Polarity

The positive line of the differential pair of system clock inputs which drives the input to the

on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the rising

edge of their associated clocks.

Positive

Edge

CK0 , CK1, CK2

(SSTL)

Negative The negative line of the differential pair of system clock inputs which drives the input to the

Edge on-DIMM PLL.

,

(SSTL)

CK0 CK1 CK2

Activates the SDRAM CK signal when high and deactivates the CK signal when low. By

Active

CKE0

deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh

High

mode.

Enables the associated SDRAM command decoder when low and disables the command

Active

(SSTL)

decoder when high. When the command decoder is disabled, new commands are ignored

S0

Low

but previous operations continue.

When sampled at the positive rising edge of the clock,

operation to be executed by the SDRAM.

,

, WE define the

RAS CAS

Active

Low

(SSTL)

Supply

(SSTL)

,

, WE

RAS CAS

VREF

VDDQ

Reference voltage for SSTL-2 inputs

Isolated power supply for the DDR SDRAM output buffers to provide improved noise

immunity

BA0, BA1

-

Selects which SDRAM bank is to be active.

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)

when sampled at the rising clock edge.

During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)

when sampled at the rising clock edge. In addition to the column address, AP is used to

invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,

autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,

autoprecharge is disabled.

A0 - A9

A10/AP

A11,A12

(SSTL)

During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control

which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the

state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.

Data and Check Bit input/output pins operate in the same manner as on conventional

DRAMs.

DQ0 - DQ63,

DQS0 - DQS7

(SSTL)

-

Data strobes: Output with read data, input with write data. Edge aligned with read data,

centered on write data. Used to capture write data.

Active

High

The data write masks, associated with one data byte. In Write mode, DM operates as a

byte mask by allowing input data to be written if it is low but blocks the write operation if it

is high. In Read mode, DM lines have no effect. DM8 is associated with check bits

CB0-CB7, and is not used on x64 modules.

Active

High

DM0 – DM7

Input

VDD , VSS

SA0 – SA2

Supply

Power and ground for the DDR SDRAM input buffers and core logic

Address inputs. Connected to either VDD or VSS on the system board to configure the

Serial Presence Detect EEPROM address.

-

This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor

must be connected from the SDA bus line to V DD to act as a pullup.

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be

connected from the SCL bus time to V DD to act as a pullup.

SDA

SCL

V DDSPD

Supply

Serial EEPROM positive power supply.

Preliminary 01 / 2002

3

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88A2GM

256MB : 32M x 64

PC2100 / PC1600 Unbuffered DDR SO-DIMM

Functional Block Diagram ( 1 Bank, 32Mx8 DDR SDRAMs )

S0

DQS0

DQS4

DM4

DM0

DQS

DM

DQS

DM

CS

D0

CS

D4

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS1

DM1

DQS5

DM5

DM

DQS

DM

DQS

CS

D1

CS

D5

DQ8

DQ9

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DQS6

DM6

DM

CS DQS

DM

CS

D6

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D2

DQS3

DM3

DQS7

DM7

DQS

CS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM

CS

D7

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D3

CK0

CS : SDRAMs D0 -D7

S0

BA0-BA1

A0-A12

RAS

120 ohm

SDRAM x 4

SDRAM x 0

BA0 - BA1 : SDRAMs D0 -D7

A0 - A12: SDRAMs D0 -D7

RAS : SDRAMs D0 -D7

CAS : SDRAMs D0 -D7

CKE0 : SDRAMs D0 -D7

WE : SDRAMs D0 -D7

CK0

CK1

CK2

CAS

CKE0

WE

CK2

Serial PD

VDDQ

D0 - D7

SCL

WP

VDD

VREF

VSS

D0 - D7

SDA

A0

A1

A2

SA0

SA1 SA2

VDDID

Strap: see Note 4

Notes :

1. DQ-to-I/O wring may be changed within a byte.

2. DQ/DQS/DM/CKE/S relationships are maintained as shown.

3. DQ/DQS/DM/DQS resistors are 22 Ohms.

4. VDDID strap connections (for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

STRAP IN (VSS): VDD is not equal to VDDQ.

Preliminary 01 / 2002

4

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88A2GM

256MB : 32M x 64

PC2100 / PC1600 Unbuffered DDR SO-DIMM

Serial Presence Detect -- Part 1 of 2

SPD Entry Value

Serial PD Data Entry (Hexadecimal) Note

Byte

Description

DDR266A DDR266B DDR200 DDR266A DDR266B DDR200

-7K

-75B

-8B

-7K

-75

-8B

Number of Serial PD Bytes Written during

Production

0

128

80

1

2

3

4

5

6.

7

8

9

Total Number of Bytes in Serial PD device

Fundamental Memory Type

256

08

07

0D

0A

01

40

00

04

75

SDRAM DDR

Number of Row Addresses on Assembly

Number of Column Addresses on Assembly

Number of DIMM Bank

13

10

1

Data Width of Assembly

X64

Data Width of Assembly (cont’)

Voltage Interface Level of this Assembly

DDR SDRAM Device Cycle Time at CL=2.5

DDR SDRAM Device Access Time from

Clock at CL=2.5

X64

SSTL 2.5V

7.5ns

7ns

8ns

70

75

80

10

0.75ns

0.8ns

75

11

12

13

14

DIMM Configuration Type

Non-Parity

SR/1x(7.8us)

X8

00

82

08

00

Refresh Rate/Type

Primary DDR SDRAM Width

Error Checking DDR SDRAM Device Width

DDR SDRAM Device Attr: Min CLk Delay,

Random Col Access

N/A

15

16

17

18

1 Clock

2,4,8

4

01

0E

04

0C

DDR SDRAM Device Attributes:

Burst Length Supported

DDR SDRAM Device Attributes: Number of

Device Banks

DDR SDRAM Device Attributes: CAS

Latencies Supported

2/2.5

0C

19

20

21

22

23

DDR SDRAM Device Attributes: CS Latency

DDR SDRAM Device Attributes: WE Latency

DDR SDRAM Device Attributes:

DDR SDRAM Device Attributes: General

Minimum Clock Cycle at CL=2

Maximum Data Access Time from Clock at

CL=2

0

01

02

20

00

A0

1

Differential Clock

+/-0.2V Voltage Tolerance

7.5ns

10ns

0.75ns

N/A

10ns

75

A0

80

24

25

26

27

28

0.75ns

0.8ns

75

00

50

3C

Minimum Clock Cycle Time at CL=1

Maximum Data Access Time from Clock at

CL=1

N/A

Minimum Row Precharge Time(tRP)

Minimum Row Active to Row Active delay

(tRRD)

20ns

15ns

20ns

15ns

20ns

15ns

50

3C

29

30

31

Minimum RAS to CAS delay (tRCD)

Minimum RAS Pulse Width (tRAS)

Module Bank Density

20ns

45ns

20ns

45ns

20ns

50ns

50

2D

40

50

32

2D

256MB

Address and Command Setup Time Before

Clock

32

33

0.9ns

1.1ns

90

B0

Address and Command Hold Time After

Clock

34

35

Data Input Setup Time Before Clock

Data Input Hold Time After Clock

0.5ns

0.6ns

50

00

BF

60

36-61 Reserved

Undefined

Initial

62

63

SPD Revision

Checksum Data

Initial

00

8F

00

45

Preliminary 01 / 2002

5

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88A2GM

256MB : 32M x 64

PC2100 / PC1600 Unbuffered DDR SO-DIMM

Serial Presence Detect -- Part 2 of 2

SPD Entry Value

Serial PD Data Entry (Hexadecimal)

Byte

Description

Note

DDR266A DDR266B DDR200 DDR266A DDR266B DDR200

-7K

-75B

NANYA

-8B

-7K

-75

-8B

64-71 Manufacturer’s JEDED ID Code

72 Module Manufacturing Location

7F7F7F0B00000000

N/A

00

73-90 Module Part number

91-92 Module Revision Code

93-94 Module Manufacturing Data

95-98 Module Serial Number

99-255 Reserved

N/A

00

N/A

00

Year/Week Code

Serial Number

Undefined

yy/ww

00

1,2

00

1. yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex)

2. ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex)

Preliminary 01 / 2002

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88A2GM

256MB : 32M x 64

PC2100 / PC1600 Unbuffered DDR SO-DIMM

Absolute Maximum Ratings

Symbol

, V

Parameter

Voltage on I/O pins relative to Vss

Rating

-0.5 to VDDQ+0.5

-0.5 to +3.6

0 to+70

Units

V

IN OUT

V

IN

Voltage on Input relative to Vss

Voltage on VDD supply relative to Vss

Voltage on VDDQ supply relative to Vss

Operating Temperature (Ambient)

Storage Temperature (Plastic)

Power Dissipation

V

DD

V

DDQ

V

T

°C

W

A

T

-55 to +150

8

STG

P

D

I

Short Circuit Output Current

50

mA

OUT

Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is

stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Capacitance

Symbol

CI1

Max.

12

30

9

Units

pF

Notes

Parameter

, CK1, , CK2,

CK1

1

Input Capacitance: CK0,

CK0

CK2

CI2

pF

Input Capacitance: A0-A11, BA0, BA1, WE ,

Input Capacitance: SA0-SA2, SCL

,

, CKE0,

RAS CAS S0

CI4

pF

1

CIO1

7

pF

1,2

Input/Output Capacitance DQ0-63; DQS0-7

CIO3

11

pF

Input/Output Capacitance: SDA

1. VDDQ = VDD = 2.5V ± 0.2V, f = 100 MHz, TA = 25 °C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V.

2. DQS inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at

the board level.

Preliminary 01 / 2002

7

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88A2GM

256MB : 32M x 64

PC2100 / PC1600 Unbuffered DDR SO-DIMM

DC Electrical Characteristics and Operating Conditions

( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)

Symbol

VDD

Parameter

Min

2.3

0

Max

2.7

0

Units

V

Notes

Supply Voltage

1

VDDQ

I/O Supply Voltage

V

VSS , VSSQ

VREF

Supply Voltage, I/O Supply Voltage

/O Reference Voltage

V

0.49 x VDDQ 0.51 x VDDQ

V

1,2

1,3

1

VTT

I/O Termination Voltage (System)

Input High (Logic1) Voltage

Input Low (Logic0) Voltage

VREF – 0.04

VREF + 0.15

-0.3

VREF + 0.04

VDDQ + 0.3

VREF- 0.15

VDDQ + 0.3

V DDQ + 0.6

V

VIH(DC)

VIL(DC)

VIN(DC)

VID(DC)

V

1

Input Voltage Level, CK and

Inputs

-0.3

V

1

CK

Input Differential Voltage, CK and

Input Leakage Current

Inputs

0.30

V

1,4

CK

II

-5

5

uA

1

Any input 0V £ VIN £ VDD; (All other pins not under test = 0V)

Output Leakage Current

IOZ

IOH

IOL

-5

5

-

uA

mA

1

(DQs are disabled; 0V £ Vout £ VDDQ

Output High Current

-16.8

16.8

(VOUT = VDDQ -0.373V, min VREF , min VTT )

Output Low Current

-

(VOUT = 0.373, max VREF , max VTT )

1. Inputs are not recognized as valid until V REF stabilizes.

2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak

noise on VREF may not exceed 2% of the DC value.

3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF ,

and must track variations in the DC level of V REF .

4. VID is the magnitude of the difference between the input level on CK and the input level on

.

CK

Preliminary 01 / 2002

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88A2GM

256MB : 32M x 64

PC2100 / PC1600 Unbuffered DDR SO-DIMM

AC Characteristics

(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating

Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.)

1. All voltages referenced to V SS .

2. Tests for AC timing, IDD , and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but

the related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.

4. AC timing and I DD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF

(or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use

conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC) unless otherwise specified.

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the

signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW

(HIGH) level.

AC Output Load Circuits

V

TT

50 ohms

Output

Timing Reference Point

VOUT

30 pF

AC Operating Conditions

( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)

Symbol

VIH(AC)

VIL(AC)

VID(AC)

VIX(AC)

Parameter/Condition

Input High (Logic 1) Voltage.

Min

Max

Unit

V

Notes

1, 2

V REF + 0.31

Input Low (Logic 0) Voltage.

V REF -?0.31

V DDQ + 0.6

V

1, 2

Input Differential Voltage, CK and

Inputs

0.62

V

1, 2, 3

1, 2, 4

CK

Input Differential Pair Cross Point Voltage, CK and

Inputs

(0.5*VDDQ ) - 0.2

(0.5*VDDQ ) +?0.2

V

CK

1. Input slew rate = 1V/ ns

2. Inputs are not recognized as valid until V REF stabilizes.

3. V ID is the magnitude of the difference between the input level on CK and the input level on CK.

4. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.

.

Preliminary 01 / 2002

9

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88A2GM

256MB : 32M x 64

PC2100 / PC1600 Unbuffered DDR SO-DIMM

Operating, Standby, and Refresh Currents

( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)

Symbol

I DD0

Parameter/Condition

PC1600

600

PC2100

680

Unit

mA

Notes

1,2

Operating Current : one bank; active / precharge; tRC = tRC (MIN) ;

tCK = tCK (MIN) ; DQ, DM, and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle

Operating Current : one bank; active / read / precharge; Burst = 2;

tRC = tRC (MIN) ; CL=2.5; tCK = tCK (MIN) ; IOUT = 0mA;

address and control inputs changing once per clock cycle

Precharge Power-Down Standby Current :

720

880

mA

1,2

I DD1

120

240

120

280

120

mA

1,2

I DD2P

I DD2N

I DD3P

all banks idle; power-down mode; CKE £ VIL (MAX) ; tCK = tCK (MIN)

Idle Standby Current : CS ³ VIH (MIN) ; all banks idle; CKE ³ VIH(MIN) ;

tCK = tCK (MIN) ; address and control inputs changing once per clock cycle

Active Power-Down Standby Current : one bank active;

power-down mode; CKE £ VIL (MAX) ; tCK = tCK (MIN)

Active Standby Current : one bank; active / precharge; CS ³ VIH (MIN) ;

CKE ³ VIH (MIN) ; tRC = tRAS (MAX) ; tCK = tCK (MIN) ; DQ, DM, and DQS

inputs changing twice per clock cycle;

400

1040

920

480

1320

1200

mA

1,2

I DD3N

I DD4R

I DD4W

address and control inputs changing once per clock cycle

Operating Current : one bank; Burst = 2; reads; continuous burst;

address and control inputs changing once per clock cycle;

DQ and DQS outputs changing twice per clock cycle; CL = 2.5;

tCK = tCK (MIN) ; IOUT = 0mA

Operating Current : one bank; Burst = 2; writes; continuous burst;

address and control inputs changing once per clock cycle;

DQ and DQS inputs changing twice per clock cycle; CL=2.5;

tCK = tCK (MIN)

t RC = t RFC (MIN)

1280

132

24

1360

132

24

mA

1,2

Auto-Refresh Current :

I DD5

I DD6

t RC = 7.8 ms

1,2,4

1,2,3

Self-Refresh Current : CKE £ ?0.2V

1. I DD specifications are tested after the device is properly initialized.

2. Input slew rate = 1V/ ns .

3. Enables on-chip refresh and address counters.

4. Current at 7.8 µs is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 µs.

Preliminary 01 / 2002

10

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88A2GM

256MB : 32M x 64

PC2100 / PC1600 Unbuffered DDR SO-DIMM

AC Timing Specifications for DDR SDRAM Devices Used on Module

( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)

-7K

-75B

-8B

Symbol

Parameter

Unit

Notes

Min.

-0.75

0.45

7

Max.

+0.75

0.55

12

Min.

-0.75

0.45

7.5

Max.

+0.75

0.55

12

Min.

-0.8

0.45

8

Max.

+0.8

0.55

12

tAC

tDQSCK

tCH

DQ output access time from CK/

ns

1,2,3,4

CK

DQS output access time from CK/

CK high-level width

CK

tCK

ns

tCL

CK low-level width

tCK

CL=2.5

CL=2

Clock cycle time

tCK

7.5

12

10

12

10

12

ns

1,2,3,4

,15,16

tDH

DQ and DM input hold time

0.5

0.6

ns

1,2,3,4

,15,16

tDS

tDIPW

tHZ

DQ and DM input setup time

0.5

1.75

-0.75

0.5

1.75

-0.75

0.6

2

ns

DQ and DM input pulse width (each input)

Data-out high-impedance time from

1,2,3,4

1, 2, 3,

4, 5

+0.75

-0.8

+0.8

CK/

CK

Data-out low-impedance time from

CK/

1, 2, 3,

4, 5

tLZ

-0.75

-0.8

ns

CK

DQS-DQ skew (DQS & associated DQ

signals)

tDQSQ

0.5

0.6

ns

1,2,3,4

tDQSQA

DQS-DQ skew (DQS & all DQ signals)

Minimum half clk period for any given

cycle; defined by clk high(tCH )

or clk low (tCL ) time

tCH

or

tCH

or

tCH

or

tHP

tCK

1,2,3,4

tCL

tHP -

tCL

tHP -

0.75ns

tHP -

1.0ns

tQH

tDQSS

tDQSL,H

tDSS

Data output hold time from DQS

tCK

1,2,3,4

0.75ns

Write command to 1st DQS latching

transition

0.75

0.35

0.2

1.25

0.75

1.25

0.75

0.35

0.2

1.25

DQS input low (high) pulse width

(write cycle)

0.35

0.2

DQS falling edge to CK setup time

(write cycle)

DQS falling edge hold time from CK

(write cycle)

tDSH

tMRD

0.2

14

0.2

15

0.2

16

tCK

ns

1,2,3,4

Mode register set command cycle time

1, 2, 3,

4, 7

tWPRES

Write preamble setup time

0

ns

1, 2, 3,

4, 6

tWPST

tWPRE

Write postamble

Write preamble

0.40

0.25

0.60

0.40

0.25

0.60

0.40

0.25

0.60

tCK

1,2,3,4

2, 3, 4,

9, 11,

12

Address and control input hold time

(fast slew rate)

tIH

tIS

tIH

0.9

1.0

1.1

ns

2, 3, 4,

9, 11,

12

Address and control input setup time

(fast slew rate)

2, 3, 4,

10, 11,

12, 14

Address and control input hold time

(slow slew rate)

Preliminary 01 / 2002

11

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88A2GM

256MB : 32M x 64

PC2100 / PC1600 Unbuffered DDR SO-DIMM

AC Timing Specifications for DDR SDRAM Devices Used on Module

( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 2 of 2)

-7K

-75B

-8B

Symbol

Parameter

Unit

Notes

Min.

1.0

Max.

Min.

1.0

Max.

Min.

1.1

Max.

2, 3, 4,

10, 11,

Address and control input setup time

(slow slewrate)

tIS

ns

12, 14

2, 3, 4,

12

tIPW

Input pulse width

2.2

-

1,2,3,4

tRPRE

tRPST

tRAS

Read preamble

0.9

0.40

45

1.1

0.60

0.9

0.40

45

1.1

0.9

0.40

50

1.1

0.60

tCK

ns

Read postamble

0.60

Active to Precharge command

Active to Active/Auto-refresh

command period

120,000

1,2,3,4

tRC

65

70

ns

Auto-refresh to Active/Auto-refresh

command period

1,2,3,4

tRFC

tRCD

tRAP

tRP

75

20

15

75

20

15

80

20

15

Active to Read or Write delay

Active to Read Command with

Autoprecharge

ns

Precharge command period

Active bank A to Active bank B

command

tRRD

tWR

Write recovery time

(tWR/

tCK )

+

(tWR/

tCK )

+

(tWR/

tCK )

+

1, 2, 3,

4, 13

Auto precharge write recovery +

precharge time

tDAL

tCK

(tRP/

tCK )

1

(tRP /

tCK )

1

(tRP /

tCK )

1

tWTR

Internal write to read command delay

Exit self-refresh to non-read

command

tCK

ns

1,2,3,4

tXSNR

75

80

tXSRD

tREFI

Exit self-refresh to read command

200

tCK

µs

1,2,3,4

1, 2, 3,

Average Periodic Refresh Interval

7.8

4, 8

Preliminary 01 / 2002

12

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88A2GM

256MB : 32M x 64

PC2100 / PC1600 Unbuffered DDR SO-DIMM

AC Timing Specification Notes

1. Input slew rate = 1V/ns.

2. The CK/

input reference level (for timing reference to CK/

) is the point at which CK and

cross: the input reference level for

CK

signals other than CK/

, is VREF.

CK

3. Inputs are not recognized as valid until VREF stabilizes.

4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT .

5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a

specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system

performance (bus turnaround) degrades accordingly.

7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid

transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in

progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW,

or transitioning from high to low at this time, depending on tDQSS .

8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device.

9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC).

10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC).

11. CK/

slew rates are >= 1.0 V/ns.

CK

12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by

design or tester characterization.

13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual system

clock cycle time. For example, for PC2100 at CL= 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5.

14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns.

Input Slew Rate

0.5 V/ns

D?elta ( tIS )

Delta ( tIH )

Unit

ps

Note

1,2

0

0.4 V/ns

+50

+100

ps

1,2

0.3 V/ns

ps

1,2

1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly

for rising transitions.

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns.

Input Slew Rate

0.5 V/ns

Delta ( tDS )

Delta ( tDH )

Unit

ps

Note

1,2

0

0.4 V/ns

+75

ps

1,2

0.3 V/ns

+150

ps

1,2

1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for

rising transitions.

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ.

Delta Rise and Fall Rate

0.0 ns/V

Delta ( tDS )

Delta ( tDH )

Unit

ps

Note

0

1,2,3,4

0.25 ns/V

+50

+100

+50

+100

ps

0.5 ns/V

ps

1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly

for rising transitions.

2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.

3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]

For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V

Using the table above, this would result in an increase in t DS and t DH of 100 ps.

4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each

device.

Preliminary 01 / 2002

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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型号：	NT256D64S88A2GM-7K
厂家：	ETC
描述：	200pin One Bank Unbuffered DDR SO-DIMM 200PIN一家银行无缓冲DDR SO -DIMM 内存集成电路动态存储器双倍数据速率时钟
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NT256D64S88A2GM-7K [ETC]

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