NT256D64S88ABG_技术文档

NT256D64S88ABG

256MB : 32M x 64

PC2700 Unbuffered DIMM

184pin One Bank Unbuffered DDR SDRAM MODULE Based on DDR333 32Mx8 SDRAM

Features

• 184-Pin Unbuffered 8-Byte Dual In-Line Memory Module

• 32Mx64 Double Data Rate (DDR) SDRAM DIMM

• DRAM DLL aligns DQ and DQS transitions with clock

transitions.

• Performance:

• Address and control signals are fully synchronous to positive

clock edge

PC2700

• Programmable Operation:

- DIMM CAS Latency: 2, 2.5

- Burst Type: Sequential or Interleave

- Burst Length: 2, 4, 8

- Operation: Burst Read and Write

• Auto-Refresh (CBR) and Self-Refresh Modes

• Automatic and controlled precharge commands

• 13/10/1 Addressing (row/column/bank)

• 7.8 µs Max. Average Periodic Refresh Interval

• Serial Presence Detect

Unit

Speed Sort

DIMM CAS Latency

f CK Clock Frequency

t CK Clock Cycle

-6

2.5

166

6

2

133

7.5

266

MHz

ns

MHz

f DQ DQ Burst Frequency

333

• Intended for 100 MHz and 133 MHz applications

• Inputs and outputs are SSTL-2 compatible

• VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2

• SDRAMs have 4 internal banks for concurrent operation

• Module has one physical bank

• Gold contacts

• SDRAMs in 66-pin TSOP Type II Package

• Differential clock inputs

• Data is read or written on both clock edges

Description

NT256D64S88ABG is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),

organized as a one-bank high-speed memory array. The 32Mx64 module is a single-bank DIMM that uses eight 32Mx8 DDR

SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 333MHz. The DIMM is intended for use

in applications operating from 133 MHz to 166 MHz clock speeds with data rates of 266 to 333 MHz. Clock enable CKE0 controls all

devices on the DIMM.

Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by

address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.

These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common

design files minimizes electrical variation between suppliers.

The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD

data are programmed and locked during module assembly. The last 128 bytes are available to the customer.

All NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.

Ordering Information

Part Number

Speed

166MHz (6ns @ CL = 2.5)

133MHz (7.5ns @ CL= 2)

Organization

32Mx64

Leads

Gold

Power

2.5V

NT256D64S88ABG-6

PC2700

REV 1.1

1

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88ABG

256MB : 32M x 64

PC2700 Unbuffered DIMM

Pin Description

CK0, CK1, CK2

Differential Clock Inputs

DQ0-DQ63

Data input/output

CKE0

RAS

Clock Enable

Row Address Strobe

Column Address Strobe

Write Enable

DQS0-DQS7,

DQS9-DQS16

VDD

Bi-directional data strobes

CAS

Power (2.5V)

Supply voltage for DQs (2.5V)

Ground

WE

VDDQ

VSS

S0

Chip Selects

A0-A9, A11, A12

A10/AP

BA0, BA1

VREF

Address Inputs

NC

SCL

SDA

SA0-2

VDDSPD

No Connect

Address Input/Auto-precharge

SDRAM Bank Address Inputs

Ref. Voltage for SSTL_2 inputs

VDD Identification flag.

Serial Presence Detect Clock Input

Serial Presence Detect Data input/output

Serial Presence Detect Address Inputs

Serial EEPROM positive power supply (2.5V)

VDDID

Pinout

1

2

3

4

5

6

7

8

Front

VREF

DQ0

VSS

DQ1

DQS0

DQ2

VDD

93

94

95

96

97

98

99

Back

VSS

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

Front

A5

Back

VSS

A6

DQ28

DQ29

VDDQ

DQS12

A3

DQ30

VSS

DQ31

NC

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

Front

VDDQ

WE

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

Back

RAS

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

DQ4

DQ5

VDDQ

DQS9

DQ6

DQ7

VSS

NC

VDDQ

DQ12

DQ13

DQS10

VDD

DQ14

DQ15

NC

VDDQ

NC

DQ20

A12

VSS

DQ21

A11

DQS11

VDD

DQ22

A8

DQ24

VSS

DQ25

DQS3

A4

VDD

DQ26

DQ27

A2

VSS

A1

NC

VDD

NC

DQ45

VDDQ

S0

DQ41

CAS

VSS

NC

DQS14

VSS

DQ46

DQ47

NC

VDDQ

DQ52

DQ53

NC

DQS5

DQ42

DQ43

VDD

DQ3

NC

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

NC

VSS

DQ48

DQ49

VSS

DQ8

DQ9

DQS1

VDDQ

CK1

NC

VDDQ

CK0

CK2

VDD

VSS

NC

A10

NC

VDDQ

DQS6

DQ50

DQ51

VSS

VDDID

DQ56

DQ57

VDD

DQS7

DQ58

DQ59

VSS

DQS15

DQ54

DQ55

VDDQ

NC

DQ60

DQ61

VSS

DQS16

DQ62

DQ63

VDDQ

SA0

CK1

A0

NC

VSS

NC

BA1

VSS

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

A9

DQ18

A7

VDDQ

DQ19

VDDQ

NC

KEY

53

54

55

56

57

58

59

60

61

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

BA0

DQ35

DQ40

145

146

147

148

149

150

151

152

153

VSS

DQ36

DQ37

VDD

DQS13

DQ38

DQ39

VSS

NC

SDA

SCL

SA1

SA2

VDDSPD

DQ23

DQ44

Note: All pin assignments are consistent for all 8-byte unbuffered versions.

REV 1.1

2

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88ABG

256MB : 32M x 64

PC2700 Unbuffered DIMM

Input/Output Functional Description

Function

Symbol

Type

Polarity

Positive The positive line of the differential pair of system clock inputs. All the DDR SDRAM

Edge address and control inputs are sampled on the rising edge of their associated clocks.

CK0, CK1, CK2

(SSTL)

Negative

The negative line of the differential pair of system clock inputs.

Edge

CK0, CK1, CK2

(SSTL)

Activates the SDRAM CK signal when high and deactivates the CK signal when low. By

Active

CKE0

deactivating the clocks, CKE low initiates the Power Down mode, or the Self-Refresh

High

mode.

Enables the associated SDRAM command decoder when low and disables the command

Active

(SSTL)

S0

decoder when high. When the command decoder is disabled, new commands are ignored

Low

but previous operations continue.

When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation

Active

Low

(SSTL)

Supply

(SSTL)

RAS, CAS, WE

VREF

to be executed by the SDRAM.

Reference voltage for SSTL-2 inputs

Isolated power supply for the DDR SDRAM output buffers to provide improved noise

immunity

Selects which SDRAM bank is to be active.

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)

when sampled at the rising clock edge.

During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)

when sampled at the rising clock edge. In addition to the column address, AP is used to

invoke Auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high,

auto-precharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,

auto-precharge is disabled.

VDDQ

BA0, BA1

-

A0 - A9

A10/AP

A11, A12

(SSTL)

During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control

which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the

state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.

Data and Check Bit input/output pins operate in the same manner as on conventional

DRAMs.

DQ0 - DQ63

(SSTL)

-

Data strobes: Output with read data, input with write data. Edge aligned with read data,

centered on write data. Used to capture write data.

Power and ground for the DDR SDRAM input buffers and core logic

Address inputs. Connected to either VDD or VSS on the system board to configure the

Serial Presence Detect EEPROM address.

This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor

must be connected from the SDA bus line to VDD to act as a pullup.

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be

connected from the SCL bus time to VDD to act as a pullup.

DQS0 - DQS7

DQS9 - DQS16

Active

High

(SSTL)

Supply

VDD, VSS

SA0 – SA2

-

SDA

SCL

VDDSPD

Supply

Serial EEPROM positive power supply.

REV 1.1

3

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88ABG

256MB : 32M x 64

PC2700 Unbuffered DIMM

Functional Block Diagram (1 Bank, 32Mx8 DDR SDRAMs)

S0

DQS0

DQS9

DQS4

DQS13

DQS

DM

DQS

DM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

D0

D4

DQS1

DQS10

DQS5

DQS14

DM

CS

DQ8

DQ9

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

D1

D5

DQS2

DQS11

DQS6

DQS15

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM

CS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

D6

D2

DQS3

DQS12

DQS7

DQS16

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM

CS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

D3

D7

BA0-BA1

A0-A13

RAS

BA0-BA1 : SDRAMs D0-D7

A0-A13 : SDRAMs D0-D7

RAS : SDRAMs D0-D7

CAS : SDRAMs D0-D7

CKE : SDRAMs D0-D7

WE : SDRAMs D0-D7

* Clock Wiring

Clock Input

*CK0/CK0

*CK1/CK1

*CK2/CK2

SDRAMs

2 SDRAMs

3 SDRAMs

CAS

* Wire per Clock Loading Table/

CKE0

WE

Wiring Diagrams

V_DDSPD

V_DD/V_DDQ

V_REF

SPD

Serial PD

A1

D0-D7

SCL

WP

SDA

A0

SA0

A2

V_SS

V_DDID

SA1 SA2

Strap: see Note 4

Notes :

1. DQ-to-I/O wiring is shown as recommended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

4. V_DDIDstrap connections (for memory device V_DD, V_DDQ):

STRAP OUT (OPEN): V_DD= V_DDQ

STRAP IN (V_SS): V_DDis not equal to V_DDQ

.

REV 1.1

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88ABG

256MB : 32M x 64

PC2700 Unbuffered DIMM

Serial Presence Detect -- Part 1 of 2

32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD

SPD Entry Value

Serial PD Data Entry (Hexadecimal) Note

Byte

Description

DDR333

-6

DDR333

-6

Number of Serial PD Bytes Written during

Production

0

128

80

1

2

3

4

5

6

7

8

9

Total Number of Bytes in Serial PD device

Fundamental Memory Type

Number of Row Addresses on Assembly

Number of Column Addresses on Assembly

Number of DIMM Bank

256

SDRAM DDR

08

07

0D

0A

01

40

00

04

60

13

10

1

X64

Data Width of Assembly

Data Width of Assembly (cont’)

Voltage Interface Level of this Assembly

DDR SDRAM Device Cycle Time at CL=2.5

DDR SDRAM Device Access Time from Clock

at CL=2.5

SSTL 2.5V

6ns

10

0.7ns

70

11

12

13

14

DIMM Configuration Type

Refresh Rate/Type

Non-Parity

SR/1x(7.8µs)

X8

00

82

08

00

Primary DDR SDRAM Width

Error Checking DDR SDRAM Device Width

DDR SDRAM Device Attr: Min CLK Delay,

Random Col Access

DDR SDRAM Device Attributes:

Burst Length Supported

DDR SDRAM Device Attributes: Number of

Device Banks

DDR SDRAM Device Attributes: CAS Latencies

Supported

N/A

15

16

17

18

1 Clock

2,4,8

4

01

0E

04

0C

2/2.5

19

20

21

22

23

DDR SDRAM Device Attributes: CS Latency

DDR SDRAM Device Attributes: WE Latency

DDR SDRAM Device Attributes:

DDR SDRAM Device Attributes: General

Minimum Clock Cycle at CL=2

Maximum Data Access Time from Clock at

CL=2

Minimum Clock Cycle Time at CL=1

Maximum Data Access Time from Clock at

CL=1

0

1

01

02

20

00

75

Differential Clock

+/-0.2V Voltage Tolerance

7.5ns

24

25

26

27

28

0.7ns

N/A

70

00

48

30

N/A

Minimum Row Precharge Time (tRP)

Minimum Row Active to Row Active delay

(tRRD)

18ns

12ns

29

30

31

Minimum RAS to CAS delay (tRCD)

Minimum RAS Pulse Width (tRAS)

Module Bank Density

18ns

42ns

256MB

48

2A

40

Address and Command Setup Time Before

Clock

32

0.75ns

75

33

34

35

Address and Command Hold Time After Clock

Data Input Setup Time Before Clock

Data Input Hold Time After Clock

0.75ns

0.45ns

Undefined

Initial

75

45

00

0A

36-61 Reserved

62

63

SPD Revision

Checksum Data

REV 1.1

5

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88ABG

256MB : 32M x 64

PC2700 Unbuffered DIMM

Serial Presence Detect -- Part 2 of 2

32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD

SPD Entry Value

Serial PD Data Entry (Hexadecimal)

Byte

Description

Note

1, 2

DDR333

-6

0B

N/A

-6

64-71 Manufacturer’s JEDEC ID Code

72 Module Manufacturing Location

7F7F7F0B00000000

00

yy/ww

00

73-90 Module Part number

91-92 Module Revision Code

93-94 Module Manufacturing Data

95-98 Module Serial Number

99-255 Reserved

N/A

Year/Week Code

Serial Number

Undefined

1. yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex)

2. ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex)

REV 1.1

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NT256D64S88ABG

256MB : 32M x 64

PC2700 Unbuffered DIMM

Absolute Maximum Ratings

Symbol

Parameter

Voltage on I/O pins relative to Vss

Rating

-0.5 to VDDQ+0.5

-0.5 to +3.6

0 to+70

Units

V

, V

IN OUT

V

Voltage on Input relative to Vss

Voltage on VDD supply relative to Vss

Voltage on VDDQ supply relative to Vss

Operating Temperature (Ambient)

Storage Temperature (Plastic)

Power Dissipation

V

IN

V

DD

V

DDQ

T

A

°C

W

T

STG

-55 to +150

8

P

D

I

Short Circuit Output Current

50

mA

OUT

Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is

stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Capacitance

Symbol

Max.

Units

Notes

Parameter

Input Capacitance: CK0, CK0, CK1, CK1, CK2, CK2

Input Capacitance: A0-A11, BA0, BA1, WE, RAS, CAS, CKE0, S0

Input Capacitance: SA0-SA2, SCL

CI1

CI2

12

30

9

pF

1

CI4

1

Input/Output Capacitance DQ0-63; DQS0-7, 9-16

Input/Output Capacitance: SDA

CIO1

CIO3

7

1, 2

11

1. VDDQ = VDD = 2.5V ± 0.2V, f = 100 MHz, TA = 25 °C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V.

2. DQS inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at

the board level.

REV 1.1

7

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88ABG

256MB : 32M x 64

PC2700 Unbuffered DIMM

DC Electrical Characteristics and Operating Conditions

(TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)

Symbol

VDD

VDDQ

Parameter

Min

2.3

0

Max

2.7

0

Units

V

Notes

Supply Voltage

1

I/O Supply Voltage

V

VSS, VSSQ

Supply Voltage, I/O Supply Voltage

I/O Reference Voltage

V

VREF

0.49 x VDDQ 0.51 x VDDQ

V

1, 2

1, 3

1

VTT

I/O Termination Voltage (System)

Input High (Logic1) Voltage

VREF – 0.04

VREF + 0.15

-0.3

VREF + 0.04

VDDQ + 0.3

VREF- 0.15

VDDQ + 0.3

V DDQ + 0.6

V

VIH (DC)

VIL (DC)

VIN (DC)

VID (DC)

V

Input Low (Logic0) Voltage

V

1

Input Voltage Level, CK and CK Inputs

Input Differential Voltage, CK and CK Inputs

-0.3

V

1

0.30

V

1, 4

Input Leakage Current

II

-5

5

uA

1

Any input 0V ≤ VIN ≤ VDD; (All other pins not under test = 0V)

Output Leakage Current

IOZ

IOH

IOL

-5

5

-

uA

mA

1

(DQs are disabled; 0V ≤ Vout ≤ VDDQ

Output High Current

-16.8

16.8

(VOUT = VDDQ -0.373V, min VREF, min VTT)

Output Low Current

-

(VOUT = 0.373, max VREF, max VTT)

1. Inputs are not recognized as valid until VREF stabilizes.

2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak

noise on VREF may not exceed 2% of the DC value.

3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF,

and must track variations in the DC level of VREF.

4. VID is the magnitude of the difference between the input level on CK and the input level on CK.

REV 1.1

8

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88ABG

256MB : 32M x 64

PC2700 Unbuffered DIMM

AC Characteristics

(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating

Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.)

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but

the related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.

4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or

to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use

conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified.

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the

signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW

(HIGH) level.

AC Output Load Circuits

V

TT

50 ohms

Output

Timing Reference Point

V

OUT

30 pF

AC Operating Conditions

(TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)

Symbol

VIH (AC)

VIL (AC)

VID (AC)

VIX (AC)

Parameter/Condition

Input High (Logic 1) Voltage.

Min

Max

Unit

V

Notes

1, 2

V REF + 0.31

Input Low (Logic 0) Voltage.

V REF - 0.31

V DDQ + 0.6

V

1, 2

Input Differential Voltage, CK and CK Inputs

Input Differential Pair Cross Point Voltage, CK and CK Inputs

0.62

V

1-3

(0.5*VDDQ) - 0.2

(0.5*VDDQ) + 0.2

V

1, 2, 4

1. Input slew rate = 1V/ ns.

2. Inputs are not recognized as valid until V REF stabilizes.

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

4. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.

REV 1.1

9

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88ABG

256MB : 32M x 64

PC2700 Unbuffered DIMM

Operating, Standby, and Refresh Currents

(TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)

Symbol

Parameter/Condition

PC2700

680

Unit

mA

Notes

1, 2

Operating Current : one bank; active / precharge; tRC = tRC (MIN) ;

tCK = tCK (MIN) ; DQ, DM, and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle

Operating Current : one bank; active / read / precharge; Burst = 2;

tRC = tRC (MIN) ; CL=2.5; tCK = tCK (MIN) ; IOUT = 0mA;

address and control inputs changing once per clock cycle

Precharge Power-Down Standby Current :

all banks idle; power-down mode; CKE ≤ VIL (MAX) ; tCK = tCK (MIN)

Idle Standby Current : CS ≥ VIH (MIN) ; all banks idle; CKE ≥ VIH(MIN) ;

tCK = tCK (MIN) ; address and control inputs changing once per clock cycle

Active Power-Down Standby Current : one bank active;

power-down mode; CKE ≤ VIL (MAX) ; tCK = tCK (MIN)

I DD0

TBD

mA

1, 2

I DD1

200

280

200

mA

1, 2

I DD2P

I DD2N

I DD3P

Active Standby Current : one bank; active / precharge; CS ≥ VIH (MIN) ;

CKE ≥ VIH (MIN) ; tRC = tRAS (MAX) ; tCK = tCK (MIN) ; DQ, DM, and DQS

inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle

Operating Current : one bank; Burst = 2; reads; continuous burst;

address and control inputs changing once per clock cycle;

DQ and DQS outputs changing twice per clock cycle; CL = 2.5;

tCK = tCK (MIN) ; IOUT = 0mA

Operating Current : one bank; Burst = 2; writes; continuous burst;

address and control inputs changing once per clock cycle;

DQ and DQS inputs changing twice per clock cycle; CL=2.5;

tCK = tCK (MIN)

480

1320

1200

mA

1, 2

I DD3N

I DD4R

I DD4W

t RC = t RFC (MIN)

1360

132

24

mA

1, 2

1, 2, 4

1-3

Auto-Refresh Current :

t RC = 7.8 µs

Self-Refresh Current : CKE ≤ 0.2V

I DD5

I DD6

Operating Current: four bank; four bank interleaving with BL = 4, address

and control inputs randomly changing; 50% of data changing at every

transfer; tRC = tRC (min); IOUT = 0mA.

TBD

mA

1

I DD7

1. I DD specifications are tested after the device is properly initialized.

2. Input slew rate = 1V/ ns.

3. Enables on-chip refresh and address counters.

4. Current at 7.8 µs is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 µs.

REV 1.1

10

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88ABG

256MB : 32M x 64

PC2700 Unbuffered DIMM

AC Timing Specifications for DDR SDRAM Devices Used on Module

(TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)

-6

Symbol

Parameter

Unit

Notes

Min.

-0.7

0.45

6

Max.

+0.7

0.55

12

tAC

tDQSCK

tCH

tCL

tCK

tDH

tDS

tDIPW

tHZ

DQ output access time from CK/CK

DQS output access time from CK/CK

CK high-level width

ns

tCK

ns

1-4

CK low-level width

CL=2.5

CL=2

Clock cycle time

7.5

12

1-4

DQ and DM input hold time

DQ and DM input setup time

0.45

1.75

-0.7

1-4, 15, 16

1-4

DQ and DM input pulse width (each input)

Data-out high-impedance time from CK/CK

Data-out low-impedance time from CK/CK

DQS-DQ skew (DQS & associated DQ signals)

DQS-DQ skew (DQS & all DQ signals)

Minimum half clk period for any given cycle;

defined by clk high (tCH ) or clk low (tCL ) time

Data Hold Skew Factor

Data output hold time from DQS

Write command to 1st DQS latching transition

DQS input low (high) pulse width (write cycle)

DQS falling edge to CK setup time (write cycle)

DQS falling edge hold time from CK (write cycle)

Mode register set command cycle time

Write preamble setup time

+0.7

0.4

1-5

1-4

tLZ

tDQSQ

tDQSQA

0.4

min

(tCH, tCL)

0.55

tHP - tQHS

0.75

0.35

0.2

12

0

0.40

0.25

tHP

tCK

1-4

tQHS

tQH

tDQSS

tDQSL,H

tDSS

tDSH

tMRD

tWPRES

tWPST

tWPRE

Ns

tCK

ns

tCK

1-4

1.25

0.60

1-4

1-4, 7

1-4, 6

1-4

Write postamble

Write preamble

Address and control input hold time (fast slew

rate)

Address and control input setup time (fast slew

rate)

Address and control input hold time (slow slew

rate)

Address and control input setup time (slow slew

rate)

2-4, 9, 11,

12

2-4, 9, 11,

12

2-4, 10-12,

14

2-4, 10-12,

14

tIH

tIS

tIH

tIS

0.75

0.8

ns

0.8

REV 1.1

11

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88ABG

256MB : 32M x 64

PC2700 Unbuffered DIMM

AC Timing Specifications for DDR SDRAM Devices Used on Module

(TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 2 of 2)

-6

Symbol

Parameter

Unit

Notes

Min.

2.2

0.9

0.40

42

Max.

tIPW

Input pulse width

Read preamble

Read postamble

ns

tCK

ns

2-4, 12

1-4

tRPRE

tRPST

tRAS

tRC

1.1

0.60

120,000

Active to Precharge command

Active to Active/Auto-refresh command period

Auto-refresh to Active/Auto-refresh command

period

60

ns

tRFC

72

ns

1-4

tRCD

tRAP

tRP

tRRD

tWR

Active to Read or Write delay

Active to Read Command with Auto-precharge

Precharge command period

Active bank A to Active bank B command

Write recovery time

18

12

15

ns

1-4

(tWR/tCK) +

(tRP/tCK)

1

tDAL

Auto precharge write recovery + recharge time

tCK

1-4, 13

tWTR

tXSNR

tXSRD

tREFI

Internal write to read command delay

Exit self-refresh to non-read command

Exit self-refresh to read command

Average Periodic Refresh Interval

tCK

ns

tCK

µs

1-4

75

200

7.8

1-4, 8

REV 1.1

12

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88ABG

256MB : 32M x 64

PC2700 Unbuffered DIMM

AC Timing Specification Notes

1. Input slew rate = 1V/ns.

2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for

signals other than CK/CK is VREF.

3. Inputs are not recognized as valid until VREF stabilizes.

4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT.

5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a

specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system

performance (bus turnaround) degrades accordingly.

7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid

transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in

progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW,

or transitioning from high to low at this time, depending on tDQSS.

8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device.

9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC).

10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC).

11. CK/CK slew rates are >= 1.0 V/ns.

12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by

design or tester characterization.

13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual system

clock cycle time. For example, for PC2100 at CL= 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5.

14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns.

Input Slew Rate

0.5 V/ns

Delta (tIS)

0

Delta (tIH)

Unit

ps

Note

1, 2

0

0.4 V/ns

+50

ps

0.3 V/ns

+100

ps

1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly

for rising transitions.

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns.

Input Slew Rate

0.5 V/ns

Delta (tDS)

Delta (tDH)

Unit

ps

Note

1, 2

0

0.4 V/ns

+75

ps

0.3 V/ns

+150

ps

1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for

rising transitions.

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ.

Delta Rise and Fall Rate

0.0 ns/V

Delta (tDS)

Delta (tDH)

Unit

ps

Note

1-4

0

0.25 ns/V

+50

ps

1-4

0.5 ns/V

+100

ps

1-4

1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly

for rising transitions.

2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.

3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]

For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V

Using the table above, this would result in an increase in t DS and t DH of 100 ps.

4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each

device.

REV 1.1

13

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88ABG

256MB : 32M x 64

PC2700 Unbuffered DIMM

Package Dimensions

FRONT

133.35

5.250

128.93

5.076

θ 2.50

0.098

Detail A

Detail B

Side

BACK

3.18

0.125 MAX

1.27+/- 0.10

0.050 +/- 0.004

Detail A

Detail B

1.00 Width

0.039

6.35

0.250

1.80

0.071

1.27 Pitch

0.05

Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated.

Units: Millimeters (Inches)

REV 1.1

14

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256D64S88ABG

256MB : 32M x 64

PC2700 Unbuffered DIMM

Revision Log

Rev

1.0

1.1

Date

Modification

07/2002

08/2002

Official Release

Added tolerance specification of +/- 0.15 to Package Dimensions

REV 1.1

15

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.


型号：	NT256D64S88ABG
厂家：	ETC
描述：	184pin One Bank Unbuffered DDR SDRAM MODULE 184PIN一家银行无缓冲DDR SDRAM模块动态存储器双倍数据速率
文件：	总15页 (文件大小：838K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NT256D64S88ABG [ETC]

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