NT256D64S88B1G-5T [ETC]
184 pin Unbuffered DDR DIMM; 184针无缓冲DDR DIMM
| 型号： | NT256D64S88B1G-5T |
| 厂家： | 
ETC |
| 描述： | 184 pin Unbuffered DDR DIMM |
| 文件： | 总28页 (文件大小：358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
512MB, 256MB and 128MB
PC3200, PC2700 and PC2100
Unbuffered DDR DIMM
184 pin Unbuffered DDR DIMM
Based on DDR400/333/266 256M bit B Die device
Features
• 184 Dual In-Line Memory Module (DIMM)
• Unbuffered DDR DIMM based on 256M bit die B device,
organized as either 32Mbx8 or 16Mbx16
• Performance:
• DRAM DLL aligns DQ and DQS transitions with clock transitions
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM CAS Latency: 2, 2.5, 3
PC3200 PC2700 PC2100
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
Unit
Speed Sort
5T
3
6K
2.5
166
6
75B
2.5
DIMM CAS Latency
fCK Clock Frequency
tCK Clock Cycle
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 7.8 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect EEPROM
• Gold contacts
200
5
133
7.5
MHz
ns
fDQ DQ Burst Frequency
400
333
266
MHz
• Intended for 133, 166 and 200 MHz applications
• Inputs and outputs are SSTL-2 compatible
• VDD = VDDQ = 2.5V ± 0.2V (2.6V ± 0.1V for PC3200)
• SDRAMs have 4 internal banks for concurrent operation
• Differential clock inputs
• SDRAMs are packaged in TSOP packages
• “Green” packaging – lead free
• Data is read or written on both clock edges
Description
NT512D64S8HB0G, NT512D64S8HB1G, NT512D64S8HB1GY, NT512D72S8PB0G, NT256D64SH88B0G, NT256D64SH88B1G,
NT256D64SH88B1GY, NT256D72S89B0G and NT128D64SH4B1G are unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM
Dual In-Line Memory Modules (DIMM). NT512D64S8HB1GY and NT256D64SH88B1GY are packaged using lead free technology.
NT512D64S8HB0G, NT512D64S8HB1G and NT512D64S8HB1GY are 512MB modules organized as dual ranks using sixteen 32Mx8
TSOP devices. NT512D72S8PB0G has ECC and is organized as dual ranks using eighteen 32Mx8 TSOP devices. NT256D64SH88B0G,
NT256D64SH88B1G and NT256D64SH88B1GY are 256MB modules organized as single rank using eight 32Mx8 TSOP devices.
NT256D72S89B0G has ECC and is organized as single rank using nine 32Mx8 TSOP devices. NT128D64SH4B1G are 128MB modules,
organized as single rank using four 16Mx16 TSOP devices.
Depending on the speed grade, these DIMMs are intended for use in applications operating up to 200 MHz clock speeds and achieves
high-speed data transfer rates of up to 400 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation
type must be programmed into the DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) can be
accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC.
REV 2.2
Aug 3, 2004
Preliminary
1
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Ordering Information
Organization
Part Number
Speed
Power
Leads
NT512D72S8PB0G-5T
64Mx72
64Mx64
32Mx72
32Mx64
16Mx64
64Mx64
NT512D64S8HB1G-5T
NT512D64S8HB1GY-5T
(lead free)
PC3200 200MHz (5ns @ CL = 3)
3-3-3 166MHz (6ns @ CL = 2.5)
NT256D72S890G-5T
NT256D64S88B1G-5T
DDR400
2.6V
NT256D64S88B1GY-5T
(lead free)
NT128D64SH4B1G-5T
NT512D64S8HB1G-6K
Gold
NT512D64S8HB1GY-6K
(lead free)
PC2700 166MHz (6ns @ CL = 2.5)
2.5-3-3 133MHz (7.5ns @ CL = 2)
NT256D64S88B1GY-6K
(lead free)
DDR333
32Mx64
NT256D64S88B0G-6K
NT128D64SH4B1G-6K
NT512D64S8HB0G-75B
NT256D64S88B0G-75B
NT128D64SH4B1G-75B
2.5V
16Mx64
64Mx64
32Mx64
16Mx64
PC2100 133MHz (7.5ns @ CL = 2.5)
2.5-3-3 100MHz (10ns @ CL = 2)
DDR266B
For the closest sales office or information, please visit: www.nanya.com
Nanya Technology Corporation
Hwa Ya Technology Park 669
Fu Hsing 3rd Rd., Kueishan,
Taoyuan, 333, Taiwan, R.O.C.
Tel: +886-3-328-1688
REV 2.2
Aug 3, 2004
Preliminary
2
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Pin Description
CK0, CK1, CK2,
Differential Clock Inputs.
DQ0-DQ63
Data input/output
CK0, CK1, CK2
CKE0, CKE1
RAS
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
DQS0-DQS7
DM0-DM7
Bidirectional data strobes
Input Data Mask
CAS
VDD
VDDQ
VSS
Power
WE
Supply voltage for DQs
S0, S1
A0-A9, A11, A12
A10/AP
Chip Selects
Ground
Address Inputs
NC
No Connect
Address Input/Auto-precharge
SDRAM Bank Address Inputs
Ref. Voltage for SSTL_2 inputs
VDD Identification flag.
SCL
SDA
SA0-2
VDDSPD
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address Inputs
Serial EEPROM positive power supply
BA0, BA1
VREF
VDDID
Pinout
Pin Front
Pin Back
Pin Front
32 A5
Pin Back
Pin Front
62 VDDQ
63 WE
Pin Back
154 RAS
1
2
3
4
5
6
7
8
9
VREF
DQ0
VSS
93 VSS
124 VSS
94 DQ4
33 DQ24
34 VSS
35 DQ25
36 DQS3
37 A4
125 A6
155 DQ45
156 VDDQ
157 S0
95 DQ5
126 DQ28
127 DQ29
128 VDDQ
129 DM3/DQS12
130 A3
64 DQ41
65 CAS
66 VSS
DQ1
DQS0
DQ2
VDD
96 VDDQ
97 DM0/DQS9
98 DQ6
158 S1
67 DQS5
68 DQ42
69 DQ43
70 VDD
159 DM5/DQS14
160 VSS
99 DQ7
38 VDD
39 DQ26
40 DQ27
41 A2
DQ3
NC
100 VSS
131 DQ30
132 VSS
161 DQ46
162 DQ47
163 NC
101 NC
10 NC
102 NC
133 DQ31
134 NC
71 NC
11 VSS
103 NC
42 VSS
43 A1
72 DQ48
73 DQ49
74 VSS
164 VDDQ
165 DQ52
166 DQ53
167 NC
12 DQ8
13 DQ9
14 DQS1
15 VDDQ
16 CK1
17 CK1
18 VSS
104 VDDQ
105 DQ12
106 DQ13
107 DM1/DQS10
108 VDD
135 NC
44 NC
45 NC
46 VDD
47 NC
48 A0
136 VDDQ
137 CK0
138 CK0
139 VSS
75 CK2
76 CK2
77 VDDQ
78 DQS6
79 DQ50
80 DQ51
81 VSS
168 VDD
169 DM6/DQS15
170 DQ54
171 DQ55
172 VDDQ
173 NC
109 DQ14
110 DQ15
111 CKE1
112 VDDQ
113 NC
140 NC
49 NC
50 VSS
51 NC
52 BA1
141 A10
142 NC
19 DQ10
20 DQ11
21 CKE0
22 VDDQ
23 DQ16
24 DQ17
25 DQS2
26 VSS
143 VDDQ
144 NC
82 VDDID
83 DQ56
84 DQ57
85 VDD
174 DQ60
175 DQ61
176 VSS
114 DQ20
115 A12
KEY
KEY
53 DQ32
54 VDDQ
55 DQ33
56 DQS4
57 DQ34
58 VSS
145 VSS
116 VSS
146 DQ36
147 DQ37
148 VDD
177 DM7/DQS16
178 DQ62
179 DQ63
180 VDDQ
181 SA0
117 DQ21
118 A11
86 DQS7
87 DQ58
88 DQ59
89 VSS
27 A9
119 DM2/DQS11
120 VDD
149 DM4/DQS13
150 DQ38
151 DQ39
152 VSS
28 DQ18
29 A7
121 DQ22
122 A8
59 BA0
90 WP
182 SA1
30 VDDQ
31 DQ19
60 DQ35
61 DQ40
91 SDA
92 SCL
183 SA2
123 DQ23
153 DQ44
184 VDDSPD
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
REV 2.2
Aug 3, 2004
Preliminary
3
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Input/Output Functional Description
Function
Symbol
Type
Polarity
The system clock inputs. All address and command lines are sampled on the cross point of
the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven
from the clock inputs and output timing for read operations is synchronized to the input
clock.
CK0, CK1, CK2,
Cross
point
(SSTL)
CK0, CK1, CK2
Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh
mode.
Active
High
CKE0, CKE1
(SSTL)
(SSTL)
Enables the associated DDR SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is
selected by S1.
Active
Low
S0, S1
When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to
be executed by the SDRAM.
Active
Low
RAS, CAS, WE
VREF
(SSTL)
Supply
Supply
(SSTL)
Reference voltage for SSTL-2 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
VDDQ
BA0, BA1
-
-
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high,
auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low,
auto-precharge is disabled.
A0 - A9
A10/AP
A11, A12
(SSTL)
(SSTL)
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
DQ0 - DQ63
-
Data strobes: Output with read data, input with write data. Edge aligned with read data,
DQS0 - DQS7,
DQS9 – DQS16
Active
High
(SSTL)
(SSTL)
centered on write data. Used to capture write data.
Data Check Bit Input/Output pins. Used on ECC modules and is not used on x64 modules.
The data write masks, associated with one data byte. In Write mode, DM operates as a byte
CB0 – CB7
-
Active mask by allowing input data to be written if it is low but blocks the write operation if it is high.
High In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is
not used on x64 modules.
DM0 – DM8
Input
VDD, VSS
Supply
Power and ground for the DDR SDRAM input buffers and core logic
Address inputs. Connected to either VDD or VSS on the system board to configure the Serial
SA0 – SA2
-
Presence Detect EEPROM address.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
SDA
-
must be connected from the SDA bus line to V DD to act as a pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
SCL
-
connected from the SCL bus time to V DD to act as a pull-up.
Serial EEPROM positive power supply.
VDDSPD
Supply
REV 2.2
4
Aug 3, 2004
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Functional Block Diagram
2 Ranks, 16 devices, 32Mx8 DDR SDRAMs
S1
S0
DQS0
DQS4
DM0/DQS9
DM4/DQS13
DM
DM
DM
DM
CS
DQS
DQS
DQS
DQS
CS
DQS
DQS
DQS
DQS
CS
DQS
DQS
DQS
DQS
CS
DQS
DQS
DQS
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
D0
D8
D4
I/O 7 D12
I/O 2
I/O 3
I/O 4
I/O 5
DQS1
DQS5
DM1/DQS10
DM5/DQS14
DM
DM
DM
DM
CS
CS
CS
CS
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
D9
D5
I/O 7 D13
I/O 2
I/O 3
I/O 4
I/O 5
DQS2
DQS6
DM2/DQS11
DM6/DQS15
DM CS
I/O 7
DM CS
I/O 7
DM
DM
CS
CS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 6
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D10
I/O 7 D14
I/O 2
D2
D6
I/O 3
I/O 4
I/O 5
DQS3
DQS7
DM3/DQS12
DM7/DQS16
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
CS
CS
CS
CS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 6
I/O 0
I/O 1
I/O 6
D3
I/O 7 D11
I/O 2
D7
I/O 7 D15
I/O 2
I/O 3
I/O 3
I/O 4
I/O 4
I/O 5
I/O 5
BA0-BA1
A0-A13
RAS
BA0-BA1 : SDRAMs D0-D15
A0-A13 : SDRAMs D0-D15
RAS : SDRAMs D0-D15
CAS : SDRAMs D0-D15
CKE : SDRAMs D0-D7
CKE : SDRAMs D8-D15
WE : SDRAMs D0-D15
VDDSPD
SPD
* Clock Wiring
Clock Input
*CK0/CK0
*CK1/CK1
*CK2/CK2
SDRAMs
4 SDRAMs
6 SDRAMs
6 SDRAMs
VDD/VDDQ
VREF
D0-D15
D0-D15
D0-D15
VSS
CAS
VDDID
* Wire per Clock Loading Table/
Wiring Diagrams
Strap: see Note 4
CKE0
CKE1
WE
Serial PD
A1
SCL
WP
SDA
A0
SA0
A2
Notes :
SA1 SA2
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. VDDID strap connections (for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD is not equal to VDDQ
.
REV 2.2
5
Aug 3, 2004
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Functional Block Diagram
1 Rank, 8 devices, 32Mx8 DDR SDRAMs
S0
DQS0
DQS4
DM0/DQS9
DM4/DQS13
DQS
DQS
DQS
DQS
DM
DQS
DQS
DQS
DQS
DM
CS
CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D0
D4
DQS1
DQS5
DM1/DQS10
DM5/DQS14
DM
DM
CS
CS
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
D5
DQS2
DQS6
DM2/DQS11
DM6/DQS15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
CS
CS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D6
D2
DQS3
DQS7
DM3/DQS12
DM7/DQS16
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
CS
CS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D3
D7
BA0-BA1
A0-A13
RAS
BA0-BA1 : SDRAMs D0-D7
A0-A13 : SDRAMs D0-D7
RAS : SDRAMs D0-D7
CAS : SDRAMs D0-D7
CKE : SDRAMs D0-D7
WE : SDRAMs D0-D7
* Clock Wiring
Clock Input
*CK0/CK0
*CK1/CK1
*CK2/CK2
SDRAMs
2 SDRAMs
3 SDRAMs
3 SDRAMs
CAS
* Wire per Clock Loading Table/
Wiring Diagrams
CKE0
WE
VDDSPD
VDD/VDDQ
VREF
SPD
Serial PD
D0-D7
D0-D7
D0-D7
SCL
WP
SDA
A0
A1
A2
VSS
VDDID
SA0
SA1 SA2
Strap: see Note 4
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. VDDID strap connections (for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD is not equal to VDDQ
.
REV 2.2
6
Aug 3, 2004
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Functional Block Diagram
1 Rank, 4 devices, 16Mx16 DDR SDRAMs
S0
CS
CS
LDQS
LDQS
DQS1
DM1/DQS10
DQ8
DQS5
DM5/DQS14
DQ40
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
DQ9
DQ41
DQ10
DQ42
DQ11
DQ43
DQ12
DQ44
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
D0
D2
UDQS
UDQS
DQS0
DM0/DQS9
DQ0
DQS4
DM4/DQS13
DQ32
UDM
I/O 8
UDM
I/O 8
I/O 10
I/O 10
DQ1
DQ33
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
DQ34
DQ2
DQ3
DQ35
DQ4
DQ36
DQ5
DQ37
DQ6
DQ38
DQ7
DQ39
CS
CS
LDQS
LDQS
DQS3
DM3/DQS12
DQ24
DQS7
DM7/DQS16
DQ56
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
D1
D3
UDQS
UDQS
DQS2
DM2/DQS11
DQ16
DQS6
DM6/DQS15
DQ48
UDM
I/O 8
UDM
I/O 8
I/O 10
I/O 10
DQ17
DQ49
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
DQ18
DQ50
DQ19
DQ51
DQ20
DQ52
DQ21
DQ53
DQ22
DQ54
DQ23
DQ55
BA0-BA1
A0-A13
RAS
BA0-BA1 : SDRAMs D0-D3
A0-A13 : SDRAMs D0-D3
RAS : SDRAMs D0-D3
CAS : SDRAMs D0-D3
CKE : SDRAMs D0-D3
WE : SDRAMs D0-D3
* Clock Wiring
Clock Input SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
NC
2 SDRAMs
2 SDRAMs
CAS
* Wire per Clock Loading Table/
Wiring Diagrams
CKE0
WE
VDDSPD
VDD/VDDQ
VREF
SPD
Serial PD
D0-D3
D0-D3
D0-D3
SCL
WP
SDA
A0
A1
A2
VSS
VDDID
SA0
SA1 SA2
Strap: see Note 4
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. VDDID strap connections (for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD is not equal to VDDQ
.
REV 2.2
7
Aug 3, 2004
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Functional Block Diagram
2 Ranks, 18 devices (ECC), 32Mx8 DDR SDRAMs
S1
S0
DQS0
DQS4
DM0/DQS9
DM4/DQS13
DM
DM
DM
DM
CS
DQS
DQS
DQS
DQS
DQS
CS
DQS
DQS
DQS
DQS
DQS
CS
DQS
DQS
DQS
DQS
CS
DQS
DQS
DQS
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
D0
D9
D4
I/O 7 D13
I/O 2
I/O 3
I/O 4
I/O 5
DQS1
DQS5
DM1/DQS10
DM5/DQS14
DM
DM
DM
DM
CS
CS
CS
CS
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
D10
D5
I/O 7 D14
I/O 2
I/O 3
I/O 4
I/O 5
DQS2
DQS6
DM2/DQS11
DM6/DQS15
DM
DM
DM
DM
CS
CS
CS
CS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
D2
D11
D6
I/O 7 D15
I/O 2
I/O 3
I/O 4
I/O 5
DQS3
DQS7
DM3/DQS12
DM7/DQS16
DM
DM
DM
DM
CS
CS
CS
CS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
D3
D12
D7
I/O 7 D16
I/O 2
I/O 3
I/O 4
I/O 5
DQS8
DM8/DQS17
VDDSPD
VDD/VDDQ
VREF
SPD
* Clock Wiring
Clock Input
*CK0/CK0
*CK1/CK1
*CK2/CK2
SDRAMs
6 SDRAMs
6 SDRAMs
6 SDRAMs
D0-D8
D0-D8
D0-D8
DM
DM
CS
CS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
VSS
VDDID
* Wire per Clock Loading Table/
Wiring Diagrams
Strap: see Note 4
D8
D17
Serial PD
SCL
WP
SDA
A0
A1
A2
SA0
SA1 SA2
Notes :
BA0-BA1
BA0-BA1 : SDRAMs D0-D17
A0-A13 : SDRAMs D0-D17
RAS : SDRAMs D0-D17
CAS : SDRAMs D0-D17
CKE : SDRAMs D0-D8
CKE : SDRAMs D9-D17
WE : SDRAMs D0-D17
1. DQ-to-I/O wring may be changed within a byte.
A0-A13
RAS
2. DQ/DQS/DM/CKE/S relationships are maintained as shown.
3. DQ/DQS/DM/DQS resistors are 22 Ohms.
4. VDDID strap connections (for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
CAS
STRAP IN (VSS): VDD is not equal to VDDQ
.
CKE0
CKE1
WE
REV 2.2
8
Aug 3, 2004
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Functional Block Diagram
1 Rank, 9 devices (ECC), 32Mx8 DDR SDRAMs
S0
DQS0
DQS4
DM0/DQS9
DM4/DQS13
DM
DQS
DQS
DQS
DQS
DQS
DM
DQS
DQS
DQS
DQS
CS
CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D0
D4
DQS1
DQS5
DM1/DQS10
DM5/DQS14
DM
DM
CS
CS
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
D5
DQS2
DQS6
DM2/DQS11
DM6/DQS15
DM
DM
CS
CS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D2
D6
DQS3
DQS7
DM3/DQS12
DM7/DQS16
DM
DM
CS
CS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D3
D7
DQS8
Serial PD
A1
DM8/DQS17
SCL
SDA
DM
CS
A0
A2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
WP
SA0
SA1 SA2
D8
VDDSPD
VDD/VDDQ
VREF
SPD
* Clock Wiring
Clock Input
SDRAMs
3 SDRAMs
3 SDRAMs
3 SDRAMs
D0-D8
D0-D8
D0-D8
*CK0/CK0
*CK1/CK1
*CK2/CK2
VSS
VDDID
* Wire per Clock Loading Table/
Wiring Diagrams
Strap: see Note 4
BA0-BA1
BA0-BA1 : SDRAMs D0-D8
A0-A13 : SDRAMs D0-D8
RAS : SDRAMs D0-D8
CAS : SDRAMs D0-D8
CKE : SDRAMs D0-D8
WE : SDRAMs D0-D8
Notes :
A0-A13
RAS
1. DQ-to-I/O wring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships are maintained as shown.
3. DQ/DQS/DM/DQS resistors are 22 Ohms.
4. VDDID strap connections (for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
CAS
CKE0
WE
STRAP IN (VSS): VDD is not equal to VDDQ
.
REV 2.2
Aug 3, 2004
Preliminary
9
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Serial Presence Detect
SPD Description
Byte
0
Description
Byte
26
27
28
29
30
31
32
33
34
Description
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Maximum Data Access Time from Clock at CL=1
1
Minimum Row Precharge Time (tRP
Minimum Row Active to Row Active delay (tRRD
Minimum RAS to CAS delay (tRCD
)
2
)
3
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Rank
)
4
Minimum RAS Pulse Width (tRAS
Module Bank Density
)
5
6
Data Width of Assembly
Address and Command Setup Time Before Clock
Address and Command Hold Time After Clock
Data Input Setup Time Before Clock
7
Data Width of Assembly (cont’)
Voltage Interface Level of this Assembly
DDR SDRAM Device Cycle Time
CL=2.5
8
9
35
Data Input Hold Time After Clock
Reserved
DDR SDRAM Device Access Time from Clock
CL=2.5
10
11
12
36-40
41
DIMM Configuration Type
Minimum Active/Auto-refresh Time (tRC
Auto-refresh to Active/Auto-refresh Command Period
(tRFC
Max Cycle Time (tCK max
Maximum DQS-DQ Skew Time (tDQSQ
)
Refresh Rate/Type
42
)
13
14
Primary DDR SDRAM Width
43
44
)
Error Checking DDR SDRAM Device Width
DDR SDRAM Device Attr: Min CLK Delay, Random Col
Access
)
15
16
17
18
45
46-61
62
Maximum Read Data Hold Skew Factor (tQHS)
DDR SDRAM Device Attributes: Burst Length
Supported
Reserved
DDR SDRAM Device Attributes: Number of Device
Banks
SPD Revision
Checksum Data
DDR SDRAM Device Attributes:
CAS Latencies Supported
63
19
20
21
22
DDR SDRAM Device Attributes: CS Latency
DDR SDRAM Device Attributes: WE Latency
DDR SDRAM Device Attributes:
DDR SDRAM Device Attributes: General
64-71
72
Manufacturer’s JEDEC ID Code
Module Manufacturing Location
Module Part number
73-90
91-92
Module Revision Code
Module Manufacturing Data
yy= Binary coded decimal year code, 0-99(Decimal),
Minimum Clock Cycle
CL=2.5
23
93-94
00-63(Hex)
ww= Binary coded decimal year code, 01-52(Decimal),
01-34(Hex)
Maximum Data Access Time from Clock at
CL=2
24
25
95-98
Module Serial Number
Reserved
Minimum Clock Cycle Time at CL=1
99-127
REV 2.2
Aug 3, 2004
Preliminary
10
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
SPD Values for NT512D64S8HBxGx
PC3200 (5T)
Value
PC2700 (6K)
Value
PC2100 (75B)
Value
Byte
Hex
80
Hex
80
Hex
80
0
1
128
256
128
256
128
256
08
08
08
2
SDRAM DDR
13
07
SDRAM DDR
13
07
SDRAM DDR
13
07
3
0D
0A
02
0D
0A
02
0D
0A
02
4
10
10
10
5
2
2
2
6
x64
40
x64
40
x64
40
7
x64
00
x64
00
x64
00
8
SSTL 2.5V
5.0ns
04
SSTL 2.5V
6.0ns
04
SSTL 2.5V
7.5ns
04
9
50
60
75
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-40
41
42
43
44
45
46-61
62
63
6.0ns
60
7.0ns
70
7.5ns
75
Non-Parity
SR/1x(7.8us)
x8
00
Non-Parity
SR/1x(7.8us)
x8
00
Non-Parity
SR/1x(7.8us)
x8
00
82
82
82
08
08
08
N/A
00
N/A
00
N/A
00
1 Clock
2,4,8
01
1 Clock
2,4,8
01
1 Clock
2,4,8
01
0E
04
0E
04
0E
04
4
4
4
2/2.5/3
0
1C
01
2/2.5
0C
01
2/2.5
0C
01
0
0
1
02
1
02
1
02
Differential Clock
±0.1V Tolerance
6ns
20
Differential Clock
±0.2V Tolerance
7.5ns
20
Differential Clock
±0.2V Tolerance
10ns
20
00
00
00
60
75
A0
75
0.70ns
7.5ns
70
0.70ns
N/A
70
0.75ns
N/A
75
00
00
7.5ns
75
N/A
00
N/A
00
15ns
3C
28
18ns
48
20ns
50
10ns
12ns
30
15ns
3C
50
15ns
3C
28
18ns
48
20ns
40ns
42ns
2A
40
45ns
2D
40
256MB
0.60ns
0.60ns
0.40ns
0.40ns
Reserved
55ns
40
256MB
0.75ns
0.75ns
0.45ns
0.45ns
Reserved
60ns
256MB
0.90ns
0.90ns
0.50ns
0.50ns
Reserved
65ns
60
75
90
60
75
90
40
45
50
40
45
50
00
00
00
37
3C
48
41
70ns
46
72ns
75ns
4B
30
8ns
20
12ns
30
12ns
0.4ns
28
0.4ns
28
0.5ns
32
0.50ns
Reserved
Initial
50
0.55ns
Reserved
Initial
55
0.75ns
Reserved
Initial
75
00
00
00
00
00
00
Checksum
8F
7F7F7F0B
Checksum
3C
7F7F7F0B
Checksum
23
7F7F7F0B
64-71
NANYA
NANYA
NANYA
00000000
00000000
00000000
72
Assembly
Module PN
--
--
--
--
--
--
Assembly
Module PN
--
--
--
--
--
--
Assembly
Module PN
--
--
--
--
--
--
73-90
91-92
93-94
95-98
99-127
Revision
Revision
Revision
Year/Week Code
Serial Number
Reserved
Year/Week Code
Serial Number
Reserved
Year/Week Code
Serial Number
Reserved
REV 2.2
Aug 3, 2004
Preliminary
11
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
SPD Values for NT256D64S88BxGx
PC3200 (5T)
Value
PC2700 (6K)
Value
PC2100 (75B)
Value
Byte
Hex
80
Hex
80
Hex
80
0
1
128
256
128
256
128
256
08
08
08
2
SDRAM DDR
13
07
SDRAM DDR
13
07
SDRAM DDR
13
07
3
0D
0A
01
0D
0A
01
0D
0A
01
4
10
10
10
5
1
1
1
6
x64
40
x64
40
x64
40
7
x64
00
x64
00
x64
00
8
SSTL 2.5V
5.0ns
04
SSTL 2.5V
6.0ns
04
SSTL 2.5V
7.5ns
04
9
50
60
75
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-40
41
42
43
44
45
46-61
62
63
6.0ns
60
7.0ns
70
7.5ns
75
Non-Parity
SR/1x(7.8us)
x8
00
Non-Parity
SR/1x(7.8us)
x8
00
Non-Parity
SR/1x(7.8us)
x8
00
82
82
82
08
08
08
N/A
00
N/A
00
N/A
00
1 Clock
2,4,8
01
1 Clock
2,4,8
01
1 Clock
2,4,8
01
0E
04
0E
04
0E
04
4
4
4
2.5/3
18
2/2.5
0C
01
2/2.5
0C
01
0
01
0
0
1
02
1
02
1
02
Differential Clock
±0.1V Tolerance
5ns
20
Differential Clock
±0.2V Tolerance
7.5ns
20
Differential Clock
±0.2V Tolerance
10ns
20
00
00
00
50
75
A0
75
0.60ns
N/A
60
0.70ns
N/A
70
0.75ns
N/A
00
00
00
N/A
00
N/A
00
N/A
00
15ns
3C
28
18ns
48
20ns
50
10ns
12ns
30
15ns
3C
50
15ns
3C
28
18ns
48
20ns
40ns
42ns
2A
40
45ns
2D
40
256MB
0.60ns
0.60ns
0.40ns
0.40ns
Reserved
60ns
40
256MB
0.75ns
0.75ns
0.45ns
0.45ns
Reserved
60ns
256MB
0.90ns
0.90ns
0.50ns
0.50ns
Reserved
60ns
60
75
90
60
75
90
40
45
50
40
45
50
00
00
00
3C
48
3C
48
3C
48
72ns
72ns
72ns
12ns
30
12ns
30
12ns
30
0.4ns
28
0.4ns
28
0.4ns
28
0.55ns
Reserved
Initial
55
0.55ns
Reserved
Initial
55
0.55ns
Reserved
Initial
55
00
00
00
00
00
00
Checksum
9C
7F7F7F0B
Checksum
3B
7F7F7F0B
Checksum
F0
7F7F7F0B
64-71
NANYA
NANYA
NANYA
00000000
00000000
00000000
72
Assembly
Module PN
--
--
--
--
--
--
Assembly
Module PN
--
--
--
--
--
--
Assembly
Module PN
--
--
--
--
--
--
73-90
91-92
93-94
95-98
99-127
Revision
Revision
Revision
Year/Week Code
Serial Number
Reserved
Year/Week Code
Serial Number
Reserved
Year/Week Code
Serial Number
Reserved
REV 2.2
Aug 3, 2004
Preliminary
12
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
SPD Values for NT128D64SH4B1G
PC3200 (5T)
Value
PC2700 (6K)
Value
PC2100 (75B)
Value
Byte
Hex
80
Hex
80
Hex
80
0
1
128
256
128
256
128
256
08
08
08
2
SDRAM DDR
13
07
SDRAM DDR
13
07
SDRAM DDR
13
07
3
0D
09
0D
09
0D
09
4
9
9
9
5
1
01
1
01
1
01
6
x64
40
x64
40
x64
40
7
x64
00
x64
00
x64
00
8
SSTL 2.5V
5.0ns
04
SSTL 2.5V
6.0ns
04
SSTL 2.5V
7.5ns
04
9
50
60
75
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-40
41
42
43
44
45
46-61
62
63
6.0ns
60
7.0ns
70
7.5ns
75
Non-Parity
SR/1x(7.8us)
x16
00
Non-Parity
SR/1x(7.8us)
x16
00
Non-Parity
SR/1x(7.8us)
x16
00
82
82
82
10
10
10
N/A
00
N/A
00
N/A
00
1 Clock
2,4,8
01
1 Clock
2,4,8
01
1 Clock
2,4,8
01
0E
04
0E
04
0E
04
4
4
4
2.5/3
18
2/2.5
0C
01
2/2.5
0C
01
0
01
0
0
1
02
1
02
1
02
Differential Clock
±0.1V Tolerance
5ns
20
Differential Clock
±0.2V Tolerance
7.5ns
20
Differential Clock
±0.2V Tolerance
10ns
20
00
00
00
50
75
A0
75
0.60ns
N/A
60
0.70ns
N/A
70
0.75ns
N/A
00
00
00
N/A
00
N/A
00
N/A
00
15ns
3C
28
18ns
48
20ns
50
10ns
12ns
30
15ns
3C
50
15ns
3C
28
18ns
48
20ns
40ns
42ns
2A
20
45ns
2D
20
128MB
0.60ns
0.60ns
0.40ns
0.40ns
Reserved
60ns
20
128MB
0.75ns
0.75ns
0.45ns
0.45ns
Reserved
60ns
128MB
0.90ns
0.90ns
0.50ns
0.50ns
Reserved
60ns
60
75
90
60
75
90
40
45
50
40
45
50
00
00
00
3C
48
3C
48
3C
48
72ns
72ns
72ns
12ns
30
12ns
30
12ns
30
0.4ns
28
0.4ns
28
0.4ns
28
0.55ns
Reserved
Initial
55
0.55ns
Reserved
Initial
55
0.55ns
Reserved
Initial
55
00
00
00
00
00
00
Checksum
83
Checksum
22
Checksum
D7
7F7F7F0B
7F7F7F0B
7F7F7F0B
64-71
NANYA
NANYA
NANYA
00000000
00000000
00000000
72
Assembly
Module PN
--
--
--
--
--
--
Assembly
Module PN
--
--
--
--
--
--
Assembly
Module PN
--
--
--
--
--
--
73-90
91-92
93-94
95-98
99-127
Revision
Revision
Revision
Year/Week Code
Serial Number
Reserved
Year/Week Code
Serial Number
Reserved
Year/Week Code
Serial Number
Reserved
REV 2.2
Aug 3, 2004
Preliminary
13
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
SPD Values for NT512D72S8PB0G
PC3200 (5T)
Byte
Value
128
Hex
80
0
1
256
08
2
SDRAM DDR
13
07
3
0D
0A
02
4
10
5
2
6
x74
48
7
x74
00
8
SSTL 2.5V
5.0ns
04
9
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-40
41
42
43
44
45
46-61
62
63
6.0ns
60
Parity
SR/1x(7.8us)
x8
02
82
08
ECC Width
1 Clock
2,4,8
08
01
0E
04
4
2.5/3
18
0
01
1
02
Differential Clock
±0.1V Tolerance
5ns
20
00
50
0.60ns
N/A
60
00
N/A
00
15ns
3C
28
10ns
15ns
3C
28
40ns
256MB
0.60ns
0.60ns
0.40ns
0.40ns
Reserved
60ns
40
60
60
40
40
00
3C
48
72ns
12ns
30
0.4ns
28
0.55ns
Reserved
Initial
55
00
00
Checksum
AF
7F7F7F0B
64-71
NANYA
00000000
72
Assembly
Module PN
--
--
--
--
--
--
73-90
91-92
93-94
95-98
99-127
Revision
Year/Week Code
Serial Number
Reserved
REV 2.2
Aug 3, 2004
Preliminary
14
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
SPD Values for NT256D72S89B0G
PC3200 (5T)
Byte
Value
128
Hex
80
0
1
256
08
2
SDRAM DDR
13
07
3
0D
0A
01
4
10
5
1
6
x72
48
7
x72
00
8
SSTL 2.5V
5.0ns
04
9
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-40
41
42
43
44
45
46-61
62
63
6.0ns
60
Parity
SR/1x(7.8us)
x8
02
82
08
ECC Width
1 Clock
2,4,8
08
01
0E
04
4
2.5/3
18
0
01
1
02
Differential Clock
±0.1V Tolerance
5ns
20
00
50
0.60ns
N/A
60
00
N/A
00
15ns
3C
28
10ns
15ns
3C
28
40ns
256MB
0.60ns
0.60ns
0.40ns
0.40ns
Reserved
60ns
40
60
60
40
40
00
3C
48
72ns
12ns
30
0.4ns
28
0.55ns
Reserved
Initial
55
00
00
Checksum
AE
7F7F7F0B
64-71
NANYA
00000000
72
Assembly
Module PN
--
--
--
--
--
--
73-90
91-92
93-94
95-98
99-127
Revision
Year/Week Code
Serial Number
Reserved
REV 2.2
Aug 3, 2004
Preliminary
15
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Absolute Maximum Ratings
Symbol
VIN, VOUT
VIN
Parameter
Voltage on I/O pins relative to VSS
Rating
-0.5 to VDDQ +0.5
-0.5 to +3.6
-0.5 to +3.6
-0.5 to +3.6
0 to +70
Units
V
Voltage on Input relative to VSS
V
VDD
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating Temperature (Ambient)
Storage Temperature (Plastic)
V
VDDQ
TA
V
°C
°C
W
TSTG
PD
-55 to +150
1
Power Dissipation (per device component)
Short Circuit Output Current
IOUT
50
mA
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is stress
rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics and Operating Conditions
TA= 0°C ~ 70°C; VDDQ= VDD= 2.5V±0.2V(PC2100,PC2700); TA= 0°C ~ 70°C; VDDQ= VDD= 2.6V±0.1V(PC3200)
Symbol
VDD
Parameter
Min
2.3
Max
2.7
Units
V
Notes
1
Supply Voltage
PC2100, PC2700
PC3200
2.5
I/O Supply Voltage
PC2100, PC2700
PC3200
2.3
VDDQ
2.7
V
1
2.5
VSS, VSSQ
VREF
Supply Voltage, I/O Supply Voltage
I/O Reference Voltage
0
0
V
V
V
V
V
V
V
0.49 x VDDQ
VREF – 0.04
VREF + 0.15
-0.3
0.51 x VDDQ
VREF + 0.04
VDDQ + 0.3
VREF - 0.15
VDDQ + 0.3
VDDQ + 0.6
1, 2
1, 3
1
VTT
I/O Termination Voltage (System)
Input High (Logic1) Voltage
VIH (DC)
VIL (DC)
VIN (DC)
VID (DC)
Input Low (Logic0) Voltage
1
Input Voltage Level, CK and CK Inputs
-0.3
1
Input Differential Voltage, CK and CK Inputs
0.30
1, 4
Input Leakage Current
II
Any input 0V ≤ VIN ≤ VDD
;
-10
-10
10
10
µA
µA
1
1
All other pins not under test = 0V
Output Leakage Current
IOZ
DQs are disabled; 0V ≤ Vout ≤ VDDQ
Output High Current
IOH
-16.8
16.8
-
-
mA
mA
1
1
(VOUT = VDDQ -0.373V, min VREF, min VTT
Output Low Current
)
IOL
(VOUT = 0.373, max VREF, max VTT
)
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak
noise on VREF may not exceed 2% of the DC value.
3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF
and must track variations in the DC level of VREF
4. VID is the magnitude of the difference between the input level on CK and the input level on CK.
,
.
REV 2.2
Aug 3, 2004
Preliminary
16
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
AC Characteristics
Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating
Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to VSS
.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the
related specifications and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to
the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions.
The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified.
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the
signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW
(HIGH) level.
AC Output Load Circuits
V
TT
50 ohms
Output
Timing Reference Point
V
OUT
30 pF
AC Operating Conditions
TA = 0 °C ~ 70 °C; VDDQ= VDD= 2.5V ± 0.2V (PC2100/PC2700); VDDQ= VDD= 2.6V ± 0.1V (PC3200)
Symbol
VIH (AC)
VIL (AC)
VID (AC)
VIX (AC)
Parameter/Condition
Input High (Logic 1) Voltage.
Min
Max
Unit
V
Notes
1, 2
VREF + 0.31
Input Low (Logic 0) Voltage.
VREF - 0.31
VDDQ + 0.6
V
1, 2
Input Differential Voltage, CK and CK Inputs
Input Differential Pair Cross Point Voltage, CK and CK Inputs
0.62
V
1, 2, 3
1, 2, 4
(0.5* VDDQ) - 0.2
(0.5* VDDQ) + 0.2
V
1. Input slew rate = 1V/ ns.
2. Inputs are not recognized as valid until VREF stabilizes.
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
REV 2.2
Aug 3, 2004
Preliminary
17
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Operating, Standby, and Refresh Currents
TA = 0 °C ~ 70 °C; VDDQ= VDD= 2.5V ± 0.2V (PC2100/PC2700); VDDQ= VDD= 2.6V ± 0.1V (PC3200)
Symbol
Parameter/Condition
Notes
1,2
Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per
clock cycle; address and control inputs changing once per clock cycle
IDD0
Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and
control inputs changing once per clock cycle
1,2
1,2
1,2
1,2
1,2
IDD1
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤ VIL (MAX); tCK = tCK (MIN)
IDD2P
IDD2N
IDD3P
IDD3N
Idle Standby Current: CS ≥ VIH (MIN); all banks idle; CKE ≥ VIH (MIN); tCK = tCK (MIN); address and control inputs changing once
per clock cycle
Active Power-Down Standby Current: one bank active; power-down mode; CKE ≤ VIL (MAX); tCK = tCK (MIN)
Active Standby Current: one bank; active/precharge; CS ≥ VIH (MIN); CKE ≥ VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and
DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle
Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle;
DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA
1,2
1,2
IDD4R
IDD4W
Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle;
DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN)
Auto-Refresh Current: tRC = tRFC (MIN)
1,2,3
1,2
IDD5
IDD6
Self-Refresh Current: CKE ≤ 0.2V
Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of
data changing at every transfer; tRC = tRC (min); IOUT = 0mA.
1,2
IDD7
1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate = 1V/ ns.
3. Current at 7.8 µs is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 µs.
All IDD current values are calculated from device level.
REV 2.2
Aug 3, 2004
Preliminary
18
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
NT512D64S8HB1Gx
NT256D64S88B1Gx
NT128D64SH4B1G
Symbol PC3200 PC2700 PC2100 PC3200
PC2700 PC2100 PC3200 PC2700 PC2100
(5T)
(6K)
(75B)
(5T)
(6K)
(75B)
(5T)
(6K)
(75B)
1915
1755
1585
995
915
825
460
420
380
IDD0
1995
340
1995
340
1825
340
1035
180
1035
180
945
180
480
80
480
80
440
80
IDD1
IDD2P
IDD2N
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
765
765
680
405
405
360
180
84
180
84
160
72
357
357
306
189
189
162
1275
3275
3195
3675
51
1275
3275
3195
2875
51
1105
2705
2625
2785
51
675
675
585
300
800
780
900
12
300
800
780
700
12
260
660
640
680
12
1675
1635
1875
27
1675
1635
1475
27
1385
1345
1425
27
IDD6
5275
5275
4065
2675
2675
2065
1300
1300
1000
IDD7
NT512D72S8PB0G
NT256256D64S89B0G
Symbol PC3200 PC2700 PC2100 PC3200
PC2700 PC2100
(5T)
(6K)
(75B)
(5T)
(6K)
(75B)
1915
1755
1585
995
915
825
IDD0
1995
340
1995
340
1825
340
1035
180
1035
180
945
180
IDD1
IDD2P
IDD2N
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
765
765
680
405
405
360
357
357
306
189
189
162
1275
3275
3195
3675
51
1275
3275
3195
2875
51
1105
2705
2625
2785
51
675
675
585
1675
1635
1875
27
1675
1635
1475
27
1385
1345
1425
27
IDD6
5275
5275
4065
2675
2675
2065
IDD7
REV 2.2
Aug 3, 2004
Preliminary
19
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
TA = 0 °C ~ 70 °C; VDDQ= VDD= 2.5V ± 0.2V (PC2100/PC2700); VDDQ= VDD= 2.6V ± 0.1V (PC3200) (Part 1 of 2)
5T
6K
75B
Symbol
Parameter
Unit
Notes
PC3200
PC2700
PC2100
Min.
Max.
+0.65
+0.55
0.55
0.55
8
Min.
Max.
+0.7
+0.7
0.55
0.55
-
Min.
Max.
+0.75
+0.75
0.55
0.55
-
tAC
tDQSCK
tCH
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
-0.65
-0.55
0.45
0.45
5
-0.7
-0.7
0.45
0.45
-
-0.75
-0.75
0.45
0.45
-
ns
ns
tCK
tCK
1-4
1-4
1-4
1-4
tCL
CK low-level width
tCK
Clock cycle time CL=3
tCK
Clock cycle time CL=2.5
Clock cycle time CL=2
6
12
6
12
7.5
12
ns
ns
1-4
1-4
tCK
-
-
7.5
12
10
12
1-4,
tDH
DQ and DM input hold time
0.4
0.45
0.5
ns
15, 16
1-4,
tDS
tDIPW
tHZ
DQ and DM input setup time
0.4
1.75
-0.6
0.45
1.75
-0.7
0.5
ns
ns
ns
15, 16
DQ and DM input pulse width (each input)
Data-out high-impedance time from CK/CK
1.75
-0.75
1-4
+0.6
+0.7
+0.75
1-4, 5
tLZ
tDQSQ
tHP
Data-out low-impedance time from CK/CK
-0.6
+0.6
0.4
-0.7
+0.7
0.45
-0.75
+0.75
0.5
ns
ns
tCK
1-4, 5
1-4
DQS-DQ skew (DQS & associated DQ signals)
Minimum half clk period for any given cycle;
defined by clk high (tCH) or clk low (tCL) time
t
CH or
tCL
t
CH or
tCL
t
CH or
tCL
1-4
tHP
-
tHP
-
tHP
-
tQH
Data output hold time from DQS
tCK
1-4
tQHS
tQHS
tQHS
tQHS
Data hold Skew Factor
0.5
0.55
1.25
0.75
1.25
ns
tCK
1-4
1-4
tDQSS
Write command to 1st DQS latching transition
DQS input low (high) pulse width
(write cycle)
0.75
0.35
1.25
0.75
0.35
0.75
0.35
tDQSL
,
tCK
tCK
tCK
tCK
1-4
1-4
tDQSH
DQS falling edge to CK setup time
(write cycle)
tDSS
tDSH
tMRD
0.2
0.2
0.2
DQS falling edge hold time from CK
(write cycle)
0.2
2
0.2
2
0.2
2
1-4
1-4
Mode register set command cycle time
tWPRES
Write preamble setup time
0
0
0
ns
1-4, 7
tWPST
tWPRE
Write postamble
Write preamble
0.40
0.25
0.60
0.40
0.25
0.60
0.40
0.25
0.60
tCK
tCK
1-4, 6
1-4
Address and control input hold time
(fast slew rate)
2-4, 9,
11, 12
tIH
0.6
0.6
0.75
0.75
0.9
0.9
ns
ns
Address and control input setup time
(fast slew rate)
2-4, 9,
11, 12
tIS
2-4,
Address and control input hold time
(slow slew rate)
tIH
0.7
0.8
1.0
ns
10, 11,
12, 14
REV 2.2
20
Aug 3, 2004
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
TA = 0 °C ~ 70 °C; VDDQ= VDD= 2.5V ± 0.2V (PC2100/PC2700); VDDQ= VDD= 2.6V ± 0.1V (PC3200) (Part 2 of 2)
5T
6K
75B
Unit
ns
Notes
Symbol
tIS
Parameter
PC3200
PC2700
PC2100
Min.
Max.
Min.
Max.
Min.
Max.
2-4,
10-12,
14
Address and control input setup time
(slow slew rate)
0.7
0.8
1.0
2-4, 12
1-4
tIPW
tRP RE
tRP ST
tRAS
Input pulse width
2.2
0.9
2.2
0.9
2.2
0.9
ns
tCK
tCK
Read preamble
1.1
0.60
1.1
0.60
1.1
0.60
1-4
Read postamble
0.40
42ns
55
0.40
42ns
60
0.40
45ns
65
1-4
Active to Precharge command
Active to Active/Auto-refresh command period
Auto-refresh to Active/Auto-refresh command
period
120us
120us
120us
1-4
tRC
ns
ns
1-4
tRFC
70
72
75
1-4
1-4
1-4
1-4
1-4
tRCD
tRAP
tRP
Active to Read or Write delay
Active to Read Command with Auto-precharge
Precharge command period
Active bank A to Active bank B command
Write recovery time
15
15
15
10
15
18
18
18
12
15
20
20
20
15
15
ns
ns
ns
ns
ns
tRRD
tWR
(tWR
/
(tWR
/
(tWR
/
tCK ) +
tCK ) +
tCK ) +
tDAL
Auto-precharge write recovery + precharge time
tCK
1-4, 13
(tRP
tCK
/
)
(tRP
tCK
/
)
(tRP
tCK
/
)
tWTR
tPDEX
tXSNR
tXSRD
tREFI
Internal write to read command delay
Power down exit time
1
5
1
6
1
tCK
ns
ns
tCK
µs
1-4
1-4
7.5
75
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
75
75
1-4
200
200
200
1-4
7.8
7.8
7.8
1-4, 8
REV 2.2
21
Aug 3, 2004
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
AC Timing Specification Notes
1. Input slew rate = 1V/ns.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for
signals other than CK/CK is VREF
.
3. Inputs are not recognized as valid until VREF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT
.
5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
high to low at this time, depending on tDQSS
.
8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC)
.
10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC)
.
11. CK/CK slew rates are >= 1.0 V/ns.
12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design
or tester characterization.
13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time. For example, for PC2100 at CL= 2.5, tDAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5.
14. An input setup and hold time derating table is used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns.
Input Slew Rate
0.5 V/ns
Delta (tIS
0
)
Delta (tIH
)
Unit
ps
Note
1, 2
1, 2
1, 2
0
0
0
0.4 V/ns
+50
ps
0.3 V/ns
+100
ps
1. Input slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising
transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
15. An input setup and hold time derating table is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns.
Input Slew Rate
0.5 V/ns
Delta (tDS
0
)
Delta (tDH
)
Unit
ps
Note
1, 2
1, 2
1, 2
0
0.4 V/ns
+75
+75
ps
0.3 V/ns
+150
+150
ps
1. I/O slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising
transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
16. An I/O Delta Rise, Fall Derating table is used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ.
Delta Rise and Fall Rate
0.0 ns/V
Delta (tDS
0
)
Delta (tDH
)
Unit
ps
Note
1-4
0
0.25 ns/V
+50
+50
ps
1-4
0.5 ns/V
+100
+100
ps
1-4
1. Input slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising
transitions.
2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.
3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]
For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V
Using the table above, this would result in an increase in tDS and tDH of 100 ps.
4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
REV 2.2
Aug 3, 2004
Preliminary
22
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Package Dimensions
Non-ECC, 16 TSOP devices
FRONT
133.35
5.250
128.93
5.076
θ 2.50
0.098
Detail A
Detail B
Side
BACK
4.00
0.157 MAX
1.27+/- 0.10
Detail A
Detail B
0.050 +/- 0.004
1.00 Width
0.039
6.35
1.27 Pitch
0.05
0.250
1.80
0.071
Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated.
Units: Millimeters (Inches)
REV 2.2
23
Aug 3, 2004
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Package Dimensions
Non-ECC, 8 TSOP devices
FRONT
133.35
5.250
128.93
5.076
θ 2.50
0.098
Detail A
Detail B
Side
BACK
3.18
0.125 MAX
1.27+/- 0.10
Detail A
Detail B
0.050 +/- 0.004
1.00 Width
0.039
6.35
1.27 Pitch
0.05
0.250
1.80
0.071
Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated.
Units: Millimeters (Inches)
REV 2.2
24
Aug 3, 2004
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Package Dimensions
Non-ECC, 4 TSOP devices
FRONT
133.35
5.250
128.93
5.076
θ 2.50
0.098
Detail A
Detail B
Side
BACK
3.18
0.125 MAX
1.27+/- 0.10
Detail A
Detail B
0.050 +/- 0.004
1.00 Width
0.039
6.35
1.27 Pitch
0.05
0.250
1.80
0.071
Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated.
Units: Millimeters (Inches)
REV 2.2
25
Aug 3, 2004
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Package Dimensions
ECC, 18 TSOP devices
FRONT
133.35
5.25
128.95
5.077
(2)θ
2.50
0.098
Detail A
Detail B
Side
BACK
4.00
0.157 max.
1.27+/- 0.10
Detail A
Detail B
0.050 +/- 0.004
1.00 Width
0.039
6.35
1.27 Pitch
0.05
0.250
1.80
0.071
Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated.
Units: Millimeters (Inches)
REV 2.2
26
Aug 3, 2004
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Package Dimensions
ECC, 9 TSOP devices
FRONT
133.35
5.25
128.95
5.077
(2)θ
2.50
0.098
Detail A
Detail B
Side
BACK
2.59
0.157 max.
1.27+/- 0.10
Detail A
Detail B
0.050 +/- 0.004
1.00 Width
0.039
6.35
1.27 Pitch
0.05
0.250
1.80
0.071
Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated.
Units: Millimeters (Inches)
REV 2.2
27
Aug 3, 2004
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Preliminary
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Revision Log
Rev
0.1
1.0
Date
Modification
12/2003
Updated format.
Dec 19,2003
Release
Correction to block diagram label.
1.1
2.0
Feb 11, 2004
Mar 4, 2004
Correction to SPD bank and checksum values.
Package dimension added for x8 wide devices.
Document reorganized by order of B die generation / size and DIMM format.
DIMM: unbuffered DIMM
Speed grades: 5T, 6K, 75B
Modules: NT512D64S8HB1G, NT256D64S88B1G, NT128D64SH4B1G
Modules: NT512D72S8PB0G, NT256D72S89B0G
Modules: NT512D64S8HB1GY, NT256D64S88B1GY
Added NT256D64S88B0G-6K speed grade to ordering information.
Corrected SPD contents.
2.1
2.2
May 11, 2004
Aug 3, 2004
Nanya Technology Corporation
Hwa Ya Technology Park 669
Fu Hsing 3rd Rd., Kueishan,
Taoyuan, 333, Taiwan, R.O.C.
Tel: +886-3-328-1688
Please visit our home page for more information: www.nanya.com
Nanya reserves the right to make changes or deletions without any notice to any of its products. Nanya makes no guarantee, warranty or representation regarding the suitability of
its products for any particular purpose. Nanya assumes no liability arising out of the application or use of its products. All parameters can and do vary in its application and must
be validated for each customer application by the customer’s technician. By purchasing Nanya products, Nanya does not convey any license under its patent rights not the rights
of others. Nanya products are not designed or intended or authorized for use in systems intended for the military or surgical implants or any other applications where life is involved
or where injury or death may occur or the loss/corruption of data or the loss of system reliability or mission critical applications. Should the buyer purchase or use Nanya products
in such unintended or unauthorized application, the Buyer and user shall indemnify and hold Nanya and its officers, employees, subsidiaries, affiliates and distributors harmless
against all claims, costs, damages, all fees and expenses directly or indirectly arising from any claim of loss, injury or death associated with unintended or unauthorized use even
if such claims alleges Nanya was negligent regarding design or manufacture of the part. Nanya and the Nanya logo are trademarks of the Nanya Technology Corporation.
Printed in Taiwan
©2004
REV 2.2
Aug 3, 2004
Preliminary
28
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
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