NT56V1616A0T-8 [ETC]
x16 SDRAM ; X16 SDRAM\n
| 型号： | NT56V1616A0T-8 |
| 厂家： | 
ETC |
| 描述： | x16 SDRAM
|
| 文件： | 总33页 (文件大小：723K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
NT56V1616A0T
DATA SHEET
1Mx16
Synchronous DRAM
REV 1.2
August , 2000
REV 1.2 , AUG. 2000
1
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
Revision History
Revision 1.2 ( August, 2000 )
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Changed data sheet format
Changed package dimension format
Changed
Item
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Input Leakage Current
From
-0.5 to Vcc+0.5 (V)
-0.5 to 4.5 (V)
-10 ~ +10 µA
0~65°C
To
VIN,VOUT
VCC, VCCQ
IIL
-1.0 to 4.6 (V)
-1.0 to 4.6 (V)
-5 ~ +5 µA
0~70°C
Ambient Temperature
Ta
Revision 1.1 ( May, 2000 )
Add Timing waveform chart
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Revision 1.0 ( May, 2000 )
First Version
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REV 1.2 , AUG. 2000
2
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
DESCRIPTION
The NTC 16Meg SDRAM is a high-speed CMOS dynamic random-access memory containing 16,777,216 bits. It is internally
configured as a dual memory array (512K x 16) with a synchronous interface (all signals are registered on the positive edge of
the clock signal, CLK). Each of the two internal banks is organized with 2,048 rows and with either 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command
which will then be followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE
command are used to select the bank and row to be accessed (A11 selects the bank, A0-10 selects the row). The address bits
coincident with the READ or WRITE command are used to select the starting column location for the burst access.
The NTC 16Meg SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle
to achieve a high speed, fully random access. Precharging one bank while accessing the alternate bank will hide the
precharge cycles and provides seamless high-speed random access operation. The NTC 16Meg SDRAM is designed to
comply with the Intel PC (66MHz) and Intel PC/100 (100MHz) specifications.
The NTC 16Meg SDRAM is designed to operate in 3.3V, low-power memory systems. An AUTO REFRESH mode is provided
along with a power saving Power-Down mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a
high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide
precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.
FEATURE
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PC100 compliant functionality and performance.
JEDEC standard 3.3 V ± 10% power supply.
LVTTL compatible inputs and outputs.
All inputs are sampled on positive edge of system clock.
Dual Banks for hidden row access/precharge.
Internal pipeline operation, column addresses can be changed every cycle.
MRS cycle with address key programmability for:
-
-
-
CAS latency ( 2 , 3 )
Burst Length ( 1 , 2 , 4 , 8 or full page)
Burst Type ( Sequential & Interleave )
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DQM for masking.
Auto Precharge and Auto Refresh modes.
Self Refresh Mode.
64ms , 4096 cycle refresh ( 15.6 us/row )
50–pin 400 mil plastic TSOP (type II) package.
PRODUCT FAMILY
Part NO.
Max Freq.
143 MHz
CL
3
tAC
Organization
Interface
LVTTL
Package
NT56V1616A0T-7
5.5 ns
400mil
50pin TSOP II
2Banks x 512Kbits x 16
NT56V1616A0T-8
125 MHz
3
6 ns
REV 1.2 , AUG. 2000
3
©NA NYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
PIN ASSIGNMENT ( Top View )
V
CC
1
2
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
DQ0
DQ1
DQ15
DQ14
3
V
SSQ
DQ2
DQ3
4
VSSQ
5
DQ13
DQ12
6
V
CCQ
DQ4
DQ5
7
VCCQ
8
DQ11
DQ10
9
V
SSQ
DQ6
DQ7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSSQ
DQ9
DQ8
V
CCQ
DQML
WE
CAS
RAS
CS
VCCQ
N.C/RFU
DQMH
CLK
CKE
N.C
A9
A11
A10
A0
A8
A7
A1
A6
A2
A5
A3
A4
V
CC
VSS
50-pin Plastic TSOP-II
PIN FUNCTIONAL DESCRIPTION
Symbol
A0 – A10 / A11
CLK
Function
Description
Address
Row address:RA0 – RA10 ; Column address: CA0 –CA7 ; Bank selection: A11
Fetches all input at the “H” edge.
System Clock
Clock Enable
CKE
Master system clock to deactivate the subsequent CLK operation.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
RAS
CAS
WE
Row address Strobe
Column Address Strobe
Write Enable
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Disables or enables device operation by masking or enabling all controls except CLK,
CKE and DQM.L(H)
CS
Chip Select
Active high. Controls the data output buffers in read mode. In write mode it masks the
data from being written to the memory array. DQML corresponds to DQ0-DQ7
DQMH corresponds to DQ8-DQ15.
DQML, DQMH
DQi
Data input/output Mask
Data Input/Output
Data I/O are multiplexed on the same table.
No connect/ Reserved for This pin should be left No Connect on the device so that the normal functionality of the
NC/RFU
Vcc, Vss
Future Use
device is not effected by the external connection to this pin.
Supply pins for the core.
Power supply , Ground
Data output power supply ,
Ground.
VccQ, VssQ
Supply pins for the output buffers.
REV 1.2 , AUG. 2000
4
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
FUNCTIONAL BLOCK DIAGRAM
Refresh
Controller
Row Adress Latch
512K x 16
Bank 0
Refresh
Counter
Adress
[ 0 : 11 ]
Sense AMP & I/O gates
Column Decoder
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
CLK
CKE
CS
DQ 6
RAS
CAS
WE
Column
Address
Buffer
DQ 7
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
HDQM
LDQM
Column Decoder
Sense AMP & I/O gates
512K x 16
Bank 1
Row Adress Latch
REV 1.2 , AUG. 2000
5
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
ORDERING INFORMATION
NT 56
V
1
6
16
A
0
T
-
XX
Speed*(10)
Package*(9)
NANYA Memory*(1)
Device*(2)
Voltage*(3)
Interface*(8)
Revision*(7)
Density*(4)
Configration*(6)
Refresh Time*(5)
(1) NANYA Memory
(6) Configuration
40 - - - - - - - - 2 bank, x 4
80 - - - - - - - - 2 bank, x 8
16 - - - - - - - - 2 bank, x 16
10 - - - - - - - - 4 bank, x 8
(2) Device
56 - - - - - - - - SDRAM
(7) Revision
A - - - - - - - - 1st version
B - - - - - - - - 2nd version
C - - - - - - - - 3rd version
D - - - - - - - - 4th version
(3) Voltage
V - - - - - - - - 3.3V
(8) Interface
0 - - - - - - - - LVTTL
1 - - - - - - - - SSTL
(4) Density
1 - - - - - - - - 16M
(9) Package
T - - - - - - - -TSOP II
F - - - - - - - -TQFP
Q - - - - - - - -QFP
6 - - - - - - - - 64M
2 - - - - - - - - 128M
(5) Refresh Time
(10) Speed
7 - - - - - - - - 2K/32ms
6 - - - - - - - - 4K/64ms
6 - - - - - - - -166MHz
7 - - - - - - - -143MHz
8 - - - - - - - -125MHz
10 - - - - - - - 100MHz
REV 1.2 , AUG. 2000
6
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Short Circuit Output Current
Power Dissipation
Symbol
VIN,VOUT
VCC, VCCQ
IOS
Rating
-1.0 to 4.6
-1.0 to 4.6
50
Unit
V
V
mA
W
PD
1
Ambient Temperature
Ta
0 to 70
-55 to 150
°C
°C
Storage Temperature
Tstg
v
Stresses greater than those listed under “Absolute Maximum Rating” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may effect reliability.
Recommended Operating Condition (Ta=0°C to 70°C)
Parameter
Symbol
VCC, VCCQ
VIH
Min.
3.0
2.0
-0.3
2.4
-
Typ.
3.3
3.0
-
Max.
3.6
Unit
V
Note
Power Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Vcc +0.3
0.8
V
VIL
V
VOH
-
V
IOH =-4.0 mA
IOL = 4.0 mA
1
VOL
0.4
V
IIL
-5
5
uA
1. 0<VIn< Vcc Input leakage current includes hi-Z output leakage for all bi-directional buffers with tri-state outputs.
Capacitance
Parameter
Symbol
CIN
Min.
2.5
Max.
5.0
Unit
pF
Input Pin Capacitance
I/O Pin Capacitance
Clock Pin Capacitance
CI/O
4.0
6.5
pF
CCLK
2.5
4.0
pF
The Capacitance parameters are sampled by Vcc=3.3V ± 10% , Ta =25°C,f =1 MHZ
REV 1.2 , AUG. 2000
7
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
DC CHARACTERISTICS
(Vcc=3.3V ± 10% , Ta=0°C to 70°C)
Version
Unit
Parameter
Symbol
Test condition
- 7
90
- 8
Operating current
(One bank active)
Burst length=1, tRC >= tRC(mim), IOL=0mA
tCLK =7ns
ICC1
80
mA
mA
ICC2P
CKE <= VIL(max), tCLK= 7ns
Precharge standby current
in power-down mode
2
2
ICC2PS
CKE & CLK <= VIL(max), tCC=oo
CKE >= VIH(min), /CS >= VIH(min), tCLK=7ns
input singles are changed one time during 7ns
ICC2N
50
30
Precharge standby current
in non power-down mode
mA
mA
CKE >= VIH(min),CLK <= VIL(min), tCC =oo
input singles are stable
ICC2NS
ICC3P
CKE<=VIL(max), tCLK=7ns
5
3
Active standby current
in power-down mode
ICC3PS
CKE & CLK <= VIL(max), tCC=oo
CKE >=VIH(min), /CS >= VIH(min), tCLK=7ns
input singles are changed one time during 7ns
CKE >= VIH(min), CLK <= VIL(min), tCC=oo
input singles are stable
ICC3N
ICC3NS
ICC4
65
25
Active standby current
in non power-down mode
(Two bank active)
mA
mA
Operating current
( Burst mode )
IOL=0mA;2 banks active; BL=4,tCLK=7ns
150
90
140
80
Refresh current
Self refresh current
ICC5
ICC6
tRC >= tRC(min) ; tCLK=7ns
CKE <= VIL(max), tCLK=7ns
mA
mA
2
AC OPERATING TEST CONDITIONS
(Vcc=3.3V ± 10% , Ta=0°C to 70°C)
Parameter
Input levels (VIH / VIL )
Value
Unit
V
2.4 / 0.4
1.4
Input timing measurement reference level
Input rise and fall time
V
tr / tf = 1 / 1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 1
AC Output Load Circuit.
Vtt = 1.4V
50 ohm
Output
Zo = 50 ohm
30 pF
(Fig.1) AC Output Load Circuit
REV 1.2 , AUG. 2000
8
©NA NYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
AC TIMING PARAMETERS ( Ta=0-70°C, Vcc=3v-3.6v )
- 7
- 8
Parameter
Symbol
Unit
ns
Notes
Min
7
Max
Min
8
Max
CL = 3
Clock cycle time
tCK
CL = 2
12
3
12
3
Clock high time
Clock low time
Input setup time
Input hold time
Output valid from
clock
tCH
tCL
tSS
tSH
ns
3
3
ns
2
2
ns
1
1
ns
CL = 3
CL = 2
5.5
6
6
6
ns
tAC
-
-
ns
Output hold from clock
tOH
2
1
2
1
ns
CAS to CAS delay
tCCD
tRRD
tDQD
tDWD
tMRD
tROH
tDQZ
tDQM
tDPL
tDAL
tSB
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
RAS to RAS bank active delay
DQM to input data delay
Write command to data-in delay
MRS to active delay
2
2
0
0
0
0
2
2
Precharge to O/P in Hi-Z
DQM to data in Hi-Z for read
DQM to data mask for write
Data-in to precharge command
Data-in to active command
Power down mode entry
Self refresh exit time
CL
2
CL
2
1
0
0
2
2
5
5
1
1
tSRX
tPDE
1
1
1
1
Power down exit setup time
Note:
1. CL=CAS Latency
FREQUENCY vs AC PARAMETERS
NT56V1616A0T- 7
(Unit:numberofclock)
Frequency
143Mhz (7ns)
125MHz(8ns)
100Mhz (10ns)
83Mhz (12ns)
CL
3
tRC
10
9
tRAS
TRP
tRCD
7
6
5
4
3
3
2
2
3
3
2
2
3
3
7
2
6
NT56V1616A0T - 8
(Unit: number of clock)
Frequency
CL
3
tRC
9
tRAS
tRP
3
tRCD
125Mhz (8ns)
100Mhz (10ns)
83Mhz (12ns)
6
5
4
3
2
2
3
7
2
2
6
2
REV 1.2 , AUG. 2000
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©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
COMMAND TRUTH TABLE
CKE
n-1
H
CKE
n
Function
Symbol
CS
RAS
CAS
WE
A11
A10
A9-A0
Device Deselect
No Operation
DESEL
NOP
X
H
L
L
L
L
L
L
L
L
L
L
H
X
H
L
L
X
H
H
H
H
H
L
X
H
L
X
H
H
H
L
X
X
V
V
V
V
V
V
X
X
X
X
X
X
L
X
X
L
X
X
V
V
V
V
V
X
X
X
X
X
X
X
V
X
H
X
Read
READ
READAP
WRITE
WRITEAP
ACT
H
X
Read w/ auto precharge
Write
H
X
L
H
L
H
X
L
Write w/ auto precharge
BankActive
H
X
L
L
H
V
L
H
X
H
H
H
L
H
L
Precharge select bank
Precharge all banks
Auto refresh
PRE
H
X
L
PALL
H
X
L
L
H
X
X
X
X
X
L
CBR
H
H
L
L
H
H
X
X
X
L
Self refresh entry from IDLE
Self refresh exit
Power Down entry from IDLE
Power Down exit
Mode register set
Burst Stop
SLFRSH
SLFRSHX
PWRDN
PWRDNX
MRS
H
L
L
L
H
L
X
X
X
L
X
X
X
L
H
L
H
X
H
BST
H
X
H
H
L
X
X
DQM TRUTH TABLE
Function
CKE n-1
CKE n
DQML / DQMH
Data write/output enable
Data mask/output disable
H
H
X
X
L
H
H: High Level, L: Low Level, X: don’ t care, V: Valid data input.
REV 1.2 , AUG. 2000
10
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
OPERATIVE COMMAND TABLE ( TABLE 1 )
Current
State
Bank
Address
X
CS
RAS
CAS
WE
Address
Action
No Operation command
Notes
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
H
L
H
L
X
X
H
L
X
X
X
X
No Operation command
ILLEGAL
ILLEGAL
BA
BA
BA
BA
X
2
2
CA,A10
Idle
H
H
L
RA
A10
X
Row Active
L
L
No Operation command
Auto Refresh or Self refresh
Mode Register Access
No Operation command
No Operation command
Read
4
5
5
L
L
Op Code
L
X
X
X
H
H
H
L
X
H
L
X
X
CA,A10
CA,A10
RA
BA
BA
BA
BA
X
Row
Active
L
Write
ILLEGAL
H
H
L
H
L
X
L
2
L
L
L
A10
X
Op-code
X
Precharge
ILLEGAL
ILLEGAL
L
L
X
H
H
H
L
X
H
L
X
H
H
L
H
L
X
X
Continue burst to end, row active
Continue burst to end, row active
Term burst, start new burst read
Term burst, start new burst write
ILLEGAL
Term burst, precharge
ILLEGAL
ILLEGAL
X
CA,A10
CA,A10
RA
BA
BA
BA
BA
X
L
Read
H
H
L
2
6
L
A10
L
L
X
L
L
X
L
Op-code
X
L
X
H
X
H
H
H
L
H
X
H
L
Burst Stop
X
H
H
L
H
L
X
X
X
X
Continue burst to end, row active
Continue burst to end, row active
Term burst start read
Term burst, new write
ILLEGAL
Term burst precharge
ILLEGAL
ILLEGAL
CA,A10
CA,A10
RA
BA
BA
BA
BA
X
L
Write
H
H
L
L
H
2
6
L
A10
L
L
H
X
L
L
X
Op-code
X
L
X
Burst Stop
Continue burst to end and enter Row
precharge
H
L
X
H
X
H
X
H
X
X
X
X
Continue burst to end and enter Row
precharge
Read with
Auto
Precharge
L
L
L
L
L
L
H
H
H
L
L
L
H
L
L
H
L
L
L
H
L
X
CA,A10
X
BA
BA
X
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
2
2
X
X
L
RA,A10
X
Op-code
BA
X
L
2
Continue burst to end and enter Row
precharge
H
L
X
H
X
H
X
H
X
X
X
X
Continue burst to end and enter Row
precharge
Write with
Auto
Precharge
L
L
L
L
L
L
H
H
H
L
L
L
H
L
L
H
L
L
L
H
L
X
CA,A10
X
BA
BA
X
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
2
2
X
X
L
RA,A10
X
Op-code
BA
X
L
2
REV 1.2 , AUG. 2000
11
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
OPERATIVE COMMAND TABLE (TABLE 1)
Current
State
Bank
Address
X
CS
RAS
CAS
WE
Address
Action
Notes
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
X
H
H
H
L
X
H
L
X
H
H
X
H
L
X
NOP-enter idle after tRP
NOP-enter idle after tRP
ILLEGAL
X
X
BA
BA
BA
BA
X
2
2
2
4
L
CA
ILLEGAL
Precharge
H
H
L
RA
ILLEGAL
L
A10
NOP-enter idle after tRP
ILLEGAL
L
X
L
X
L
L
Op-code
X
ILLEGAL
X
H
H
H
L
X
H
H
L
X
H
L
X
X
NOP-enter idle after tRCD
NOP-enter idle after tRCD
ILLEGAL
X
X
X
BA
BA
BA
BA
X
2
2
2
2
X
H
L
CA
ILLEGAL
RowActive
H
H
L
RA
ILLEGAL
L
A10
ILLEGAL
L
X
L
X
ILLEGAL
L
L
Op-code
X
ILLEGAL
X
H
H
H
L
X
H
H
L
X
H
L
X
X
NOP
X
X
NOP
X
BA
BA
BA
BA
X
ILLEGAL
2
2
2
2
Write
Recovery
X
H
L
CA
ILLEGAL
H
H
L
RA
ILLEGAL
L
A10
ILLEGAL
L
X
L
X
ILLEGAL
L
L
Op-code
X
ILLEGAL
X
H
H
L
X
H
L
X
H
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
NOP – enter idle after tRC
NOP – enter idle after tRC
ILLEGAL
X
X
Refresh
H
L
X
ILLEGAL
L
X
ILLEGAL
L
L
X
ILLEGAL
X
H
H
H
L
X
H
H
L
X
NOP
X
NOP
Mode
Register Set
X
ILLEGAL
X
X
X
ILLEGAL
X
X
ILLEGAL
Note:
1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs.
2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection.
3. Satisfy the timing of tCCD and tWR (Write Recovery Time)to prevent bus contention.
4. NOP to bank precharge or in idle state. Precharge activated bank by BA or A10.
5. Illegal if any bank is not idle.
6. Not bank-specific ; BURST STOP affects the most recent READ or WRITE burst, regardless of bank.
REV 1.2 , AUG. 2000
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NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
OPERATIVE COMMAND TABLE (TABLE 2)
Current
State(n)
CKE
n-1
H
CKE
CS
RAS
CAS
WE
Address
Action
Notes
n
X
H
X
H
X
X
X
X
X
X
X
X
INVALID
L
Exit Self Refresh-Idle after
tRFC(ABI)
7
7
L
H
L
H
H
H
X
Exit Self Refresh-Idle after
tRFC(ABI)
Self Refresh
L
L
L
H
H
H
L
X
H
H
H
H
H
L
L
L
L
H
H
L
H
L
L
X
X
X
X
X
H
L
X
X
X
X
X
X
L
X
X
X
ILLEGAL
ILLEGAL
ILLEGAL
X
X
X
X
H
H
L
L
H
L
X
X
H
L
L
L
X
X
X
H
H
H
L
X
X
H
H
H
L
X
X
X
NOP
INVALID
Exit Power Down - ABI
Exit Power Down - ABI
ILLEGAL
L
L
L
X
X
X
8
8
Power Down
ILLEGAL
L
L
L
X
X
X
H
H
L
X
X
X
ILLEGAL
NOP
Refer to Table 1
Enter Power Down
Enter Power Down
ILLEGAL
X
X
H
L
H
H
H
H
H
H
H
H
H
L
H
L
L
X
X
X
9
9
L
L
All Banks
Idle ( ABI)
L
L
L
L
L
L
H
H
L
X
H
H
L
X
RA
X
ILLEGAL
Row (&bank) A ctive
NOP
L
L
L
L
L
L
L
L
L
L
X
Enter Self Refresh
Mode Register Access
NOP
9
X
X
X
X
X
X
L
OP Code
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
L
H
L
H
L
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clock Suspend
Any State
Other than
Listed above
10
10
L
Note:
7. CKE low to high transition is asynchronous.
8. CKE low to high transition is asynchronous if restart internal clock.
A minimum setup time 1CLK + tSI must be satisfied before any command other than exit.
9. Power down and self refresh can be entered only from the both banks idle state.
10. Must be a legal command.
REV 1.2 , AUG. 2000
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NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
1. When CS is set ‘ High ’ at a clock transition from ‘ Low’ to ‘ high’ , all inputs except CKE and DQM are invalid.
2. When issuing an active, read or write command, the bank is selected by A11
A11
0
Active, read or write
BankA
1
Bank B
3. The auto precharge function is enable or disable by the A10 input when the read and write command is issued.
A10
0
A11
0
Operation
After the end of burst, bank A holds the idle status.
After the end of burst, bank A is precharged automatically.
After the end of burst, bank B holds the idle status.
After the end of burst, bank B is precharged automatically.
1
0
0
1
1
1
4. when issuing a precharge command, the bank to be precharged is selected by the A10 and A11 input.
A10
0
A11
0
Operation
Bank A is precharge.
0
1
Bank B is Precharge.
1
x
Both banks A & B are precharged.
REV 1.2 , AUG. 2000
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NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
Device Operation
Power Up Sequence
·
·
Apply power and start clock, attempt to maintain CKE= “ H” , DQM= “ H” . Other pins are NOP condition at their inputs.
Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
Initialization Sequence
After the following initialization sequence, the device is ready for full functionality:
·
·
·
·
Precharge both banks.
Issue 2 or more Auto refresh (CBR) commands to the device.
Issue a mode register set (MRS) command to set the device mode of operation.
After tRMD (3 clocks) is met. The device is ready for operation.
** Step 2 and 3 are interchangeable.
Precharge Select bank (PRE)
The precharge operation will be performed on the active bank when the precharge selected bank command is issued. When
the precharge command is issued with address A10 low, A11 selects the bank to be precharged. At the end of the precharge
selected bank command the selected bank will be in idle state after the minimum tRP is met.
Precharge All (PALL)
Both banks are precharged at the same time when this command is issued. When the precharge command is issued with
address A10 high then all banks will be precharged. At the end of the precharge all command both banks will be in idle state
after the minimum tRP is met.
Auto Precharge
AUTO PRECHARGE is a feature which performs the same individual-bank PRECHARGE function described above, but
without requiring an explicit command. This is accomplished by using A10 to enable AUTO PRECHARGE in conjunction with a
specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is
automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where AUTO
PRECHARGE does not apply. AUTO PRECHARGE is nonpersistent in that it is either enabled or disabled for each individual
READ or WRITE command.
AUTO PRECHARGE ensures that the PRECHARGE is initiated at the earliest valid stage within a burst.
The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined
as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the
Operation section of this data sheet.
Burst Terminate
The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered
READ or WEITE command prior to the BURST TERMINATE command will be truncated as shown in the Operation section of
this data sheet.
NOP and Device Deselect (NOP, DSEL)
The device is deselected by deactivating the CS signal. In this mode the device ignores all the control inputs. The SDRAMs
are put in NOP mode when CS is active and by deactivating, RAS , CAS and WE . For both Deselect and NOP the device will
finish the current operation when this command is issued.
Row Activate (ACT)
This command is used to select a row in a specified bank of the device. Read and write operation can only be initiated on this
activated bank after the minimum tRCD time has elapsed from the activate command.
Read Bank (READ)
This command is issued after the row activate command to initiate the burst read of data. The read command is initiated by
activating CS , CAS and deasserting WE at the same clock sampling (rising) edge as described in the command truth table.
The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command.
REV 1.2 , AUG. 2000
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NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
Write Bank (WRITE)
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by
activating CS , CAS and WE at the same clock sampling (rising) edge as described in the command truth table. The length of
the burst will be determined by the values programmed during the MRS command.
Functionality of SDRAM device:
The following operations are supported by SDRAM:
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
Burst Read
Burst Write
Multi bank Ping-Pong access
Burst Read with Autoprecharge
Burst Write with Autoprecharge
Burst Read terminated with precharge
Burst Write terminated with precharge
Burst Read terminated with another Burst Read/Write
Burst Write terminated with another Burst Write/Read
DQM masking
Fastest command to command delay of 1 clock
Precharge All command
Auto Refresh
CL=2,3
Burst Length 1,2,4, 8 and full page (256)
Self Refresh Command
Power down
Terminating a read burst
Terminating a write burst
Mode Register Set (MRS)
This command is used to program the SDRAM for the desired operating mode. This command is normally used after power up
as defined in the power up sequence before the actual operation of the SDRAM is initiated. The functionality of the SDRAM
device can be altered by re-programming the mode register through the execution of Mode Register Set command. Both
banks must be precharged (i.e. in idle state) before the MRS command can be issued.
Mode Register Definition
The mode register is set by the input to the address pins (A0 to A11) during mode register set cycles. The mode register
consists of five sections, each of which is assigned to address pins.
A9, A8, A7: (OP Mode):
The synchronous DRAM has two types of write modes. One is the burst write mode, and the other is the single write mode.
These bits specify write mode.
Burst read and burst write:
Burst write is performed for the specified burst length starting from the column address specified in the write cycle.
Burst read and single write:
Data is only written to the column address specified during the write cycle, regardless of the burst length.
A6, A5, A4: (CAS Latency):
These pins specify the CAS latency.
A3: (BT):
A burst type is specified. When full-page burst is performed, only "sequential" can be selected.
A2, A1, A0: (Burst Length):
These pins specify the burst length.
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NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
Mode Register set: (Programming mode)
BA
11
A10
10
A9
9
A8
8
A7
7
A6
6
A5
5
A4
4
A3
3
A2
2
A1
1
A0
0
Address bus
Mode Register (Mx)
Reserved
OP Mode
CAS Latency
BT
Burst Length
CAS Latency
A4
Burst Type
Type
Burst Length
BT=0
A6
0
A5
Latency
Reserved
Reserved
2
A3
0
A2
A1
A0
0
BT=1
1
0
0
1
0
1
0
1
0
1
Sequential
Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
1
1
2
4
8
2
0
0
0
1
4
8
3
1
Reserved
Reserved
Reserved
Reserved
0
Reserved
Reserved
Reserved
Full Page (256)
Reserved
Reserved
Reserved
Reserved
1
1
1
0
1
1
OP Mode
A9
0
1
A8
A7
0
0
Mode
0
0
Normal ( Burst read and burst write )
Single write and burst read
Burst Length
2
Starting Bit
Interleave
Sequential
A0
0
0-1
1-0
0-1
1-0
1
A1
0
A0
0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0
1
1
0
4
8
1
1
A2
0
A1
0
A0
0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn+1,Cn+2
Cn+3, Cn+4…
…Cn-1, Cn ….
0
0
1
0
0
1
1
0
1
1
0
0
1
1
0
1
1
0
1
1
1
Full Page
(256)
n = A0-A7
(location0-255)
Not supported
REV 1.2 , AUG. 2000
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NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
Multi-bank ping pong access
Two-bank Ping-Pong accesses are described in the following diagram. Another bank can be activated while the first bank is
being accessed as shown. RAS to RAS delay tRRD must be met while activating another bank.
Read and Write with Autoprecharge
Burst reads and writes with auto precharge commands are initiated with Autoprecharge if A10 is at a high state while the read
or write commands are issued.
Precharge Termination of Burst
Burst reads and writes without Autoprecharge can be terminated prematurely by a precharge command. If the burst read or
write command was issued in auto precharge mode then the commands may not be terminated prematurely for that bank.
Precharge Command After a Burst Read
The earliest a precharge command can be issued after a Read command without the loss of data is CL + BL – 2 clocks. The
precharge command can be issued as soon as the tRAS time is met. The earliest time that precharge can be issued is shown
for the CAS Latency = 3 device.
Precharge Termination of a Burst Read
Burst Read (with no Autoprecharge) can be terminated earlier using a precharge command along with the DQM . It allows
starting the precharge early. The remaining data is undefined. DQM should be used to mask the invalid data.
Precharge Termination of a Burst Write
To terminate Burst Write early with precharge command the DQM signal must be used as shown. Data sampled tDPL clocks
before precharge command will be written correctly. Data sampled afterward and before the precharge command is undefined.
DQM must be used to prevent the location from being corrupted. DQM must be asserted active to prevent location (A3 and A4
in this case) from being corrupted. DQ(A2) will be written correctly as tDPL is met.
Read Terminated by Read
A Read command will terminate the previous read command and the data will be available after CAS Latency for the new
command. Fastest command to command delay is determined by tCCD (1 clock as shown).
Write Terminated by Write
A Write command will terminate the previous write command and the new burst write command will start with the new
command as shown. Fastest command to command delay is determined by tCCD (1 clock as shown).
Read Terminated by Write
A Write command terminates the previous read command and the new burst write will start . The minimum command delay for
valid operation (i.e. read-modified-write) = CAS Latency + 2. The DQM must be held active for 3 clocks to keep the output
buffer in HiZ as shown to prevent an internal IO buffer conflict between the read data (in pipe) and the write data driven on the
input pins.
Write Terminated by Read
A Read command terminates the previous write command and the new burst read will start as shown. In case of tCCD=1,
CL=3, and tDQZ=2, there is no loss of data bandwidth even if DQM is activated to mask the write data.
The Burst Stop Command is defined by having RAS and CAS high with, CAS and WE low at the rising edge of the clock.
When using the Burst Stop Command during a burst read cycle, it should be issued x cycles before the clock edge at which the
last desired data element is valid, where x equals the CAS latency minus one.
When using the Burst Stop Command during a burst write cycle, the input data applied coincident with the Burst Stop
Command will be ignored. The last data written (provided that DQM is low at that time) will be the input data applied one clock
previous to the Burst Stop Command.
REV 1.2 , AUG. 2000
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NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
SDRAM commands to two banks in consecutive clocks
Given COMMAND1 detected by SDRAM component (to bank(i)), it will handle correctly COMMAND2 (to bank(j)) that is
detected in the next clock or later clock.
Also, note that COMMAND1 (or COMMAND2) can be: Precharge-Bank, Internally-Scheduled_Auto-Precharge, Activate,
Read or Write. Command1/2 cannot be a Precharge-All. Next command to same bank after Precharge
Precharge-Bank
If a Precharge-Bank command (to bank(k)) is detected by SDRAM component in CLK(n), then there can be no commands
presented to this bank until CLK(n+tRP).
Precharge-All
If a Precharge-All command is detected by SDRAM component in CLK(n), then there can be no commands presented to this
component until CLK(n+tRP).
Read-Auto Precharge
If a Read with Auto-Precharge command (to bank(k)) is detected by SDRAM component in CLK(n), then there can be no
commands presented to this bank until CLK(n+CL+BL-2+tRP).
Write-Auto Precharge
If a Write with Auto-Precharge command (to bank(k)) is detected by SDRAM component in CLK(n), then there can be no
commands presented to this bank until CLK(n+BL+Tdal-1).
Back to back command with Auto precharge
Read or write burst initiated with auto precharge (A10=high during read or write) will execute the read or write normally with the
exception that after the burst operation is over the accessed bank will start precharge. To access the bank again the user must
reactivate with an active bank command.
The commands initiated with auto-precharge cannot be terminated with any other commands for that bank.
Auto Refresh (CBR) Command
An auto refresh (CBR) refreshes the SDRAM array. Refresh addresses are generated internally by the SDRAM device and
incremented after each auto refresh automatically. No commands (including another auto refresh) can be issued until a
minimum tRC is satisfied.
Self Refresh Entry/Exit
The self refresh mode is entered by holding CS , RAS , CAS ,CKE low and WE high at the rising edge of the clock. Once the
SDRAM enters the Self Refresh mode, all inputs except CKE will be in a don’ t care state and outputs will be tri-stated. The
external clock may be halted while the device is in Self Refresh mode, however, the clock must be restarted200 cycles before
CKE is high. The self refresh command is exited by asserting CKE high. A new command may be given tRC clocks after CKE
is high.
Multibank Operation
The following table specifies some of the timing parameters used for the timing diagrams. CL, tRCD and tRP can all have
values of 2 or 3.
CL
BL
CAS latency
Burst Length
3 clocks
4
tRP
RAS Precharge
RAS active time
RAS to CAS delay
3 clocks
5 clocks
3 clocks
tRAS
tRCD
REV 1.2 , AUG. 2000
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NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
TIMING WAVEFORM
Power Up Initialization Sequence
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
CS
High level is necessary
tRP
tRC
tRC
RAS
CAS
ADD
Key
RAa
A
11
10
A
RAa
High-z
DQ
WE
High level is necessary
DQM
Power up Precharge
Row Active
(A-bank)
Auto Refresh
MRS
Auto Refresh
Input stable
(All banks)
for 200us
: Don't care
REV 1.2 , AUG. 2000
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NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
Active / Precharge Power Down Mode ( CL =2 , BL =4 )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
tSS
tSS
tSS
CLK
CS
RAS
ADD
Ra
Ca
A11
Ra
A10
tSHZ
DQ
Q
a0
Qa1
Qa2
WE
DQM
Row
Read
Precharge
Active
Precharge
Power-down
Exit
Precharge
Power-down
Exit
Active
Power-down Power-down
Entry Exit
Active
: Don't care
REV 1.2 , AUG. 2000
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NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
Mode Register Set Cycle
Auto Refresh Cycle
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
CLK
CKE
CS
HIGH
HIGH
tRC
RAS
CAS
ADD
Key
Ra
Hi - Z
Hi - Z
DQ
WE
DQM
MRS
New Command
Auto Refresh
New Command
: Don't care
REV 1.2 , AUG. 2000
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NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
Self Refresh Entry & Exit Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
CS
tSS
tRC
RAS
CAS
ADD
A11
A10
Hi-Z
DQ
WE
DQM
Self Refresh Exit
Auto Refresh
: Don't care
Self Refresh Entry
REV 1.2 , AUG. 2000
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NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
Single Bit Read-Write-Read Cycle at same page ( CL = 3 , BL = 1 )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
CS
tCC
tCH
tCL
HIGH
tRAS
tRC
tRP
tRCD
RAS
CAS
ADD
tCCD
tSH
tSS
Cb
Ra
Ca
Cc
Rb
tSS
tSH
BS
BS
Ra
BS
BS
BS
BS
Rb
A
11
A
10
tRAC
tSAC
DQ
Qa
Db
Qc
tSLZ
tOH
WE
tSS tSH
DQM
Row Active
Read
Write
Read
Precharge
Row Active
: Don't care
REV 1.2 , AUG. 2000
24
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
Read & Write Cycle at Same Bank ( BL = 4 )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
CS
HIGH
tRC
tRCD
RAS
CAS
ADD
Ra
Ca0
Rb
Cb0
A11
A10
Ra
Rb
tRAC
tRAC
DQ CL=2
CL=3
Qa0
Qa1
Qa2
Qa3
Db0
Db0
Db1
Db2
Db3
tSAC
tOH
tSHZ
Qa2
tRDL
Qa0
tOH
Qa1
Qa3
tSHZ
Db1
Db2
Db3
tSAC
tRDL
WE
DQM
Row Active
( A-Bank )
Read
( A-Bank )
Precharge
( A-Bank )
Row Active
( A-Bank )
Write
( A-Bank )
Precharge
( A-Bank )
REV 1.2 , AUG. 2000
25
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
Read & Write Cycle with Random Row at Different Bank ( BL = 4 )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
CS
HIGH
RAS
CAS
ADD
RAa
CAa
RBb
CBb
RAc
CAc
A11
A10
RAa
RBb
RAc
tCDL
CL=2
CL=3
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1
Q
Q
DQ
QAa0 QAa1 QAa2 QAa3
QAc0
WE
DQM
Row Active
( A-Bank )
Read
( A-Bank )
Row Active
( A-Bank )
Precharge
( A-Bank )
Write
Row Active
Read
( A-Bank )
( A-Bank ) ( A-Bank )
: Don't care
REV 1.2 , AUG. 2000
26
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
Page Read Cycle at Different Bank ( BL = 4 )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
HIGH
CKE
CS
RAS
CAS
ADD
RAa
CAa
RBb
CBb
CAc
CBd
CAe
A11
RAa
RBb
A10
DQ
CL=2
CL=3
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
WE
DQM
Row Active
( A-Bank )
Read
Row Active
Read
( A-Bank )
Read
( A-Bank )
Read
( A-Bank )
Read
( A-Bank )
Precharge
( A-Bank )
( A-Bank ) ( A-Bank )
: Don't care
REV 1.2 , AUG. 2000
27
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
Page Write Cycle at Different Bank ( BL = 4 )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
CS
HIGH
RAS
CAS
ADD
RAa
Ca0
RBb
CBb
CAc
CBd
A11
RAa
RBb
A
10
DQ
WE
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1
tRDL
tRDL
DQM
Row Active
( A-Bank )
Write
Row Active
Write
( B-Bank )
Write
( A-Bank )
Write
( B-Bank )
Precharge
( Both-Bank )
( A-Bank ) ( B-Bank )
: Don't care
REV 1.2 , AUG. 2000
28
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
Page Read & Write Cycle at Same Bank ( CL = 2 , BL = 4 )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
CS
HIGH
tRCD
RAS
CAS
ADD
Ra
Ca0
Cb0
Cc0
Cd0
A11
Ra
A
10
tRDL
Qa0
Qa1
Qa0
Qb0
Qb1
Qb0
Qb2
Dc0
Dc0
Dc1
Dd0
Dd0
Dd1
CL=2
CL=3
DQ
Qa1
Qb1
Dc1
tCDL
Dd1
WE
DQM
Row Active
( A-Bank )
Read
( A-Bank )
Read
( A-Bank )
Write
( A-Bank )
Write
( A-Bank )
Precharge
( A-Bank )
: Don't care
REV 1.2 , AUG. 2000
29
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
Read Interruption by Precharge Command & Read Burst Stop Cycle
( BL = Full Page )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
CS
HIGH
RAS
CAS
ADD
RAa
CAa
CAb
A
11
RAa
A
10
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
CL=2
CL=3
DQ
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
WE
DQM
Row Active
( A-Bank )
Read
( A-Bank )
Burst
Stop
Read
( A-Bank )
Precharge
( A-Bank )
: Don't care
REV 1.2 , AUG. 2000
30
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
Write Interruption by Precharge Command & Write Burst Stop Cycle
( BL = Full Page )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
CS
HIGH
RAS
CAS
ADD
RAa
CAa
CAb
A11
RAa
A
10
tRDL
tBDL
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
DQ
WE
DQM
Row Active
( A-Bank )
Write
( A-Bank )
Burst
Stop
Write
( A-Bank )
Precharge
( A-Bank )
: Don't care
REV 1.2 , AUG. 2000
31
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
Clock Suspension & DQM Operation Cycle ( CL = 2 , BL = 4 )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
CS
HIGH
RAS
CAS
ADD
Ra
Ca
Cb
Cc
A11
Ra
A10
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Dc0
Dc2
DQ
tSHZ
tSHZ
WE
DQM
Row Active
Read
Clock
Suspension
Read
Read
DQM
Write Write
DQM
Clock
Suspension DQM
Write
: Don't care
REV 1.2 , AUG. 2000
32
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V1616A0T
16Mb: 1Mx16
Synchronous DRAM
PACKAGE DIMENSIONS
( 400mil; 50-Pin; Thin Small Outline Package )
Dimension in inch
Dimension in mm
Symbol
Min
-
Nom
-
Max
0.047
0.006
0.041
0.018
0.008
0.830
0.405
-
Min
-
Nom
-
Max
1.20
0.15
1.05
0.45
0.21
21.08
10.29
-
A
A1
A2
b
0.002
0.037
0.010
0.005
0.820
0.396
-
0.004
0.039
0.014
0.006
0.825
0.400
0.031
0.463
0.031
0.020
-
0.05
0.95
0.25
0.12
20.82
10.06
-
0.10
1.00
0.35
0.15
20.95
10.16
0.80
11.76
0.80
0.50
-
c
D
E
e
HE
L
0.455
-
0.471
-
11.56
-
11.96
-
L1
S
y
0.016
-
0.024
0.040
0.004
5 º
0.40
-
0.60
1.03
0.10
5 º
-
-
-
-
q
0 º
-
0 º
-
Note:
1. Dimension D&E do not include interlead flash.
2. Dimension S includes end flash.
3. Controlling dimension : MM
REV 1.2 , AUG. 2000
33
©NA NYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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