NT68P62U [ETC]
8-Bit Microcontroller for Monitor (32K OTP ROM Type); 8位微控制器监视器( 32K OTP ROM类型)型号: | NT68P62U |
厂家: | ETC |
描述: | 8-Bit Microcontroller for Monitor (32K OTP ROM Type) |
文件: | 总56页 (文件大小:521K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NT68P62-01
8-Bit Microcontroller for Monitor (32K OTP ROM Type)
Features
n Operating voltage range: 4.5V to 5.5V
n CMOS technology for low power consumption
n 6502 8-bit CMOS CPU core
n 8 MHz operation frequency
n 32K bytes of OTP (one time programming) ROM
n 512 bytes of RAM
n Two layers of interrupt management
NMI interrupt sources
- INTE0 (External INT with selectable edge trigger)
- INTMUTE (Auto Mute Activated)
IRQ interrupt sources
- INTS0/1 (SCL Go-low INT)
n One 8-bit base timer
- INTA0/1 (Slave Address Matched INT)
- INTTX0/1 (Shift Register INT)
- INTRX0/1 (Shift Register INT)
- INTNAK0/1 (No Acknowledge)
- INTSTOP0/1 (Stop Condition Occurred INT)
- INTE1 (External INT with Selectable Edge Trigger)
- INTV (VSYNC INT)
n 13 channels of 8-bit PWM outputs with 5V open drain
n 4 channel A/D converters with 6-bit resolution
n 25 bi-directional I/O port pins (8 dedicated I/O pins)
n Hsync/vsync signals processor for separate
&
composite signal, including hardware sync signals
polarity detection and freq. counters with 2 sets of
Hsync counting interval
- INTMR (Base Timer INT)
n Hsync/Vsync polarity controlled output, 5 selectable
free run output signals and self-test patterns, auto-
mute function, half freq. I/O function
n Two built-in I2C bus interfaces support VESA
- INTADC (AD Conversion Done INT)
n Hardware watch-dog timer function
n 40-pin P-DIP and 42-pin S-DIP packages
DDC1/2B+
General Description
2
The NT68P62 is a new generation of monitor mC for auto-
sync and digital control applications. Particularly, this chip
supports various and efficient functions to allow users to
easily develop USB monitors. It contains the 6502 8-bit
CPU core, 512 bytes of RAM used as working RAM and
stack area, 32K bytes of OTP ROM, 13-channel of 8-bit
PWM D/A converters, 4-channel A/D converters for keys
detection which can save I/O pins, one 8-bit pre-loadable
base timer, internal Hsync and Vsync signals processor,
and a watch-dog timer which prevents the system from
abnormal operation and two IC bus interface. The user
can store EDID data in the 128 bytes of RAM for DDC1/2B,
so that user can reduce a dedicated EEPROM for EDID.
And Half frequency output function can save external one-
shot circuit. All of these designs are committed to offer our
user saving component cost. The 42 pin S-DIP IC provides
two additional I/O pins – port40 & port41, Part number
NT68P62U represents the S-DIP IC. For future reference,
port40 & port42 is only available for the 42 pin S-DIP IC.
1
V2.2
NT68P62-01
Pin Configurations
40-Pin P-DIP
[PGM] DAC2
DAC1/ADC3
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VSYNCI/INTV [A14]
HSYNCI
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSYNCI/INTV [A14]
HSYNCI
[PGM] DAC2
DAC1/ADC3
[OE] DAC0/ADC2
[VPP] RESET
DAC3 [MODE0]
DAC4/SCL1 [MODE1]
DAC5/SDA1 [MODE2]
P41
3
4
2
[OE] DAC0/ADC2
3
DAC3 [MODE0]
DAC4/SCL1 [MODE1]
DAC5/SDA1 [MODE2]
DAC6 [RESET]
CREG
VDD
5
4
[VPP] RESET
P40
GND
6
5
VDD
7
DAC6 [RESET]
CREG
6
GND
OSCO
OSCO
8
7
OSCI
9
P07/HSYNCO [A7]
P06/VSYNCO [A6]
P05/DAC12 [A5]
P04/DAC11 [A4]
P03/DAC10 [A3]
P02/DAC9 [A2]
P01/DAC8 [A1]
P00/DAC7 [A0]
P31/SCL0 [A13]
P30/SDA0 [A12]
P20 [DB0]
8
P07/HSYNCO [A7]
OSCI
P15/INTE0
10
11
12
13
14
15
16
17
18
19
20
21
9
P15/INTE0
P06/VSYNCO [A6]
P05/DAC12 [A5]
[CE] P14/PATTERN
[A11] P13/HALFI
[A10] P12/HALFO
[A9] P11/ADC1
[A8] P10/ADC0
P16/INTE1
[CE] P14/PATTERN
10
11
12
13
14
15
16
17
18
19
20
[A11] P13/HALFI
[A10] P12/HALFO
[A9] P11/ADC1
[A8] P10/ADC0
P04/DAC11 [A4]
P03/DAC10 [A3]
P02/DAC9 [A2]
P01/DAC8 [A1]
P00/DAC7 [A0]
P16/INTE1
[DB7] P27
[DB7] P27
[DB6] P26
[DB5] P25
[DB4] P24
[DB3] P23
P31/SCL0 [A13]
P30/SDA0 [A12]
P20 [DB0]
[DB6] P26
[DB5] P25
[DB4] P24
P21 [DB1]
P21 [DB1]
P22 [DB2]
[DB3] P23
P22 [DB2]
* [ ]: OTP Mode
* [ ]: OTP Mode
42-Pin S-DIP
Block Diagram
VDD
CREG
GND
SCL0
SDA0
SCL1
Voltage
Regulator
OTP Program ROM
32K Bytes
IIC BUS
OSCI
SDA1
OSCO
Timing Generator
DAC0 - DAC7
SRAM + STACK
512 Bytes
PWM DACs
INTE0/1
VSYNCI/INTV
HSYNCI
DAC8 - DAC12
CPU core
6502
ADC0 - ADC3
A/D Converter
8-Bit Base Timer
Watch Dog Timer
P00 - P07
VSYNCO
HSYNCO
Interrupt
Controller
P10 - P16
P20 - P27
P30 - P31
P40 - P41
PATTERN
I/O Ports
H/V Sync Signals
Processor
HALFI
HALFO
2
NT68P62-01
Pin Description
Pin No.
Designation
Reset Init.
I/O
Description
40 Pin
42 Pin
1
1
DAC2
O
[ I ]
Open drain 5V, D/A converter output 2
[OTP ROM program control]
[PGM ]
2
3
2
3
DAC1/ADC3
DAC1
DAC0
O
O
Open drain 5V, D/A converter output 1, shared with A/D
converter channel 3 input
DAC0/ADC2
Open drain 5V, D/A converter output 0, shared with A/D
converter channel 2 input
[OTP ROM program output enable]
[OE ]
4
4
I
Schmitt Trigger input pin, low active reset with internal
pulled down 50KW register *
[OTP ROM program supply voltage]
RESET
[ P ]
[ VPP ]
VDD
5
6
7
8
9
5
7
P
P
Power
GND
Ground
8
OSCO
OSCI
O
I
Crystal OSC output
Crystal OSC input
9
10
P15/INTE0
I/O
Bi-directional I/O pin with internal pulled up 22KW register,
shared with input pin of external interrupt source0 (NMI),
with schmitt trigger, selectable triggered, and internal pulled
up 22KW register
10
11
11
12
P14/PATTERN
I/O
Bi-directional I/O pin with internal pulled up 22KW register,
shared with the output of self test pattern
[ A15/CE ]
P13/HALFI
[ I ]
I/O
[ OTP ROM program address buffer & chip enable ]
P13
Bi-directional I/O pin with internal pulled up 22KW register,
shared with half hsync input, shared with A/D converter
channel 3 input
[ A11 ]
[ I ]
I/O
[ OTP ROM program address buffer ]
12
13
14
15
13
14
15
16
P12/HALFO
P12
P11
P10
P16
Bi-directional I/O pin with internal pulled up 22KW register,
shared with half hsync output
[ OTP ROM program address buffer ]
[ A10 ]
[ I ]
I/O
P11/ADC1
Bi-directional I/O pin with internal pulled up 22KW register,
shared with A/D converter channel 1 input
[ OTP ROM program address buffer ]
[ A9 ]
[ I ]
I/O
P10/ADC0
Bi-directional I/O pin with internal pulled up 22KW register,
shared with A/D converter channel 0 input
[ OTP ROM program address buffer ]
[ A8 ]
[ I ]
I/O
P16/INTE1
Bi-directional I/O pin with internal pulled up 22KW register,
shared with input pin of external interrupt source1, with
Schmitt Trigger, selectable triggered, and an internal pulled
up 22KW register
3
NT68P62-01
Pin Description (continued)
Pin No.
Designation
Reset Init.
I/O
Description
40 Pin
42 Pin
16 - 23
17 - 24
P27 – P20
I/O
Bi-directional I/O pin, push-pull structure with high current
drive/sink capability
[ DB7 ] – [ DB0]
P30/SDA0
[ I/O ] [ OTP ROM program data buffer ]
24
25
26
27
28
25
26
27
28
29
P30
P31
P00
P01
P02
I/O
Open drain 5V bi-directional I/O pin P30, shared with SDA0
pin of I2C bus Schmitt Trigger buffer
[ A12 ]
[ I ]
I/O
[ OTP ROM program address buffer ]
P31/SCL0
Open drain 5V bi-directional I/O pin P31, shared with SCL0
pin of I2c bus Schmitt Trigger buffer
[ A13 ]
[ I ]
I/O
[ OTP ROM program address buffer ]
P00/DAC7
Bi-directional I/O pin with internal pulled up 22KW register,
shared with open drain 5V D/A converter output 8
[ OTP ROM program address buffer ]
[ A0 ]
[ I ]
I/O
P01/DAC8
Bi-directional I/O pin with internal pulled up 22KW register,
shared with open drain 5V D/A converter output 9
[ OTP ROM program address buffer ]
[ A1 ]
[ I ]
I/O
P02/DAC9
Bi-directional I/O pin with internal pulled up 22KW register,
shared with open drain 5V D/A converter output 10
[ OTP ROM program address buffer ]
[ A2 ]
[ I ]
I/O
29
30
31
32
33
30
31
32
33
34
P03/DAC10
P03
P04
P05
P06
P07
Bi-directional I/O pin with internal pulled up 22KW register,
shared with open drain 5V D/A converter output 11
[ OTP ROM program address buffer ]
[ A3 ]
[ I ]
I/O
P04/DAC11
Bi-directional I/O pin with internal pulled up 22KW register,
shared with open drain 5V D/A converter output 12
[ OTP ROM program address buffer ]
[ A4 ]
[ I ]
I/O
P05/DAC12
Bi-directional I/O pin with internal pulled up 22KW register,
shared with open drain 5V D/A converter output 13
[ OTP ROM program address buffer ]
[ A5 ]
[ I ]
I/O
P06/VSYNCO
Bi-directional I/O pin with internal pulled up 22KW register,
shared with vsync out
[ A6 ]
[ I ]
I/O
[ OTP ROM program address buffer ]
P07/HSYNCO
Bi-directional I/O pin with internal pulled up 22KW register,
shared with hsync out
[ A7 ]
[ I ]
O
[ OTP ROM program address buffer ]
34
35
35
36
CREG
On chip voltage regulator output, external regulating
cap.(10µF ~ 100µF) should be connected here
DAC6
O
[ I ]
Open drain 5V, D/A converter output 6
[ OTP ROM reset ]
[RESET]
36
38
DAC5/SDA1
[ MODE2 ]
O
Open drain 5V, D/A converter output 5, shared with open
drain SDA1 line of I2C bus, Schmitt Trigger buffer
[ OTP ROM mode select ]
[ I ]
4
NT68P62-01
Pin Description (continued)
Pin No. Designation
Reset Init.
I/O
Description
40 Pin
42 Pin
37
39
DAC4/SCL1
[ MODE1 ]
O
Open drain 5V, D/A converter output 4, shared with open
drain SCL1 line of I2C bus, Schmitt Trigger buffer
[ OTP ROM mode select ]
[ I ]
38
39
40
41
DAC3
[ MODE0 ]
O
[ I ]
Open drain 5V, D/A converter output 3
[ OTP ROM mode select ]
HSYNCI
I
Debouncing & Schmitt Trigger input pin for video horizontal
sync signal, internal pull high, shared with composite sync
input
40
42
VSYNCI/INTV
VSYNCI
I
Debouncing & Schmitt trigger input pin for video vertical
sync signal, internal pull high, shared with input pin of
external interrupt source intv with Schmitt Trigger,
selectable triggered, and internal pulled up 22KW register
[ OTP ROM program address buffer ]
[ I ]
[ A14 ]
P40
-
-
6
I/O
I/O
Bi-directional I/O pin with internal pulled up 22KW register,
only 42 pin S-DIP available
37
P41
Bi-directional I/O pin with internal pulled up 22KW register,
only 42 pin S-DIP available
* This RESET pin must be pulled high by external pulled-up register (5KW suggestion), or it will remain in low voltage to
continually rest system.
5
NT68P62-01
Functional Description
1. 6502 CPU
The 6502 is an 8-bit CPU that provides 56 instructions, decimal and binary arithmetic, thirteen addressing modes, true
indexing capability, programmable stack pointer and variable length stack, a wide selection of addressable memory ranges,
and interrupt input options.
The CPU clock cycle is 4MHz (8MHz system clock divided by 2). Please refer to the 6502 data sheet for more detailed
information.
7
7
7
0
0
0
Accumnlator A
Index Register Y
Index Register X
15
8
Program Counter PCH
PCL
7
7
0
0
Stack Pointer SP
7
0
C
N
V
D
I
Z
Status Register P
B
Carry
1=TRUE
Zero
1=Result ZERO
1=DISABLE
IRQ Disable
Decimal Mode 1=TRUE
BRK Command 1=BRK
Overflow
Negative
1=TRUE
1=NEG
Figure 1.1. The 6502 CPU Registers and Status Flags
6
NT68P62-01
2. Instruction Set List
Instruction Code
Meaning
Operation
ADC
Add with carry
Logical AND
A + M + C → A, C
A‧ M → A
AND
ASL
BCC
BCS
BEQ
BIT
Shift left one bit
C ← M7 …M0 ← 0
Branch on C = 0
Branch on C = 1
Branch on Z = 1
Branch if carry clears
Branch if carry sets
Branch if equal to zero
Bit test
A‧ M, M7→N, M6→V
Branch on N = 1
Branch on Z = 0
Branch on N = 0
Forced Interrupt PC+2↓ PC↓
Branch on V = 0
Branch on V = 1
0 → C
BMI
Branch if minus
BNE
BPL
BRK
BVC
BVS
CLC
CLD
CLI
Branch if not equal to zero
Branch if plus
Break
Branch if overflow clears
Branch if overflow sets
Clear carry
Clear decimal mode
Clear interrupt disable bit
Clear overflow
0 → D
0 → I
CLV
CMP
CPX
CPY
DEC
DEX
DEY
EOR
INC
0 → V
Compare Accumulator to memory
Compare with index register X
Compare with index register Y
Decrement memory by one
Decrement index X by one
Decrement index Y by one
Logical exclusive-OR
Increment memory by one
Increment index X by one
Increment index Y by one
A - M
X - M
Y - M
M - 1 → M
X - 1 → X
Y - 1 → Y
A ⊕ M→A
M + 1 → M
INX
X + 1 → X
INY
Y + 1 → Y
7
NT68P62-01
Instruction Set List (continued)
Instruction Code
Meaning
Operation
JMP
JSR
LDA
LDX
LDY
Jump to new location
Jump to subroutine
(PC+1)→ PCL, (PC+2)→ PCH
PC+2↓, (PC+1)→ PCL, (PC+2)→ PCH
Load accumulator with memory
Load index register X with memory
Load index register Y with memory
M → A
M → X
M → Y
LSR
NOP
ORA
Shift right one bit
No operation
Logical OR
0 → M7 …M0 → C
No operation (2 cycles)
A + M → A
PHA
PHP
PLA
PLP
ROL
ROR
RTI
Push accumulator on stack
Push status register on stack
Pull accumulator from stack
Pull status register from stack
Rotate left through carry
A ↓
P ↓
A ↑
P ↑
C ← M7 …M0 ← C
C → M7 …M0 → C
P ↑, PC ↑
PC ↑, PC+1 → PC
A - M - C → A, C
1 → C
Rotate right through carry
Return from interrupt
RTS
SBC
SEC
SED
SEI
Return from subroutine
Subtract with borrow
Set carry
Set decimal mode
1 → D
Set interrupt disable status
Store accumulator in memory
Store index register X in memory
Store index register Y in memory
Transfer accumulator to index X
Transfer accumulator to index Y
Transfer stack pointer to index X
Transfer index X to accumulator
Transfer index X to stack pointer
Transfer index Y to accumulator
1 → I
STA
STX
STY
TAX
TAY
TSX
TXA
TXS
TYA
A → M
X → M
Y → M
A → X
A → Y
S → X
X → A
X → S
Y → A
* Refer to 6502 programming data book for more details.
8
NT68P62-01
3. RAM: 512 X 8 bits
The built-in 512 X 8-bit SRAM is used for data memory and stack area. The RAM addressing range is from $0080 to $027F.
The contents of RAM are undetermined at power-up and are not affected by system reset. Software programmers can
allocate stack area in the RAM by setting stack pointer register (S). Because the 6502 default stack pointer is $01FF,
programmers must set S register to FFH when starting the program.
as;
LDX #$FF
TXS
$0000
System Registers
Unused
$003D
$0080
RAM
stack pointer
$01FF
( 512 Bytes )
$027F
$0280
Unused
$7FFF
$8000
( 32 K Bytes )
OTP
ROM
$FFFA
$FFFB
$FFFC
$FFFD
$FFFE
$FFFF
NMI-L
NMI-H
RST-L
RST-H
IRQ-L
IRQ-H
NMI vector
RESET vector
IRQ vector
4. ROM: 32K X 8 bits
NT68P62 provides 32K ROM space for programming. The ROM space is located from $8000 to $FFFF.
The addresses, from $FFFA to $FFFF, are reserved for the 6502 CPU vectors, thus users must arrange them by
themselves.
9
NT68P62-01
5. System Registers
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Control Registers for I/O Port0 & Port1
$0000
$0001
PT0
PT1
FFH
7FH
P07
-
P06
P16
P05
P15
P04
P14
P03
P13
P02
P12
P01
P11
P00
P10
RW
RW
Control Register to Control Port2 I/O Direction
$0002
PT2DIR
FFH
W
P27OE
P26OE
P25OE
P24OE
P23OE
P22OE
P21OE
P20OE
Control Registers for I/O Port2 - 4
$0003
$0004
$0005
PT2
PT3
PT4
FFH
03H
03H
P27
-
P26
-
P25
-
P24
-
P23
-
P22
P21
P31
P41
P20
P30
P40
RW
RW
RW
-
-
Only available for the 42 Pin SDIP version
Control Registers for Synprocessor
$0006
$0007
SYNCON
HV CON
FFH
FFH
-
-
-
-
-
-
-
-
-
-
-
R
INSEN
HSEL
S/ C
W
INSEN
HPOLI
-
ENHSEL
VPOLI
-
HSEL
S/ C
FFH
FFH
HSYNCI
-
VSYNCI
-
HPOLO
HPOLO
VPOLO
VPOLO
R
W
ENHOUT
HCL7
ENHOUT
$0008
$0009
HCNT L
HCNT H
00H
HCL6
HCL5
HCL4
HCL3
HCL2
HCH2
-
HCL1
HCH1
-
HCL0
HCH0
-
R
R
00H HCNTOV
CLRHOV
-
-
-
HCH3
-
-
-
-
W
R
$000A
$000B
VCNT L
00H
00H
VCL7
VCL6
VCL5
VCL4
VCL3
VCL2
VCH2
-
VCL1
VCH1
-
VCL0
VCH0
-
VCNT H
VCNTOV
CLRVOV
-
-
VCH5
VCH4
VCH3
R
-
-
-
-
-
-
W
W
$000C
$000D
FREECON
HALFCON
FFH
FFH
ENPAT
PAT1
FREQ2
-
FREQ1
-
FREQ0
-
-
-
-
W
W
ENHALF
NOHALF
HALFPOL
$000E
$000F
AUTOMUTE FFH
HDIFFVL3 HDIFFVL2 HDIFFVL1 HDIFFVL0
ENHDIFF
-
ENPOL
ENOVER
Control Registers to Enable PWM 8 - 15 Channels
ENDAC
FFH
-
W
ENDK10
ENDK8
ENDK12
ENDK11
ENDK9
ENDK7
Control Registers for ADC 0 - 3 Channels
$0010
ENADC
FFH
-
-
-
W
CSTA
ENADC3
AD03
ENADC2
AD02
ENADC1
AD01
ENADC0
AD00
$0011
$0012
$0013
$0014
AD0 REG
AD1 REG
AD2 REG
AD3 REG
C0H
00H
00H
00H
-
-
-
-
-
-
-
-
AD05
AD15
AD25
AD35
AD04
AD14
AD24
AD34
R
R
R
R
AD13
AD12
AD11
AD10
AD23
AD22
AD21
AD20
AD33
AD32
AD31
AD30
10
NT68P62-01
System Registers (continued)
Addr.
$0016
$0017
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Control Register for Polling (Read) Interrupt Groups & Clearing (Write) INTE0 & INTMUTE Interrupt Requests
NMIPOLL
IRQPOLL
00H
00H
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
INTE0
CLRE0
IRQ1
INTMUTE
CLRMUTE
IRQ0
R
W
R
IRQ2
Control Registers of Interrupt Enable
$0018
$0019
$001A
$001B
IENMI
IEIRQ0
IEIRQ1
IEIRQ2
00H
00H
00H
00H
-
-
-
-
-
-
-
-
-
-
-
-
INTE0
INTMUTE
RW
RW
RW
RW
INTS0
INTS1
-
INTA0
INTA1
-
INTTX0
INTTX1
INTADC
INTRX0
INTRX1
INTV
INTNAK0 INTSTOP0
INTNAK1 INTSTOP1
INTE1
INTMR
Control Registers for Polling (Read) & Clearing (Write) Interrupt Requests
$001C
$001D
$001E
IRQ0
IRQ1
IRQ2
00H
00H
00H
-
-
-
-
-
-
-
-
-
-
-
-
INTS0
CLRS0
INTS1
CLRS1
-
INTA0
CLRA0
INTA1
CLRA1
-
INTTX0
CLRTX0
INTTX1
INTRX0
CLRRX0
INTRX1
CLRRX1
INTV
INTNAK0 INTSTOP0
CLRNAK0 CLRSTOP0
INTNAK1 INTSTOP1
CLRNAK1 CLRSTOP1
R
W
R
CLRTX1
INTADC
CLRADC
W
R
INTE1
INTMR
-
-
CLRV
CLRE1
CLRMR
W
Selection of Edge Triggered for INTV, INTE0 & 1 Interrupts
$001F
$0020
TRIGGER
CLR WDT
FFH
-
-
-
-
-
-
INTVR
INTE1R
0
INTE0R
1
R/W
W
Control Registers for Clearing Watch Dog Timer
0
1
0
1
0
1
Control Register for DDC1/2B+ of Channel 0
$0021
$0022
$0023
$0024
CH0ADDR
CH0TXDAT
CH0RXDAT
CH0CON
A0H
00H
00H
E0H
ADR7
TX7
ADR6
TX6
ADR5
TX5
RX5
-
ADR4
TX4
ADR3
TX3
ADR2
TX2
RX2
-
ADR1
TX1
-
W
W
R
TX0
RX0
-
RX7
RX6
RX4
RX3
RX1
START
STOP
W
MD1/ 2
-
ENDDC
-
TXACK
-
START
-
STOP
-
-
-
R
SRW
$0025
CH0CLK
FFH
DDC2BR2 DDC2BR1
DDC2BR0
W
MODE
MRW
RSTART
Control Register for DDC1/2B+ of Channel 1
$0026
$0027
$0028
CH1ADDR
CH1TXDAT
CH1RXDAT
A0H
00H
00H
ADR7
TX7
ADR6
TX6
ADR5
TX5
ADR4
TX4
ADR3
TX3
ADR2
TX2
ADR1
TX1
-
W
W
R
TX0
RX0
RX7
RX6
RX5
RX4
RX3
RX2
RX1
11
NT68P62-01
System Registers (continued)
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$0029
CH1CON
E0H
-
START
STOP
-
-
W
MD1/ 2
-
ENDDC
-
TXACK
-
START
-
STOP
-
-
-
R
SRW
$002A
CH1CLK
FFH
DDC2BR2 DDC2BR1
DDC2BR0
W
MODE
MRW
RSTART
Control Registers for Base Timer
$002E
$002F
BT
00H
03H
BT7
-
BT6
-
BT5
-
BT4
-
BT3
-
BT2
-
BT1
BT0
W
W
BTCON
BTCLK
ENBT
Control Registers for PWM Channel 0 - 13
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
$0038
$0039
$003A
$003B
$003C
$003D
DACH0
DACH1
DACH2
DACH3
DACH4
DACH5
DACH6
80H
80H
80H
80H
80H
80H
80H
-
DKVL7
DKVL7
DKVL7
DKVL7
DKVL7
DKVL7
DKVL7
-
DKVL6
DKVL6
DKVL6
DKVL6
DKVL6
DKVL6
DKVL6
-
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
-
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
-
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
-
DKVL2
DKVL2
DKVL2
DKVL2
DKVL2
DKVL2
DKVL2
-
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
-
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
-
RW
RW
RW
RW
RW
RW
RW
DACH7
DACH8
80H
80H
80H
80H
80H
80H
DKVL7
DKVL7
DKVL7
DKVL7
DKVL7
DKVL7
DKVL6
DKVL6
DKVL6
DKVL6
DKVL6
DKVL6
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
DKVL2
DKVL2
DKVL2
DKVL2
DKVL2
DKVL2
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
RW
RW
RW
RW
RW
RW
DACH9
DACH10
DACH11
DACH12
12
NT68P62-01
6. Timing Generator
This block generates the system timing and control signal
and compacitor included, users can externally add these
components for proper operating.
to be supplied to the CPU and on-chip peripherals.
A
crystal quartz, ceramic resonator, or an external clock
signal which will be provided to the OSCI pin generates
system timing. It generates 8MHz system clock, 4MHz for
the CPU. Although internal circuits have a feedback resister
The typical clock frequency is 8MHz. Different frequencies
will affect the operation of those on-chip peripherals whose
operating frequency is based on the system clock.
OSCI
External Clock
Unconnected
OSCI
8MHz
OSCO
OSCO
(2)
(1)
NT68P62
NT68P62
Figure 6.1. Oscillator Connections
7. RESET
The NT68P62 can be reset by the external reset pin or by
the internal watch-dog timer. This is used to reset or start
the microcontroller from a POWER DOWN condition.
During the time that this reset pin is held LOW (*reset line
must be held LOW for at least two CPU clock cycles),
The reset status is as follows:
1. PORT0、PORT1、PORT2、PORT3 (& PORT4) pins
will act as I/O ports with HIGH output
2. Sync processor counters reset and VCNT | HCNT
latches cleared
writing to or from the mC is inhibited. When a positive edge
3. All sync outputs are disabled
is detected on the RESET input, the mC will immediately
begin the reset sequence.
After a system initialization time of six CPU clock cycles,
the mask interrupt flag will be set and the mC will load the
program counter from the memory vector locations $FFFC
and $FFFD. This is the start location for program control.
4. Base timer is disabled and cleared
5. Various Interrupt sources are disabled and cleared
6. A/D converter is disabled and stopped
7. DDC1/2B+ function is disabled
8. PWM DAC0 – DAC6 output 50% duty waveform and
DAC7 - DAC12 is disabled
9. Watch-dog timer is cleared and enabled
An internal Schmitt Trigger buffer at the RESET pin is
provided to improve noise immunity.
13
NT68P62-01
8. A/D Converters
(CONVERSION START) in the ENADC control register.
When conversion is finished, system will set this INTADC
bit. Users can monitor this bit to get the valid A/D
conversion data in the AD latch registers ($0011 - $0014).
Users can also open interrupt sources to remind users to
get the stable digital data. Notice that only at the activated
A/D channel, its latched data are available.
The structure of these analog to digital converters is 6-bit
successive approximation. Analog voltage is supplied from
external sources to the A/D input pins and the result of the
conversion is stored in the 6-bit data latch registers ($0011
& $0014). The A/D channels are activated by clearing the
correspondent control bits in the ENADC control register.
When users write '0' into one of the enable control bits, its
correspondent I/O pin or DAC will be switched to the A/D
converter input pin (ADC0 & ADC1 shared with PORT10 &
PORT 11; ADC2 & ADC3 shared wit DAC0 & DAC1).
The analog voltage to be measured should be stabled
during the conversion operation and the variation will not
exceed LSB for the best accuracy in measurement.
Conversion will be started by clearing CSTA bit
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$0010
ENADC
FFH
-
-
-
W
CSTA
ENADC3
ENADC2
ENADC1
ENADC0
$0011
$0012
$0013
$0014
$001B
$001E
AD0 REG
AD1 REG
AD2 REG
AD3 REG
IEIRQ2
C0H
00H
00H
00H
00H
00H
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AD05
AD04
AD03
AD13
AD02
AD12
AD22
AD32
INTV
AD01
AD11
AD21
AD31
INTE1
INTE1
CLRE1
AD00
AD10
R
R
AD15
AD14
AD25
AD24
AD23
AD20
R
AD35
AD34
AD33
AD30
R
-
-
-
-
-
-
INTADC
INTADC
CLRADC
INTMR
INTMR
CLRMR
R/W
R
IRQ2
INTV
CLRV
W
Reference ADC Table (VDD = 5.0V)
15
16
17
18
19
1A
1B
1.50V
1.58V
1.66V
1.74V
1.82V
1.90V
1.98V
1C
1D
1E
1F
20
21
22
2.06V
23
24
25
26
27
28
29
2.59V
2A
2B
2C
2D
2E
2F
30
3.14V
2.12V
2.20V
2.28V
2.35V
2.44V
2.51V
2.67V
2.75V
2.82V
2.91V
2.98V
3.07V
3.22V
3.30V
3.38V
3.46V
3.54V
3.62V
Note: It is strongly recommended that the ADC’ s input signal should be allocated in the ADC’ s linear voltage range
(1.5V~3.5V) to obtain a stable digital value. Do not use the outer ranges (0V~1.4V & 3.6V~5.0V) in which the
converted digital value is not guaranteed.
14
NT68P62-01
9. PWM DACs (Pulse Width Modulation D/A Converters)
There are 13 PWM D/A converters with 8-bit resolution in NT68P62. All of these D/A (DAC0 - DAC12) converters are open-
drain output structure with external 5V applied maximum. DAC0 – DAC6 are dedicated PWM channels, and DAC7 - DAC12
are shared with I/O pins. Those shared PWM channels are activated by clearing the correspondent control bits in the
ENDAC control register ($000F). When users write '0' into one of the enable control bits, its correspondent I/O pin will be
switched to PWM output pin.
The PWM refresh rate is 62.5KHz operating on 8MHz system clock. There are 13 readable DACH registers corresponding to
13 PWM channels ($0030 - $003D). Each PWM output pulse width is programmable by setting the 8 bit digital to the
corresponding DACH registers. When these DACH registers are set to 00H, the DAC will output LOW (GND level) and every
1 bit addition will add 62.5ns pulse width. After reset, all DAC outputs are set to 80H (1/2 duty output). (Please refer to Figure
9.1 for the detailed timing diagram of PWM D/A output.)
8MHz Fosc
PWM value : 255
00
0
1
2
3
m-1
m
0
1
255
01
02
03
m
255(FF)
Figure 9.1. The DAC Output Timing Diagram and Wave Table
15
NT68P62-01
PWM DACs (continued)
DAC0 & DAC1 are shared with ADC2 & ADC3 input pins respectively. If ENADC2/3 bit in the ENADC control register is
cleared to LOW, A/D converters will activate simultaneously. After the chip is reset, ENADC2/3 bits will be in HIGH state
and DAC0 & DAC1 will act as PWM output pins.
DAC4 & DAC5 are shared with SCL1 & SDA1 I/O pins respectively. If users clear the ENDDC bit in the CH1CON control
register to LOW, channel 1 of DDC will be activated. When used as DDC channel, the I/O port will be an open drain structure
and include 'Schmitt Trigger' buffer for noise immunity. After the chip is reset, ENDDC bits will be in HIGH state and DAC4 -
DAC5 will act as PWM output pins.
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$000F
ENDAC
FFH
-
-
W
ENDK8
ENDK12
-
ENDK11
-
ENDK10
ENDK9
ENDK7
$0010
ENADC
FFH
-
W
CSTA
ENADC3
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
-
ENADC2
DKVL2
DKVL2
DKVL2
DKVL2
DKVL2
DKVL2
DKVL2
-
ENADC1
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
-
ENADC0
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
-
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
$0038
$0039
$003A
$003B
$003C
$003D
DACH0
DACH1
DACH2
DACH3
DACH4
DACH5
DACH6
80H
80H
80H
80H
80H
80H
80H
-
DKVL7 DKVL6
DKVL7 DKVL6
DKVL7 DKVL6
DKVL7 DKVL6
DKVL7 DKVL6
DKVL7 DKVL6
DKVL7 DKVL6
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
-
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
-
RW
RW
RW
RW
RW
RW
RW
-
-
DACH7
DACH8
80H
80H
80H
80H
80H
80H
DKVL7 DKVL6
DKVL7 DKVL6
DKVL7 DKVL6
DKVL7 DKVL6
DKVL7 DKVL6
DKVL7 DKVL6
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
DKVL2
DKVL2
DKVL2
DKVL2
DKVL2
DKVL2
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
RW
RW
RW
RW
RW
RW
DACH9
DACH10
DACH11
DACH12
DAC control register ($000F) and DAC value register ($0030 - $003D)
16
NT68P62-01
10. Watch-Dog Timer (WDT)
The NT68P62 implements a watch-dog timer reset to avoid
system stop or malfunction. The clock of the WDT is from
on-chip RC oscillator which does not require any external
components. Thus, the WDT will run, even if the clock on
the OSCI/OSCO pins of the device have been stopped.
The WDT time interval is about 0.5 second. The WDT must
be cleared within every 0.5 second when the software is in
normal sequence, otherwise the WDT will overflow and
cause a reset. The WDT is cleared and enabled after the
system is reset, and can not be disabled by the software.
Users can clear the WDT by writing 55H to CLRWDT
register ($0020).
as;
LDA #$55
STA $0020
Addr.
$0020
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
CLR WDT
-
0
1
0
1
0
1
0
1
W
11. Interrupt Controller
The system provides two kinds of interrupt sources: NMI &
IRQ. The NMI can not be masked and if enabling NMI
interrupt sources, users will execute the NMI interrupt
vector anytime when sources are activated. The IRQ
interrupts can be masked by executing a CLI instruction or
setting the interrupt mask flag directly in the mC status
register. In process IRQ interrupt, if the interrupt mask flag
is not set, the mC will begin an interrupt sequence. The
program counter and processor status register will be
stored in the stack. The mC will then set the interrupt mask
flag HIGH so that no further interrupts may occur. At the
end of this cycle, the program counter will be loaded from
addresses $FFFE & $FFFF, then transferring program
control to the memory vector located at these addresses.
For NMI interrupt, mC will transfer execution sequence to
the memory vector located at addresses $FFFA & $FFFB.
When manipulating various interrupt sources, NT68P62
divides them into two groups for accessing them easily.
One is NMI group and the other is IRQ group.
-
-
The NMI group includes INTE0, INTMUTE.
The IRQ group includes subgroup of IRQ0, IRQ1,RQ2:
IRQ0: DDC1/2B+ Channel 0 interrupt sources; It
includes INTS0, INTA0, INTTX0, INTRX0,
INTNAK0 and INTSTOP0 interrupts.
IRQ1: DDC1/2B+ Channel 1 interrupt sources; It
includes INTS0, INTA1, INTTX1, INTRX1,
INTNAK1 and INTSTOP1.
IRQ2: It includes INTADC, INTV, INTE1 and INTMR
interrupt sources.
Below are the interrupt sources.
Nonmaskable Interrupt Group:
Interrupt
Meaning
Action
INTE0 INT
External 0 INT
It will be activated by the rising edge or falling edge of external interrupt pulse.
The triggered edge can be selected by EDGE0 bit.
INTMUTE
Auto Mute
It will be activated when the mute condition occurres (Hsync frequency
change). Please refer the synprocessor section for more detailed explanation.
Maskable Interrupt Group:
Interrupt
Meaning
Action
INTADC
A/D Converion
Done
User activates the ADC by clearing the CSTART bit. When AD conversion is
done, this bit will be set.
INTV INT
Vsync INT
It will be activated as the rising edge of every vsync pulse.
INTE1 INT
External 1 INT
It will be activated by the rising edge or falling edge of external interrupt pulse.
The triggered edge can be selected by EDGE1 bit.
INTMR INT
Timer INT
It will be activated as the rising edge of every when the Base Timer counter
overflows and counting from $FF to $00.
17
NT68P62-01
DDC Channel 0/1 Maskable Interrupt Sources:
Interrupt
Meaning
Action
INTS INT
SCL Go-Low INT In DDC1 mode, it will be activated when the external device proceed a DDC2
communication. This action includes pull the SCL line to ground or send out an
'START' condition directly. System will respond to this action by changing
DDC1 mode to DDC2 slave mode.
INTA INT
Address Matched It will be activated at DDC2 slave mode when the external device call NT68P62
INT
slave address. If this calling address matches the NT68P62 address, system
will generate this interrupt to remind user
INTTX INT
INTRX INT
INTNAK INT
Transfer Buffer
Empty INT
It will be activated at DDC2 mode when transmission buffer, IIC_TXDAT, is
empty at transmission mode.
Receiving Buffer
Overflow INT
It will be activated at DDC2 mode when new data have store in the
IIC_RXDAT register at receive mode.
No Acknowledge
INT
At transmission mode, this interrupt will be activated when NT68P62 have
send out one byte data but the external device does not respond an
acknowledge bit to it.
INTSTOP INT
DDC2 Stop INT
In SLAVE mode, this interrupt will be activated when the NT68P62 receives an
'STOP' condition.
IRQ0
IEIRQ0
INTSTOP0
INTNAK0
INTRX0
INTTX0
INTA0
IRQ0
INTS0
IRQ1
IRQ2
IEIRQ1
INTSTOP1
INTNAK1
INTRX1
INTTX1
INTA1
IRQ1
IRQ (to CPU 6502)
INTS1
IEIRQ2
INTMR
INTE1
IRQ2
INTV
INTADC
NMIPOLL
INTMUTE
INTE0
IENMI
NMI (to CPU 6502)
Figure 11.1. Interrupt Controller Structure
18
NT68P62-01
Enabling Interrupts: The system will disable all of these
interrupts after reset. Users can enable each of the
interrupts by setting the interrupt enable bits at IENMI,
IEIRQ0 - IEIRQ3 control registers. For example, if users
want to enable external interrupt 0 (INTE0), write '1' to
INTE0 bit in the IENMI control register. At the INTE0 pin,
whenever NT68P62 has detected an interrupt message, it
will generate an interrupt sequence to fetch the NMI vector.
Because these IEX control registers can be read, users can
read back what interrupts he has been activated. At polling
sequence, users need not poll those unactivated interrupts.
Polling Interrupts: When NMI interrupt occurrs, at NMI
interrupt service routine, users must poll the INTE0 &
INTMUTE bit in the NMIPOLL control register to confirm the
NMI interrupt source. The polling sequence decides the
priority of NMI interrupt acceptation. When IRQ interrupt
occurrs, at IRQ interrupt service routine, users must poll the
IRQ0 - IRQ3 in the IRQPOLL control register to confirm the
IRQ interrupt source. In the same way, the polling
sequence decides the priority of IRQ interrupt acception.
When deciding the IRQ source, users can further confirm
the real interrupt source by polling the Correspondent IRQX
control register ($001C - $001E).
Requesting Interrupts to be set: No matter user have been
set the interrupt enable bits or not, if the interrupt triggered
condition is matched, system will set the correspondent bits
in the IRQ0 - IRQ3 control registers or in the NMIPOLL
control register (INTE0 & INTMUTE bits). For example, if at
VSYNCI pin, system have detected a pulse occurring,
system will set the INTV bit in the IRQ2 control register.
Clearing the Interrupt Request bit: When interrupt occurrs,
the CPU will jump to the address defined by the interrupt
vector to execute interrupt service routine. Users can check
which one of the interrupt sources is activated and
operating a tast. It is that upon entering the interrupt service
routine, the request bit that caused the interrupt must be
cleared by user before finishing the service routine and
returning to normal instruction sequence. If users forget to
clear this request bit, after returning to main program, it will
interrupt CPU again because the request bit remains
activated. Simply, users just need write '1' to the polling bits
in the NMIPOLL & IRQX registers ($0016 & $001C -
$001E) to clear those completed interrupt sources.
Interrupt Groups: System divides IRQ interrupt sources into
several groups, ex IRQ0, IRQ1, IRQ2 and IRQ3. At each of
these groups, if its membership in the one of the interrupt
groups have been activated, its group bit in the IRQPOLL
control register will be set. For example, if the INTS0 of the
first DDC1/2B+ channel is activated, the INTS0 bit in the
IRQ0 will be set and the IRQ0 bit in the IRQPOLL control
register also will be set. Notice that the IRQ0 bit will be
cleared by system when all of its membership of interrupt
sources, INTS0, INTTX0, INTRX0, INTNAK0 and
INTSTOP0 have been cleared by the user or system. The
NMI group is also oprating the same procedure as IRQ
groups.
Selecting interrupt triggered edge: At INTV, INTE0 & INTE1
interrupt sources, these are now edge triggered type.
System provides the selection of rising or falling edge
triggered under user’ s control. After reset, the rising edge
triggered are provided and the content is 'FF' in the
TRIGGER control register ($001F). User just clear control
bits in this TRIGGER register and switch these interrupts to
falling edge triggered.
19
NT68P62-01
Control Bit Description
Addr.
$0016
$0017
Register
NMIPOLL
IRQPOLL
INIT
00H
00H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Control Register for Polling Interrupt
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
INTE0
CLRE0
IRQ1
INTMUTE
CLRMUTE
IRQ0
R
W
R
IRQ2
Control Registers of Interrupt Enable
$0018
$0019
$001A
$001B
IENMI
IEIRQ0
IEIRQ1
IEIRQ2
00H
00H
00H
00H
-
-
-
-
-
-
-
-
-
-
-
-
INTE0
INTNAK0
INTNAK1
INTE1
INTMUTE
INTSTOP0
INTSTOP1
INTMR
RW
RW
RW
RW
INTS0
INTS1
-
INTA0
INTA1
-
INTTX0
INTTX1
INTADC
INTRX0
INTRX1
INTV
Control Registers for Polling (Read) & Clearing (Write) Interrupt Requests
$001C
$001D
IRQ0
IRQ1
00H
00H
-
-
-
-
-
-
-
-
-
-
INTS0
CLRS0
INTS1
CLRS1
-
INTA0
CLRA0
INTA1
CLRA1
-
INTTX0
INTRX0
INTNAK0
INTSTOP0
R
W
R
CLRTX0 CLRRX0 CLRNAK0 CLRSTOP0
INTTX1 INTRX1 INTNAK1 INTSTOP1
CLRTX1 CLRRX1 CLRNAK1 CLRSTOP1
W
W
CLRADC
CLRV
CLRE1
CLRMR
Selection of Edge Triggered for INTE0 & 1 Interrupt
INTVR
$001F
TRIGGER
FFH
-
-
-
-
-
INTE1R
INTE0R
R/W
20
NT68P62-01
then the input signal can be read. This port output is HIGH
after reset.
P00 - P05 are shared with DAC7 - DAC12 respectively. If
12. I/O PORTs
The NT68P62 has 25 pins dedicated to input and output.
These pins are grouped into 4 ports.
ENDK7 - ENDK12 is set to LOW in ENDAC register, P00 -
P05 will act as DAC7 - DAC12 respectively (Figure 12.2).
12.1. PORT0: P00 - P07
After the chip is reset, ENDK7 - ENDK12 will be in the
HIGH state and P00 - P05s will act as I/O ports.
PORT0 is an 8-bit bi-directional CMOS I/O port with PMOS
as internal pull-up (Figure 12.1). Each pin of PORT0 may
be bit programmed as an input or output port without
software control the data direction register. When PORT0
works as output, the data to be output are latched to the
port data register and output to the pin. PORT0 pins that
have '1's written to them are pulled HIGH by the internal
PMOS pull-ups. In this state they can be used as input,
P06 、 P07 are shared with VSYNCO
& HSYNCO
respectively. If ENHOUT、 ENVOUT is set to LOW in
HVCON register, P06 、 P07 will act as VSYNCO &
HSYNCO respectively (Figure 12.3). After the chip is reset,
ENHOUT & ENVOUT will be in the HIGH state and
P06、P07 will act as I/O pins.
Addr.
$0000
$0007
Register
PT0
INIT
FFH
FFH
Bit7
P07
-
Bit6
P06
-
Bit5
P05
Bit4
P04
Bit3
P03
Bit2
P02
Bit1
P01
Bit0
P00
R/W
RW
R
HV CON
HSYNCI
VSYNCI
HPOLI
VPOLI
HPOLO
VPOLO
-
-
-
-
FFH
FFH
ENHOUT
-
ENVOUT
-
HPOLO
ENDK8
VPOLO
ENDK7
W
W
ENDK11
$000F
ENDAC
ENDK12
ENDK10
ENDK9
PWM
VDD
Output
PWM
Data In
I/O
Figure 12.2. PWM Output Structure
VDD
Data Out
O/P
Data In
Data Out
Figure 12.1. I/O Structure
Figure 12.3. Output Structure
21
NT68P62-01
12.2. Port1: P10 - P16
PORT10 - PORT16 is a 7-bit bi-directional CMOS I/O port
with PMOS as internal pull-up (Figure 12.1). Each bi-
directional I/O pin may be bit programmed as an input or
output port without software control the data direction
register. When PORT1 works as output, the data to be
output is latched to the port data register and output to the
pin. PORT1 pins that have '1's written to them are pulled
HIGH by the internal PMOS pull-ups. In this state they can
be used as input, then the input signal can be read. This
port output HIGH after reset.
sync processor paragraph. After the chip is reset, the
ENHALF bits will be in HIGH state and P12、P13 will act
as I/O pins.
P14 is shared with output pin of self test pattern. If users
clear the PATTERN bit in the SYNCON control register
and the free running function has been activated, the P14
will switch to output pin of the self test pattern. This pattern
output pin is push-pull structure. After the chip is reset,
PATTERN bits will be in the HIGH state and P14 will act as
I/O pin. (Refer the 'Syncprocessor' section for more
detailed information.)
P10 & P11 are shared with AD0 & AD1 input pins
respectively. If the ENADC0/1 bit in the ENADC control
register is cleared to LOW, A/D converters will activate
P15 & P16 can be shared with external interrupt INTE0 &
INTE1 pins if the INTE0/1 bits are set in the control register
of interrupt enable ($0016 & $0019). These interrupt pin
have 'Schmitt Trigger' input buffers. After the chip is reset,
INTE0/1 bits will be in HIGH state and P15 & P16 will act
as I/O pin.
simultaneously. After the chip is reset, ENADC0/1 bits will
be in the HIGH state and P10 - P11 will act as I/O pins.
P12 、 P13 are shared with HALF SIGNALS input and
OUTPUT pins by accessing the OUTCON control register.
If the ENHALF bit is cleared to LOW, P13 will switch to
HALFHI pin (input pin) and P12 will switch to HALFHO pin
(output pin, Figure 12.3). For HALFHI & HALFHO pin
description, please refer half frequency function in the H/V
Refer 'INTERRUPT CONTROLLER' paragraph above for
more details about the interrupt function.
Addr.
$0001
$000C
Register
PT1
INIT
7FH
FFH
Bit7
Bit6
Bit5
P15
-
Bit4
P14
-
Bit3
P13
-
Bit2
P12
Bit1
Bit0
R/W
RW
W
-
P16
P11
P10
FREECON
FREQ2
ENPAT
CSTA
PAT0
-
FREQ1
FREQ0
$0010
ENADC
FFH
-
-
W
ENADC3
ENADC2
ENADC1
ENADC0
$0018
$001B
IENMI
00H
00H
-
-
-
-
-
-
-
-
-
-
-
INTE0
INTE1
INTMUTE
INTMR
RW
RW
IEIRQ2
INTV
VDD
VDD
Data Out
I/P
.
I/O
Data Input
Data OE
Figure 12.4. Schmitt Input Structure
Data In
Figure 12.5. I/O Structure
22
NT68P62-01
12.3. PORT2: P20 - P27
PORT2, an 8-bit bi-directional I/O port (Figure 12.5), may be programmed as an input or output pin by the software control.
When setting the PT2DIR control bit to '0', its correspondent pin will act as an output pin. On the other hand, clear PT2DIR
bit to '1', act as input pin. When programmed as an input, it has an internal pull-up resistor. When programmed as an output,
the data to be output is latched to the port data register and output to the pin with push-pull structure. This port acts as input
port after reset.
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$0002
$0003
PT2DIR
PT2
FFH
FFH
W
P27OE
P27
P26OE
P26
P25OE
P25
P24OE
P24
P23OE
P23
P22OE
P22
P21OE
P21
P20OE
P20
RW
$0010
$0029
ENADC
FFH
FFH
-
-
-
W
CSTA
ENADC3
STOP
ENADC2
RXACK
ENADC1
TXACK
ENADC0
-
CH1CON
START
RW
ENDDC
MD1/ 2
SRW
12.4. PORT3: P30 - P31
PORT3 is an 2 bit bi-directional open-drain I/O port (Figure 12.6). Each pin of PORT3 may be bit programmed as an input or
output port with open drain structure. When PORT3 works as output, the data to be output is latched to the port data register
and output to the pin. When PORT3 pins that have '1's written to them, users must connect PORT3 with external pulled-up
resistor and then PORT3 can be used as input (the input signal can be read). This port output HIGH after reset.
2
P30、P31 include Schmitt Trigger buffers for noise immunity and can be configured as the IC pins SDA0 & SCL0
respectively. If set ENDDC to LOW in CH0DDC control register, P30、P31 will act as SDA0 & SCL0 I/O pins respectively
and will be an open drain structure (Figure 12.6). After the chip is reset, this ENDDC bit will be in HIGH state and PORT3
will act as I/O pins.
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$0004
PT3
FFH
-
-
-
-
-
-
P31
P30
RW
$0029
CH1CON
FFH
START
STOP
RXACK
I/O
TXACK
-
RW
ENDDC
MD1/ 2
SRW
Data Out
Data In
Figure 12.6. PORT3
23
NT68P62-01
12.5. PORT4: P40 - P41
PORT4 is available only on the 42pin SDIP IC. PORT40 - PORT41 is an 2-bit bi-directional CMOS I/O port with PMOS as
internal pull-up (Figure 12.1). Each bi-directional I/O pin may be bit programmed as an input or output port without software
control the data direction register. When PORT4 works as output, the data to be output is latched to the port data register
and output to the pin. PORT4 pins that have '1's written to them are pulled HIGH by the internal PMOS pull-ups. In this state
they can be used as input. The input signal can be read. This port outputs HIGH after reset.
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$0005
PT4
FFH
-
-
-
-
-
-
P41
P40
RW
13. H/V Sync Signals Processor
The functions of the sync processor include polarity detection, Hsync & Vsync signals counting, and programmable sync
signals output. It also provides 3-sets of free running signals and special output of test pattern at burn-in process when
activating the free running output function. The NT68P62 can properly handle either composite or separate sync signal
inputs even without sync signal input. As to processing the composite sync signal, a hardware separator will be activated to
extract the HSYNC signal under user controlled. The input at HSYNCI can be either a pure horizontal sync signal or a
composite sync signal. For the sync waveform refer to Figure 13.1 & Figure 13.2.
The sync processor block diagram is shown in Figure 13.3. Both VSYNCI & HSYNCI pins have Schmitt Trigger and filtering
process to improve noise immunity. Any pulse that is shorter than 125 ns, will be regarded as a glitch and will be ignored.
(a) Positive polarity
(b) Negative polarity
Figure 13.1. Separate H Sync. Waveform
(a) Positive Polarity
(b) Negative Polarity
Figure 13.2. Composite H Sync. Waveform
24
NT68P62-01
VCNTL
VCNTH
Control
Logic
Enable
V sync.
Latch
INTV
S/C
Enable
Reset
8us
VSYNC
INPUT
Schmitt
Trigger
Digital
Filter
V sync.
counter
V
1
0
HSEL
ENHSEL
16.384 ms
32.968 ms
0
1
0
Enable
Reset
H sync.
counter
1
AUTO
MUTE
V
Enable
H sync.
Latch
H & V
INTMUTE
Sync.
Polarity
Detector
H
HSYNC
INPUT
Digital
Filter
Schmitt
Trigger
Sync
Separator
HCNTL
HCNTH
HPOLO
HPOLI
H Sync.
Output
Control
H
HSYNCO
PATTERN
ENPAT, PAT10/1
Pattern
O/P
Control
FREQ0/1/2
FREE_RUN
Control
S/C
VPOLI
V Sync.
Output
Control
V
0
1
VSYNCO
V
VPOLO
Figure 13.3. Sync. Processor Block Diagram
25
NT68P62-01
13.1. V & H Counter Register: VCNTL/H, HCNTL/H
Vsync counter: VCNTL/H, the 14-bit READ ONLY register, contains information of the Vsync frequency. An internal counter
counts the numbers of 8us pulse between two VSYNC pulses. When a next VSYNC signal is recognized, the counter is
stopped and the VCNTH/L register latches the counter value and then the counter counts from zero again for evaluating next
VSYNC time interval. The counted data can be converted to the time duration between two successive Vsync pulses by time
8 us. If no VSYNC incoming, the counter will overflow and set VCNTOV bit (in VCNTH register) to HIGH. Once the VCNTOV
set to HIGH, it keeps in the HIGH state until writing '1' to it (CLRVOV bit).
Hsync counter: If the ENHSEL bit is set to HIGH, the internal counter counts the Hsync pulses between two Vsync pulses.
The HCNTL/H control registers contain the numbers of Hsync pulse between two Vsync pulses. These data can determine if
the Hsync frequency is valid or not to determine the accurate video mode.
The system supports two other options of interval for user counting the frequency of Hsync pulses. If users clear the
ENHSEL and set the HSEL bits properly, this internal counter counts the Hsync pulses during this system defined time
interval. The time interval is defined below:
Hsync Freq
Note
ENHSEL
HSEL
1
0
0
-
Disabled
16.384 ms
32.768 ms
After system reset or users disabling
0
1
After system reset, this interval will be disabled and the content of ENHSEL & HSEL0 bits are '1'. When this function is
disabled, the HCNTL/H counter is working on the VSYNC pulse. It is invalid to write '00' to them.
Latching the hsync counter: The counted value will be latched by the HCNTH/L register pairs which are updated by Vsync
pulse or system defined time interval. (Refer the Figure 13.4 for the opration of HCNTL/H counter.) If the counter overflows,
the HCNTOV bit (in HCNTH register) will be set to HIGH. Once the HCNTOV is set to HIGH, it keeps in the HIGH state until
writing '1' to it (CLRHOV bit). When setting this CLRHOV bit, the HCNT counter will not be reset to zero.
Latch HCNT register
Latch HCNT register
Reset H sync. counter
Reset H sync. counter
Start pulse counting
Start pulse counting
●
●
●
VSYNCI
HSYNCI
●
●
●
●
●
●
16.384ms/32.768ms
(Setting HSEL0/1 bits)
●
●
●
HSYNCI
Figure 13.4. Hsync Counter Operation
26
NT68P62-01
●
●
●
(1) HSYNCI
(2) HSYNCI
Composite H sync. waveform (H EOR V)
Composite H sync. waveform (H OR V)
●
●
●
Hsync pulse or no pulse, the output signal of Hsync will be inserted.
2ms
HSYNCO
VSYNCO
●
●
●
Original
Hsync Pulse
Original
Hsync Pulse
Inserted Hsync Pulse
Widen 9 ms
Figure 13.5. Composite H & V Sync. Processing
27
NT68P62-01
Sync. Mode
Processing
Set S/C = '0'
Clear VCNTOV & HCNTOV
Open INTV & clear INTV flag
System Default:
Freq.
Calculating
S/C = '1' & ENSEL = '1'
Set S/C = '1' & ENSEL = ''0'
& SELECT TIME INTRVAL
(16.384 or 32.968ms)
Open INTV & clear INTV flag
Clear VCNTOV & HCNTOV
Delay 2 * TIME INTELVAL
No
INTV ?
Yes
1. Extract VCNTL/H 14 bit data
Delay 132 ms
2. 14 bits data * 8 us
= Vsync. time duration
3. Its reciprocal
Yes Off Mode
HCNTH = '00'
?
Delay 132 ms
is Vsync. freq.
No
Yes
Suspend Mode
Yes
VCNTOV = '1'
?
VCNTOV = '1'
?
No
1. Extract HCNTL/H
12 bit data
STAND-BY Mode
Yes
No
2. 12 bit data * Vsync. freq.
= Hsync. freq.
HCNTH = '00'
?
or 12 bits data/time interval
(16.382 or 32.968 ms)
3. Its reciprocal
Worng Mode
Yes
HCNTH ='00'
NORMAL Mode
Seperate Sync.
?
No
is Hsync. time duration.
No
Read VCNT|HCNT
Counter Register
Read VCNT|HCNT
Counter Register
Return
NORMAL Mode
Composite Sync.
Freq.
Calculating
Return
Figure 13.6. H & V Sync. Software Control Flow Chart (for reference only)
28
NT68P62-01
13.2. Sync Processor Control Register:
Polarity: The detection of Hsync or Vsync polarity is
achieved by hardware circuit that samples the sync signal's
voltage level periodically. Users can read HPOLI & VPOLI
bit from HVCON register, which bit = '1' represents positive
polarity and '0' represents negative polarity. Furthermore,
users can read HSYNCI and VSYNCI bit in HVCON
register to detect H & V sync input signal. Users can control
the polarity of H & V sync output signal by writing the
appropriate data to the HPOLO and VPOLO bits in the
HVCON register, '1' represents positive polarity and '0',
negative polarity.
Sync output: In pin assignment, VSYNCO & HSYNCO
represent Vsync & Hsync output which are shared with P06
& P07 respectively. If ENVOUT & ENHOUT is set to '0' in
HVCON register, P06 & P07 will act as VSYNCO &
HSYNCO output pins. When the input sync is separate
signal, the V/HSYNCO will output the same signal as input
without delay. But if the input sync is composite signal, the
VSYNCO signal will have fixed delay time about 20ns and
the HSYNCO has nonfixed delay time about 125ns.
Half frequency Input and output: In pin assignment, when
users set ENHALF bits to '0' in HALFCON register, the
HALFHO pin will act as output pin and output half of input
signal in the HALFHI pin with 50% duty (see Figure 13.7). If
Composite sync: Users have to determine whether the
incoming signal is separate sync or composite sync and set
S/C & ENHSEL /HSEL bit properly. If the input sync
set NOHALF to '0', HALFHO will output the same signal in
the HALFHI pin and user can control its polarity of output
HALFHO by setting HALFPOL bit, '1' for positive and '0' for
signal is composite, after set S/ C to '0', the sync separator
block will be activated (please refer Figure 13.5). At the
area of Vsync pulse, there can exist Hsync pulses or not.
For the output of Hsync, users can active hardware to
interpolate the Hsync pulses in that area by clearing the
negative polarity. After the chip is reset, ENHALF 、
NOHALF & HALFPOL will be in the HIGH state and P12 &
P13 will act as I/O pins. It is recommended to add a Schmitt
Trigger buffer at front of the HALFI pin.
INSEN bit. The width of these inserted pulses is 2uS fixed
and the time interval is the same as previous one.
According to the last Hsync pulse outside the Vsync pulse
duration, the hardware will arrange the interval of these
hardware interpolated pulses. These inserted Hsync pulse
have 125 nS phase deviation maximum. The Vsync pulse
can be extracted by hardware from composite Hsync
signal, and the delay time of output Vsync signal will be
limited bellow 20ns. For inserting Hsync pulse safely, the
extracted Vsync pulse will be widens about 9ms. Because
evenly inserting the Hsync pulse, the last inserted Hsync
pulse will have different frequency from original ones.
System will not implement this insertion function, users
Free run signal output: User can select one of free running
frequency (list bellow) outputting to HYSNCO & VSYNCO
pin by setting the FREQ0/1/2 bits. If user does not enable
H/VSYNCO by clearing ENVOUT or ENHOUT bits, any
setting of FREQ0/1/2 bits will be invalid. After system
reset, NT68P62 does not provide free running frequency
and both of FREQ0/1/2 bits are set to ' 1'. The free running
frequency can be set according the table below:
must clear INSEN bit in the SYNCON control register to
activate this function. After reset, S/ C & INSEN bits
default value is HIGH and clear the VCNT | HCNT counter
latches to zero.
Free Running Freq.
Hsync Freq.
Vsync Freq.
Note
FREQ2
FREQ1
FREQ0
Refer to
Figure 13.7
1
0
0
0
8M/256=31.2K
Hsync/512=61.0Hz
2
3
4
5
0
0
0
1
1
1
0
1
1
0
1
1
1
0
8M/4/9/5=44.4K
8M/128=62.5K
8M/4/5/5=80K
Hsync/512=86.8Hz
Hsync/3/5/7/8=74.4Hz
Hsync/1024=78.1Hz
Hsync/1024=88.7Hz
1
0/1
0
8M/4/2/11=90.9K
1
Disabled Free
Run function
After System
Reset
29
NT68P62-01
Self testing pattern: At activating free running function, the system will generate the testing pattern when clearing the
ENPAT bit. The PORT14 pin will switch from I/O pin to pattern output pin (push-pull structure). The system provides four
types of testing patterns. Refer the figure below. Set the PAT0 bits to select the pattern type (Figure 13.8). If the free run
function has not been enabled, any change of ENPAT & PAT0 bits will be invalid. Refer the Figure 13.9 for the porch time
of video pattern.
PAT0
Test Pattern
Note
0
1
(1)
(2)
Only activated on ENPAT bit be cleared
The porch of self test pattern are listed below:
Free Running
Freq.
Front Porch of
VBLANK
BACK Porch of Front Porch of
BACK Porch of
HBLANK
VSYNC
PULSE WIDTH
HSYNC
PULSE WIDTH
VBLANK
HBLANK
1
2
3
4
5
460ns
128ms
90.5ms
51ms
864ms
2.00ms
1.93ms
1.92ms
1.94ms
1.94ms
64ms
1ms
1ms
1ms
1ms
1ms
589ms
528ms
596ms
515ms
1.18ms
424ns
185ns
436ns
64ms
64ms
64ms
64ms
51.5ms
46.6ms
Mode change detection: The system provides a hardware detection of Sync signal changed and support user to respond to
this transition an proper process as soon as possible. There are three kinds of detections to set INTMUTE bit.
Hsync counter: Users can enable HDIFF comparison by clearing ENHDIFF bit and then preload an difference value to
HDIFF0-3 bits in the AUTOMUTE control register ($000E). The system will latch the new value of Hsync counter and
compare it with the last latched value. If this difference is great than this user defined value at HDIFF0-3 bits, system will set
the INTMUTE interrupt bit.
H/V polarity: Users can enable polarity detection by clearing ENPOL bit. The system will set the INTMUTE bit when the
polarity of Hsync or Vsync have been changed.
H/V counter overflow: Users can enable the detection of sync counters overflow by clearing ENOVER bit. The system will
set the INTMUTE bit whenever the counter of Hsync or Vsync has been overflowed.
The above three sources of setting this INTMUTE bit can be enabled or disabled by user. If user opens this interrupt, the
system will generate an NMI interrupt to remind users anytime. At user's manipulation, a software debounce to confirm the
transition of sync signal for one more times will make this system stable and reliable, but it will affect the response time. After
system reset, this 'automute' function will be disabled and the HDIFF0-2 control bits will be cleared to ' $0F'.
HALFHI
HALFHO: Half freq. Output signal (50% duty)
HALFHO output signal when NOHALF bit clear to LOW
(the same signal as in the HALFHI pin)
Figure 13.7. Half Freq. Sync. Waveform
30
NT68P62-01
(1)
(2)
Figure 13.8. Two Types of Testing Pattern
64ms
VSYNC
Video
Back-Porch
Front-Porch
1ms
HSYNC
Video
Back-Porch
Front-Porch
Figure 13.9. The Porch of Free Running Self Test Pattern
31
NT68P62-01
13.3 Power Saving Mode detect:
Video mode is listed as below, especially from mode 2 to mode 4 just for power saving. All of modes can be detected by
NT68P62 (Figure 13.6). These modes can be easily be detected.
Mode
(1) Normal
(2) Stand-by
(3) Suspend
(4) Off
H-Sync
Active
V-Sync
Active
Inactive
Active
Active
Inactive
Inactive
Inactive
Control Bit Description:
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Control Registers for Synprocessor
$0006
SYNCON
FFH
FFH
-
-
-
-
-
-
-
-
-
-
-
R
INSEN
HSEL
S/ C
W
INSEN
HPOLI
-
ENHSEL
VPOLI
-
HSEL
S/ C
$0007
HV CON
FFH
FFH
HSYNCI VSYNCI
HPOLO
HPOLO
VPOLO
VPOLO
R
-
-
W
ENHOUT
HCL7
ENVOUT
$0008
$0009
HCNT L
HCNT H
00H
HCL6
HCL5
HCL4
HCL3
HCL2
HCH2
-
HCL1
HCH1
-
HCL0
HCH0
-
R
R
00H HCNTOV
CLRHOV
-
-
-
HCH3
-
-
-
-
W
R
$000A
$000B
VCNT L
00H
00H
VCL7
VCL6
VCL5
VCL4
VCL3
VCL2
VCH2
-
VCL1
VCH1
-
VCL0
VCH0
-
VCNT H
VCNTOV
CLRVOV
-
-
VCH5
VCH4
VCH3
R
-
-
-
-
-
-
W
W
$000C
$000D
$000E
FREECON
HALFCON
FFH
FFH
ENPAT
ENHALF
ENHDIFF
PAT0
NOHALF
ENPOL
FREQ2
-
FREQ1
-
FREQ0
-
HALFPOL
ENOVER
-
-
-
W
W
AUTOMUTE FFH
HDIFFVL3 HDIFFVL2 HDIFFVL1 HDIFFVL0
32
NT68P62-01
14. Base Timer (BT)
The BASE TIMER is an 8-bit counter, and its clock source
can be chosen with 1ms or 1ms by setting the BTCLK bit ('0'
for 1ms and '1' for 1ms). The BT can be enabled or disabled
a value by writing a value to the BT register (write only) at
any time and then the BT will start to count up from this
preloaded value. When the BT’ s value reaches FFH, it will
generate a timer interrupt if the timer interrupt is enabled,
and then the counter will wrap around to 00H. The timer’ s
maxium interval is 256ms or 256ms depending on the
BTCLK value.
by the ENBT bit in the BTCON register. The BT will start
counting while clearing the ENBT bit to‘ 0’ . After the chip is
reset, the BTCLK and ENBT bits are set to '1' (the BT is
disabled). Before enabling the BT, it can be preloaded with
1us
0
BT7 BT6 BT5 BT4 BT3 BT2 BT1 BT0
INTMR INT
1
1ms
BTCLK
Control Bit Description:
Addr.
$002E
$002F
Register
BT
INIT
00H
03H
Bit7
BT7
-
Bit6
BT6
-
Bit5
BT5
-
Bit4
BT4
-
Bit3
BT3
-
Bit2
BT2
-
Bit1
Bit0
R/W
W
BT1
BT0
BT CON
W
ENBT
BTCLK
33
NT68P62-01
15. I2C Bus Interface: DDC1 & DDC2B Slave Mode
2
Data transfer: At first, user must put one byte transmitted
data into CH0/1TXDAT register in advance, and activate
Interface: IC bus interface is a two-wire, bi-directional
serial bus which provides a simple, efficient way for data
communication between devices, and minimizes the cost of
connecting among various peripheral devices. NT68P62
I2C bus by setting ENDDC bit to '0'. Then open INTTX0/1
interrupt source by setting INTTX0/1 to '1' in the IEIRQ0/1
registers. On the first 9 rising edges of Vsync, system will
shift out invalid bit in shift register to SDA pin to empty shift
register. When shift register is empty and on next rising
edge of Vsync, it will load data in the CH0/1TXDAT
registers to internal shift register. At the same time,
NT68P62 will shift out MSB bit and generate an INTTX0/1
interrupts to remind user to put next byte data into
CH0/1TXDAT register. After eight rising clocks, there have
been eight bits shifted out in proper order and shift register
becomes empty again. At the ninth rising clock, it will shift
the ninth bit (null bit '1') out to SDA. And on the next rising
edge of Vsync clock, system will generate an INTTX0/1
interrupts again. By the same way, NT68P62 will load new
data from CH0/1TXDAT registers to internal shift register
and shift out one bit right away. Beware that user should
put one new data into CH0/1TXDAT registers properly
before the shift register is empty (the next INTTX0/1
interrupt). If not, the hardware will tansmit the last byte data
repeatedly.
provides two I2C channels. Both of them are shared with
I/O pins and their structures are open drain. When the
system is reset, these channels are originally general I/O
pins structure. All of these I2C bus function will be activated
only after their ENDDC bits are cleared to '0' (CH0/1CON
registers).
DDC1 & DDC2B+ function: Two modes of operation have
been implemented in NT68P62, uni-directional mode
(DDC1 mode) and bi-directional mode (DDC2B+ mode).
These channels will be activated as DDC1 function initially
when users enable DDC function. These channels will
switch automatically to DDC2B+ function from DDC1
function when a low pulse greater than 500ns is detected
on the SCL line. Users can start a master communication
directly from DDC1 communication by clearing MODE bit
in the CH0/1CLK control register.
The channels can return to DDC1 function when users set
the MD1/ 2 bit to '1' in the CH0/1CON registers.
Vsync clock: Only in the separate SYNC mode, can the
Vsync pulse be used as data transfer clock, its frequency
can be up to 25KHz maximum. In composite Vsync mode,
NT68P62 can not transmit any data to SDA pin, regardless
whether the Vsync can be extracted from composite Hsync
signal.
15.1. DDC1 bus interface
Vsync input and SDA pin: In DDC1 function, the Vsync pin
is used as input clock pin and SDA pin is used as data
output pin. This function comprises two data buffers: one is
preloading data buffer for putting one byte data in advance
by user (CH0/1TXDAT), and the other is shift register for
shifting out one bit data to SDA line, which users can not
access directly. These two data buffer cooperate properly.
For the timing diagram please refer to Figure 15.1. After
system resets, the I2C bus interface is in DDC1 mode.
34
NT68P62-01
Control Bit Description:
Addr.
Register
INIT
Bit7
Bit6
Bit5
-
Bit4
Bit3
Bit2
-
Bit1
INTE0
CLRE0
IRQ1
Bit0
R/W
R
$0016
NMIPOLL
00H
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
INTMUTE
CLRMUTE
IRQ0
-
-
-
-
W
$0017
$0019
$001A
$001C
IRQPOLL
IEIRQ0
IEIRQ1
IRQ0
00H
00H
00H
00H
-
-
-
IRQ2
INTRX0
INTRX1
INTRX0
R
INTS0
INTS1
INTS0
CLRS0
INTS1
CLRS1
INTA0
INTA1
INTA0
INTTX0
INTTX1
INTTX0
INTNAK0 INTSTOP0
INTNAK1 INTSTOP1
INTNAK0 INTSTOP0
RW
RW
R
CLRA0 CLRTX0
INTA1 INTTX1
CLRA1 CLRTX1
CLRRX0 CLRNAK0 CLRSTOP0
INTRX1 INTNAK1 INTSTOP1
CLRRX1 CLRNAK1 CLRSTOP1
W
$001D
IRQ1
00H
R
W
Control Register for DDC1/2B+ of Channel 0
$0021
$0022
$0023
$0024
CH0ADDR
A0H
ADR7
TX7
ADR6
TX6
ADR5
TX5
RX5
-
ADR4
TX4
ADR3
TX3
ADR2
TX2
RX2
-
ADR1
TX1
-
W
W
R
CH0TXDAT 00H
CH0RXDAT 00H
TX0
RX0
-
RX7
RX6
RX4
RX3
RX1
CH0CON
E0H
START
STOP
TXACK
W
MD1/
-
-
START
-
STOP
-
RXACK
-
-
R
$0025
CH0CLK
FFH
A0H
DDC2BR2 DDC2BR1
DDC2BR0
W
Control Register for DDC1/2B+ of Channel 1
$0026
$0027
$0028
$0029
CH1ADDR
ADR7
TX7
ADR6
TX6
ADR5
TX5
RX5
-
ADR4
TX4
ADR3
TX3
ADR2
TX2
RX2
-
ADR1
TX1
-
W
W
R
CH1TXDAT 00H
CH1RXDAT 00H
TX0
RX0
-
RX7
RX6
RX4
RX3
RX1
CH1CON
CH1CLK
E0H
FFH
START
STOP
TXACK
W
MD1/
-
-
START
-
STOP
-
RXACK
-
-
R
$002A
DDC2BR2 DDC2BR1
DDC2BR0
W
35
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grT)iXs●Dt●eArT
te data
Ao●y●TtaadrteDaaeistxatetrb●y●
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e
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g
NT68P62-01
Figure 15.1. DDC1 Mode Timing Diagram
15.2. DDC2B + Slave & Master Mode Bus Interface
The built-in DDC2B+ I2C bus Interface features as follows :
1. After entering to DDC1 function and clearing this bit, the
system will be changed from DDC1 to DDC2B+
MASTER mode operation.
- SLAVE mode (NT68P62 is addressed by a master
which drives SCL signal)
2. After entering to DDC2B+ slave mode function and
clearing this bit, the system will changed from slave
mode into master mode operation.
- MASTER mode (NT68P62 addresses external device
and send out SCL clock)
- Compatible with I2C bus standard
- One default address (A0H) and one programable
address
As clearing
bit, system will send out a 'START'
- Automatic wait state insertion
- Interrupt generation for status control
- Detection of START and STOP signals
condition and wait for user to put the calling address into
CH0/1TXDAT control register. Notice that user must
predetermine the direction of master mode transmission
before putting calling address.
Below is the DDC2B+ function with channel 0, and the
manipulation of channel 1 is the same as channel 0.
The DDC2B+ will be activated as SLAVE mode initially.
Users can switch to MASTER mode by clearing the
bit under either of these conditions listed as follows:
36
O●N●N
●
●
●
NT68P62-01
Figure 15.2. DDC2B Data Transfer
37
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vMic d)e Timing Diagram
oe
NT68P62-01
Figure 15.3. DDC2B Write Mode Spec.
38
wk6aodne2l2erlodrdewredgsteolese
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giacxeettaertnoF
a
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M
rvsoitc e)atTaiminintogT
d
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d
D
XiDagATambuffer
r
NT68P62-01
Figure 15.4. DDC2B Read Mode Spec.
39
NT68P62-01
15.3. DDC2B Slave Mode Bus Interface
system receives an address data from an external device, it
will store it in the CH0RXDAT register. The system
supports 'A0' default address and another one set of
addresses which can be accessed by writting the
CH0ADDR register. Upon receiving the calling address
from an external device, the system will compare this
received data with the default 'A0' address and data in the
CH0ADDR register. Either of these address matched, the
system will set the INTA0 bit in the IRQ0 register. If the
user sets INTA0 bit to '1' (in IEIRQ0 register) in advanced
and addresses match, the NT68P62 will generate a INTA0
interrupt. Under the address matching condition, the
NT68P62 will send an acknowledge bit to an external
device. If address does not match, the NT68P62 will not
generate INTA0 interrupt and neglect the data change on
SDA line in the future.
Enable I2C and INTS: After user clears the
to ‘ 0’ ,
NT68P62 will enter into DDC1 mode, and it will switch to
DDC2B SLAVE mode while a low pulse is detected on SCL
line. The DDC2B bus consists of two wires, SCL and SDA;
SCL is the data transmission clock and SDA is the data
line. NT68P62 will remind user that the mode has changed
by generating a INTS interrupt. When users set MD1/ to
'1' at this time, the NT68P62 will return back to DDC1
mode. (For DDC2B please refer to Figure 15.2.) The figure
2
exhibits what are important in IC: START signal, slave
ADDRESS, transferred data (proceed byte by byte) and a
STOP signal.
Start condition: When SCL & SDA lines are at HIGH state,
an external device (master) may initiate communication by
sending a START signal (defined as SDA from high to low
transition while SCL is at high state). When there is a
START condition, NT68P62 will set the 'START' bit to '1'
and user can poll this status bit to control DDC2B
transmission at any time. This bit will keep '1' until user
clears it. After sending a START signal for DDC2B
communication, an external device can repeatedly send
start condition without sending a STOP signal to terminate
this communication. This is used by external device to
communicate with another slave or with the same slave in
different mode (Read or Write mode) without releasing the
bus.
Data transmission direction: In INTA0 interrupt servicing
routine, user must check the LSB of address data in
CH0RXDAT register. According to I2C bus protocol, this bit
indicates the DDC2B data transfer direction in later
transmission; '1' indicates a request for 'READ MODE'
action (external master device read data from system), '0'
indicates a 'WRITE MODE' action (external master device
write data to system). The timing about READ mode and
WRITE mode please refer to Figure 15.3 and Figure 15.4.
The data transfer can proceeded byte by byte in a direction
specified by the R/
is received.
bit after a successful slave address
Address matched and INTA0: After the START condition, a
The system will switch to either 'READ' mode or 'WRITE'
mode automatically which is determined by this direction
bit.
slave address is sent by an external device. When I2C bus
interface changes to DDC2B mode, NT68P62 will act as a
receiver first to receive this one byte data. This address
data is 7 bits long followed by the eighth bit (R/W) that
indicates data transfer direction. When the NT68P62
INTSTOP
STOP Detector
TXDAT
SDA
INTTX
out
TXACK
INTNAK
in9 bits Shift Register
clk
VSYNC
SCL
ENDDC
INTRX
RXDAT
INTS
INTA
R/W
Compare Logic
MD1/2
MODE
ADDR
DDC2BR [2..0]
Clock Generator
Figure 15.5. DDC Structure Block
40
NT68P62-01
Data transfer and wait: The data on the SDA line must be
stable during the HIGH period of the clock on the SCL line.
The HIGH and LOW state of the SDA line can only change
when the clock signal on the SCL line is LOW. Each byte
data is eight bits long and one clock pulse for one bit of
data transfer. Data is transferred with the most significant
bit (MSB) first. In the wired-AND connection, any slower
device can hold the SCL line LOW to force the faster
device into a wait state. Data transmition will be suspended
until the slower device is ready for the next byte transfer by
releasing the SCL line.
The INTTX0 on the READ mode: External device read data
from NT68P62. At INTTX0 interrupt, the system will load
new data from CH0TXDAT register which has been put by
user beforehand into internal shift register and continue
sending out this new data. After this new loading data be
shifted out according every SCL clock, system will request
user to put next byte data into CH0TXDAT register.
If both of shift register and CH0TXDAT register are empty
and user still not load data to CH0TXDAT register, the SCL
will be held LOW and waiting by NT68P62 after receiving
the acknowledgment bit.
Acknowledge: The acknowledgment will be generated at
ninth clock by whom receiving data. In the WRITE MODE,
NT68P62 system must respond to this acknowledgment.
At SCL holded low by system, after user has put one new
byte data into CH0TXDAT register, the SCL will be
released for generation of SCL transmission clock. At this
time, system will load this byte data into shift register and
generate a INTTX0 interrupt again to remind user putting
next byte into CH0TXDAT register. The timing diagram
refer to Figure 15.4.
Users should clear the
bit in the CH0CON to open
the ‘ ACK’ function. After receiving one byte data from
external device, NT68P62 will automatically send this
acknowledgment bit.
In the READ mode, an external device must respond to the
acknowledgment bit after every byte data is sent out. The
system will set the INTNAK bit when external device does
not send out the '0' acknowledgment bit. Furthermore, user
can open this interrupt source by clearing the INTNAK bit in
the IEIRQ0 register.
After every one byte data transfer, system will monitor if
external master device has sent out this acknowledgment
bit or not. If not, system will set the INTNAK bit (the
acknowledgment is LOW signal). Users will get a INTNAK
interrupt if INTNAK has been enabled as a interrupt source.
The INTTX0 & INTRX0 interrupt: After NT68P62 complete
one byte transmission or receiving, it will generate an
INTTX0 (READ mode) & INTRX0 (WRITE mode) interrupts.
These interrupts are generated at the falling edge of the
ninth clock. Users can control the flow of DDC2B
transmission at these interrupts.
STOP condition: When SCL & SDA line have been
released (hold on 'high' state), DDC2B data transfer is
always terminated by a STOP condition generated by
external device. A STOP signal is defined as a LOW to
HIGH transition of SDA while SCL is at HIGH state. When
there is a STOP condition, NT68P62 will set the 'STOP' bit
& INTSTOP bit to '1' and user can poll this status bit or
open a INTSTOP interrupt to control DDC2B transmission
at any time. This bit will keep '1' until user clears it by
writing '1' to this bit. Notice the SCL and SDA lines must
The INTRX0 on the WRITE mode: NT68P62 read data
from external master device. When users detect an
INTRX0 interrupt, it means there has one byte data
received and user can read out by accessing CH0RXDAT
control register. At the same time, if user responded an
'ACK' signal beforehand, the shift register will send out this
'ACK' bit (low voltage) and continue to receive the next byte
data. If both of shift register and CH0RXDAT register are
full and user still did not load data from CH0RXDAT
register, the SCL will be held LOW and waiting for
NT68P62. After user obtains one byte data from
CH0RXDAT register, the SCL will be released for
generation of SCL transmission clock. External device can
continue sending next byte data to NT68P62. The timing
diagram refers to Figure 15.3. User must responde a NAK
signal in advance to stop the transmission.
conform to I2C bus specifications. For the software
flowchart can please refer Figure 15.6. Please refer to the
standard I2C bus specification for details.
Change to DDC1 mode: After an external device terminates
DDC2 transmission by sending a STOP condition, users
can set MD1/ to '1' for changing to DDC1 mode. On the
other hand, when the SCL line has been released (pulled-
up), user can force NT68P62 to DDC1 mode
communication at any time.
41
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NT68P62-01
Figure 15.6. Slave Mode INT Operation
42
NT68P62-01
15.4 DDC2B+ Master Mode Bus Interface
Most of the DDC manipulation is the same as SLAVE mode
except the SCL clock generation. In the MASTER mode,
the control of SCL clock source belongs to NT68P62. Users
must set the calling address and transmission direction in
beforehand, the shift register will send out an 'ACK' bit (low
voltage) and continue to receive next byte data. If both the
shift register and CH0RXDAT register are full and user still
did not load data from CH0RXDAT register, the SCL will be
held LOW and wait for NT68P62. After user has received
one byte data from CH0RXDAT register, the SCL will be
released for generation of SCL transmission clock. An
external device can continue sending next byte data to
NT68P62. Refer Figure 15.7 for the timing diagram. User
must respond to a NAK signal in advance to stop the
transmission. Before the last two bytes of data is received,
user should respond an 'NAK' signal. Then, system will
send out 'NAK' bit after receiving the last byte data and
'STOP' condition to notify the slave terminated current
transmission.
advance. Access the
&
bits to control the
transmission
flow
of
DDC2B+
master
mode
communication.
Start condition: After user clearing
&
bit,
the system will generate a 'START' condition on the SCL &
SDA lines and wait for user to put the calling address into
TXDAT buffer and send to SDA line. The frequency of SCL
is dependant on the baud-rate setting value (DDCBR0 -
DDCBR2) in register CH0CLK. And the data transmission
direction will be dependant on the
calling address, '1' for read operation and '0' for write
operation.
bit and the LSB of
The INTTX0 on the WRITE mode: External device read
data from NT68P62. At INTTX0 interrupt, the system will
load new data from CH0TXDAT register which has been
put by user beforehand into internal shift register and
continue sending out this new data. After this new loading
data be shifted out according every SCL clock, system will
request user to put next byte data into CH0TXDAT register.
Calling address: Calling address is 8 bits long. It should be
put in the CH0TXDAT. The setting of LSB bit in this TXDAT
buffer should be as same as
bit.
STOP condition: There are several cases that the system
will send out 'STOP' condition on the SCL & SDA lines.
First, in the 'READ' operation, if user sets TXACK bit to '1',
the system will send out 'NAK' condition on the bus after
receiving one byte data and then send out 'STOP' condition
automatically later. Second, in the 'START' condition and
after sending out calling address, if no slave has respond to
a 'ACK' signal, the master will send out 'STOP' condition
If both of shift register and CH0TXDAT register are empty
and user still not load data to CH0TXDAT register, the SCL
will be held LOW and wait for NT68P62 after receiving the
acknowledgment bit.
If SCL is held low by system, and user has put one new
byte data into CH0TXDAT register, the SCL will be
released for generation of SCL transmission clock. At this
time, system will load this byte data into shift register and
generate an INTTX0 interrupt again to remind user putting
next byte into CH0TXDAT register. Refer to Figure 15.8 for
the timing diagram.
automatically. Third, if user sets
bit to '1', the
system will generate a 'STOP' condition after the current
byte transmission is done. Notice that if slave device did
not released SCL and SDA line, the system can not send
out 'STOP' condition.
After 'STOP' condition, the master will release SCL & SDA
lines and return to SLAVE mode.
Repeat start condition: If clearing the
bit to '0' in
the ' WRITE' operation, system will send out a R' EPEAT
START'. Notice that if slave device did not release SCL and
SDA line, the system can not send out 'REPEAT START
condition.
The INTTX0
&
INTRX0 interrupt: After NT68P62
completing one byte transmission or receiving, it will
generate an INTTX0 (WRITE mode) & INTRX0 (READ
mode) interrupts. Users can control the flow of DDC2B
transmission at these interrupts.
SCL baud rate selection: There are three Baud Rate bits for
user to select one of eight clock rates on the SCL line. After
system reset, the default value of these Baud Rate bits
(DDC2BR0-2) are '111'.
The INTRX0 on the read mode: NT68P62 reads data from
external slave device. When users detect a INTRX0
interrupt, it means there is one byte data received and user
can read out by accessing CH0RXDAT control register. At
the same time, if the user responded an 'ACK' signal
43
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NT68P62-01
DDC2BR2
0.00
DDC2BR1
0.00
DDC2BR0
0.00
Baud Rate
400K
0.00
0.00
1.00
200K
0.00
1.00
0.00
100K
0.00
1.00
1.00
50K
1.00
0.00
0.00
25K
1.00
0.00
1.00
12.5K
6.25K
3.125K
1.00
1.00
0.00
1.00
1.00
1.00
44
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NT68P62-01
45
NT68P62-01
Control Register:
Addr
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Control Register for Polling Interrupt Groups
$0016
NMIPOLL
00H
-
-
-
-
-
-
-
-
-
-
-
-
INTE0
INTMUTE
R
CLRE0
CLRMUT
E
W
$0017
IRQPOLL
00H
-
-
-
-
-
IRQ2
IRQ1
IRQ0
R
Control Registers of Interrupt Enable
$0018
$0019
$001A
$001B
IENMI
IEIRQ0
IEIRQ1
IEIRQ2
00H
00H
00H
00H
-
-
-
-
-
-
-
-
-
-
-
-
INTE0
INTNAK0
INTNAK1
INTE1
INTMUTE
INTSTOP0
INTSTOP1
INTMR
W
W
W
W
INTS0
INTS1
-
INTA0
INTA1
-
INTTX0
INTTX1
-
INTRX0
INTRX1
INTV
Control Registers for Polling Interrupt Requests
$001C
$001D
$001E
IRQ0
IRQ1
IRQ2
00H
00H
00H
-
-
-
-
-
-
-
-
-
-
-
-
INTS0
CLRS0
INTS1
CLRS1
-
INTA0
CLRA0 CLRTX0
INTA1 INTTX1
CLRA1 CLRTX1
INTTX0
INTRX0
CLRRX0
INTRX1
CLRRX1
INTV
INTNAK0
INTSTOP0
R
W
R
CLRNAK0 CLRSTOP0
INTNAK1 INTSTOP1
CLRNAK1 CLRSTOP1
W
R
-
-
INTADC
INTE1
INTMR
-
CLRADC
CLRV
CLRE1
CLRMR
W
Control Register for DDC1/2B+ of Channel 0
$0021
CH0ADDR A0H
ADR7
TX7
ADR6
TX6
ADR5
TX5
RX5
-
ADR4
TX4
ADR3
TX3
ADR2
TX2
RX2
-
ADR1
TX1
-
W
W
R
$0022 CH0TXDAT 00H
$0023 CH0RXDAT 00H
TX0
RX0
-
RX7
RX6
RX4
RX3
RX1
$0024
CH0CON
E0H
START
STOP
W
MD1/
-
-
START
-
STOP
-
-
-
-
R
$0025
CH0CLK
FFH
DDC2BR2 DDC2BR1 DDC2BR0
W
Control Register for DDC1/2B+ of Channel 1
$0026
$0027
$0028
$0029
CH1ADDR A0H
CH1TXDAT 00H
CH1RXDAT 00H
ADR7
TX7
ADR6
TX6
ADR5
TX5
RX5
-
ADR4
TX4
ADR3
TX3
ADR2
TX2
RX2
-
ADR1
TX1
-
W
W
R
TX0
RX0
-
RX7
RX6
RX4
RX3
RX1
CH1CON
E0H
START
STOP
W
MD1/
-
-
START
-
STOP
-
-
-
R
$002A
CH1CLK
FFH
DDC2BR2 DDC2BR1 DDC2BR0
W
46
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NT68P62-01
47
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NT68P62-01
48
NT68P62-01
User Referenced Flow Chart
Comparison With NT68P61A
Item
Maximum ROM Size
RAM Size
NT68P61A Status
24K Bytes
NT68P62 Status
32K Bytes
Notes
256 Bytes
512 Bytes
PWM Channel
14 channels
13 channels
5V & 12V Open Drain O/P
31.25 KHz
5V Open Drain O/P Only
62.5 KHz
PWM Channel Refresh
Rate
A/D Converter Channel
V Counter Bit No.
2 channels
12 Bits
4 channels
14 Bits
6 bit resolution
(handle Vsync freq. down
to 30.5Hz)
(handle Vsync freq. down
to 7.6Hz)
H Interval
8.192 ms
16.384 & 32.768 ms
Auto Mute
X
2 sets
X
O
5 sets
Free Run Freq.
Self Test Pattern
IIC Bus Channel
IIC Bus Baud Rate
IIC Mode Supported
External Interrupt
NMI Interrupt
O
2 self test patterns
1 channel
Max 100KHz
DDC1/2B
1 set
2 channels
Max 400KHz
DDC1/2B+
2 sets
X
O
Interrupt Trigger Edge
Programmable
X
O
MASK ROM option
4K/8K/16K/24K
24K/32K
49
NT68P62-01
°
DC Electrical Characteristics (VDD = 5V, TA = 25 C, Oscillator freq. = 8MHz, Unless otherwise specified)
Symbol
IDD
Parameter
Operating Current
Input High Voltage
Min.
Typ.
Max.
Unit
mA
V
Conditions
20
No Loading
VIH1
2
P00-P07, P12-P16,
P20-P27, P40, P41
, VSYNCI, HSYNCI, HALFHI INTE0,
INTE1
VIH2
VIL1
Input High Voltage
Input Low Voltage
3
V
V
SCL0/1, SDA0/1,P10, P11, P30, P31 pins
0.8
P00-P07, P12-P16,
P20-P27, P40, P41
, VSYNCI, HSYNCI, HALFHI,
INTE0, INTE1
VIL2
IIH
Input Low Voltage
Input High Current
1.5
V
SCL0/1, SDA0/1, P10, P11 P30 ,P31 pins
-200
-350
P00-P07, P10-P16,
P20-P27, P40,P41
mA
VSYNCI, HSYNCI, HALFHI,
(VIH=2.4V);
VOH1
Output High Voltage
2.4
V
P00-P07, P10-P16, P40,
P41 (IOH = -100mA)
VSYNCO, HSYNCO (IOH = -4mA)
HALFHO (IOH = -4mA)
PATTERN, P20-P27 (IOH = -10mA)
external applied voltage
VOH2
VOL
Output High Voltage
(DAC0-DAC12)
5
V
V
Output Low Voltage
0.4
P00-P07, P10-P16, P40,
P41, DAC0-12 (IOL= 4mA)
SCL0/1, SDA0/1 (IOL= 5mA)
VSYNCO, HSYNCO (IOL = 4mA)
HALFHO (IOL = 4mA)
PATTERN, P20-P27 ( IOL= 10mA)
ROL
50
11
100
22
150
33
KW
KW
Pull Down Resistor (
)
ROH1
Pull up Resistor
(INTE0, INTE1)
ROH2
ROH3
Pull up Resistor
(PORT0, PORT1, & PORT4)
11
11
22
22
33
33
KW
KW
Pull up Resistor
(HSYNCI & VSYNCI & HALFI)
50
NT68P62-01
°
AC Electrical Characteristics (V =5V, T =25 C, Oscillator freq.=8MHz, unless otherwise specified)
Symbol
Fsys
Parameter
System Clock
Min.
Typ.
Max.
Unit
MHz
ms
Conditions
8
tCNVT
A/D Conversion Time
A/D Converter Error
750
1
Voffset
Vlinear
LSB
V
A/D Input Dynamic Range of
Linearity Conversion
1.5
3.5
tDELAY
The Delay Time of Vsync input
and Vsync output
20
ns
Composite sync with fixed
delay (Refer Figure 13.5)
tRESET
Fvsync
tVPW
Reset Pulse Width Low
Vsync Input Frequency
Vsync Input Pulse Width
Hsync Input Frequency
2
8
tCYCLE
Hz
tCYCLE = 2/ Fsys
25K
2000
120
7
tVSYNC = 1/Fvsync
ms
Fhsync
tHPW1
KHz
ms
tHSYNC = 1/Fhsync
Maximum Pulse Width of Hsync
Input High (Positive Polarity)
0.25
tHPW2
tERROR1
tERROR2
Minimum Pulse Width of Hsync
Input Low (Positive Polarity)
9.125
ms
ms
Counting Deviation of Base
Timer
1
1
1ms clock source
Counting Deviation of Base
Timer
ms
1ms clock source
51
●
ut
NT68P62-01
DDC1 Mode
Symbol
Parameter
Vsync High Time
Min.
Typ.
Max.
Unit
Conditions
tVPW
0.50
2000
ms
Fvsync
tDD
Vsync Input Frequency
Data Valid
25K
500
500
Hz
ns
ns
tVSYNC =1/Fvsync
200
tMODE
Time for Transition to DDC2B
Mode
52
NT68P62-01
DDC2B+ Mode
Symbol
Parameter
Min.
Typ.
Max.
Unit
fSCL
tBUF
SCL Clock Frequency
400
KHz
Bus Free Between a STOP and START Condition
Hold Time for START Condition
LOW Period of The SCL Clock
HIGH Period of The SCL Clock
Set-up Time for a Repeated START Condition
Data Hold Time
4.7
0.8
1.3
0.8
1.3
200
300
ms
ms
ms
ms
ms
ns
ns
ms
ns
ms
tHD; STA
tLOW
tHIGH
tSU; STA
tHD; DAT
tSU; DAT
tR
Data Set-up Time
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Set-up Time for STOP Condition
1
tF
300
tSU; STO
0.80
53
NT68P62-01
Ordering Information
Part No.
NT68P62
NT68P62U
Packages
40L P-DIP
42L S-DIP
54
ne
NT68P62-01
Package Information
P-DIP 40L Outline Dimensions
unit: inches/mm
Symbol
Dimensions in inches
0.210 Max.
Dimensions in mm
5.33 Max.
A
A1
A2
0.010 Min.
0.25 Min.
0.155±0.010
3.94±0.25
B
B1
C
0.018 +0.004
-0.002
0.46 +0.10
-0.05
0.050 +0.004
-0.002
1.27 +0.10
-0.05
0.010 +0.004
-0.002
0.25 +0.10
-0.05
D
E
2.055 Typ. (2.075 Max.)
0.600±0.010
52.20 Typ. (52.71 Max.)
15.24±0.25
E1
e1
L
0.550 Typ. (0.562 Max.)
0.100±0.010
13.97 Typ. (14.27 Max.)
2.54±0.25
0.130±0.010
3.30±0.25
0° ~ 15°
0° ~ 15°
16.64±0.89
2.36 Max.
a
eA
0.655±0.035
0.093 Max.
S
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E1 does not include resin fins.
3. Dimension S includes end flash.
55
ne
NT68P62-01
Package Information
S-DIP 42L Outline Dimensions
unit: inches/mm
Symbol
Dimensions in inches
0.200 Max.
Dimensions in mm
5.08 Max.
A
A1
A2
b
0.020 Min.
0.51 Min.
0.157 Max.
4.0 Max.
0.051 Max.
0.031 Min.
0.021 Max.
0.016 Min.
1.3 Max.
0.8 Min.
b1
0.53 Max.
0.40 Min.
c
0.013 Max.
0.010 Min.
1.531 Max.
1.512 Min.
0.32 Max.
0.23 Min.
38.9 Max.
38.4 Min.
(1)
D
(1)
E
0.551 Max.
0.539 Min.
0.070
14.0 Max.
13.7 Min.
1.778
e
e1
L
0.600
15.24
0.126 Max.
0.114 Min.
0.622 Max.
0.600 Min.
0.675 Max.
0.626 Min.
0.007
3.2 Max.
2.9 Min.
ME
MH
15.80 Max.
15.24 Min.
17.15 Max.
15.90 Min.
0.18
w
Z(1)
0.068 Max.
1.73 Max.
Notes:
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
56
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