P4C1256L-70PC [ETC]

LOW POWER 32K x 8 STATIC CMOS RAM; 低功耗32K x 8静态CMOS RAM


型号：	P4C1256L-70PC
厂家：	ETC
描述：	LOW POWER 32K x 8 STATIC CMOS RAM 低功耗32K x 8静态CMOS RAM 内存集成电路静态存储器光电二极管
文件：	总8页 (文件大小：84K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

P4C1256L

LOW POWER 32K x 8

STATIC CMOS RAM

FEATURES

V_CCCurrent (Commercial/Industrial)

— Operating: 70mA/85mA

— CMOS Standby: 100µA/100µA

Access Times

—55/70 (Commercial or Industrial)

Single 5 Volts ±10% Power Supply

Easy Memory Expansion Using CE and OE

Inputs

Common Data I/O

Three-State Outputs

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Automatic Power Down

Packages

—28-Pin 600 mil DIP

—28-Pin 330 mil SOP

DESCRIPTION

The P4C1256L is a 262,144-bit low power CMOS locations are specified on address pinsA₀toA₁₄. Read-

static RAM organized as 32Kx8. The CMOS memory ing is accomplished by device selection (CE and out-

requires no clocks or refreshing, and has equal access put enabling (OE) while write enable (WE) remains

and cycle times. Inputs are fully TTL-compatible. The HIGH. By presenting the address under these condi-

RAM operates from a single 5V±10% tolerance power tions, the data in the addressed memory location is pre-

supply.

sented on the data input/output pins. The input/output

pins stay in the HIGH Z state when either CE or OE is

Access times of 55 ns and 70 ns are available. CMOS HIGH or WE is LOW.

is utilized to reduce power consumption to a low level.

Package options for the P4C1256L include 28-pin 600

mil DIP and 28-pin 330 mil SOP packages.

The P4C1256L device provides asynchronous opera-

tion with matching access and cycle times. Memory

PIN CONFIGURATION

FUNCTIONAL BLOCK DIAGRAM

262,144-BIT

(8)

MEMORY

ARRAY

I/O

A11

INPUT

DATA

COLUMN I/O

CONTROL

A₁₀

I/O

I/0₈

I/0₇

I/0₆

I/0₅

I/0₄

I/0₁

I/0₂

COLUMN

SELECT

I/0₃

• • • • • •

GND

(7)

DIP (P6), SOP (S11-2)

TOP VIEW

Means Quality, Service and Speed

1Q97

125

P4C1256L

RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE

Temperature Range (Ambient)

Commercial (0°C to 70°C)

Supply Voltage

4.5V ≤ V_CC≤ 5.5V

4.5 ≤ V_CC≤ 5.5V

Industrial (-40°C to 85°C)

MAXIMUM RATINGS

Stresses greater than those listed can cause permanent damage to the device. These are absolute stress

ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those

given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can

adversely affect device reliability.

Symbol

V_CC

Parameter

Supply Voltage with Respect to GND

Terminal Voltage with Respect to GND (up to 7.0V)

Operating Ambient Temperature

Storage Temperature

Min

-0.5

Max

7.0

Unit

V_TERM

T_A

V_CC+ 0.5

-55

-65

125

150

°C

S_TG

I_OUT

I_LAT

Output Current into Low Outputs

Latch-up Current

>200

DC ELECTRICAL CHARACTERISTICS

(Over Recommended Operating Temperature & Supply Voltage)

Max

Parameter

Unit

Min

Symbol

Test Conditions

Output High Voltage

(I/O₀- I/O₇)

V_OH

I_OH= –1mA, V_CC= 4.5V

2.4

I_OL= 2.1mA

0.4

V_OL

Output Low Voltage

(I/O₀- I/O₇)

2.2

V_CC+ 0.3

0.8

V_IH

V_IL

Input High Voltage

Input Low Voltage

-0.5

GND ≤ V_IN≤ V_CC

Ind'l.

-5

-2

µA

Input Leakage Current

I_LI

Com'l.

GND ≤ V_OUT≤ V_CC

CE ≥ V_IH

Ind'l.

Com'l.

-5

-2

I_LO

Output Leakage Current

µA

I_SB

V_CC= 5.5V, I_OUT= 0 mA

V_CCCurrent

TTL Standby Current

(TTL Input Levels)

CE = V_IH

V_CCCurrent

V_CC= 5.5V, I_OUT= 0 mA

100

µA

I_SB1

CMOS Standby Current

(CMOS Input Levels)

CE ≥ V_CC-0.2V

126

P4C1256L

CAPACITANCES

(V_CC= 5.0V, T_A= 25˚C, F = 1.0 MHz)

Unit

Symbol

Parameter

Test Conditions

Max

C_IN

Input Capacitance

V_IN= 0V

_OUT= 0V

C_OUT

Output Capacitance

POWER DISSIPATION CHARACTERISTICS VS. SPEED

Temperature

Parameter

Unit

Symbol

-55

-70

Range

-70

Commercial

Industrial

I_CC

Dynamic Operating Current

*Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate.

The device is continuously enabled for writing, i.e. CE and WE ≤ V_IL(max), OE is high. Switching

inputs are 0V and 3V.

**As above but @ f=1 MHz and V_IL/ V_IH= 0V/ V_CC.

AC ELECTRICAL CHARACTERISTICS - READ CYCLE

(Over Recommended Operating Temperature & Supply Voltage)

-70

-55

Parameter

Unit

Symbol

Max

Min

Max

Min

t_RC

Read Cycle Time

Address Access Time

t_AA

t_AC

t_OH

Chip Enable Access

Time

Output Hold from

Address Change

Chip Enable to

Output in Low Z

t_LZ

Chip Disable to

Output in High Z

t_HZ

Output Enable Low

to Data Valid

t_OE

t_OLZ

t_OHZ

t_PU

Output Enable Low

to Low Z

Output Enable High

to High Z

Chip Enable to

Power Up Time

t_PD

Chip Disable to

Power Down Time

127

P4C1256L

READ CYCLE NO. 1 (OE CONTROLLED)⁽¹⁾

(5)

ADDRESS

(4)

OLZ

(4)

OHZ

(4)

DATA OUT

NOTES:

1. WE is HIGH for READ cycle.

4. Transition is measured ± 200 mV from steady state voltage

prior to change, with loading as specified in Figure1. This

parameter is sampled and not 100% tested.

5. READ Cycle Time is measured from the last valid address to

the first transitioning address.

2. CE is LOW and OE is LOW for READ cycle.

3. ADDRESS must be valid prior to, or coincident with

CE transition LOW.

READ CYCLE NO. 2 (ADDRESS CONTROLLED)

(5)

ADDRESS

DATA OUT

DATA VALID

PREVIOUS DATA VALID

READ CYCLE NO. 3 (CE CONTROLLED)

(8)

DATA OUT

DATA VALID

HIGH IMPEDANCE

I_CC

SUPPLY

CURRENT

128

P4C1256L

AC CHARACTERISTICS - WRITE CYCLE

(Over Recommended Operating Temperature & Supply Voltage)

-55

-70

Symbol

Parameter

Unit

Min

Max

Min

Max

t_WC

t_CW

Write Cycle Time

Chip Enable Time

to End of Write

t_AW

t_AS

t_WP

t_AH

t_DW

Address Valid to

End of Write

Address Set-up

Time

Write Pulse Width

Address Hold

Time

Data Valid to End

of Write

Data Hold Time

t_DH

t_WZ

Write Enable to

Output in High Z

t_OW

Output Active from

End of Write

WRITE CYCLE NO. 1 (WE CONTROLLED)⁽⁶⁾

(9)

ADDRESS

DATA VALID

DATA IN

(4,7)

(4)

(7)

DATA OUT

DATA UNDEFINED

HIGH IMPEDANCE

Notes:

6. CE and WE must be LOW for WRITE cycle.

7. OE is LOW for this WRITE cycle to show twz and tow.

8. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.

9. Write Cycle Time is measured from the last valid address to the first transitioning address.

129

P4C1256L

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE CONTROLLED)⁽⁶⁾

(9)

ADDRESS

DATA VALID

DATA IN

(6)

DATA OUT

HIGH IMPEDANCE

TRUTH TABLE

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

3ns

Mode

CE OE WE I/O

Power

Input Rise and Fall Times

Standby

High Z Standby

Input Timing Reference Level

1.5V

Output Timing Reference Level

Output Load

High Z Active

D_OUTDisabled

See Figures 1 and 2

D_OUT

Active

Read

Write

High Z Active

+5V

= 638.7 Ω

1800 Ω

= 1.77 V

OUT

30pF* (5pF* for t , t , t

HZ LZ OHZ

990 Ω

30pF* (5pF* for t , t

HZ LZ OHZ

)

and t

OLZ WZ OW

)

and t

OLZ WZ OW

Figure 1. Output Load

Figure 2. Thevenin Equivalent

* including scope and test fixture.

Note:

To avoid signal reflections, proper termination must be used; for

example, a 50Ω test environment should be terminated into a 50Ω

load with 1.77V (Thevenin Voltage) at the comparator input, and a

589Ω resistor must be used in series with D_OUTto match 639Ω

(Thevenin Resistance).

Because of the high speed of the P4C1256L, care must be taken

when testing this device; an inadequate setup can cause a normal

functioning part to be rejected as faulty. Long high-inductance leads

that cause supply bounce must be avoided by bringing the V_CCand

ground planes directly up to the contactor fingers. A 0.01 µF high

frequency capacitor is also required between V_CCand ground.

130

P4C1256L

DATA RETENTION

Symbol

Min

Parameter

Max

Unit

Test Conditions

CE ≥ V_CC-0.2V,

V_DR

V_CCfor Data Retention

2.0

5.5

V_IN≥ V_CC-0.2V or V_IN≤ 0.2V

I_CCDR(1)

Data Retention Current

V_DR= 2.0V

µA

V_DR= 3.0V

Chip Deselect to Data

Retention Time

t_CDR

See Retention Waveform

t_R

Operating Recovery Time

1. CE ≥ V_DR-0.2V

LOW V_CCDATA RETENTION WAVEFORM

Data Retention Mode

4.5V

CDR

2.2V

CE ≥ V

-0.2V

2.2V

131

P4C1256L

TEMPERATURE RANGE SUFFIX

PACKAGE SUFFIX

Package

Description

Suffix

Temperature

Description

Range Suffix

Commercial Temperature Range,

0˚C to +70˚C

Plastic DIP, 600 mil wide standard

SOP, 330 mil wide standard

Industrial Temperature Range,

-40˚C to +85˚C

ORDERING INFORMATION

Performance Semiconductor's part numbering scheme is as follows:

P4C 1256L

Temperature Range: C,I

Package Code: P, S

Speed (Access/Cycle Time): 55,70

Device Number: 1256L

Static RAM Prefix

SELECTION GUIDE

The P4C1256L is available in the following temperature, speed and package options.

Speed (ns)

Temperature

Range

Package

-70

-55

-70PC

-70SC

Commercial

Temperature

Plastic DIP 600

Plastic SOP 330

-55PC

-55SC

-70PI

-70SI

Industrial

Temperature

Plastic DIP 600

Plastic SOP 330

-55PI

-55SI

132

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