P50N02LD [ETC]
N-Channel Logic Level Enhancement Mode Field Effect Transistor; N沟道逻辑电平增强模式场效应晶体管
| 型号： | P50N02LD |
| 厂家： | 
ETC |
| 描述： | N-Channel Logic Level Enhancement Mode Field Effect Transistor |
| 文件： | 总3页 (文件大小：47K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P50N02LD
NIKO-SEM
TO-252 (D PAK)
D
PRODUCT SUMMARY
1. GATE
2. DRAIN
3. SOURCE
V(BR)DSS
25
RDS(ON)
12m
ID
G
55A
Ω
S
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS SYMBOL
Gate-Source Voltage VGS
LIMITS
±20
55
UNITS
V
TC = 25 °C
Continuous Drain Current
ID
TC = 100 °C
38
A
Pulsed Drain Current1
Avalanche Current
IDM
IAR
150
36
Avalanche Energy
Repetitive Avalanche Energy2
L = 0.1mH
L = 0.05mH
TC = 25 °C
TC = 100 °C
EAS
EAR
250
8.6
80
mJ
W
Power Dissipation
PD
41
Operating Junction & Storage Temperature Range
Lead Temperature (1/16” from case for 10 sec.)
Tj, Tstg
TL
-55 to 150
275
°C
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
Junction-to-Case
SYMBOL
TYPICAL
MAXIMUM
UNITS
2.5
65
Rθ
Rθ
Rθ
JC
JA
Junction-to-Ambient
Case-to-Heatsink
°C / W
0.7
CS
1Pulse width limited by maximum junction temperature.
2Duty cycle 1％
≤
ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted)
LIMITS
MIN TYP MAX
PARAMETER
SYMBOL
TEST CONDITIONS
UNIT
STATIC
VGS = 0V, I = 250 A
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
V(BR)DSS
VGS(th)
IGSS
25
µ
D
V
0.8 1.2
2.5
VDS = V , I = 250 A
µ
GS
D
VDS = 0V, VGS = ±20V
VDS = 20V, VGS = 0V
±250 nA
25
Zero Gate Voltage Drain Current
IDSS
A
µ
VDS = 20V, VGS = 0V, TC = 125 °C
250
MAY-24-2001
1
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P50N02LD
NIKO-SEM
TO-252 (D PAK)
On-State Drain Current1
ID(ON)
RDS(ON)
gfs
VDS = 10V, VGS = 10V
VGS = 7V, ID = 20A
55
A
13
12
16
16
15
Drain-Source On-State
Resistance1
m
Ω
V
GS = 10V, ID = 30A
VDS = 15V, ID = 40A
DYNAMIC
Forward Transconductance1
S
Input Capacitance
Ciss
Coss
Crss
Qg
1400
380
200
40
V
GS = 0V, VDS = 15V, f = 1MHz
pF
nC
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge2
Gate-Source Charge2
Gate-Drain Charge2
Turn-On Delay Time2
Rise Time2
VDS = 0.5V(BR)DSS, VGS = 10V,
ID = 30A
Qgs
Qgd
td(on)
tr
12
25
9
VDS = 15V, R = 1
Ω
150
20
L
nS
Turn-Off Delay Time2
td(off)
ID 35A, VGS = 10V, RGS = 2.5Ω
Fall Time2
tf
30
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C)
Continuous Current IS
ISM
55
170
1.3
A
Pulsed Current3
Forward Voltage1
VSD
trr
IF = IS, VGS = 0V
V
nS
A
Reverse Recovery Time
Peak Reverse Recovery Current
Reverse Recovery Charge
70
IRM(REC)
200
IF = IS, dlF/dt = 100A / µS
Qrr
0.043
µC
1Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％.
2Independent of operating temperature.
3Pulse width limited by maximum junction temperature.
REMARK: THE PRODUCT MARKED WITH “P50N02LD”, DATE CODE or LOT #
MAY-24-2001
2
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P50N02LD
NIKO-SEM
TO-252 (D PAK)
TO-252 (DPAK) MECHANICAL DATA
mm
mm
Typ.
0.8
Dimension
Dimension
Min.
9.35
2.2
Typ.
Max.
10.1
2.4
Min.
Max.
A
B
C
D
E
F
H
I
6.4
5.2
6.6
5.4
1
0.48
0.89
0.45
0.03
6
0.6
J
1.5
K
L
0.6
0.6
0.64
4.4
0.9
4.6
0.23
6.2
M
N
G
MAY-24-2001
3
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