PCM1602AR-B-N12STSY-SP [ETC]
SPECIFICATIONS FOR LCD MODULE; 规格液晶模块
| 型号： | PCM1602AR-B-N12STSY-SP |
| 厂家： | 
ETC |
| 描述： | SPECIFICATIONS FOR LCD MODULE |
| 文件： | 总22页 (文件大小：2795K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPECIFICATIONS
FOR LCD MODULE
CUSTOMER
CUSTOMER PART NO.
PACER DISPLAY NO.
DESCRIPTION
APPROVED BY
DATE
PCM0802C`
PREPARED BY
CHECKED BY
APPROVED BY
Copyright © 2006 Pacer PLC
PAGE
1
OF 22
DOCUMENT REVISION HISTORY:
DATE
PAGE
DESCRIPTION
1999.8.
2005.3.
ꢀꢁꢁꢂ.12
-
-
4
First release
Modify the full specification
Update the part number system
Copyright © 2006 Pacer PLC
PAGE
2
OF 22
Contents
1. Module Classification Information
2. Precautions in use of LCD Modules
3. General Specification
4. Absolute Maximum Ratings
5. Electrical Characteristics
6. Optical Characteristics
7. Interface Pin Function
8. Power Supply
9. Contour Drawing & Block Diagram
10. Function Description
11. Character Generator ROM Pattern
12. Instruction Table
13. Timing Characteristics
14. Initializing of LCM
15. Quality Assurance
16. Reliability
Copyright © 2006 Pacer PLC
PAGE
3
OF 22
1. Module Classification Inform ation
P C M 1 6 0 2 A R - B - B 6 W T D W - S P
1 3
1
2
3
4
5
6
7
8
9
1 0 1 1 1 2
1 BrandΚPACER DISPLAY
2
Κ
Display Type CMꢀ Character Type, GMꢀ Graphic Type,
NONEꢀ Custom-made
Display Font Characters X Lines / Rows X Columns /Others
3
Κ
4 Model serials no.
5 RoHS compliant: RꢀYES NONEꢀ NO
Mꢀ SMT Type
6
IC Package Type˖
Bꢀ COB Type
Tꢀ TAB Type
Gꢀ COG Type
Fꢀ COF Type
Sꢀ Special
PꢀTN Positive
NꢀTN Negative
7
LCD Mode˖
Yꢀ STN Positive, Yellow Green
Bꢀ STN Negative, Blue
Gꢀ STN Positive, Gray
Wꢀ FSTN Positive
Tꢀ FSTN Negative
Fꢀ FFSTN Negative
Sꢀ Special
6ꢀ 6:00,12ꢀ12:00, SꢀSpecial
8 Viewing direction
N ꢀ Normal Temperature
Wꢀ Wide Temperature
Sꢀ Special
9 Temperature range
Rꢀ Reflective
Tꢀ Transmissive
Fꢀ Transflective
Sꢀ Special
10 LCD Polarizer Type
11 Backlight Type
Nꢀ None
Dꢀ LED
Eꢀ EL
Fꢀ CCFL
Sꢀ Special
Yꢀ Yellow-green
Bꢀ Blue
12 Backlight Color
Aꢀ Amber
Wꢀ White
Gꢀ Green
Rꢀ Red
Sꢀ Special
13 Internal Code
Copyright © 2006 Pacer PLC
PAGE
4
OF 22
2. Precautions in use of LCD Modules
(1)Avoid applying excessive shocks to the module or making any alterations or modifications to
it.
(2)Don’t make extra holes on the printed circuit board, modify its shape or change the
components of LCD module.
(3)Don’t disassemble the LCM.
(4)Don’t operate it above the absolute maximum rating.
(5)Don’t drop, bend or twist LCM.
(6)Soldering: only to the I/O terminals.
(7)Storage: please storage in anti-static electricity container and clean environment.
3. General Specification
Item
Number of Characters
Dimension
Unit
Ё
8 characters x 2 Lines
Module dimension(No Backlight )
79.0 x 44.0 x 10.0˄MAX˅
mm
Module dimension(With LED Backlight )
79.0 x 44.0 x 14.0˄MAX˅
63.0 x 25.0
mm
mm
mm
mm
mm
mm
mm
View area
Active area
Dot size
57.17 x 23.00
1.15 x 1.36
Dot pitch
1.23 x 1.44
Character size
Character pitch
LCD type
6.07 x 11.44
7.30 x 11.56
STN
Duty
1/16
View direction
Backlight Type
6 o’clock or 12 o’clock
None, YELLOW-GREEN
Copyright © 2006 Pacer PLC
PAGE
5
OF 22
4. Absolute Maxim um Ratings
Item
Symbol
VI
Min
-0.3
Max
Unit
V
Input Voltage
VDD+0.3
Supply Voltage For Logic
Supply Voltage For LCD
VDD-VSS
VDD-V0
Top
-0.3
7.0
0
V
Vdd-13.5
0
V
Standard
Operating Temp.
Storage Temp.
50
60
70
80
Temperature LCM
Tstr
-10
Wide Temperature Operating Temp.
LCM
Top
-20
Storage Temp.
Tstr
-30
5. Electrical Characteristics
Item
Symbol
VDD-VSS
VDD-V0
VIH
Condition
Min
4.5
Typ
Max
5.5
Unit
V
Ё
Supply Voltage For Logic
Supply Voltage For LCD
Input High Volt.
5.0
4.8
Ё
Ta=25
4.5
5.5
V
Ё
0.7 VDD
VSS
VDD
V
Ё
Ё
Input Low Volt.
VIL
0.3 VDD
2.0
V
Supply Current
IDD
VDD=5V
0.8
1.2
mA
Forward
current
=150 mA
Supply Voltage of
VLED
3.8
4.1
4.3
V
Yellow-green backlight
Number of
LED die
2x15= 30
Copyright © 2006 Pacer PLC
PAGE
6
OF 22
6. Optical Characteristics
Item
View Angle
Symbol
(V)ꢀ
Condition
CR 2
CR 2
Ё
Min
-20
-30
Ё
Typ
Ё
Ё
3
Max
35
Unit
deg
deg
Ё
(H)ꢁ
CR
30
Ё
Contrast Ratio
Response Time
Ё
Ё
Ё
Ё
T rise
T fall
250
250
ms
Ё
Ё
ms
Definition of Operation Voltage (Vop)
Definition of Response Time ( Tr , Tf )
Non-selected
Conition
Non-selected
Conition
Selected Conition
Selected Wave
Non-selected Wave
Intensity
100
Intensity
10
Cr Max
Cr = Lon / Loff
90
100
Vop
Tr
Tf
Driving Voltage(V)
[positive type]
[positive type]
Conditions :
Operating Voltage : Vop
Viewing Angle(ꢀΔꢁ) : 0°Δ 0°
Frame Frequency : 64 HZ Driving Waveform : 1/N duty , 1/a bias
Definition of viewing angle(CR 2)
Copyright © 2006 Pacer PLC
PAGE
7
OF 22
b
f
= 180
l
r
= 270
= 90
= 0
7. Interface Pin Function
Pin No. Symbol
Level
0V
Description
1
2
VSS
VDD
Ground
Supply Voltage for logic
5.0V
3
V0
(Variable) Operating voltage for LCD
4
RS
H/L
H/L
H: DATA, L: Instruction code
H: Read(MPUꢂModule) L: Write(MPUꢂModule)
5
R/W
E
6
H,HꢂL Chip enable signal
7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
LED(+)
LED(-)
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
Data bit 0
8
Data bit 1
9
Data bit 2
10
11
12
13
14
15
16
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
Anode of LED Backlight
Cathode of LED Backlight
Copyright © 2006 Pacer PLC
PAGE
8
OF 22
8. POWER SUPPLY
SINGLE SUPPLY VOLTAGE TYPE
DUAL SUPPLY VOLTAGE TYPE
Copyright © 2006 Pacer PLC
PAGE
9
OF 22
9. Contour Drawing &Block Diagram
79.0
75.0
NO B/L
LED B/L
63.0[V.A.]
10.0[MAX.]
5.0¡ À0.5
14.0[MAX.]
9.0¡ 0À.5
57.17[A.A.]
C
L
2-R1.25
C
C
L
L
16- 1.0
P2.54X(16-1)=38.1
2- 2.5
10.2
4.0
1.6¡ 0À.1
1.6¡ 0À.1
76.0
84.0¡ 0À.5
7.30
6.07
1.15
Vdd
V0
Vss
LCD PANEL
8X2 CHARACTERS
E
8
8
R/W
RS
40
DB0
DB7
8
*S6A0069 OR EQUIVALENT
0.08
Copyright © 2006 Pacer PLC
PAGE 10 OF 22
10. Function Description
The LCD display Module is built in a LSI controller, the controller has two 8-bit registers, an
instruction register (IR) and a data register (DR).
The IR stores instruction codes, such as display clear and cursor shift, and address information
for display data RAM (DDRAM) and character generator (CGRAM). The IR can only be written
from the MPU. The DR temporarily stores data to be written or read from DDRAM or
CGRAM. When address information is written into the IR, then data is stored into the DR from
DDRAM or CGRAM. By the register selector (RS) signal, these two registers can be selected.
RS R/W
Operation
0
0
1
1
0
1
0
1
IR write as an internal operation (display clear, etc.)
Read busy flag (DB7) and address counter (DB0 to DB7)
Write data to DDRAM or CGRAM (DR to DDRAM or CGRAM)
Read data from DDRAM or CGRAM (DDRAM or CGRAM to DR)
Busy Flag (BF)
When the busy flag is 1, the controller LSI is in the internal operation mode, and the next
instruction will not be accepted. When RS=0 and R/W=1, the busy flag is output to DB7. The
next instruction must be written after ensuring that the busy flag is 0.
Address Counter (AC)
The address counter (AC) assigns addresses to both DDRAM and CGRAM
Display Data RAM (DDRAM)
This DDRAM is used to store the display data represented in 8-bit character codes. Its extended
capacity is 80×8 bits or 80 characters. Below figure is the relationships between DDRAM
addresses and positions on the liquid crystal display.
High bits
Low bits
Example: DDRAM addresses 4E
AC
1
0
0
1
1
1
0
AC6 AC5 AC4 AC3 AC2 AC1 AC0
(hexadecimal)
Copyright © 2006 Pacer PLC
PAGE 11 OF 22
Display position DDRAM address
1
2
3
4
5
6
7
8
00 01 02 03 04 05 06 07
08 09 10 11 12 13 14 15
ꢀ-Line by 8 -Character Display
Character Generator ROM (CGROM)
The CGROM generate 5×8 dot or 5×10 dot character patterns from 8-bit character codes. See
Table 2.
Character Generator RAM (CGRAM)
In CGRAM, the user can rewrite character by program. For 5×8 dots, eight character patterns
can be written, and for 5×10 dots, four character patterns can be written.
Write into DDRAM the character code at the addresses shown as the left column of table 1. To
show the character patterns stored in CGRAM.
Copyright © 2006 Pacer PLC
PAGE 12 OF 22
Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character
patterns
Table 1.
F o r 5 * 8 d o t c h a ra c te r p a tte rn s
C h a ra c te r C o d e s
( D D R A M d a ta )
C h a ra c te r P a tte rn s
( C G R A M d a ta )
C G R A M A d d re s s
7
6
5
4
3
2
1
0
5
4
3
2
1
0
7
6
5
4
3
2
1
0
H ig h
L o w
H ig h
L o w
H ig h
L o w
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
0
0
0
0
0
C h a ra c te r
p a tte rn ( 1 )
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*
0
0
0
0
0
0
0
0
0
0
0
C u rs o r p a tte rn
0
0
0
0
0
0
C h a ra c te r
p a tte rn ( 2 )
0
0
0
0
0
0
0
*
*
0
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
C u rs o r p a tte rn
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
*
*
*
F o r 5 * 1 0 d o t c h a ra c te r p a tte rn s
C h a ra c te r C o d e s
( D D R A M d a ta )
C h a ra c te r P a tte rn s
( C G R A M d a ta )
C G R A M A d d re s s
7
6
5
4
3
2
1
0
5
4
3
2
1
0
7
6
5
4
3
2
1
0
H ig h
L o w
H ig h
L o w
H ig h
L o w
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
0
0
0
0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
*
*
*
0
0
0
0
0
0
0
0
0
0
0
0
*
0
0
0
0
0
C h a ra c te r
p a tte rn
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*
C u rs o r p a tte rn
1
1
1
1
*
*
*
*
*
*
*
: " H ig h "
Copyright © 2006 Pacer PLC
PAGE 13 OF 22
11. Character Generator ROM Pattern
Table.2
Copyright © 2006 Pacer PLC
PAGE 14 OF 22
12. Instruction Table
Instruction Code
Instruction
Execution time
(fosc=270Khz)
Description
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Write “00H” to DDRAM and set
Clear Display
Return Home
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1.53ms
1.53ms
DDRAM address to “00H” from AC
Set DDRAM address to “00H” from AC
and return cursor to its original position
if shifted. The contents of DDRAM are
not changed.
Ё
Entry Mode
Set
Assign cursor moving direction and
enable the shift of entire display.
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
I/D SH
39ꢃs
39ꢃs
Display
ON/OFF
Control
Set display (D), cursor (C), and blinking
of cursor (B) on/off control bit.
D
C
B
Set cursor moving and display shift
control bit, and the direction, without
changing of DDRAM data.
Cursor or
Display Shift
Ё
Ё
0
0
0
0
0
0
0
0
1
1
S/C R/L
39ꢃs
39ꢃs
Set interface data length
(DL:8-bit/4-bit), numbers of display line
(N:2-line/1-line)and, display font type
(F:5×11 dots/5×8 dots)
Ё
Ё
Function Set
0
1
DL
N
F
Set CGRAM
Address
0
0
0
0
0
1
AC5 AC4 AC3 AC2 AC1 AC0
39ꢃs
39ꢃs
Set CGRAM address in address counter.
Set DDRAM
Address
AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter.
Whether during internal operation or not
can be known by reading BF. The
Read Busy
Flag and
Address
0
1
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
0ꢃs
contents of address counter can also be
read.
Write Data to
RAM
Write data into internal RAM
(DDRAM/CGRAM).
1
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
43ꢃs
43ꢃs
Read Data
from RAM
Read data from internal RAM
(DDRAM/CGRAM).
Ϡ ”Ё”Κdon’t care
Copyright © 2006 Pacer PLC
PAGE 15 OF 22
13. Tim ing Characteristics
13.1ʳ Write Operation
VIH1
VIH1
VIL1
RS
VIL1
AS
AH
AH
t
t
t
R/W
VIL1
VIL1
EH
PW
Ef
t
VIH1
VIL1
VIH1
VIL1
E
VIL1
Er
t
DSW
H
t
t
VIH1
VIL1
VIH1
VIL1
DB0 to DB7
Valid data
cycE
t
Ta=25 , VDD=5.0± 0.5V
Item
Symbol
tcycE
PWEH
tEr,tEf
tAS
Min
Typ
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Max
Ё
Unit
ns
Enable cycle time
1200
140
Ё
Ё
Enable pulse width (high level)
Enable rise/fall time
ns
25
Ё
Ё
Ё
Ё
ns
Address set-up time (RS, R/W to E)
Address hold time
0
ns
tAH
10
40
10
ns
Data set-up time
tDSW
tH
ns
Data hold time
ns
Copyright © 2006 Pacer PLC
PAGE 16 OF 22
13.2ʳ Read Operation
VIH1
VIL1
VIH1
VIL1
RS
AS
AH
AH
t
t
VIH1
VIH1
R/W
E
EH
PW
t
t
Ef
VIH1
VIL1
VIH1
VIL1
VIL1
Er
DHR
t
t
DDR
t
VOH1
VOH1
Valid data
cycE
DB0 to DB7
VOL1*
*VOL1
t
NOTE: *VOL1 is assumed to be 0.8V at 2 MHZ operation.
Ta=25 , VDD=5.0± 0.5V
Item
Enable cycle time
Symbol
tcycE
Min
1200
140
Ё
Typ
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Max
Ё
Unit
ns
Ё
Enable pulse width (high level)
Enable rise/fall time
PWEH
tEr,tEf
tAS
ns
25
Ё
Ё
ns
Address set-up time (RS, R/W to E)
Address hold time
0
ns
tAH
10
Ё
ns
Data delay time
tDDR
100
ns
Ё
Data hold time
tDHR
10
ns
Copyright © 2006 Pacer PLC
PAGE 17 OF 22
13.3 Timing Diagram of VDD Against V0.
Power on sequence shall meet the requirement of Figure 4, the timing diagram of VDD against
V0
.
VDD
95%
LOGIC SUPPLY
VOLTAGE
V0
0V
50ms(typical)
0V
LCD SUPPLY
VOLTAGE
Copyright © 2006 Pacer PLC
PAGE 18 OF 22
14.Initializing of LCM
Power on
Wait for more than 40 ms after VDDrises to 4.5 V
BF can not be checked before this instruction.
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
*
*
*
*
Wait for more than 39us
BF can not be checked before this instruction.
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
N
0
F
1
*
0
*
*
*
*
*
*
*
*
*
Wait for more than 39 µs
BFcan not be checked before this instruction.
Function set
RS
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R/W
0
0
0
0
1
*
0
*
*
*
*
*
*
*
*
*
N
F
Wait for more than 37us
RS
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Display ON/OFF control
R/W
0
0
0
0
0
*
*
*
*
0
0
1
D
C
B
*
*
*
*
Wait for more than 37 µs
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RS
0
0
R/W
0
0
Display Clear
0
0
0
0
0
0
0
1
*
*
*
*
*
*
*
*
Wait for more than 1.53ms
RS
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R/W
0
0
Entry Mode Set
0
0
0
1
0
0
*
*
*
*
*
*
*
SH *
I/D
Initialization ends
4-Bit Ineterface
Copyright © 2006 Pacer PLC
PAGE 19 OF 22
Poweron
Waitformorethan40msafterVDDrisesto4.5V
BFcannotbecheckedbeforethisinstruction.
Functionset
RS
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R/W
0
0
0
1
1
N F
*
*
Waitformorethan39us
BFcannotbecheckedbeforethisinstruction.
Functionset
RS
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R/W
0
0
0
1
1
N F
*
*
Waitformorethan37us
RS
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DisplayON/OFFcontrol
R/W
0
0
0
0
0
1
B C
D
Waitformorethan37µs
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RS
0
R/W
0
DisplayClear
0
0
0
0
0
0
0
1
Waitformorethan1.53ms
RS
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R/W
0
EntryModeSet
0
0
0
0
0
1
S
I/D
Initializationends
8-BitIneterface
Copyright © 2006 Pacer PLC
PAGE 20 OF 22
15.Quality Assurance
Screen Cosmetic Criteria
Item
Defect
Judgment Criterion
Partition
A)Clear
Size: d mm
0.1
Acceptable Qty in active area
d
Disregard
0.1<d 0.2
0.2<d 0.3
0.3<d
6
2
0
Note: Including pin holes and defective dots which must
be within one pixel size.
1
Spots
Minor
B)Unclear
Size: d mm
0.2
Acceptable Qty in active area
d
Disregard
0.2<d 0.5
0.5<d 0.7
0.7<d
6
2
0
Size: d mm
d 0.3
Acceptable Qty in active area
Disregard
2
Bubbles in Polarizer
0.3<d 1.0
1.0<d 1.5
1.5<d
3
1
0
Minor
In accordance with spots cosmetic criteria. When the light
3
4
Scratch
reflects on the panel surface, the scratches are not to be
remarkable.
Above defects should be separated more than 30mm each
other.
Minor
Minor
Allowable Density
Not to be noticeable coloration in the viewing area of the
LCD panels.
5
Coloration
Minor
Back-light type should be judged with back-light on state
only.
Copyright © 2006 Pacer PLC
PAGE 21 OF 22
16.Reliability
Content of Reliability Test
Environmental Test
Applicable
Standard
Test Item
Content of Test
Test Condition
High
Temperature
storage
Low
Temperature
storage
Endurance test applying the high storage
temperature for a long time.
60
96hrs
——
——
——
——
Endurance test applying the high storage
temperature for a long time.
-10
96hrs
High
Endurance test applying the electric stress
(Voltage & Current) and the thermal stress
to the element for a long time.
50
96hrs
Temperature
Operation
Low
Temperature
Operation
High
Temperature/
Humidity
Storage
Endurance test applying the electric stress
under low temperature for a long time.
0
96hrs
Endurance test applying the high
temperature and high humidity storage for a
long time.
60 ,90%RH
96hrs
——
——
High
Endurance test applying the electric stress
(Voltage & Current) and temperature /
humidity stress to the element for a long
time.
Temperature/
Humidity
Operation
50 ,90%RH
96hrs
Endurance test applying the low and high
temperature cycle.
Temperature
Cycle
-10
25
60
-10 /60
10 cycles
——
30min
5min
1 cycle
30min
Mechanical Test
Vibration test
10~22Hzꢂ1.5mmp-p
22~500Hzꢂ1.5G
Total 0.5hrs
50G Half sign
wave 11 msedc
3 times of each
direction
Endurance test applying the vibration
during transportation and using.
——
——
Constructional and mechanical endurance
test applying the shock during
transportation.
Shock test
***Supply voltage for logic system=5V. Supply voltage for LCD system =Operating voltage at 25
Copyright © 2006 Pacer PLC
PAGE 22 OF 22
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