PCM3000/PCM3001 [ETC]
PCM3000. PCM3001 - Sound Plus Stereo Audio CODEC 18-BITS. SERIAL INTERFACE ; PCM3000 。 PCM3001 - 声音加上立体声音频编解码器18位。串行接口\n
| 型号： | PCM3000/PCM3001 |
| 厂家： | 
ETC |
| 描述： | PCM3000. PCM3001 - Sound Plus Stereo Audio CODEC 18-BITS. SERIAL INTERFACE
|
| 文件： | 总20页 (文件大小：335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
49%
F
PCM3001E
PCM3000
PCM3001
PCM3000E
Stereo Audio CODEC
TM
18-BITS, SERIAL INTERFACE
FEATURES
● MONOLITHIC 18-BIT ∆Σ ADC AND DAC
DESCRIPTION
The PCM3000/3001 is a low cost single chip stereo
audio CODEC (analog-to-digital and digital-to-analog
converter) with single-ended analog voltage input and
output.
● 16- OR 18-BIT INPUT/OUTPUT DATA
● STEREO ADC:
Single-ended Voltage Input
Both ADCs and DACs employ delta-sigma modula-
tion with 64X oversampling. The ADCs include a
digital decimation filter and the DACs include an 8X
oversampling digital interpolation filter. The DACs
also include digital attenuation, de-emphasis, infinite
zero detection and soft mute to form a complete
subsystem. PCM3000/3001 operates with left-justi-
fied, right-justified, I2S or DSP data formats.
64X Oversampling
High Performance:
–88dB
94dB
94dB
THD+N
SNR
Dynamic Range
Digital High-Pass Filter
● STEREO DAC:
Single-ended Voltage Output
Analog Low Pass Filter
8X Oversampling Digital Filter
High Performance:
PCM3000 can be bit-mapped with a 3-wire serial
interface for special features and data formats.
PCM3001 can be pin-programmed for data formats.
–90dB
98dB
97dB
THD+N
SNR
Dynamic Range
Fabricated on a highly advanced 0.6µ CMOS process,
PCM3000/3001 is suitable for a wide variety of cost-
sensitive consumer applications where good perfor-
mance is required. Applications include sampling key-
boards, digital mixers, mini-disc recorders, hard-disk
recorders, karaoke systems, DSP-based car stereo,
DAT recorders, and video conferencing.
● SPECIAL FEATURES (PCM3000):
Digital De-emphasis
Digital Attenuation (256 Steps)
Soft Mute
Analog Loop Back
● SAMPLE RATE: Up to 48kHz
● SYSTEM CLOCK: 256fS, 384fS, 512fS
● SINGLE +5V POWER SUPPLY
● SMALL PACKAGE: 28-Pin SSOP
Digital Out
Lch In
Decimation
Digital Filter
Delta-Sigma
Modulator
Analog Front-End
Digital In
Rch In
Serial Interface
and
Mode Control
Lch Out
Rch Out
Low Pass Filter
and
Output Buffer
Multi-Level
Delta-Sigma
Modulator
Oversampling
Interpolation
Digital Filter
Mode Control
System Clock
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
FAXLine: (800) 548-6133 (US/Canada Only)
• Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
© 1996 Burr-Brown Corporation
PDS-1342D
Printed in U.S.A., August, 1998
SPECIFICATIONS
All specifications at +25°C, VDD = VCC = +5V, fS = 44.1kHz, SYSCLK = 384fS, CLKIO Input, 18-bit data, unless otherwise noted.
PCM3000E/3001E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUT/OUTPUT
Input Logic
(1)
Input Logic Level: VIH
2.0
VDC
VDC
µA
(1)
VIL
0.8
±1
(2)
Input Logic Current: IIN
(3)
Input Logic Current: IIN
–120
µA
(4)
Input Logic Level: VIH
0.64 x VDD
VDC
VDC
µA
(4)
VIL
0.28 x VDD
(4)
Input Logic Current: IIN
±40
Output Logic
(5)
Output Logic Level: VOH
IOUT = –1.6mA
IOUT = +3.2mA
IOUT = –3.2mA
IOUT = +3.2mA
4.5
4.5
VDC
VDC
VDC
VDC
(5)
VOL
0.5
0.5
(6)
Output Logic Level: VOH
(6)
VOL
CLOCK FREQUENCY
Sampling Frequency (fS)
System Clock Frequency
32
44.1
48
kHz
MHz
MHz
MHz
256fS
384fS
512fS
8.1920
12.2880
16.3840
11.2896
16.9344
22.5792
12.2880
18.4320
24.5760
ADC CHARACTERISTICS
RESOLUTION
18
Bits
DC ACCURACY
Gain Mismatch Channel-to-Channel
Gain Error
±1.0
±2.0
±20
±1.7
±20
±5.0
±5.0
% of FSR
% of FSR
Gain Drift
ppm of FSR/°C
%of FSR
Bipolar Zero Error
Bipolar Zero Drift
High-Pass Filter Off(7)
High-Pass Filter Off(7)
ppm of FSR/°C
DYNAMIC PERFORMANCE(8)
THD+N: VIN = –0.5dB
VIN = –60dB
f = 1kHz
–88
–31
94
–80
dB
dB
dB
dB
dB
f = 1kHz
Dynamic Range
f = 1kHz, A-Weighted
f = 1kHz, A-Weighted
90
90
88
Signal-to-Noise Ratio
Channel Separation
94
92
DIGITAL FILTER PERFORMANCE(8)
Passband
0.454fS
Hz
Hz
dB
dB
sec
Stopband
0.583fS
–65
Passband Ripple
±0.05
Stopband Attenuation
Delay Time (Latency)
17.4/fS
0.019fS
DIGITAL HIGH PASS FILTER RESPONSE
–3dB Frequency
mHz
ANALOG INPUT
Voltage Range
Center Voltage
Input Impedance
0dB (Full Scale)
CEXT = 470pF
2.9
2.1
15
Vp-p
V
kΩ
ANTI-ALIASING FILTER
–3dB Frequency
170
kHz
NOTES: (1) Pins 16, 17, 18, 22, 25, 26, 27, 28: LRCIN, BCKIN, DIN, CLKIO, MC/FMT2, MD/FMT1, ML/FMT0, RSTB. (2) Pins 16, 17, 18, 22: LRCIN, BCKIN, DIN,
CLKIO (Schmitt Trigger Input). (3) Pins 25, 26, 27, 28: MC/FMT2, MD/FMT1, ML/FMT0, RSTB (Schmitt Trigger Input, 70kΩ Internal Pull-Up Resistor). (4) Pin 20:
XTI. (5) Pins 19, 22: DOUT,CLKIO. (6) Pin 21: XTO. (7) High Pass Filter disabled (PCM3000 only) to measure DC offset. (8) fIN = 1kHz, using Audio Precision System
II, rms mode with 20kHz LPF, 400Hz HPF used for performance calculation. (9) With no load on XTO and CLKIO.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no
responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN
product for use in life support devices and/or systems.
®
2
PCM3000/3001
SPECIFICATIONS (CONT)
All specifications at +25°C, VDD = VCC = 5V, fS = 44.1kHz, SYSCLK = 384fS, CLKIO Input, 18-bit data, unless otherwise noted.
PCM3000E/3001E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DAC CHARACTERISTICS
RESOLUTION
18
Bits
DC ACCURACY
Gain Mismatch Channel-to-Channel
Gain Error
Gain Drift
Bipolar Zero Error
Bipolar Zero Drift
±1.0
±1.0
±20
±1.0
±20
±5.0
±5.0
% of FSR
% of FSR
ppm of FSR/°C
% of FSR
ppm of FSR/°C
DYNAMIC PERFORMANCE(8)
THD+N: VOUT = 0dB (Full Scale)
VOUT = –60dB
Dynamic Range
Signal-to-Noise Ratio (Idle Channel)
Channel Separation
–90
–34
97
98
95
–80
dB
dB
dB
dB
dB
EIAJ A-Weighted
EIAJ A-Weighted
90
92
90
DIGITAL FILTER PERFORMANCE
Passband
Stopband
Passband Ripple
Stopband Attenuation
Delay Time
0.445fS
Hz
Hz
dB
dB
sec
0.555fS
–35
±0.17
11.1/fS
ANALOG OUTPUT
Voltage Range
Center Voltage
0.62 x VCC
0.5 x VCC
Vp-p
VDC
kΩ
Load Impedance
AC Load
5
ANALOG LOW PASS FILTER
Frequency Response
f = 20kHz
–0.16
dB
POWER SUPPLY REQUIREMENTS
Voltage Range: VCC
VDD
Supply Current: +ICC, +IDD
4.5
4.5
5
5
32
160
5.5
5.5
50
VDC
VDC
mA
(9)
VCC = VDD = 5V
VCC = VDD = 5V
Power Dissipation
250
mW
TEMPERATURE RANGE
Operation
Storage
–25
–55
+85
+125
°C
°C
ABSOLUTE MAXIMUM RATINGS
PACKAGE INFORMATION
Supply Voltage
PACKAGE DRAWING
+VDD, +VCC1, +VCC2 ...................................................................... +6.5V
Supply Voltage Differences............................................................... ±0.1V
GND Voltage Differences.................................................................. ±0.1V
Digital Input Voltage ...................................................... –0.3 to VDD + 0.3V
Analog Input Voltage......................................... –0.3 to VCC1, VCC2 + 0.3V
Power Dissipation .......................................................................... 300mW
Input Current ................................................................................... ±10mA
Operating Temperature Range ......................................... –25°C to +85°C
Storage Temperature ...................................................... –55°C to +125°C
Lead Temperature (soldering, 5s).................................................. +260°C
(reflow, 10s) ..................................................... +235°C
PRODUCT
PACKAGE
NUMBER(1)
PCM3000E/3001E
28-Pin SSOP
324
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
ELECTROSTATIC
DISCHARGE SENSITIVITY
Thermal Resistance, θJA .............................................................. 100°C/W
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
®
3
PCM3000/3001
PIN CONFIGURATION—PCM3000
PIN CONFIGURATION—PCM3001
Top View
SSOP
Top View
SSOP
1
2
VIN
CC1
AGND1
L
RSTB 28
ML 27
1
2
VIN
CC1
AGND1
L
RSTB 28
FMT0 27
FMT1 26
FMT2 25
DGND 24
VDD 23
V
V
3
MD 26
3
4
V
V
V
REFL
REFR
INR
MC 25
4
V
V
V
REFL
REFR
INR
5
DGND 24
VDD 23
5
6
6
7
C
C
C
C
INPR
INNR
INNL
INPL
CLKIO 22
XTO 21
XTI 20
7
C
C
C
C
INPR
INNR
INNL
INPL
CLKIO 22
XTO 21
8
8
9
9
XTI 20
10
DOUT 19
DIN 18
10
DOUT 19
DIN 18
11 VCOM
12
OUTR
13 AGND2
14
CC2
11 VCOM
12
OUTR
13 AGND2
14
CC2
V
BCKIN 17
LRCIN 16
V
BCKIN 17
LRCIN 16
V
V
OUTL 15
V
VOUTL 15
PIN ASSIGNMENTS PCM3000/3001
PIN
NAME
VIN
CC1
AGND1
REFL
REFR
I/O
DESCRIPTION
1
L
IN
—
ADC Analog Input, Lch
ADC Analog Power Supply
ADC Analog Ground
2
V
3
—
4
V
—
ADC Input Reference, Lch
ADC Input Reference, Rch
ADC Analog Input, Rch
ADC Anti-alias Filter Capacitor (+), Rch
ADC Anti-alias Filter Capacitor (–), Rch
ADC Anti-alias Filter Capacitor (–), Lch
ADC Anti-alias Filter Capacitor (+), Lch
DAC Output Common
5
V
—
6
VINR
IN
7
CINPR
—
8
C
INNR
CINNL
INPL
VCOM
OUTR
AGND2
CC2
VOUT
—
9
—
10
11
12
13
14
15
16
17
18
19
20
21
22
C
—
—
V
OUT
—
DAC Analog Output, Rch
DAC Analog Ground
V
—
DAC Analog Power Supply
DAC Analog Output, Lch
Sample Rate Clock Input (fS)(2)
Bit Clock Input
L
OUT
IN
LRCIN
BCKIN
DIN
IN
IN
Data Input
DOUT
XTI
OUT
IN
Data Output
Oscillator Input
XTO
OUT
I/O
Oscillator Output
CLKIO
Buffered Output of Oscillator or External Clock
Input(2)
23
24
VDD
—
—
IN
Digital Power Supply
Digital Ground
DGND
25 MC/FMT2
26 MD/FMT1
27 ML/FMT0
Serial Control Bit Clock (PCM3000)/Data
Format Control 2 (PCM3001)(1, 2)
IN
IN
IN
Serial Control Data (PCM3000)/Data Format
Control 1 (PCM3001)(1, 2)
Serial Control Strobe Pulse/Data Format
Control 0 (PCM3001)(1, 2)
Reset(1)
28
RSTB
NOTES: (1) With 70kΩ typical internal pull-up resistor. (2) Schmitt trigger input.
®
4
PCM3000/3001
TYPICAL PERFORMANCE CURVES
ADC SECTION
At TA = +25°C, VCC = VDD = +5V, fIN = 1.0kHz, VIN = 2.9Vp-p, and SYSCLK = 384fS, unless otherwise noted.
THD+N vs TEMPERATURE
THD+N vs POWER SUPPLY
0.01
0.008
0.006
0.004
0.002
4.0
3.0
2.0
1.0
0
0.01
0.008
0.006
0.004
0.002
4.0
3.0
2.0
1.0
0
–60dB
–60dB
0dB
0dB
–25
0
25
50
75 85
100
4.5
4.75
5.0
5.25
5.5
Temperature (°C)
V
CC (V)
THD+N vs SYSTEM CLOCK
and SAMPLING FREQUENCY
SNR and DYNAMIC RANGE vs POWER SUPPLY
0.01
0.008
0.006
0.004
0.002
4.0
3.0
2.0
1.0
0
98
96
94
92
90
98
96
94
92
90
44.1kHz
–60dB
Dynamic Range
48kHz
48kHz
SNR
0dB
44.1kHz
256fS
384fS
512fS
4.5
4.75
5.0
5.25
5.50
System Clock
VCC (V)
THD+N vs OUTPUT DATA RESOLUTION
–60dB
0.01
4.0
3.0
2.0
1.0
0
0.008
0.006
0.004
0.002
0dB
16-Bit
18-Bit
Resolution
®
5
PCM3000/3001
TYPICAL PERFORMANCE CURVES
DAC SECTION
At TA = +25°C, VCC = VDD = +5V, fIN = 1.0kHz, and SYSCLK = 384fS, unless otherwise noted.
THD+N vs TEMPERATURE
THD+N vs POWER SUPPLY
0.01
0.008
0.006
0.004
0.002
4.0
3.0
2.0
1.0
0
0.01
0.008
0.006
0.004
0.002
4.0
3.0
2.0
1.0
0
–60dB
–60dB
0dB
0dB
–25
0
25
50
75 85
100
4.5
4.75
5.0
5.25
5.5
Temperature (°C)
V
CC (V)
THD+N vs SYSTEM CLOCK
and SAMPLING FREQUENCY
SNR and DYNAMIC RANGE vs POWER SUPPLY
Dynamic Range
100
98
96
94
92
100
98
96
94
92
0.01
0.008
0.006
0.004
0.002
4.0
3.0
2.0
1.0
0
48kHz
SNR
–60dB
0dB
48kHz
44.1kHz
512fS
44.1kHz
4.5
4.75
5.0
5.25
5.50
256fS
384fS
System Clock
VCC (V)
THD+N vs INPUT DATA RESOLUTION
0.01
4.0
0.008
0.006
0.004
0.002
3.0
2.0
1.0
0
–60dB
0dB
16-Bit
18-Bit
Resolution
®
6
PCM3000/3001
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VCC = VDD = +5V, and SYSCLK = 384fS, unless otherwise noted.
ADC DIGITAL FILTER
OVERALL CHARACTERISTICS
0
STOPBAND ATTENUATION CHARACTERISTICS
0
–20
–50
–100
–150
–200
–40
–60
–80
–100
0
8
16
24
32
0
0.25
0.50
0.75
1.00
Normalized Frequency (x fS Hz)
Normalized Frequency (x fS Hz)
PASSBAND RIPPLE CHARACTERISTICS
HIGH PASS FILTER RESPONSE
0.2
0.0
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
0.125
0.250
0.375
0.500
0
1
2
3
4
Normalized Frequency (x fS Hz)
Normalized Frequency (x fS/1000 Hz)
ANTI-ALIASING FILTER
ANTI-ALIASING FILTER OVERALL
FREQUENCY RESPONSE (CEXT = 470pF, 1000pF)
ANTI-ALIASING FILTER PASSBAND
FREQUENCY RESPONSE (CEXT = 470pF, 1000pF)
0
–10
–20
–30
–40
–50
0.2
0.0
470pF
470pF
–0.2
–0.4
–0.6
–0.8
–0.1
1000pF
1000pF
0
10
100
1k
10k
100k
1M
10M
0
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
®
7
PCM3000/3001
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VCC = VDD = +5V, and SYSCLK = 384fS, unless otherwise noted.
DAC DIGITAL FILTER
OVERALL FREQUENCY CHARACTERISTIC
0
PASSBAND RIPPLE CHARACTERISTIC
0
–0.2
–0.4
–0.6
–0.8
–1
–20
–40
–60
–80
–100
0
0.4536fS
1.3605fS
2.2675fS
3.1745fS
4.0815fS
0
0.1134fS
0.2268fS
0.3402fS
0.4535fS
Frequency (Hz)
Frequency (Hz)
DE-EMPHASIS FREQUENCY RESPONSE (3kHz)
DE-EMPHASIS ERROR (3kHz)
0
–2
0.6
0.4
–4
0.2
–6
0
–8
–10
–12
–0.2
–0.4
–0.6
0
0
0
5k
10k
15k
20k
25k
0
0
0
3628
7256
10884
14512
19999.35
21768
Frequency (Hz)
Frequency (Hz)
DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)
DE-EMPHASIS ERROR (44.1kHz)
0.6
0.4
0.2
0
–2
–4
–6
–8
0
–0.2
–0.4
–0.6
–10
–12
5k
10k
15k
20k
25k
4999.8375
9999.675
14999.5125
Frequency (Hz)
Frequency (Hz)
DE-EMPHASIS FREQUENCY RESPONSE (48kHz)
DE-EMPHASIS ERROR (48kHz)
0
–2
–4
–6
–8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–10
–12
5k
10k
15k
20k
25k
5442
10884
16326
Frequency (Hz)
Frequency (Hz)
ANALOG OUTPUT FILTER
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(10Hz~10MHz)
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(20Hz~24kHz, Expanded Scale)
10
5
0
1.0
0.5
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
0
–0.5
–1.0
10
100
1k
10k
100k
1M
10M
20
100
1k
10k
24k
Frequency (Hz)
Frequency (Hz)
®
8
PCM3000/3001
BLOCK DIAGRAM
C
INPL
CINNL
(+)
(–)
Analog
Front-End
Circuit
Decimation
and
High Pass Filter
Delta-Sigma
Modulator
LRCIN
BCKIN
DIN
VIN
L
VREF
L
Serial Data
Interface
Reference
ADC
VREFR
(–)
(+)
Analog
Front-End
Circuit
Decimation
and
High Pass Filter
Delta-Sigma
Modulator
VINR
DOUT
CINNR
INPR
Loop Control
C
ML (FMT0)(1)
MC (FMT2)(1)
MD (FMT1)(1)
Analog
Low-Pass
Filter
Multi-Level
Delta-Sigma
Modulator
Interpolation
Filter
8X Oversampling
VOUT
L
Mode
Control
Interface
VCOM
DAC
Analog
Low-Pass
Filter
Multi-Level
Delta-Sigma
Modulator
Interpolation
Filter
8X Oversampling
VOUTR
Reset
RSTB
Power Supply
Clock/OSC Manager
AGND2 VCC
2
AGND1 VCC
1
DGND
VDD
CLKIO
XTO
XTI
NOTE: (1) FMT0, FMT1, FMT2 are for PCM3001 only.
470pF
CINPL
CINNL
10
9
2.2µF
+
15kΩ
VIN
L
1
4
1kΩ
1kΩ
(+)
(–)
Delta-Sigma
Modulator
VREF
L
+
4.7µF
VREF
FIGURE 1. Analog Front-End (Single-Channel).
®
9
PCM3000/3001
PCM AUDIO INTERFACE
The three-wire digital audio interface for PCM3000/3001 is
on LRCIN (Pin 16), BCKIN (Pin 17), DIN (Pin 18), and
DOUT (Pin 19). PCM3000/3001 can operate with seven
different data formats. For PCM3000, these formats are
selected through PROGRAM REGISTER 3 in the software
mode. For PCM3001, data formats are selected by pin-
strapping the three format pins. Figures 2, 3 and 4 illustrate
audio data input/output format and timing.
PCM3000/3001 can accept 32, 48, or 64 bit clocks (BCKIN)
in one clock of LRCIN. Only formats 0, 2, and 6 can be
selected when 32 bit clocks/LRCIN are applied.
FORMAT 0: FMT[2:0] = “000”
DAC: 16-Bit, MSB-First, Right-Justified
L–ch
3
R–ch
LRCIN
BCKIN
DIN
16
1
2
14 15 16
LSB
1
2
3
14 15 16
LSB
MSB
MSB
ADC: 16-Bit, MSB-First, Left-Justified
LRCIN
BCKIN
L–ch
R–ch
1
2
3
14 15 16
1
2
3
14 15 16
1
DOUT
MSB
LSB
MSB
LSB
FORMAT 1: FMT[2:0] = “001”
DAC: 18-Bit, MSB-First, Right-Justified
L–ch
R–ch
LRCIN
BCKIN
18
1
2
3
16 17 18
LSB
1
2
3
16 17 18
LSB
DIN
MSB
MSB
ADC: 18-Bit, MSB-First, Left-Justified
LRCIN
BCKIN
L–ch
R–ch
DOUT
1
2
3
16 17 18
LSB
1
2
3
16 17 18
LSB
1
MSB
MSB
FORMAT 2: FMT[2:0] = “010”
DAC: 16-Bit, MSB-First, Right-Justified
L–ch
3
R–ch
LRCIN
BCIN
16
1
2
14 15 16
LSB
1
2
3
14 15 16
LSB
DIN
MSB
MSB
ADC: 16-Bit, MSB-First, Right-Justified
LRCIN
BCIN
L–ch
3
R–ch
16
1
2
14 15 16
LSB
1
2
3
14 15 16
LSB
DOUT
MSB
MSB
FIGURE 2. Audio Data Input/Output Format.
®
10
PCM3000/3001
FORMAT 3: FMT[2:0] = "011"
DAC: 18-Bit, MSB-First, Right-Justified
R-ch
LRCIN
BCKIN
L-ch
18
1
2
3
16 17 18
LSB
1
2
3
16 17 18
LSB
DIN
MSB
MSB
ADC: 18-Bit, MSB-First, Right-Justified
R-ch
LRCIN
BCKIN
L-ch
18
1
2
3
16 17 18
LSB
1
2
3
16 17 18
LSB
DOUT
MSB
MSB
FORMAT 4: FMT[2:0] = "100 "
DAC: 18-Bit, MSB-First, Left-Justified
R-ch
LRCIN
BCKIN
L-ch
1
2
3
16 17 18
LSB
1
2
3
16 17 18
LSB
1
DIN
MSB
MSB
ADC: 18-Bit, MSB-First, Left-Justified
R-ch
LRCIN
BCKIN
L-ch
DOUT
1
2
3
16 17 18
LSB
1
2
3
16 17 18
LSB
1
MSB
FORMAT 5: FMT[2:0] = "101"
DAC: 18-Bit, MSB-First, I2S
L_ch
LRCIN
BCKIN
R-ch
1
2
3
16 17 18
1
2
3
16 17 18
DIN
MSB
LSB
MSB
LSB
ADC: 18-Bit, MSB-First, I2S
L-ch
LRCIN
BCKIN
R-ch
1
2
3
16 17 18
LSB
1
2
3
16 17 18
LSB
DOUT
MSB
MSB
FORMAT 6: FMT[2:0] = "110"
DAC: 16-Bit, MSB-First, DSP-Frame
L-ch
LRCIN
BCKIN
R-ch
16
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
LSB
1
DIN
MSB
LSB
MSB
ADC: 16-Bit, MSB-First, DSP-Frame
L-ch
LRCIN
R-ch
BCKIN
16
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
LSB
1
DOUT
MSB
LSB
MSB
FIGURE 3. Audio Data Input/Output Format.
®
11
PCM3000/3001
tLRP
LRCIN
BCKIN
1.4V
1.4V
tLB
tBL
tBCH
tBCL
tBCY
tDIS
tDIH
DIN
1.4V
tBDO
tLDO
DOUT
0.5 x VDD
BCKIN Pulse Cycle Time
BCKIN Pulse Width High
BCKIN Pulse Width Low
tBCY
tBCH
tBCL
tBL
300ns (min)
120ns (min)
120ns (min)
40ns (min)
40ns (min)
tBCY (min)
BCKIN Rising Edge to LRCIN Edge
LRCIN Edge to BCKIN Rising Edge
LRCIN Pulse Width
tLB
tLRP
tDIS
DIN Set-up Time
40ns (min)
40ns (min)
40ns (max)
40ns (max)
20ns (max)
20ns (max)
DIN Hold Time
tDIH
tBDO
tLDO
tRISE
tFALL
DOUT Delay Time to BCKIN Falling Edge
DOUT Delay Time to LRCIN Edge
Rising Time of All Signals
Falling Time of All Signals
FIGURE 4. Audio Data Input/Output Timing.
Table I lists the relationship of typical sampling frequencies
and system clock frequencies, and Figures 5 and 6 illustrate
the typical system clock connections and external system
clock timing.
SYSTEM CLOCK
The system clock for PCM3000/3001 must be either 256fS,
384fS or 512fS, where fS is the audio sampling frequency.
The system clock can be either a crystal oscillator placed
between XTI (Pin 20) and XTO (Pin 21), or an external
clock input. If an external clock is used, the clock is
provided to either XTI or CLKIO (Pin 22), and XTO is open.
PCM3000/3001 has an XTI clock detection circuit which
senses if an XTI clock is operating. When the external clock
is delivered to XTI, CLKIO is a buffered output of XTI.
When XTI is connected to ground, the external clock must
be tied to CLKIO. For best performance, the “External
Clock Input 2” circuit in Figure 5 is recommended.
SAMPLING RATE FREQUENCY
(kHz)
SYSTEM CLOCK FREQUENCY
(MHz)
256fS
384fS
512fS
32
44.1
48
8.1920
11.2896
12.2880
12.2880
16.9340
18.4320
16.3840
22.5792
24.5760
TABLE I. System Clock Frequencies.
RESET
PCM3000/3001 also has a system clock detection circuit
which automatically senses if the system clock is operating at
256fS, 384fS, or 512fS. When 384fS or 512fS system clock is
used, the clock is divded into 256fS automatically. The 256fS
clock is used to operate the digital filter and the modulator.
PCM3000/3001 has an internal power-on reset circuit, as
well as an external forced reset (RSTB, Pin 28). The internal
power-on reset initializes (resets) when the supply voltage
VDD >4V (typ). External forced reset occurs when RSTB =
LOW, setting the outputs of the DAC to VCC/2. The power-
on reset has an initialization period equal to 1024 system
clock periods after VDD >4V and RSTB = “HIGH”. During
®
12
PCM3000/3001
CLKIO
256fS Internal System Clock
Clock Divider
C1
X’tal
XTI
R
C2
XTO
C1, C2 = 10 to 33pF
PCM3000/3001
CRYSTAL RESONATOR CONNECTION
CLKIO
CLKIO
External Clock
(TTL I/F)
256fS Internal System Clock
Clock Divider
256fS Internal System Clock
Clock Divider
XTI
XTI
External Clock
(CMOS I/F)
R
R
XTO
XTO
PCM3000/3001
EXTERNAL CLOCK INPUT 1: (XTO is open)
PCM3000/3001
EXTERNAL CLOCK INPUT 2: (XTO is open)
FIGURE 5. System Clock Connections.
tCLKIH tCLKIL
XTI
CLKIO
3.2V
1.4V
2.0V
0.8V
XTI or CLKIO
System Clock Pulse Width High tCLKIH
System Clock Pulse Width Low tCLKIL
12ns (min)
12ns (min)
FIGURE 6. External System Clock Timing.
®
13
PCM3000/3001
the initialization period, the outputs of the DAC are invalid,
and the analog outputs are forced to VCC/2. The output of the
ADC is also invalid during initialization or forced reset, and
the digital outputs are forced to all zeroes. Digital output
data is valid after 4096/fS once reset conditions are removed.
Figures 7 and 8 illustrate the power-on reset and reset-pin
reset timing.
SYNCHRONIZATION WITH THE DIGITAL AUDIO
SYSTEM
PCM3000/3001 operates with LRCIN synchronized to the
system clock. The CODEC does not require any specific
phase relationship between LRCIN and the system clock, but
there must be synchronization. If the synchronization be-
tween the system clock and LRCIN changes more than 6 bit
FUNCTION
ADC/DAC
DEFAULT (PCM3000/3001)
Audio Data Format (7 Selectable Formats)
ADC/DAC
DAC: 16-bit, MSB-first, Right-Justified
ADC: 16-bit, MSB-first, Left-Justified
LRCIN Polarity
Loop Back Control
Left Channel Attenuation
Right Channel Attenuation
Attenuation Control
ADC/DAC
ADC/DAC
DAC
DAC
DAC
Left/Right = High/Low
OFF
0dB
0dB
Left Channel and Right Channel = Individual Control
Infinite Zero Detection
DAC Output Control
Soft Mute Control
DAC
DAC
DAC
OFF
Output Enabled
OFF
De-emphasis (OFF, 32kHz, 44.1kHz, 48kHz)
Power Down Control
DAC
ADC
OFF
OFF
High Pass Filter Operation
ADC
ON
TABLE II. Selectable Functions.
4.4V
4.0V
3.6V
VDD
Reset
Reset Removal
Internal Reset
System Clock
1024 System Clock Periods
FIGURE 7. Internal Power-On Reset Timing.
tRST = 40ns minimum
RSTB-pin
tRST
Reset
Reset Removal
Internal Reset
1024 System Clock Periods
System Clock
FIGURE 8. External Forced Reset Timing.
ML
MC
MD
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
FIGURE 9. Control Data Input Format.
®
14
PCM3000/3001
some noise may occur. During the transitions between
normal data and undefined states, the output has
discontinuities, which will cause output noise.
clocks (BCKIN) during one sample (LRCIN) period because
of phase jitter on LRCIN, internal operation of the DAC will
stop within 1/fS, and the analog output will be forced to
bipolar zero (VCC/2) until the system clock is re-synchronized
to LRCIN. Internal operation of the ADC will also stop with
1/fS, and the digital output codes will be set to bipolar zero
until re-synchronization occurs. If LRCIN is synchronized
with 5 or less bit clocks to the system clock, operation will be
normal.
OPERATIONAL CONTROL
PCM3000 can be controlled in a software mode with a
three-wire serial interface on MC (Pin 25), MD (Pin 26), and
ML (Pin 27). Table II indicates selectable functions, and
Figures 9 and 12 illustrate control data input format and
timing. PCM3001 only allows for control of data format.
Figures 10 and 11 illustrate the effects on the output when
synchronization is lost. Before the outputs are forced to
bipolar zero (<1/fS seconds), the outputs are not defined and
Reset Removal or Power-Down(1) OFF
Internal Reset
DAC VOUT
Reset
32/fS
VCOM
(= 1/2 x VCC2)
4096/fS
(2)
Zero
ADC DOUT
NOTES: (1) Power-Down is for PCM3000 only. (2) The HPF transient response
(exponentially attenuationed signal with 200ms time constant) appears intially.
FIGURE 10. DAC Output and ADC Output for Reset and Power-Down.
State of
Synchronization
Synchronous
Asynchronous
Synchronous
within
1/fS
22.2/fS
Undefined Data
VCOM
(= 1/2 x VCC2)
Undefined
Data
DAC VOUT
Normal
Normal
32/fS
Undefined Data
Normal(1)
Normal
ADC DOUT
ZERO
NOTE: (1) The HPF transient response (exponentially attenuationed signal with 200ms time constant) appears initally.
FIGURE 11. DAC Output and ADC Output When Synchronization is Lost.
®
15
PCM3000/3001
tMHH
tMLH
tMLS
1.4V
1.4V
ML
MC
MD
tMCH
tMCL
tMLL
tMCY
LSB
1.4V
tMDS
tMDH
MC Pulse Cycle Time
tMCY
tMCL
tMCH
tMDS
tMDH
tMLL
tMLH
tMLS
tMLH
100ns (min)
40ns (min)
40ns (min)
40ns (min)
MC Pulse Width LOW
MC Pulse Width HIGH
MD Setup Time
MD Hold Time
40ns (min)
ML Low Level Time
ML High Level Time
ML Setup Time
40ns + 1SYSCLK (min)
40ns + 1SYSCLK (min)
40ns (min)
ML Hold Time
40ns (min)
SYSCLK: 1/256fS or 1/384fS
FIGURE 12. Control Data Input Timing.
MAPPING OF PROGRAM REGISTERS
B15
res
B14
res
B13
res
B12
res
B11
res
B10
A1
B9
A0
B8
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER 0
REGISTER 1
LDL
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
res
res
res
res
res
res
res
res
res
res
res
res
res
res
res
A1
A1
A1
A0
A0
A0
LDR
AR7
AR6
res
AR5
ATC
LOP
AR4
IZD
AR3
OUT
AR2
DM1
AR1
AR0
REGISTER 2
REGISTER 3
PDWN BYPS
res res
DM0 MUT
LRP res
res
FMT2 FMT1 FMT0
PROGRAM REGISTER 0
A (1:0): Bit 10, 9 Register Address
These bits define the address for REGISTER 0:
PROGRAM REGISTER (PCM3000)
The software mode allows the user to control special functions.
PCM3000’s special functions are controlled using four pro-
gram registers which are 16 bits long. There are four distinct
registers, with bits 9 and 10 determining which register is in
use. Table III describes the functions of the four registers.
A1
A0
0
0
Register 0
res:
Bit 11 : 15 Reserved
REGISTER
NAME
BIT
NAME
DESCRIPTION
These bits are reserved and should be set to “0”.
Register 0
Register 1
Register 2
A (1:0)
res
LDL
Register Address “00”
LDL:
Bit 8 DAC Attenuation Data Load Control for
Left Channel
Reserved, should be set to “0”
DAC Attenuation Data Load Control for Lch
Attenuation Data for Lch
AL (7:0)
This bit is used to simultaneously set analog
outputs of the left and right channels. The output
level is controlled by AL (7:0) attenuation data
when this bit is set to “1”. When set to “0”, the
new attenuation data will be stored into a register,
and the output level will remain at the previous
attenuation level. The LDR bit in REGISTER 1
has the equivalent function as LDL. When either
LDL or LDR is set to “1”, the output level of the
left and right channels are simultaneously con-
trolled.
A (1:0)
res
LDR
Register Address “01”
Reserved, should be set to “0”
DAC Attenuation Data Load Control for Rch
DAC Attenuation for Rch
AR (7:0)
A (1:0)
res
PDWN
BYPS
ATC
IZD
OUT
DEM (1:0)
MUT
Register Address “10”
Reserved, should be set to “0”
ADC Power Down Control
ADC High-Pass Filter Operation Control
DAC Attenuation Data Mode Control
DAC Infinite Zero Detection Circuit Control
DAC Output Enable Control
DAC De-emphasis Control
Lch and Rch Soft Mute Control
Register 3
A (1:0)
res
Register Address “11”
Reserved, should be set to “0”
LOP
FMT (2:0)
LRP
ADC/DAC Analog Loop-back Control
ADC/DAC Audio Data Format Selection
ADC/DAC Polarity of LR-clock Selection
TABLE III. Functions of the Registers.
®
16
PCM3000/3001
AL (7:0): Bit 7 :0 DAC Attenuation Data for Left Channel
BYPS: Bit 7
ADC High-Pass Filter Bypass Control
AL7 and AL0 are MSB and LSB, respectively.
The attenuation level (ATT) is given by:
This bit determines enables or disables the high-
pass filter for the ADC.
ATT = 20 x log10 (ATT data/256) (dB)
BYPS
AL (7:0)
ATTENUATION LEVEL
0
1
High-Pass Filter Enabled
High-Pass Filter Disabled (bypassed)
00h
01h
:
FEh
FFh
–∞dB (Mute)
–48.16dB
:
–0.07dB
0dB
ATC:
Bit 5
DAC Attenuation Channel Control
When set to “1”, the REGISTER 0 attenuation
data can be used for both DAC channels. In this
case, the REGISTER 1 attenuation data is ig-
nored.
PROGRAM REGISTER 1
A (1:0): Register Address
ATC
These bits define the address for REGISTER 1:
0
1
Individual Channel Attenuation Data Control
Common Channel Attenuation Data Control
A1
A0
0
1
Register 1
IZD:
Bit 4
DAC Infinite Zero Detection Circuit
Control
res:
Bit 15 : 11 Reserved
This bit enables the Infinite Zero Detection Circuit
in PCM3000. When enabled, this circuit will dis-
connect the analog output amplifier from the delta-
sigma DAC when the input is continuously zero for
65,536 consecutive cycles of BCKIN.
These bits are reserved and should be set to “0”
LDR:
Bit 8 DAC Attenuation Data Load Control for
Right Channel
This bit is used to simultaneously set analog
outputs of the left and right channels. The output
level is controlled by AR (7:0) attenuation data
when this bit is set to “1”. When set to “0”, the
new attenuation data will be stored into a register,
and the output level will remain at the previous
attenuation level. The LDL bit in REGISTER 0
has the equivalent function as LDR. When either
LDL or LDR is set to “1”, the output level of the
left and right channels are simultaneously con-
trolled.
IZD
0
1
Infinite Zero Detection Disabled
Infinite Zero Detection Enabled
OUT:
Bit 3
DAC Output Enable Control
When set to “1”, the outputs are forced to VCC/2
(bipolar zero). In this case, all registers in
PCM3000 hold the present data. Therefore, when
set to “0”, the outputs return to the previous
programmed state.
AR (7:0): Bit 7 : 0
DAC Attenuation Data for Right
Channel
OUT
0
1
DAC Outputs Enabled (normal operation)
DAC Outputs Disabled (forced to BPZ)
AR7 and AR0 are MSB and LSB respectively.
See REGISTER 0 for the attenuation formula.
DM (1:0):Bit 2,1
DAC De-emphasis Control
These bits select the de-emphasis mode as shown
below:
PROGRAM REGISTER 2
A (1:0): Bit 10, 9 Register Address
These bits define the address for REGISTER 2:
DM1
DM0
0
0
1
0
1
0
De-emphasis OFF
De-emphasis 48kHz ON
De-emphasis 44.1kHz ON
A1
A0
1
0
Register 2
1
1
De-emphasis 32kHz ON
res:
Bit 15:11, 6 Reserved
These bits are reserved and should be set to “0”.
PDWN: Bit 8 ADC Power-Down Control
MUT:
Bit 0
DAC Soft Mute Control
When set to “1”, both left and right-channel DAC
outputs are muted at the same time. This muting
is done by attenuating the data in the digital filter,
so there is no audible click noise when soft mute
is turned on.
This bit places the ADC section in a power-down
mode, forcing the output data to all zeroes. This
has no effect on the DAC section.
MUT
PDWN
0
1
Mute Disable
Mute Enable
0
1
Power Down Mode Disabled
Power Down Mode Enabled
®
17
PCM3000/3001
PROGRAM REGISTER 3
A (1:0): Bit 10, 9 Register Address
These bits define the address for REGISTER 3:
LOP:
Bit 5
ADC to DAC Loop-back Control
When this bit is set to “1”, the ADC’s audio data
is sent directly to the DAC. The data format will
default to I2S. In Format 6 (DSP Frame), Loop-
back is not supported.
A1
A0
1
1
Register 3
LOP
res:
Bit 15:11, 8:6, 0
Reserved
0
1
Loop-back Disable
Loop-back Enable
These bits are reserved, and should be set to “0”.
FMT (2:0) Bit 4:2 Audio Data Format Select
LRP:
Bit 1
ADC and DAC Polarity of LR-clock
Selection. Applies only to Formats
0 through 4.
These bits determine the input and output audio
data formats.
LRP
FMT2 FMT1 FMT0
DAC
ADC
Data Format
Data Format
0
1
Left-Channel is “H”, Right-Channel is “L”.
Left-Channel is “L”, Right-Channel is “H”.
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
16-bit, MSB-first,
Right-justified
16-bit, MSB-first,
Left-justified
18-bit, MSB-first,
Right-justified
18-bit, MSB-first,
Left-justified
PCM3001 DATA FORMAT CONTROL
16-bit, MSB-first,
Right-justified
16-bit, MSB-first,
Right-justified
The input and output data formats are controlled by pins 27
(FMT0), 26 (FMT1), and 25 (FMT2). Setting these pins to
the same values shown for the bit-mapped PCM3001 con-
trols the data formats.
18-bit, MSB-first,
Right-justified
18-bit, MSB-first,
Right-justified
16-/18-bit, MSB-first,
Left-justified
18-bit, MSB-first,
Left-justified
1
1
0
1
1
0
16-/18-bit, MSB-first, I2S
18-bit, MSB-first, I2S
16-bit, MSB-first,
DSP-frame
16-bit, MSB-first,
DSP-frame
1
1
1
Reserved
Reserved
+5V
Register Control
Interface
1
Reset
Serial
Control
or
Format
Control
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
(1)
3
Line In Left-Channel
2.2µF(2)
4.7µF
4.7µF
+
+
+
+
4
5
Reference
Line In Right-Channel
2.2µF(2)
Analog
Front-End
Analog
Front-End
(1)
6
7
10 to 33pF
470pF
Delta-Sigma
8
CLK/OSC
Manager
9
470pF
10µF
Decimation
Filter
10
11
12
13
14
Digital
Line Out Right-Channel
+
Audio
Digital
Audio
Data
Interpolation
Filter
Post
Low-Pass
Filter
Interface
Delta-Sigma
Bias
(1)
LPF and
Buffer
LPF and
Buffer
Line Out Left-Channel
Post
Low-Pass
Filter
NOTES: (1) Bypass capacitor = 0.1µF to 10µF. (2) The input capacitor
affects the pole of the HPF. Example: 2.2µF sets the cut-off frequency
to 4.8Hz, with a 66ms time constant.
FIGURE 13. Typical Connection Diagram for PCM3000/3001.
®
18
PCM3000/3001
CINP AND CINN INPUTS
APPLICATION AND LAYOUT
CONSIDERATIONS
A 470pF to 1000pF film capacitor is recommended between
CINPL and CINNL, CINPR, and CINNR to create an anti-alias
filter, which will have an 170kHz to 80kHz cut-off frequency.
These capacitors should be located as close as possible to the
CINP and CINN pins to avoid introducing unexpected noise or
dynamic errors into the delta-sigma modulator.
POWER SUPPLY BYPASSING
The digital and analog power supply lines to PCM3000/
3001 should be bypassed to the corresponding ground pins
with both 0.1µF ceramic and 10µF tantalum capacitors as
close to the device pins as possible. Although PCM3000/
3001 has three power supply lines to optimize dynamic
performance, the use of one common power supply is
generally recommended to avoid unexpected latch-up or pop
noise due to power supply sequencing problems. If separate
power supplies are used, back-to-back diodes are recom-
mended to avoid latch-up problems.
VCOM INPUTS
A 4.7µF to 10µF tantalum capacitor is recommended be-
tween VCOM and AGND2 to ensure low source impedance
of the DAC output common. This capacitor should be
located as close as possible to the VCOM pin to reduce
dynamic errors on the DAC common.
GROUNDING
SYSTEM CLOCK
In order to optimize dynamic performance of PCM3000/
3001, the analog and digital grounds are not internally
connected. PCM3000/3001 performance is optimized with a
single ground plane for all returns. It is recommended to tie
all PCM3000/3001 ground pins with low impedance con-
nections to the analog ground plane. PCM3000/3001 should
reside entirely over this plane to avoid coupling high fre-
quency digital switching noise into the analog ground plane.
The quality of the system clock can influence dynamic
performance of both the ADC and DAC in the PCM3000/
3001. The duty cycle, jitter, and threshold voltage at the
system clock input pin must be carefully managed. When
power is supplied to the part, the system clock, bit clock
(BCKIN) and a word clock (LCRIN) should also be supplied
simultaneously. Failure to supply the audio clocks will result
in a power dissipation increase of up to three times normal
dissipation and may degrade long term reliability if the
maximum power dissipation limit is exceeded.
VOLTAGE INPUT PINS
A tantalum capacitor, between 2.2µF and 10µF, is recom-
mended as an AC-coupling capacitor at the inputs. Combined
with the 15kΩ characteristic input impedance, a 2.2µF cou-
pling capacitor will establish a 4.8Hz cutoff frequency for
blocking DC. The input voltage range can be increased by
adding a series resistor on the analog input line. This series
resistor, when combined with the 15kΩ input impedance,
creates a voltage divider and enables larger input ranges.
RSTB CONTROL
If the capacitance between VREF and VCOM exceeds 4.7µF,
an external reset control delay time circuit must be used.
THEORY OF OPERATION
ADC SECTION
VREF INPUTS
The PCM3000/3001 ADC consists of a bandgap reference,
a stereo single-to-differential converter, a fully differential
5th-order delta-sigma modulator, a decimation filter (includ-
ing digital high pass), and a serial interface circuit. The
Block Diagram in this data sheet illustrates the architecture
of the ADC section, Figure 1 shows the single-to-differential
converter, and Figure 14 illustrates the architecture of the
5th-order delta-sigma modulator and transfer functions.
A 4.7µF to 10µF tantalum capacitor is recommended be-
tween VREFL, VREFR, and AGND1 to ensure low source
impedance for the ADC’s references. These capacitors should
be located as close as possible to the reference pins to reduce
dynamic errors on the ADC reference.
Analog In
X(z)
–
–
+
–
1st SW-CAP
Integrator
+
2nd SW-CAP
Integrator
3rd SW-CAP
Integrator
+
4th SW-CAP
Integrator
5th SW-CAP
Integrator
Qn(z)
Digital Out
Y(z)
+
+
+
+
+
+
+
+
H(z)
Comparator
1-Bit
DAC
Y(z) = STF(z) • X(z) + NTF(z) • Qn(z)
Signal Transfer Function
Noise Transfer Function
STF(z) = H(z)/[1 + H(z)]
NTF(z) = 1/[1 + H(z)]
FIGURE 14. Simplified 5th-Order Delta-Sigma Modulator.
®
19
PCM3000/3001
sigma modulator is shown in Figure 15. This 5-level delta-
sigma modulator has the advantage of stability and clock
jitter sensitivity over the typical one-bit (2 level) delta-sigma
modulator.
An internal high precision reference with two external ca-
pacitors provides all reference voltages which are required
by the ADC, which defines the full scale range for the
converter. The internal single-to-differential voltage con-
verter saves the design, space and extra parts needed for
external circuitry required by many delta-sigma converters.
The internal full differential signal processing architecture
provides a wide dynamic range and excellent power supply
rejection performance.
The combined oversampling rate of the delta-sigma modu-
lator and the internal 8X interpolation filter is 64fS for a
256fSsystem clock. The theoretical quantization noise per-
formance of the 5-level delta-sigma modulator is shown in
Figure 16.
The input signal is sampled at 64X oversampling rate,
eliminating the need for a sample-and-hold circuit, and
simplifying anti-alias filtering requirements. The 5th-order
delta-sigma noise shaper consists of five integrators which
use a switched-capacitor topology, a comparator and a
feedback loop consisting of a one-bit DAC. The delta-sigma
modulator shapes the quantization noise, shifting it out of
the audio band in the frequency domain. The high order of
the modulator enables it to randomize the modulator out-
puts, reducing idle tone levels.
3rd ORDER ∆Σ MODULATOR
0
–10
–20
–30
–40
–50
–60
–70
–80
The 64fS one-bit data stream from the modulator is con-
verted to 1fS 18-bit data words by the decimation filter,
which also acts as a low pass filter to remove the shaped
quantization noise. The DC components are removed by a
high pass filter function contained within the decimation
filter.
–90
–100
–110
–120
–130
–140
–150
THEORY OF OPERATION
DAC SECTION
0
5
10
15
20
25
30
The delta-sigma DAC section of PCM3000/3001 is based on
a 5-level amplitude quantizer and a 3rd-order noise shaper.
This section converts the oversampled input data to 5-level
delta-sigma format. A block diagram of the 5-level delta-
Frequency (kHz)
FIGURE 16. Quanitzation Noise Spectrum.
+
–
+
–
+
+
+
+
Z–1
Z–1
Z–1
In
8fS
18-Bit
+
+
+
5-level Quantizer
4
3
2
1
0
Out
64fS (256fS)
FIGURE 15. 5-Level ∆Σ Modulator Block Diagram.
®
20
PCM3000/3001
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