PCM3000E [TI]
SINGLE-ENDED ANALOG INPUT/OUTPUT;
| 型号： | PCM3000E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SINGLE-ENDED ANALOG INPUT/OUTPUT 输入元件 光电二极管 输出元件 商用集成电路 |
| 文件： | 总40页 (文件大小：598K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PCM3000
PCM3001
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SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
18-BIT STEREO AUDIO CODEC, SINGLE-ENDED ANALOG INPUT/OUTPUT
FEATURES
•
•
Single 5-V Power Supply
Small Package: SSOP-28
•
•
•
•
Monolithic 18-Bit ∆Σ ADC and DAC
16- or 18-Bit Input/Output Data
Accepts Seven Alternate Formats
Stereo ADC:
APPLICATIONS
•
•
•
•
•
•
•
•
Sampling Keyboards
Digital Mixers
– Single-Ended Voltage Input
– 64× Oversampling Digital Filter
• Pass-Band Ripple: ±0.05 dB
• Stop-Band Attenuation: –65 dB
– High Performance:
Mini-Disk Recorders
Hard-Disk Recorders
Karaoke Systems
DSP-Based Car Stereo
DAT Recorders
• THD+N: –88 dB
Video Conferencing
• SNR: 94 dB
DESCRIPTION
• Dynamic Range: 94 dB
– Digital High-Pass Filter
Stereo DAC
The PCM3000/3001 is a low-cost, single-chip stereo
audio codec (analog-to-digital and digital-to-analog
converter) with single-ended analog voltage input and
output.
•
– Single-Ended Voltage Outut
– Analog Low-Pass Filter
– 8× Oversampling Digital Filter
• Pass-Band Ripple: ±0.17 dB
• Stop-Band Attenuation: 35 dB
– High Performance:
Both ADCs and DACs employ delta-sigma modu-
lation with 64-times oversampling. The ADCs include
a digital decimation filter and the DACs include an
8-times oversampling digital interpolation filter. The
DACs also include digital attenuation, de-emphasis,
infinite zero detection and soft mute to form a
complete subsystem. The PCM3000/3001 operates
with left-justified, right-justified, I2S or DSP data
formats.
• THD+N: –90 dB
• SNR: 98 dB
• Dynamic Range: 97 dB
Special Features (PCM3000)
– Digital De-Emphasis
The PCM3000 can be programmed with a three-wire
serial interface for special features and data formats.
The PCM3001 can be pin-programmed for data
formats.
•
– Digital Attenuation (256 Steps)
– Soft Mute
The PCM3000 and PCM3001 are fabricated using a
highly advanced CMOS process and are available in
a small 28-pin SSOP package. The PCM3000/3001
are suitable for a wide variety of cost-sensitive
consumer applications where good performance is
required.
– Digital Loopback
•
•
Sample Rate: 4 kHz to 48 kHz
System Clock: 256 fs, 384 fs, 512 fs
Digital
Decimation
Filter
Lch In
Digital Out
Digital In
Delta-Sigma
Modulator
Analog Front-End
Rch In
Serial Interface
and
Mode Control
Low-Pass Filter
and
Output Buffer
Multilevel
Delta-Sigma
Modulator
Digital
Interpolation
Filter
Lch Out
Rch Out
Mode Control
System Clock
B0006-03
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2004, Texas Instruments Incorporated
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, VDD = VCC = 5 V, fS = 44.1 kHz, SYSCLK = 384 fS, CLKIO input, and 18-bit data, unless
otherwise noted
PARAMETER
DIGITAL INPUT/OUTPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input Logic
(1)
VIH
2
Input logic level
VDC
(1)
VIL
0.8
±1
(2)
IIN
Input logic current
µA
(3)
IIN
–120
(4)
VIH
0.64 VDD
VDC
Input logic level
(4)
VIL
0.28 VDD
(4)
IIN
Input logic current
±40
µA
Output Logic
(5)
VOH
IOUT = –1.6 mA
IOUT = 3.2 mA
IOUT = –3.2 mA
IOUT = 3.2 mA
4.5
4.5
Output logic level
Output logic level
(5)
VOL
0.5
0.5
VDC
(6)
VOH
(6)
VOL
Clock Frequency
fS Sampling frequency
4(7)
1.024
1.536
2.048
44.1
11.2896
16.9344
22.5792
48
12.288
18.432
24.576
kHz
256 fS
384 fS
512 fS
System clock frequency
MHz
ADC CHARACTERISTICS
Resolution
18
Bits
DC Accuracy
Gain mismatch, channel-to-channel
±1
±2
±5
±5
% of FSR
Gain error
Gain drift
±20
±1.7
±20
ppm of FSR/°C
% of FSR
Bipolar zero error
Bipolar zero drift
High-pass filter off(8)
High-pass filter off(8)
ppm of FSR/°C
(1) Pins 16, 17, 18, 22, 25, 26, 27, 28: LRCIN, BCKIN, DIN, CLKIO, MC/FMT2, MD/FMT1, ML/FMT0, RSTB
(2) Pins 16, 17, 18, 22: LRCIN, BCKIN, DIN, CLKIO (Schmitt-trigger input)
(3) Pins 25, 26, 27, 28: MC/FMT2, MD/FMT1, ML/FMT0, RSTB (Schmitt-trigger input, 70-kΩ internal pullup resistor)
(4) Pin 20: XTI
(5) Pins 19, 22: DOUT, CLKIO
(6) Pin 21: XTO
(7) Refer to Application Bulletin SBAA033 for information relating to operation at lower sampling frequencies.
(8) High-pass filter disabled (PCM3000 only) to measure dc offset
2
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VDD = VCC = 5 V, fS = 44.1 kHz, SYSCLK = 384 fS, CLKIO input, and 18-bit data, unless
otherwise noted
PARAMETER
Dynamic Performance(9)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f = 1 kHz, VIN = –0.5 dB
f = 1 kHz, VIN = –60 dB
f = 1 kHz, A-weighted
f = 1 kHz, A-weighted
–88
–31
94
–80
THD+N
dB
Dynamic range
90
90
88
dB
dB
dB
Signal-to-noise ratio
Channel separation
94
92
Digital Filter Performance
Pass band
Stop band
0.454 fS
Hz
Hz
dB
dB
s
0.583 fS
–65
Pass-band ripple
Stop-band attenuation
Delay time (latency)
Digital High-Pass Filter Response
Cutoff frequency
±0.05
17.4/fS
–3 dB
0.019 fS
mHz
ANALOG INPUT
Voltage range
0 dB (full scale)
2.9
2.1
15
Vp-p
VDC
kΩ
Center voltage
Input impedance
Antialiasing Filter
Cutoff frequency
–3 dB, CEXT = 470 pF
170
18
kHz
Bits
DAC CHARACTERISTICS
Resolution
DC Accuracy
Gain mismatch, channel-to-channel
±1
±1
±5
±5
% of FSR
% of FSR
Gain error
Gain drift
±20
±1
ppm of FSR/°C
% of FSR
Bipolar zero error
Bipolar zero drift
±20
ppm of FSR/°C
Dynamic Performance(9)
VOUT = 0 dB (full scale)
VOUT = –60 dB
–90
–34
97
–80
THD+N
dB
Dynamic range
EIAJ A-weighted
EIAJ A-weighted
90
92
90
dB
dB
dB
Signal-to-noise ratio (idle channel)
Channel separation
98
95
Digital Filter Performance
Pass band
0.445 fS
Hz
Hz
dB
dB
s
Stop band
0.555 fS
–35
Pass-band ripple
Stop-band attenuation
Delay time
±0.17
11.1/fS
(9) fIN = 1 kHz, using the System Two™ audio measurement system by Audio Precision™, rms mode with 20-kHz LPF, 400-Hz HPF
used for performance calculation or measurement.
3
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VDD = VCC = 5 V, fS = 44.1 kHz, SYSCLK = 384 fS, CLKIO input, and 18-bit data, unless
otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Output
Voltage range
0.62 VCC
0.5 VCC
Vp-p
VDC
kΩ
Center voltage
Load impedance
AC load
5
Analog Low-Pass Filter
Frequency response
f = 20 kHz
–0.16
dB
POWER SUPPLY REQUIREMENTS
VCC
4.5
4.5
5
5
5.5
5.5
50
VDC
VDC
mA
Voltage range
VDD
(10)
ICC, IDD
Supply current
VCC = VDD = 5 V
VCC = VDD = 5 V
32
Power dissipation
160
250
mW
TEMPERATURE RANGE
TA
Operation
–25
–55
85
°C
°C
Tstg
θJA
Storage
125
Thermal resistance
100
°C/W
(10) With no load on XTO and CLKIO
PACKAGE/ORDERING INFORMATION
PACKAGE
CODE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
PRODUCT
PACKAGE
QUANTITY
PCM3000E
PCM3000E/2K
PCM3001E
Rails
47
2000
47
PCM3000E
PCM3000E
PCM3001E
Tape and reel
Rails
28-pin SSOP
DB
PCM3001E
PCM3001E/2K
Tape and reel
2000
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Supply voltage: VDD, VCC1, VCC
Supply voltage differences
GND voltage differences
Digital input voltage
2
–0.3 V to 6.5 V
±0.1 V
±0.1 V
–0.3 to VDD + 0.3 V, < 6.5 V
Analog input voltage
–0.3 to VCC1, VCC2 + 0.3 V, < 6.5 V
Power dissipation
300 mW
±10 mA
Input current (any pins except supplies)
Operating temperature
–25°C to 85°C
–55°C to 125°C
260°C, 5 s
Storage temperature
Lead temperature, soldering
Package temperature (IR reflow, peak)
235°C
4
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
5
MAX
5.5
UNIT
VDC
VDC
Vp-p
Analog supply voltage, VCC1, VCC
2
Digital supply voltage, VDD
4.5
5
5.5
Analog input voltage, full scale (–0 dB)
Digital input logic family
2.9
TTL
System clock
8.192
32
24.576
48
MHz
kHz
kΩ
Digital input clock frequency
Sampling clock
Analog output load resistance
Analog output load capacitance
Digital output load capacitance
Operating free-air temperature, TA
5
50
10
pF
pF
–25
85
°C
5
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
PIN CONFIGURATION—PCM3000/3001
PCM3000
PCM3001
(TOP VIEW)
(TOP VIEW)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V L
RSTB
ML
MD
MC
DGND
V L
RSTB
FMT0
FMT1
FMT2
DGND
V
DD
CLKIO
XTO
XTI
DOUT
DIN
BCKIN
LRCIN
IN
IN
2
2
V
CC
1
V
CC
1
3
3
AGND1
AGND1
4
4
V
V
L
REF
V
V
L
REF
5
5
R
REF
R
REF
6
6
V R
V
DD
V R
IN
IN
7
7
C PR
CLKIO
XTO
XTI
DOUT
DIN
BCKIN
LRCIN
C PR
IN
IN
8
8
C NR
C NR
IN
IN
9
9
C NL
C NL
IN
IN
10
11
12
13
14
10
11
12
13
14
C PL
C PL
IN
IN
VCOM
VCOM
V
R
OUT
V
R
OUT
AGND2
AGND2
V
CC
2
V
OUT
L
V
CC
2
V
OUT
L
P0007-01
PIN ASSIGNMENTS—PCM3000
NAME
AGND1
AGND2
BCKIN
CINNL
CINNR
CINPL
CINPR
CLKIO
DGND
DIN
PIN
3
I/O
DESCRIPTION
–
–
I
ADC analog ground
DAC analog ground
Bit clock input(1)
13
17
9
–
–
–
–
I/O
–
I
ADC antialias filter capacitor (–), Lch
ADC antialias filter capacitor (–), Rch
ADC antialias filter capacitor (+), Lch
ADC antialias filter capacitor (+), Rch
8
10
7
22
24
18
19
16
25
26
27
28
2
Buffered oscillator output or external clock input(1)
Digital ground
Data input(1)
DOUT
LRCIN
MC
O
I
Data output
Sample rate clock input (fS)(1)
Serial mode control, bit clock
Serial mode control, data
Serial mode control, strobe pulse
Reset, active-low(1)(2)
I
MD
I
ML
I
RSTB
I
VCC
1
2
–
–
–
–
I
ADC analog power supply
DAC analog power supply
Digital power supply
VCC
14
23
11
1
VDD
VCOM
DAC output common
VIN
VIN
VOUT
VOUT
VREF
VREF
L
ADC analog input, Lch
ADC analog input, Rch
DAC analog output, Lch
DAC analog output, Rch
ADC input reference, Lch
ADC input reference, Rch
R
6
I
L
15
12
4
O
O
–
–
R
L
R
5
(1) Schmitt-trigger input
(2) With 70-kΩ typical internal pullup resistor
6
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
PIN ASSIGNMENTS—PCM3000 (continued)
NAME
XTI
PIN
20
I/O
I
DESCRIPTION
Oscillator input
Oscillator output
XTO
21
O
PIN ASSIGNMENTS—PCM3001
NAME
AGND1
AGND2
BCKIN
CINNL
CINNR
CINPL
CINPR
CLKIO
DGND
DIN
PIN
3
I/O
DESCRIPTION
–
–
I
ADC analog ground
DAC analog ground
Bit clock input(1)
13
17
9
–
–
–
–
I/O
–
I
ADC antialias filter capacitor (–), Lch
ADC antialias filter capacitor (–), Rch
ADC antialias filter capacitor (+), Lch
ADC antialias filter capacitor (+), Rch
Buffered oscillator output or external clock input(1)
Digital ground
8
10
7
22
24
18
19
27
26
25
16
28
2
Data input(1)
DOUT
FMT0
FMT1
FMT2
LRCIN
RSTB
O
I
Data output
Audio data format control 0(1)(2)
Audio data format control 1(1)(2)
Audio data format control 2(1)(2)
Sample rate clock input (fS)(1)
Reset, active-low(1)(2)
I
I
I
I
VCC
1
2
–
–
–
–
I
ADC analog power supply
DAC analog power supply
Digital power supply
VCC
14
23
11
1
VDD
VCOM
DAC output common
VIN
VIN
VOUT
VOUT
VREF
VREF
L
ADC analog input, Lch
R
6
I
ADC analog input, Rch
L
15
12
4
O
O
–
–
I
DAC analog output, Lch
DAC analog output, Rch
ADC input reference, Lch
ADC input reference, Rch
Oscillator input
R
L
R
5
XTI
20
21
XTO
O
Oscillator output
(1) Schmitt-trigger input
(2) With 70-kΩ typical internal pullup resistor
7
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF ADC SECTION
All specifications at TA = 25°C, VCC = VDD = 5 V, fIN = 1 kHz, fS = 44.1 kHz, 18-bit data, VIN = 2.9 Vp-p, and SYSCLK = 384 fS,
unless otherwise noted
THD+N
vs
TEMPERATURE
THD+N
vs
POWER SUPPLY
0.010
0.008
0.006
0.004
0.002
4
3
0.010
0.008
0.006
0.004
0.002
4
3
−60 dB
−60 dB
2
1
0
2
1
0
FS
FS
−25
0
25
50
75
100
4.25
4.50
4.75
5.00
5.25
5.50
5.75
T
A
− Free-Air Temperature − °C
V
CC
− Supply Voltage − V
G001
G002
Figure 1.
Figure 2.
THD+N
vs
SNR AND DYNAMIC RANGE
vs
SYSTEM CLOCK AND SAMPLING FREQUENCY
POWER SUPPLY
98
96
94
92
90
98
96
0.010
0.008
0.006
0.004
0.002
4
44.1 kHz
3
−60 dB
Dynamic Range
94
92
90
2
1
0
48 kHz
48 kHz
SNR
FS
44.1 kHz
512 f
S
4.25
4.50
4.75
5.00
5.25
5.50
5.75
256 f
384 f
S
S
V
CC
− Supply Voltage − V
System Clock
G004
G003
Figure 3.
Figure 4.
8
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF ADC SECTION (continued)
All specifications at TA = 25°C, VCC = VDD = 5 V, fIN = 1 kHz, fS = 44.1 kHz, 18-bit data, VIN = 2.9 Vp-p, and SYSCLK = 384 fS,
unless otherwise noted
THD+N
vs
OUTPUT DATA RESOLUTION
0.010
0.008
0.006
0.004
0.002
4
3
2
1
0
−60 dB
FS
16-Bit
18-Bit
Resolution
G005
Figure 5.
TYPICAL PERFORMANCE CURVES OF DAC SECTION
All specifications at TA = 25°C, VCC = VDD = 5 V, fIN = 1 kHz, fS = 44.1 kHz, 18-bit data, and SYSCLK = 384 fS, unless
otherwise noted
THD+N
vs
TEMPERATURE
THD+N
vs
POWER SUPPLY
0.010
0.008
0.006
0.004
0.002
0.010
0.008
0.006
0.004
0.002
4
3
4
3
−60 dB
−60 dB
2
1
0
2
1
0
FS
FS
−25
0
25
50
75
100
4.25
4.50
4.75
5.00
5.25
5.50
5.75
T
A
− Free-Air Temperature − °C
V
CC
− Supply Voltage − V
G006
G007
Figure 6.
Figure 7.
9
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF DAC SECTION (continued)
All specifications at TA = 25°C, VCC = VDD = 5 V, fIN = 1 kHz, fS = 44.1 kHz, 18-bit data, and SYSCLK = 384 fS, unless
otherwise noted
THD+N
SNR AND DYNAMIC RANGE
vs
vs
SYSTEM CLOCK AND SAMPLING FREQUENCY
POWER SUPPLY
0.010
0.008
0.006
0.004
0.002
4
100
98
96
94
92
100
98
96
94
92
Dynamic Range
3
SNR
48 kHz
2
−60 dB
48 kHz
44.1 kHz
1
FS
44.1 kHz
384 f 512 f
S
0
4.25
4.50
4.75
5.00
5.25
5.50
5.75
256 f
S
S
V
CC
− Supply Voltage − V
System Clock
G009
G008
Figure 8.
Figure 9.
THD+N
vs
INPUT DATA RESOLUTION
0.010
4
3
0.008
0.006
0.004
0.002
−60 dB
FS
2
1
0
16-Bit
18-Bit
Resolution
G010
Figure 10.
10
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs)
All specifications at TA = 25°C, VCC = VDD = 5 V, and SYSCLK = 384 fS, unless otherwise noted
DECIMATION FILTER
OVERALL CHARACTERISTICS
STOP-BAND ATTENUATION CHARACTERISTICS
0
−50
0
−20
−40
−100
−150
−200
−60
−80
−100
0
8
16
24
32
0.0
0.2
0.4
0.6
0.8
1.0
Normalized Frequency [× f Hz]
Normalized Frequency [× f Hz]
S
S
G011
G012
Figure 11.
Figure 12.
PASS-BAND RIPPLE CHARACTERISTICS
0.2
0.0
−0.2
−0.4
−0.6
−0.8
−1.0
0.0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency [× f Hz]
S
G013
Figure 13.
11
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) (continued)
All specifications at TA = 25°C, VCC = VDD = 5 V, and SYSCLK = 384 fS, unless otherwise noted
HIGH-PASS FILTER
HIGH-PASS FILTER RESPONSE
0.2
0.0
−0.2
−0.4
−0.6
−0.8
−1.0
0
1
2
3
4
Normalized Frequency [× f /1000 Hz]
S
G014
Figure 14.
ANTIALIASING FILTER
ANTIALIASING FILTER PASS-BAND
FREQUENCY RESPONSE (CEXT = 470 pF, 1000 pF)
ANTIALIASING FILTER OVERALL
FREQUENCY RESPONSE (CEXT = 470 pF, 1000 pF)
0.2
0.0
0
−10
−20
−30
−40
−50
470 pF
470 pF
−0.2
−0.4
−0.6
−0.8
−1.0
1000 pF
1000 pF
1
10
100
1k
10k
100k
1
10
100
1k
10k 100k
1M
10M
f − Frequency − Hz
f − Frequency − Hz
G015
G016
Figure 15.
Figure 16.
12
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs)
All specifications at TA = 25°C, VCC = VDD = 5 V, and SYSCLK = 384 fS, unless otherwise noted
DIGITAL FILTER
OVERALL FREQUENCY CHARACTERISTIC
PASS-BAND RIPPLE CHARACTERISTIC
0
−20
0.0
−0.2
−0.4
−0.6
−0.8
−1.0
−40
−60
−80
−100
0 0.4536 f
1.3605 f
2.2675 f
3.1745 f 4.0815 f
0
0.1134 f
0.2268 f
0.3402 f
0.4535 f
S
S
S
S
S
S
S
S
S
f − Frequency − Hz
f − Frequency − Hz
G017
G018
DE-EMPHASIS FILTER
DE-EMPHASIS FREQUENCY RESPONSE (32 kHz)
DE-EMPHASIS ERROR (32 kHz)
0
−2
0.6
0.4
−4
0.2
−6
0.0
−8
−0.2
−0.4
−0.6
−10
−12
0
5k
10k
15k
20k
25k
0
3628
7256
10884
14512
f − Frequency − Hz
f − Frequency − Hz
G019
G020
13
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued)
All specifications at TA = 25°C, VCC = VDD = 5 V, and SYSCLK = 384 fS, unless otherwise noted
DE-EMPHASIS FREQUENCY RESPONSE (44.1 kHz)
DE-EMPHASIS ERROR (44.1 kHz)
0
−2
0.6
0.4
−4
0.2
−6
0.0
−8
−0.2
−0.4
−0.6
−10
−12
0
5k
10k
15k
20k
25k
0
4999.8375 9999.675 14999.5125 19999.35
f − Frequency − Hz
f − Frequency − Hz
G021
G022
DE-EMPHASIS FREQUENCY RESPONSE (48 kHz)
DE-EMPHASIS ERROR (48 kHz)
0
−2
0.6
0.4
−4
0.2
−6
0.0
−8
−0.2
−0.4
−0.6
−10
−12
0
5k
10k
15k
20k
25k
0
5442
10884
16326
21768
f − Frequency − Hz
f − Frequency − Hz
G023
G024
14
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued)
All specifications at TA = 25°C, VCC = VDD = 5 V, and SYSCLK = 384 fS, unless otherwise noted
ANALOG LOW-PASS FILTER
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(20 Hz–24 kHz, EXPANDED SCALE)
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(10 Hz–10 MHz)
10
5
1.0
0
−5
0.5
0.0
−10
−15
−20
−25
−30
−35
−40
−45
−50
−55
−60
−0.5
−1.0
10
100
1k
10k
100k
1M
10M
20
100
1k
10k 24k
f − Frequency − Hz
f − Frequency − Hz
G026
G025
15
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
Block Diagram
C PL
IN
C NL
IN
(+)
(−)
Analog
Front-End
Circuit
Decimation
and
High-Pass Filter
Delta-Sigma
Modulator
V
L
LRCIN
BCKIN
IN
V
L
REF
Serial Data
Interface
Reference
ADC
V
R
REF
DIN
(−)
(+)
Analog
Front-End
Circuit
Decimation
and
High-Pass Filter
Delta-Sigma
Modulator
V R
IN
DOUT
C NR
IN
Loop Control
C PR
IN
(1)
ML(FMT0)
Analog
Low-Pass
Filter
Multilevel
Delta-Sigma
Modulator
Interpolation
Filter
8× Oversampling
Mode
Control
Interface
V L
OUT
(1)
MC(FMT2)
(1)
VCOM
MD(FMT1)
DAC
Analog
Low-Pass
Filter
Multilevel
Delta-Sigma
Modulator
Interpolation
Filter
8× Oversampling
V R
OUT
Reset
RSTB
Power Supply
Clock/OSC Manager
AGND2
V 2
CC
AGND1
V 1
CC
DGND
V
DD
CLKIO
XTO
XTI
B0004-05
16
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
470 pF
C PL
IN
C NL
IN
10
9
2.2 µF
15 kΩ
V
V
L
IN
−
+
1
4
+
−
+
1 kΩ
1 kΩ
(+)
(−)
Delta-Sigma
Modulator
L
REF
+
4.7 µF
V
REF
S0011-04
Figure 17. Analog Front-End (Single-Channel)
PCM AUDIO INTERFACE
The four-wire digital audio interface for the PCM3000/3001 is on LRCIN (pin 16), BCKIN (pin 17), DIN (pin 18),
and DOUT (pin 19). The PCM3000/3001 can operate with seven different data formats. For the PCM3000, these
formats are selected through program register 3 in the software mode. For the PCM3001, data formats are
selected by pin-strapping the three format pins. Figure 18, Figure 19, Figure 20 and Figure 21 illustrate the audio
data input/output format. Figure 22 shows the audio data input/output timing. The PCM3000/3001 can accept 32,
48, or 64 bit clocks (BCKIN) during one clock of LRCIN. Only formats 0, 2, and 6 can be selected when 32 bit
clocks/LRCIN are applied.
17
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
FORMAT 0: FMT[2:0] = 000
DAC: 16-Bit, MSB-First, Right-Justified
LRCIN
BCKIN
DIN
Left-Channel
Right-Channel
16
1
2
3
14 15 16
LSB
1
2
3
14 15 16
MSB
MSB
LSB
ADC: 16-Bit, MSB-First, Left-Justified
Left-Channel
Right-Channel
LRCIN
BCKIN
DOUT
1
1
2
3
14 15 16
LSB
1
2
3
14 15 16
LSB
MSB
MSB
FORMAT 1: FMT[2:0] = 001
DAC: 18-Bit, MSB-First, Right-Justified
LRCIN
BCKIN
Left-Channel
Right-Channel
DIN
18
1
2
3
16 17 18
LSB
1
2
3
16 17 18
LSB
MSB
MSB
ADC: 18-Bit, MSB-First, Left-Justified
Left-Channel
Right-Channel
LRCIN
BCKIN
DOUT
1
1
2
3
16 17 18
LSB
1
2
3
16 17 18
LSB
MSB
MSB
T0016-07
Figure 18. Audio Data Input/Output Format (Formats 0 and 1)
18
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PCM3001
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SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
FORMAT 2: FMT[2:0] = 010
DAC: 16-Bit, MSB-First, Right-Justified
LRCIN
BCKIN
Left-Channel
Right-Channel
DIN
16
1
2
3
14 15 16
LSB
1
2
3
14 15 16
LSB
MSB
MSB
ADC: 16-Bit, MSB-First, Right-Justified
Left-Channel
Right-Channel
LRCIN
BCKIN
DOUT
16
1
2
3
14 15 16
LSB
1
2
3
14 15 16
LSB
MSB
MSB
FORMAT 3: FMT[2:0] = 011
DAC: 18-Bit, MSB-First, Right-Justified
LRCIN
BCKIN
Left-Channel
Right-Channel
DIN
18
1
2
3
16 17 18
LSB
1
2
3
16 17 18
LSB
MSB
MSB
ADC: 18-Bit, MSB-First, Right-Justified
LRCIN
BCKIN
Left-Channel
Right-Channel
DOUT
18
1
2
3
16 17 18
LSB
1
2
3
16 17 18
LSB
MSB
MSB
T0016-08
Figure 19. Audio Data Input/Output Format (Formats 2 and 3)
19
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PCM3001
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SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
FORMAT 4: FMT[2:0] = 100
DAC: 18-Bit, MSB-First, Left-Justified
LRCIN
BCKIN
DIN
Left-Channel
Right-Channel
1
1
2
3
16 17 18
LSB
1
2
3
16 17 18
LSB
MSB
MSB
ADC: 18-Bit, MSB-First, Left-Justified
Left-Channel
Right-Channel
LRCIN
BCKIN
DOUT
1
1
2
3
16 17 18
LSB
1
2
3
16 17 18
LSB
MSB
MSB
FORMAT 5: FMT[2:0] = 101
2
DAC: 18-Bit, MSB-First, I S
Left-Channel
Right-Channel
LRCIN
BCKIN
DIN
1
2
3
16 17 18
1
2
3
16 17 18
MSB
LSB
MSB
LSB
2
ADC: 18-Bit, MSB-First, I S
Left-Channel
Right-Channel
LRCIN
BCKIN
DOUT
1
2
3
16 17 18
LSB
1
2
3
16 17 18
LSB
MSB
MSB
T0016-09
Figure 20. Audio Data Input/Output Format (Formats 4 and 5)
20
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
FORMAT 6: FMT[2:0] = 110
DAC: 16-Bit, MSB-First, DSP-Frame
LRCIN
BCKIN
Left-Channel
Right-Channel
DIN
16
1
2
3
14 15 16
LSB
1
2
3
14 15 16
LSB
1
MSB
MSB
ADC: 16-Bit, MSB-First, DSP-Frame
Left-Channel
Right-Channel
LRCIN
BCKIN
DOUT
16
1
2
3
14 15 16
LSB
1
2
3
14 15 16
LSB
1
MSB
MSB
T0016-10
Figure 21. Audio Data Input/Output Format (Format 6)
21
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
t
(LRP)
1.4 V
LRCIN
t
t
(LB)
(BCL)
t
t
(BL)
(BCH)
1.4 V
1.4 V
BCKIN
DIN
t
t
t
(DIS)
(DIH)
(BCY)
t
t
(LDO)
(BDO)
0.5 V
DD
DOUT
T0021−02
BCKIN pulse cycle time
t(BCY)
300 ns (min)
120 ns (min)
120 ns (min)
40 ns (min)
40 ns (min)
t(BCY) (min)
40 ns (min)
40 ns (min)
40 ns (max)
40 ns (max)
BCKIN pulse duration, HIGH
BCKIN pulse duration, LOW
BCKIN rising edge to LRCIN edge
LRCIN edge to BCKIN rising edge
LRCIN pulse duration
t(BCH)
t(BCL)
t(BL)
t(LB)
t(LRP)
t(DIS)
t(DIH)
t(BDO)
t(LDO)
DIN setup time
DIN hold time
DOUT delay time to BCKIN falling edge
DOUT delay time to LRCIN edge
Rising time of all signals
t(RISE) 20 ns (max)
t(FALL) 20 ns (max
Falling time of all signals
Figure 22. Audio Data Input/Output Timing
SYSTEM CLOCK
The system clock for the PCM3000/3001 must be either 256 fS, 384 fS, or 512 fS, where fS is the audio sampling
frequency. The system clock can be either a crystal oscillator placed between XTI (pin 20) and XTO (pin 21), or
an external clock input. If an external clock is used, the clock is provided to either XTI or CLKIO (pin 22), and
XTO is open. The PCM3000/3001 has an XTI clock detection circuit which senses if an XTI clock is operating.
When the external clock is delivered to XTI, CLKIO is a buffered output of XTI. When XTI is connected to
ground, the external clock must be tied to CLKIO. For best performance, the external-clock-input-2 circuit in
Figure 23 is recommended.
The PCM3000/3001 also has a system-clock detection circuit which automatically senses if the system clock is
operating at 256 fS, 384 fS, or 512 fS. When a 384-fS or 512-fS system clock is used, the clock is divided into
256 fS automatically. The 256-fS clock is used to operate the digital filters and the modulators.
Table 1 lists the relationship of typical sampling frequencies and system clock frequencies, and Figure 23 and
Figure 24 illustrate the typical system clock connections and external system clock timing.
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PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
CLKIO
256-f Internal System Clock
S
Clock Divider
C
C
1
Xtal
XTI
R
2
XTO
C = C = 10 to 33 pF
PCM3000/3001
1
2
Crystal Resonator Connection (Xtal must be fundamental mode, parallel resonant)
CLKIO
CLKIO
External Clock
(TTL I/F)
256-f Internal System Clock
S
256-f Internal System Clock
S
Clock Divider
Clock Divider
XTI
XTI
External Clock
(CMOS I/F)
R
R
XTO
XTO
PCM3000/3001
External Clock Input 1 : (XTO is open)
PCM3000/3001
External Clock Input 2 : (XTO is open)
S0017−01
Figure 23. System Clock Connections
23
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
Table 1. System Clock Frequencies
SAMPLING RATE FREQUENCY (kHz)
SYSTEM CLOCK FREQUENCY (MHz)
256 fS
384 fS
12.2880
16.9344
18.4320
512 fS
32
44.1
48
8.1920
11.2896
12.2880
16.3840
22.5792
24.5760
t
(CLKIH)
XTI
CLKIO
3.2 V
2.0 V
XTI or CLKIO
1.4 V
0.8 V
t
(CLKIL)
T0005-06
System clock pulse duration, HIGH
System clock pulse duration, LOW
t(CLKIH)
t(CLKIL)
12 ns (min)
12 ns (min)
Figure 24. External System Clock Timing
POWER-ON RESET
The PCM3000/3001 has internal power-on reset circuitry. Power-on reset occurs when the system clock (XTI or
CLKIO) is active and VDD > 4 V. For the PCM3001, the system clock must complete a minimum of 3 complete
cycles prior to VDD > 4 V to ensure proper reset operation. The initialization sequence requires 1024 system
cycles for completion, as shown in Figure 25. Figure 26 shows the state of the DAC and ADC outputs during and
after the reset sequence.
4.4 V
4.0 V
3.6 V
V
DD
Reset
Reset Removal
Internal Reset
3 Clocks Minimum
1024 System Clock Periods
System Clock
(XTI or CLKIO)
T0014-04
Figure 25. Internal Power-On Reset Timing
24
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
(1)
Reset Removal or Power Down Off
Reset
Internal Reset
Ready/Operation
32/f
S
DAC V
OUT
VCOM
(0.5 V 2)
CC
4096/f
S
(2)
Zero Data
Zero Data
Normal Data
ADC DOUT
T0019-03
(1) Power down is for PCM3000 only.
(2) The HPF transient response (exponentially attenuated signal from ±1.5% dc with 200-ms time constant) appears
initially.
Figure 26. DAC Output and ADC Output for Reset and Power Down
EXTERNAL RESET
The PCM3000/3001 includes a reset input, RSTB (pin 28). As shown in Figure 27, the external reset signal must
drive RSTB low for a minimum of 40 nanoseconds while the system clock is active in order to initiate the reset
sequence. Initialization starts on the rising edge of RSTB, and requires 1024 system clock cycles for completion.
Figure 26 shows the state of the DAC and ADC outputs during and after the reset sequence.
t
= 40 ns (min)
(RST)
RSTB Pulse Duration
RSTB
t
(RST)
Reset
Reset Removal
Internal Reset
1024 System Clock Periods
System Clock
(XTI or CLKIO)
T0015-04
Figure 27. External Forced-Reset Timing
SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM
The PCM3000/3001 operates with LRCIN synchronized to the system clock. The codec does not require any
specific phase relationship between LRCIN and the system clock, but there must be synchronization of LRCIN
and the system clock. If the synchronization between the system clock and LRCIN changes more than 6 bit
clocks (BCKIN) during one sample (LRCIN) period because of phase jitter on LRCIN, internal operation of the
DAC stops within 1/fS, and the analog output is forced to bipolar zero (VCC2/2) until the system clock is
resynchronized to LRCIN. Internal operation of the ADC also stops within 1/fS, and the digital output codes are
set to bipolar zero until resynchronization occurs. If LRCIN is synchronized within 5 or fewer bit clocks to the
system clock, operation remains normal.
Figure 28 illustrates the effects on the output when synchronization is lost. Before the outputs are forced to
bipolar zero (<1/fS seconds), the outputs are not defined and some noise may occur. During the transitions
between normal data and undefined states, the output has discontinuities, which cause output noise.
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PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
Resynchronization
Synchronization Lost
Synchronous
Asynchronous
Synchronous
State of Synchronization
Within 1/f
22.2/f
S
S
Undefined
Data
VCOM
(0.5 V 2)
Undefined
Data
DAC V
OUT
Normal Data
Normal Data
CC
32/f
S
Undefined
Data
(1)
ADC DOUT
Normal Data
Zero Data
Normal Data
T0020-04
(1) The HPF transient response (exponentially attenuated signal from ±1.5% dc with 200-ms time constant) appears
initially.
Figure 28. DAC Output and ADC Output For Loss of Synchronization
OPERATIONAL CONTROL
The PCM3000 can be controlled in the software mode with a three-wire serial interface on MC (pin 25),
MD (pin 26), and ML (pin 27). Table 2 indicates selectable functions, and Figure 29 and Figure 30 illustrate
control data input format and timing. The PCM3001 only allows for control of data format.
Table 2. Selectable Functions
FUNCTION
ADC/DAC
DEFAULT (PCM3000)
Audio data format (7 selectable formats)
ADC/DAC
DAC: 16-bit, MSB-first, right-justified
ADC: 16-bit, MSB-first, left-justified
LRCIN polarity
ADC/DAC
ADC/DAC
DAC
Left/right = high/low
Loopback control
OFF
Left-channel attenuation
Right-channel attenuation
Attenuation control
0 dB
DAC
0 dB
DAC
Left channel and right channel = individual control
Infinite zero detection
DAC output control
DAC
OFF
Output enabled
OFF
DAC
Soft mute control
DAC
De-emphasis (OFF, 32 kHz, 44.1 kHz, 48 kHz)
Power-down control
DAC
OFF
ADC
OFF
High-pass filter operation
ADC
ON
ML
MC
B14 B13 B12 B11 B10
B9
B8
B6
B5
B4
B3
B2
B1
B0
MD
B15
B7
T0023-01
Figure 29. Control Data Input Format
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PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
t
(MHH)
t
(MLH)
t
(MLS)
1.4 V
ML
t
(MCL)
t
(MLL)
t
(MCH)
MC
MD
1.4 V
1.4 V
t
(MCY)
LSB
t
(MDS)
t
(MDH)
T0024-01
MC pulse cycle time
t(MCY)
t(MCL)
t(MCH)
t(MDS)
t(MDH)
t(MLL)
t(MHH)
t(MLS)
t(MLH)
100 ns (min)
MC pulse duration, LOW
MC pulse duration, HIGH
MD setup time
40 ns (min)
40 ns (min)
40 ns (min)
40 ns (min)
MD hold time
ML low-level time
ML high-level time
ML setup time(2)
40 ns + 1 SYSCLK(1) (min)
40 ns + 1 SYSCLK(1) (min)
40 ns (min)
ML hold time(3)
40 ns (min)
SYSCLK (period): 1/256 fS or 1/384 fS or 1/512 fS
(1) SYSCK: system clock cycle
(2) ML rising edge to the next MC rising edge
(3) MC rising edge for LSB-to-ML rising edge
Figure 30. Control Data Input Timing
MAPPING OF PROGRAM REGISTERS
B15 B14 B13 B12 B11
B10
A1
B9
A0
B8
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER 0 res
REGISTER 1 res
REGISTER 2 res
REGISTER 3 res
res
res
res
res
res
res
res
res
res
res
res
res
res
res
res
res
LDL
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
A1
A1
A1
A0
A0
A0
LDR
AR7
AR6
res
AR5
ATC
AR4
IZD
AR3
AR2
AR1
AR0
PDWN BYPS
res res
OUT DEM1 DEM0 MUT
res
res
LOP FMT2 FMT1 FMT0 LRP
NOTE: res indicates a reserved bit, which should be set to 0.
PROGRAM REGISTER (PCM3000)
The software mode allows the user to control special functions. The PCM3000 special functions are controlled
using four program registers which are each 16 bits long. There are four distinct registers, with bits 9 and 10
determining which register is in use. Table 3 describes the functions of the four registers.
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PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
Table 3. Functions of the Registers
REGISTER NAME
REGISTER BIT(S)
BIT NAME
res
DESCRIPTION
Reserved, should be set to 0
Register address 00
Register 0
15–11
10–9
8
A[1:0]
LDL
DAC attenuation data load control for
Lch
7–0
15–11
10–9
8
AL[7:0]
res
DAC attenuation data for Lch
Reserved, should be set to 0
Register address 01
Register 1
Register 2
A[1:0]
LDR
DAC attenuation data load control for
Rch
7–0
AR[7:0]
res
DAC attenuation data for Rch
Reserved, should be set to 0
Register address 10
15–11
10–9
A[1:0]
PDWN
BYPS
res
8
ADC power-down control
7
6
ADC high-pass filter bypass control
Reserved, should be set to 0
DAC attenuation data mode control
DAC infinite zero detection circuit control
DAC output enable control
5
ATC
4
IZD
3
OUT
DEM[1:0]
MUT
res
2–1
0
DAC de-emphasis control
DAC Lch and Rch soft mute control
Reserved, should be set to 0
Register address 11
Register 3
15–11
10–9
8–6
5
A[1:0]
res
Reserved, should be set to 0
ADC/DAC analog loopback control
ADC/DAC audio data format selection
ADC/DAC polarity of LR-clock selection
Reserved, should be set to 0
LOP
4–2
1
FMT[2:0]
LRP
0
res
PROGRAM REGISTER 0
res:
Bits 15:11 – Reserved
These bits are reserved and should be set to 0.
A[1:0]:
Bits 10:9 – Register Address
These bits definte the address for REGISTER 0:
A1
A0
0
0
Register 0
LDL:
Bit 8 – DAC Attenuation Data Load Control for Left Channel
This bit is used to simultaneously set the analog outputs of the left and right channels. The output
level is controlled by AL[7:0] attenuation data when this bit is set to 1. When set to 0, the new
attenuation data is stored into a register, and the output level remains at the previous attenuation
level. The LDR bit in REGISTER 1 has the equivalent function as LDL. When either LDL or LDR is
set to 1, the output levels of the left and right channels are simultaneously controlled.
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PCM3000
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SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
AL[7:0]:
Bits 7:0 – DAC Attenuation Data for Left Channel
AL7 and AL0 are the MSB and LSB, respectively. The attenuation level (ATT) is given by
ATT = 20 × log10 (AL[7:0]/256) (dB), except AL[7:0] = FFh
AL[7:0]
00h
01h
:
ATTENUATION LEVEL
–∞ dB (mute)
–48.16 dB
:
FEh
FFh
–0.07 dB
0 dB (default)
PROGRAM REGISTER 1
res:
Bits 15:11 – Reserved
These bits are reserved and should be set to 0.
A[1:0]:
Bits 10:9 – Register Address
These bits definte the address for REGISTER 1.
A1
A0
0
1
Register 1
LDR:
Bit 8 – DAC Attenuation Data Load Control for Right Channel
This bit is used to simultaneously set the analog outputs of the left and right channels. The output
level is controlled by AR[7:0] attenuation data when this bit is set to 1. When set to 0, the new
attenuation data is stored into a register, and the output level remains at the previous attenuation
level. The LDL bit in REGISTER 0 has the equivalent function as LDR. When either LDL or LDR is
set to 1, the output levels of the left and right channels are simultaneously controlled.
AR[7:0]:
Bits 7:0 – DAC Attenuation Data for Right Channel
AR7 and AR0 are the MSB and LSB, respectively. The attenuation level (ATT) is given by
ATT = 20 × log10 (AR[7:0]/256) (dB), except AR[7:0] = FFh
AR[7:0]
00h
01h
:
ATTENUATION LEVEL
–∞ dB (mute)
–48.16 dB
:
FEh
FFh
–0.07 dB
0 dB (default)
PROGRAM REGISTER 2
res:
Bits 15:11 – Reserved
These bits are reserved and should be set to 0.
A[1:0]:
Bits 10:9 – Register Address
These bits define the address for REGISTER 2:
A1
A0
1
0
Register 2
29
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
PDWN:
Bit 8 – ADC Power-Down Control
This bit places the ADC section in a power-down mode, forcing the output data to all zeroes. This has no effect
on the DAC section or the contents of the mode registers.
PDWN
0
1
Power-down mode disabled (default)
Power-down mode enabled
BYPS:
Bit 7 – ADC High-Pass Filter Bypass Control
This bit enables or disables the high-pass filter for the ADC.
BYPS
0
1
High-pass filter enabled (default)
High-pass filter disabled (bypassed)
res:
Bit 6 – Reserved
This bit is reserved and should be set to 0.
ATC:
Bit 5 – DAC Attenuation Data Mode Control
When set to 1, the REGISTER 0 attenuation data is used for both DAC channels. In this case, the REGISTER 1
attenuation data is ignored.
ATC
0
1
Individual channel attenuation data control (default)
Common channel attenuation data control
IZD:
Bit 4 – DAC Infinite Zero Detection Circuit Control
This bit enables the infinite zero detection circuit in the PCM3000. When enabled, this circuit disconnects the
analog output amplifier from the delta-sigma DAC when the input is continuously zero for 65,536 consecutive
cycles of BCKIN.
IZD
0
1
Infinite zero detection disabled (default)
Infinite zero detection enabled
OUT:
Bit 3 – DAC Output Enable Control
When set to 1, the outputs are forced to VCC/2 (bipolar zero). In this case, all registers in the PCM3000 hold the
present data. Therefore, when set to 0, the outputs return to the previous programmed state.
OUT
0
1
DAC outputs enabled (default normal operation)
DAC outputs disabled (forced to BPZ)
DEM[1:0]: Bits 2:1 – DAC De-Emphasis Control
These bits select the de-emphasis mode as shown.
DEM1
DEM0
0
0
1
1
0
1
0
1
De-emphasis OFF (default)
De-emphasis 48 kHz ON
De-emphasis 44.1 kHz ON
De-emphasis 32 kHz ON
30
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
MUT:
Bit 0 – DAC Soft Mute Control
When set to 1, both left- and right-channel DAC outputs are muted at the same time. This muting is done by
attenuating the data in the digital filter, so that there is no audible click noise when soft mute is turned on.
MUT
0
1
Mute disabled (default)
Mute enabled
PROGRAM REGISTER 3
res:
Bits 15:11 – Reserved
These bits are reserved and should be set to 0.
A[1:0]:
Bits 10:9 – Register Address
These bits define the address for REGISTER 3.
A1
A0
1
1
Register 3
res:
Bits 8:6 – Reserved
These bits are reserved and should be set to 0.
LOP:
Bit 5 – ADC to DAC Loopback Control
When this bit is set to 1, the ADC audio data is sent directly to the DAC. The data format defaults to I2S; DOUT
is still available in loopback mode.
LOP
0
1
Loopback disabled (default)
Loopback enabled
FMT[2:0]: Bits 4:2 – Audio Data Format Select
These bits determine the input and output audio data formats. (default: FMT[2:0] = 000b)
FM2
0
FMT1
FMT0
DAC DATA FORMAT
16-bit, MSB-first, right-justified
18-bit, MSB-first, right-justified
16-bit, MSB-first, right-justified
18-bit, MSB-first, right-justified
16-/18-bit, MSB-first, left-justified
16-/18-bit, MSB-first, I2S
ADC DATA FORMAT
16-bit, MSB-first, left-justified
18-bit, MSB-first, left-justified
16-bit, MSB-first, right-justified
18-bit, MSB-first, right-justified
18-bit, MSB-first, left-justified
18-bit, MSB-first, I2S
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
16-bit, MSB-first, DSP-frame
Reserved
16-bit, MSB-first, DSP-frame
Reserved
1
LRP:
Bit 1 – ADC-to-DAC LRCK Polarity Select
Polarity of LRCIN applies only to formats 0 through 4.
LOP
0
1
Left channel is H, right channel is L (default).
Left channel is L, right channel is H.
res:
Bit 0 – Reserved
This bit is reserved and should be set to 0.
PCM3001 DATA FORMAT CONTROL
The input and output data formats are controlled by pins 27 (FMT0), 26 (FMT1), and 25 (FMT2). Set these pins
to the same values shown for the bit-mapped PCM3000 controls in program register 3.
31
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
THEORY OF OPERATION
ADC SECTION
The PCM3000/3001 ADC consists of a band-gap reference, a stereo single-to-differential converter, a fully
differential 5th-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface
circuit. The block diagram in this data sheet illustrates the architecture of the ADC section. Figure 17 shows the
single-to-differential converter, and Figure 31 illustrates the architecture of the 5th-order delta-sigma modulator
and transfer functions.
An internal high-precision reference with two external capacitors provides all reference voltages required by the
ADC, which defines the full scale range for the converter. The internal single-to-differential voltage converter
saves the space and extra parts needed for external circuitry which is required by many delta-sigma converters.
The internal full-differential signal processing architecture provides a wide dynamic range and excellent power
supply rejection performance.
The input signal is sampled at a 64× oversampling rate, eliminating the need for a sample-and-hold circuit, and
simplifying antialias filtering requirements. The 5th-order delta-sigma noise shaper consists of five integrators
which use a switched-capacitor topology, a comparator, and a feedback loop consisting of a one-bit DAC. The
delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain.
The high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels.
The 64-fS 1-bit data stream from the modulator is converted to 1-fS, 18-bit data words by the decimation filter,
which also acts as a low-pass filter to remove the shaped quantization noise. The dc components are removed
by a high-pass filter function contained within the decimation filter.
Analog
In
−
−
st
nd
rd
th
th
1
2
3
4
5
X(z)
+
+
+
SW-CAP
SW-CAP
SW-CAP
SW-CAP
SW-CAP
Qn(z)
Integrator
Integrator
Integrator
Integrator
Integrator
−
Digital
Out
Y(z)
+
+
+
+
+
+
+
+
H(z)
Comparator
1-Bit
DAC
Y(z) = STF(z) * X(z) + NTF(z) * Qn(z)
Signal Transfer Function
Noise Transfer Function
STF(z) = H(z) / [1 + H(z)]
NTF(z) = 1 / [1 + H(z)]
B0005-01
Figure 31. Simplified Fifth-Order Delta-Sigma Modulator
DAC SECTION
The delta-sigma DAC section of the PCM3000/3001 is based on a 5-level amplitude quantizer and a 3rd-order
noise shaper. This section converts the oversampled input data to a 5-level delta-sigma format. A block diagram
of the 5-level delta-sigma modulator is shown in Figure 32. This 5-level delta-sigma modulator has the advantage
of improved stability and reduced clock-jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modulator and the internal 8× interpolation filter is 64 fS for a
256-fS system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator is
shown in Figure 33.
32
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
+
−
+
−
+
In
+
+
+
−1
−1
−1
Z
8 f
S
Z
Z
18-Bit
+
+
+
5-Level Quantizer
4
3
2
1
0
Out
64 f
S
B0008-02
Figure 32. 5-Level ∆Σ Modulator Block Diagram
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
0
5
10
15
20
25
30
f − Frequency − kHz
G027
Figure 33. Quantization Noise Spectrum
33
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
APPLICATION INFORMATION
APPLICATION AND LAYOUT CONSIDERATIONS
TYPICAL CONNECTION
A typical connection diagram for the PCM3000/3001 is shown in Figure 34.
+5V
Register Control
1
2
3
28
27
26
25
24
23
Reset
Interface
Serial
Control
or
Format
Control
(1)
(2)
(2)
4.7 µF
4.7 µF
+
+
2.2 µF
2.2 µF
+
+
4
5
6
7
8
Line In Left-Channel
Line In Right-Channel
Reference
Analog
Front-End
Analog
Front-End
(1)
22
21
20
19
10 to 33 pF
470 pF
Delta-Sigma
CLK/OSC
Manager
9
470 pF
Decimation
Filter
10
11
12
Digital
+
4.7 µF
Audio
18
17
16
15
Digital
Audio
Data
Interface
Interpolation
Filter
Post
Line Out Right-Channel
Low-Pass
Filter
Delta-Sigma
Bias
13
14
(1)
LPF and
Buffer
LPF and
Buffer
Post
Low-Pass
Filter
Line Out Left-Channel
S0018-01
(1) Bypass capacitor = 0.1 µF and 10 µF.
(2) The input capacitor affects the pole of the HPF. Example: 2.2 µF sets the cutoff frequency to 4.8 Hz, with a 66-ms
time constant.
Figure 34. Typical Connection Diagram for PCM3000/3001
POWER SUPPLY BYPASSING
The digital and analog power-supply lines to the PCM3000/3001 should be bypassed to the corresponding
ground pins with both 0.1-µF ceramic and 10-µF tantalum capacitors as close to the device pins as possible to
maximize the performance of the ADC and DAC. Although the PCM3000/3001 has three power supply lines to
optimize dynamic performance, the use of one common power supply is generally recommended to avoid
unexpected latch-up or pop noise due to power-supply sequencing problems. If separate power supplies are
used, back-to-back diodes between the two power sources near the device are recommended to avoid latch-up
problems.
34
PCM3000
PCM3001
www.ti.com
SBAS055A–OCTOBER 2000–REVISED OCTOBER 2004
APPLICATION INFORMATION (continued)
GROUNDING
In order to optimize dynamic performance of the PCM3000/3001, the analog and digital grounds are not
internally connected. PCM3000/3001 performance is optimized with a single ground plane for all returns. It is
recommended to tie all PCM3000/3001 ground pins to the analog ground plane using low-impedance
connections. The PCM3000/3001 should reside entirely over this plane to avoid coupling high-frequency digital
switching noise into the analog ground plane.
VOLTAGE INPUTS
A tantalum or aluminum electrolytic capacitor, between 2.2 µF and 10 µF, is recommended as an ac-coupling
capacitor at the inputs. Combined with the 15-kΩ characteristic input impedance, a 2.2-µF coupling capacitor
establishes a 4.8-Hz cutoff frequency for blocking dc. The input voltage range can be increased by adding a
series resistor on the analog input line. This series resistor, when combined with the 15-kΩ input impedance,
creates a voltage divider and enables larger input ranges.
VREF INPUTS
A 4.7-µF to 10-µF tantalum capacitor is recommended between VREFL, VREFR, and AGND1 to ensure low source
impedance for the ADC references. These capacitors should be located as close as possible to the reference
pins to reduce dynamic errors on the ADC reference.
CINP AND CINN INPUTS
A 470-pF to 1000-pF film or NPO ceramic capacitor is recommended between CINPL and CINNL, and also
between CINPR and CINNR to create an antialias filter that has a 170-kHz to 80-kHz cutoff frequency. These
capacitors should be located as close as possible to the CINP and CINN pins to avoid introducing undesirable
noise or dynamic errors into the delta-sigma modulator.
VCOM INPUT
A 4.7-µF to 10-µF tantalum capacitor is recommended between VCOM and AGND2 to ensure low source
impedance of the DAC output common. This capacitor should located as close as possible to the VCOM pin to
reduce dynamic errors on the DAC common.
SYSTEM CLOCK
The quality of the system clock can influence the dynamic performance of both the ADC and DAC in the
PCM3000/3001. The duty cycle, jitter, and threshold voltage at the system clock input pin should be carefully
managed. When power is supplied to the part, the system clock, bit clock (BCKIN), and word clock (LCRIN) must
also be supplied simultaneously. Failure to supply the audio clocks results in a power dissipation increase of up
to three times normal dissipation and may degrade long-term reliability if the maximum power dissipation limit is
exceeded.
RSTB CONTROL
If capacitors greater than 4.7 µF are used on VREF and VCOM, an external reset control with delay time
corresponding to the VREF, VCOM response is required.
35
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
PCM3000E
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
28
28
28
28
28
28
28
47 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCM3000E/2K
PCM3000E/2KG4
PCM3000EG4
PCM3001E
SSOP
SSOP
SSOP
SSOP
SSOP
SSOP
DB
DB
DB
DB
DB
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
47 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
47 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCM3001E/2K
PCM3001E/2KG4
PCM3001EG/2K
PCM3001EG4
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Pb-Free
(RoHS)
CU SNBI
Level-1-260C-UNLIM
SSOP
DB
28
47 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jun-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
PCM3000E/2K
PCM3001E/2K
SSOP
SSOP
DB
DB
28
28
2000
2000
330.0
330.0
17.4
17.4
8.5
8.5
10.8
10.8
2.4
2.4
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jun-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
PCM3000E/2K
PCM3001E/2K
SSOP
SSOP
DB
DB
28
28
2000
2000
336.6
336.6
336.6
336.6
28.6
28.6
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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