PCM3002/PCM3003 [ETC]
PCM3002. PCM3003 - 16-/20-Bit Single-Ended Analog Input/Output SoundPlus STEREO AUDIO CODECs ; PCM3002 。 PCM3003 - 16位/ 20位单端模拟输入/输出SoundPlus立体声音频编解码器\n
| 型号： | PCM3002/PCM3003 |
| 厂家： | 
ETC |
| 描述： | PCM3002. PCM3003 - 16-/20-Bit Single-Ended Analog Input/Output SoundPlus STEREO AUDIO CODECs
|
| 文件： | 总23页 (文件大小：341K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
PCM3002
PCM3003
PCM3003
PCM3002
16-/20-Bit Single-Ended Analog Input/Output
TM
STEREO AUDIO CODECs
FEATURES
DESCRIPTION
● MONOLITHIC 20-BIT ∆Σ ADC AND DAC
● 16-/20-BIT INPUT/OUTPUT DATA
● SOFTWARE CONTROL: PCM3002
● HARDWARE CONTROL: PCM3003
The PCM3002 and PCM3003 are low cost single chip
stereo audio CODECs (analog-to-digital and digital-to-
analog converters) with single-ended analog voltage
input and output.
The ADCs and DACs employ delta-sigma modulation
with 64X oversampling. The ADCs include a digital
decimation filter, and the DACs include an 8X
oversampling digital interpolation filter. The DACs
also include digital attenuation, de-emphasis, infinite
zero detection and soft mute to form a complete
subsystem. PCM3002 and PCM3003 operate with
left-justified, right-justified, or I2S data formats.
● STEREO ADC:
Single-Ended Voltage Input
64X Oversampling
High Performance
THD+N: –86dB
SNR: 90dB
Dynamic Range: 90dB
● STEREO DAC:
Single-Ended Voltage Output
Analog Low Pass Filter
8X Oversampling Digital Filter
High Performance
PCM3002 and PCM3003 provide a power-down mode
that operates on the ADCs and DACs independently.
Fabricated on a highly advanced 0.6µs CMOS pro-
cess, PCM3002 and PCM3003 are suitable for a wide
variety of cost-sensitive consumer applications where
good performance is required.
THD+N: –86dB
SNR: 94dB
Dynamic Range: 94dB
PCM3002’s multi-functions are controlled by soft-
ware and the PCM3003’s functions include de-empha-
sis, power down, and audio data format selections,
which are controlled by hardware.
● SPECIAL FEATURES
Digital De-emphasis
Digital Attenuation (256 Steps)
Soft Mute
Digital Loop Back
Power Down: ADC/DAC Independent
● SAMPLING RATE: Up to 48kHz
● SYSTEM CLOCK: 256fS, 384fS, 512fS
● SINGLE +3V POWER SUPPLY
● SMALL PACKAGE: 24-Lead SSOP
Lch In
Digital Out
Digital In
Decimation
Digital Filter
Delta-Sigma
Analog Front-End
Modulator
Rch In
Serial Interface
and
Mode Control
Low Pass Filter
and
Output Buffer
Multi-Level
Delta-Sigma
Modulator
Oversampling
Interpolation
Digital Filter
Lch Out
Rch Out
Serial Mode Control
System Clock
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
FAXLine: (800) 548-6133 (US/Canada Only)
• Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
© 1997 Burr-Brown Corporation
PDS-1414B
Printed in U.S.A. August, 1998
SPECIFICATIONS
All specifications at +25°C, VDD = VCC = 3.0V, fS = 44.1kHz, SYSCLK = 384fS, and 16-bit data, unless otherwise noted.
PCM3002E/3003E
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
DIGITAL INPUT/OUTPUT
Input Logic
(1, 2, 3)
Input Logic Level: VIH
0.7 x VDD
VDC
VDC
µA
(1, 2, 3)
VIL
0.3 x VDD
±1
(2)
Input Logic Current: IIN
(1)
Input Logic Current: IIN
100
µA
Output Logic
(5)
Output Logic Level: VOH
IOUT = –1mA
IOUT = +1mA
IOUT = +1mA
VDD –0.3
VDC
VDC
VDC
(5)
VOL
0.3
0.3
(4)
Output Logic Level: VOL
CLOCK FREQUENCY
Sampling Frequency (fS)
System Clock Frequency
32
44.1
48
kHz
MHz
MHz
MHz
256fS
384fS
512fS
8.1920
12.2880
16.3840
11.2896
16.9344
22.5792
12.2880
18.4320
24.5760
ADC CHARACTERISTICS
RESOLUTION
20
Bits
DC ACCURACY
Gain Mismatch Channel-to-Channel
Gain Error
±1.0
±2.0
±20
±1.7
±20
±3.0
±5.0
% of FSR
% of FSR
Gain Drift
ppm of FSR/°C
% of FSR
Bipolar Zero Error
Bipolar Zero Drift
High-Pass Filter Disabled(6)
High-Pass Filter Disabled(6)
ppm of FSR/°C
DYNAMIC PERFORMANCE(7)
THD+N: VIN = –0.5dB
VIN = –60dB
–86
–28
90
–80
dB
dB
dB
dB
dB
Dynamic Range
A-Weighted
A-Weighted
86
86
84
Signal-to-Noise Ratio
Channel Separation
90
88
DIGITAL FILTER PERFORMANCE
Passband
0.454fS
Hz
Hz
Stopband
0.583fS
–65
Passband Ripple
±0.05
dB
Stopband Attenuation
Delay Time
dB
17.4/fS
0.019fS
sec
mHz
HPF Frequency Response
–3dB
–3dB
ANALOG INPUT
Voltage Range
0.60 VCC
0.50 VCC
30
Vp-p
V
Center Voltage
Input Impedance
kΩ
Anti-Aliasing Filter Frequency Response
150
kHz
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no
responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN
product for use in life support devices and/or systems.
®
PCM3002/3003
2
SPECIFICATIONS
All specifications at +25°C, VDD = VCC = 3.0V, fS = 44.1kHz, SYSCLK = 384fS, CLKIO Input, 18-bit data, unless otherwise noted.
PCM3002E/3003E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DAC CHARACTERISTICS
RESOLUTION
20
Bits
DC ACCURACY
Gain Mismatch Channel-to-Channel
Gain Error
Gain Drift
Bipolar Zero Error
Bipolar Zero Drift
±1.0
±1.0
±20
±1.0
±20
±3
±5
% of FSR
% of FSR
ppm of FSR/°C
% of FSR
ppm of FSR/°C
DYNAMIC PERFORMANCE(8)
THD+N: VOUT = 0dB (Full Scale)
VOUT = –60dB
Dynamic Range
Signal-to-Noise Ratio
Channel Separation
–86
–28
94
94
91
–80
dB
dB
dB
dB
dB
EIAJ, A-Weighted
EIAJ, A-Weighted
88
88
86
DIGITAL FILTER PERFORMANCE
Passband
Stopband
Passband Ripple
Stopband Attenuation
Delay Time
0.445fS
Hz
Hz
dB
dB
sec
0.555fS
–35
±0.17
11.1/fS
ANALOG OUTPUT
Voltage Range
Center Voltage
0.60 x VCC
0.5 x VCC
Vp-p
VDC
kΩ
Load Impedance
AC-Coupling
f = 20kHz
10
LPF Frequency Response
–0.16
dB
POWER SUPPLY REQUIREMENTS
Voltage Range: VCC, VDD
–25°C to +85°C
0° C to +70°C(9)
VCC = VDD = 3.0V
VCC = VDD = 3.0V
VCC = VDD = 3.0V
VCC = VDD = 3.0V
2.7
2.4
3.0
3.0
18
50
54
3.6
3.6
24
VDC
VDC
mA
µA
mW
µW
Supply Current: Operation
Power-Down
Power Dissipation: Operation
Power-Down(10)
72
150
TEMPERATURE RANGE
Operation
Storage
–25
–55
+85
+125
°C
°C
Thermal Resistance, ΘJA
100
°C/W
NOTES: (1) Pins 7, 8, 17 and 18: RST, ML, MD, MC for the PCM3002; PDAD, PDDA, DEM1, DEM0 for PCM3003 (Schmitt-Trigger input with 100kΩ typical internal
pull-down resistor). (2) Pins 9, 10, 11, 15: SYSCLK, LRCIN, BCKIN, DIN (Schmitt Trigger input). (3) Pin16: 20BIT for PCM3003 (Schmitt-Trigger input, 100kΩ
typical internal pull-down resistor). (4) Pin 12: DOUT. (5) Pin 16: ZFLG (open drain output). (6) High Pass Filter for Offset Cancel. (7) fIN = 1kHz, using Audio
Precision System II, rms mode with 20kHz LPF, 400Hz HPF used for performance calculation. (8) fOUT = 1kHz, using Audio Precision System II, rms mode with
20kHz LPF, 400Hz HPF used for performance calculation. (9) Applies for voltages between 2.4V to 2.7V for 0°C to +70°C and 256fS/512fS operation (384fS not
available). (10) SYSCLK, BCKIN, and LRCIN are stopped.
PACKAGE INFORMATION
ELECTROSTATIC
DISCHARGE SENSITIVITY
PACKAGE DRAWING
PRODUCT
PACKAGE
NUMBER(1)
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
PCM3002E/3003E
24-Lead SSOP
338
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
+VDD, +VCC1, +VCC2 ...................................................................... +6.5V
Supply Voltage Differences............................................................... ±0.1V
GND Voltage Differences.................................................................. ±0.1V
Digital Input Voltage ...................................................... –0.3 to VDD + 0.3V
Analog Input Voltage......................................... –0.3 to VCC1, VCC2 + 0.3V
Power Dissipation .......................................................................... 300mW
Input Current ................................................................................... ±10mA
Operating Temperature Range ......................................... –25°C to +85°C
Storage Temperature ...................................................... –55°C to +125°C
Lead Temperature (soldering, 5s).................................................. +260°C
(reflow, 10s) ..................................................... +235°C
®
3
PCM3002/3003
PIN CONFIGURATION—PCM3002
PIN CONFIGURATION—PCM3003
Top View
SSOP
Top View
SSOP
PCM3002
PCM3003
1
2
3
4
5
6
7
8
9
VCC
1
VCC
2
24
1
2
3
4
5
6
7
8
9
VCC
1
VCC2
24
V
V
V
V
V
CC1
AGND1 23
AGND2 22
VCOM 21
V
V
V
V
V
CC1
AGND1 23
AGND2 22
VCOM 21
INR
INR
REFL
REFR
INL
REFL
REFR
INL
VOUT
R
20
VOUT
R
20
V
OUTL 19
MC 18
MD 17
VOUTL 19
RST
PDAD
DEM0 18
DEM1 17
20BIT 16
DIN 15
ML
PDDA
SYSCLK
ZFLG 16
DIN 15
SYSCLK
10 LRCIN
11 BCKIN
12 DOUT
10 LRCIN
11 BCKIN
12 DOUT
VDD 14
VDD 14
DGND 13
DGND 13
PIN ASSIGNMENTS—PCM3002
PIN ASSIGNMENTS—PCM3003
PIN
NAME
I/O
DESCRIPTION
PIN
NAME
VCC
CC1
INR
VREF
REFR
VIN
I/O
DESCRIPTION
1
V
V
CC1
CC1
—
—
ADC Analog Power Supply
ADC Analog Power Supply
ADC Analog Input, Rch
ADC Reference, Lch
1
1
—
—
ADC Analog Power Supply
ADC Analog Power Supply
ADC Analog Input, Rch
ADC Reference, Lch
2
2
V
3
V
INR
VREF
REFR
VIN
IN
3
V
IN
4
L
—
4
L
—
5
V
—
ADC Reference, Rch
5
V
—
ADC Reference, Rch
ADC Analog Input, Lch
ADC Power Down, Active LOW(1, 2)
DAC Power Down, Active LOW(1, 2)
System Clock Input(2)
Sample Rate Clock Input (fS)(2)
Bit Clock Input(2)
6
L
IN
ADC Analog Input, Lch
Reset, Active LOW(1, 2)
Strobe Pulse for Mode Control(1, 2)
System Clock Input(2)
Sample Rate Clock Input (fS)(2)
Bit Clock Input(2)
6
L
IN
7
RST
ML
IN
7
PDAD
PDDA
SYSCLK
LRCIN
BCKIN
DOUT
DGND
VDD
IN
8
IN
8
IN
9
SYSCLK
LRCIN
BCKIN
DOUT
DGND
VDD
IN
9
IN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
IN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
IN
IN
IN
OUT
—
Data Output
OUT
—
Data Output
Digital Ground
Digital Ground
—
Digital Power Supply
Data Input(2)
—
Digital Power Supply
DIN
IN
DIN
IN
Data Input
ZFLG
MD
OUT
IN
Zero Flag Output, Active LOW(3)
Serial Data for Mode Control(1, 2)
Bit Clock for Mode Control(1, 2)
DAC Analog Output, Lch
DAC Analog Output, Rch
ADC/DAC Common
20BIT
DEM1
DEM0
IN
20-Bit Format Select(1, 2)
De-emphasis Control(1, 2)
De-emphasis Control 0(1, 2)
DAC Analog Output, Lch
DAC Analog Output, Rch
ADC/DAC Common
IN
MC
IN
IN
VOUT
L
OUT
OUT
—
VOUT
L
OUT
OUT
—
VOUTR
VOUTR
VCOM
VCOM
AGND2
AGND1
—
DAC Analog Ground
AGND2
AGND1
—
DAC Analog Ground
—
ADC Analog Ground
—
ADC Analog Ground
V
CC2
—
DAC Analog Power Supply
V
CC2
—
DAC Analog Power Supply
NOTES: (1) With 100kΩ typical internal pull-down resistor. (2) Schmitt-Trigger
NOTE: (1) With 100kΩ typical internal pull-down resistor. (2) Schmitt-Trigger
input. (3) Open drain output.
input.
®
PCM3002/3003
4
TYPICAL PERFORMANCE CURVES
ADC SECTION
At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, fSYSCLK = 384fS, and FSIGNAL = 1kHz, unless otherwise noted.
THD+N vs TEMPERATURE
DYNAMIC RANGE and SNR vs TEMPERATURE
0.010
0.008
0.006
0.004
0.002
5.0
4.0
2.0
3.0
1.0
94
92
90
88
86
5.0
4.0
2.0
3.0
1.0
–60dB
Dynamic Range
SNR
0.5dB
–25
0
25
50
75 85
100
–25
0
25
50
75 85
100
Temperature (°C)
Temperature (°C)
DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE
Dynamic Range
THD+N vs SUPPLY VOLTAGE
–60dB
94
92
90
88
86
94
92
90
88
86
0.010
0.008
0.006
0.004
0.002
5.0
4.0
3.0
2.0
1.0
SNR
–0.5dB
2.4
2.7
3.0
3.3
3.6
2.4
2.7
3.0
3.3
3.6
Supply Voltage (V)
Supply Voltage (V)
THD+N vs SAMPLING FREQUENCY
DYNAMIC RANGE and SNR vs SAMPLING FREQUENCY
0.010
0.008
0.006
0.004
0.002
5.0
4.0
3.0
2.0
1.0
94
92
90
88
86
94
92
90
88
86
–60dB
–0.5dB
32
44.1
48
32
44.1
48
f
S (kHz)
fS (kHz)
®
5
PCM3002/3003
TYPICAL PERFORMANCE CURVES
DAC SECTION
At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, fSYSCLK = 384fS, and FSIGNAL = 1kHz, unless otherwise noted.
THD+N vs TEMPERATURE
DYNAMIC RANGE and SNR vs TEMPERATURE
0.010
0.008
0.006
0.004
0.002
4.0
3.0
2.0
1.0
0
98
96
94
92
90
98
96
94
92
90
–60dB
Dynamic Range
SNR
FS
–25
0
25
50
75 85
100
–25
0
25
50
75 85
100
Temperature (°C)
Temperature (°C)
THD+N vs SUPPLY VOLTAGE
–60dB
DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE
0.010
0.008
0.006
0.004
0.002
4.0
3.0
2.0
1.0
0
98
96
94
92
90
98
96
94
92
90
Dynamic Range
SNR
FS
2.4
2.7
3.0
3.3
3.6
2.4
2.7
3.0
3.3
3.6
Supply Voltage (V)
Supply Voltage (V)
DYNAMIC RANGE and SNR
vs SAMPLING FREQUENCY and SYSTEM CLOCK
THD+N vs SAMPLING FREQUENCY
and SYSTEM CLOCK
0.010
0.008
0.006
0.004
0.002
4.0
3.0
2.0
1.0
0
98
96
94
92
90
98
96
94
92
90
256fS, 512fS
–60dB
FS
384fS
SNR
256fS, 512fS
384fS
256fS, 512fS
Dynamic
Range
384fS
32
44.1
48
32
44.1
48
fS (kHz)
fS (kHz)
®
PCM3002/3003
6
TYPICAL PERFORMANCE CURVES
Output Spectrum
At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, fSYSCLK = 384fS, and FSIGNAL = 1kHz, unless otherwise noted.
DACs
ADCs
OUTPUT SPECTRUM (FS, N = 8192)
OUTPUT SPECTRUM (FS, N = 8192)
0
0
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–100
–120
–140
0
5
10
15
20 22
25
0
5
10
15
20 22
25
Frequency (kHz)
Frequency (kHz)
OUTPUT SPECTRUM (FS, N = 8192)
OUTPUT SPECTRUM (–60dB, N = 8192)
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–100
–120
–140
0
5
10
15
20 22
25
0
5
10
15
20 22
25
Frequency (kHz)
Frequency (kHz)
THD+N vs SIGNAL LEVEL
THD+N vs SIGNAL LEVEL
100
10
100
10
1
1
0.1
0.1
0.001
0.001
0.001
0.001
–96
–84
–72
–60
–48
–36
–24
–12
0
–96
–84
–72
–60
–48
–36
–24
–12
0
Signal Level (dB)
Signal Level (dB)
®
7
PCM3002/3003
TYPICAL PERFORMANCE CURVES
Supply Current
At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, fSYSCLK = 384fS, DIN = BPZ, and VIN = BPZ, unless otherwise noted.
ICC + IDD vs TEMPERATURE
ICC + IDD vs SUPPLY VOLTAGE
25
20
15
10
5
2.5
2.0
1.5
1.0
0.5
0
25
20
15
10
5
2.5
2.0
1.5
1.0
0.5
0
ADC & DAC
ADC & DAC
ADC
ADC
DAC
DAC
Power Down & OFF
Power Down & OFF
0
0
–50
–25
–0
25
50
75
100
2.4
2.7
3.0
3.3
3.6
Temperature (°C)
Supply Voltage (V)
ICC + IDD vs SAMPLING FREQUENCY
20
ADC & DAC
512fS
19
18
17
16
15
256fS
32
44.1
fS (kHz)
48
®
PCM3002/3003
8
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, and fSYSCLK = 384fS, unless otherwise noted.
ADC DIGITAL FILTER
OVERALL CHARACTERISTICS
STOPBAND ATTENUATION CHARACTERISTICS
0
–50
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–100
–150
–200
0
0
0
8
16
24
32
0.5
0.5
0
0.2
0.4
0.6
0.8
1.0
Normalized Frequency (x fS Hz)
Normalized Frequency (x fS Hz)
TRANSIENT BAND CHARACTERISTICS
PASSBAND RIPPLE CHARACTERISTICS
0.2
0.0
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–4.13dB at 0.5 x fS
–0.2
–0.4
–0.6
–0.8
–1.0
0.1
0.2
0.3
0.4
0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55
Normalized Frequency (x fS Hz)
Normalized Frequency (x fS Hz)
HIGH PASS FILTER RESPONSE
HIGH PASS FILTER RESPONSE
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
0.1
0.2
0.3
0.4
0
1
2
3
4
Normalized Frequency (x fS/1000 Hz)
Normalized Frequency (x fS/1000 Hz)
®
9
PCM3002/3003
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, and fSYSCLK = 384fS, unless otherwise noted.
ANTI-ALIASING FILTER
ANTI-ALIASING FILTER OVERALL
FREQUENCY RESPONSE
ANTI-ALIASING FILTER PASSBAND
FREQUENCY RESPONSE
0
–10
–20
–30
–40
–50
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
10
100
1k
10k
100k
1M
10M
0
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
®
PCM3002/3003
10
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, and fSYSCLK = 384fS, unless otherwise noted.
DAC DIGITAL FILTER
OVERALL FREQUENCY CHARACTERISTICS
(fS = 44.1kHz)
PASSBAND RIPPLE CHARACTERISTICS (fS = 44.1kHz)
0
–20
0
–0.2
–0.4
–0.6
–0.8
–1.0
–40
–60
–80
–100
0
50k
100k
150k
0
5k
10k
15k
20k
Frequency (Hz)
Frequency (Hz)
DE-EMPHASIS FREQUENCY RESPONSE (32kHz)
DE-EMPHASIS ERROR (32kHz)
0
–2
0.6
0.4
–4
0.2
–6
0
–8
–10
–12
–0.2
–0.4
–0.6
0
0
0
5k
10k
15k
20k
25k
25k
25k
0
0
0
3628
7256
10884
14512
19999.35
21768
Frequency (Hz)
Frequency (Hz)
DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)
DE-EMPHASIS ERROR (44.1kHz)
0.6
0.4
0.2
0
–2
–4
–6
–8
0
–0.2
–0.4
–0.6
–10
–12
5k
10k
15k
20k
4999.8375
9999.675
14999.5125
Frequency (Hz)
Frequency (Hz)
DE-EMPHASIS FREQUENCY RESPONSE (48kHz)
DE-EMPHASIS ERROR (48kHz)
0
–2
–4
–6
–8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–10
–12
5k
10k
15k
20k
5442
10884
16326
Frequency (Hz)
Frequency (Hz)
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(1Hz~20kHz)
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(10Hz~10MHz)
20
0
0.15
0.10
0.05
0
–20
–40
–60
–80
–100
–0.05
–0.10
–0.15
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
®
11
PCM3002/3003
BLOCK DIAGRAM
(+)
(–)
Analog
Front-End
Circuit
Decimation
and
High Pass Filter
Delta-Sigma
Modulator
LRCIN
BCKIN
DIN
V
INL
VREF
L
Serial Data
Interface
ADC
Reference
VCOM
VREF
R
R
(–)
(+)
Analog
Front-End
Circuit
Decimation
and
High Pass Filter
Delta-Sigma
Modulator
VIN
DOUT
MC(1 )/DEM0(2)
MD(1 )/DEM1(2)
Analog
Low-Pass
Filter
Multi-Level
Delta-Sigma
Modulator
Interpolation
Filter
8X Oversampling
VOUT
L
Mode
Control
Interface
VCOM
DAC
ML(1 )
20BIT(2 )
Analog
Low-Pass
Filter
Multi-Level
Delta-Sigma
Modulator
Interpolation
Filter
8X Oversampling
VOUT
R
PDDA(1)
Reset and
RST(1)/PDAD(2)
Power Down
Zero Detect(1)
Power Supply
Clock
AGND2 VCC
2
AGND1 VCC
1
DGND
VDD
SYSCLK
ZFLG(1)
NOTES: (1) MC, MD, ML, RST, and ZFLG are for PCM3002 only. (2) DEM0, DEM1, 20BIT, PDAD, and PDDA are for PCM3003 only.
1.0µF
+
30kΩ
VIN
R
1
(+)
(–)
Delta-Sigma
Modulator
VCOM
21
4
VREF
L
+
4.7µF
V
REFR
+
5
4.7µF
VREF
+
4.7µF
FIGURE 1. Analog Front-End (Single-Channel).
®
PCM3002/3003
12
PCM AUDIO INTERFACE
are selected through PROGRAM REGISTER 3 in the soft-
ware mode. For the PCM3003, data formats are selected by
20BIT (pin 16). Figures 2, 3 and 4 illustrate audio data
input/output format and timing.
The four-wire digital audio interface for PCM3002/3003 is
comprised of: LRCIN (pin 10), BCKIN (pin 11), DIN (pin
15), and DOUT (pin 12). PCM3002/3003 can operate with
four different data formats. The PCM3002 may be used with
any of the four input/output data formats (Formats 0 - 3),
while the PCM3003 may only be used with selected input/
output formats (Formats 0 - 1). For PCM3002, these formats
PCM3002/3003 can accept 32-, 48-, or 64-bit clocks (BCKIN)
in one clock of LRCIN. Only 16-bit data formats can be
selected when 32-bit clocks/LRCIN are applied.
FORMAT 0: PCM3002/3003
DAC: 16-Bit, MSB-First, Right-Justified
L–ch
3
R–ch
LRCIN
BCKIN
DIN
16
1
2
14 15 16
LSB
1
2
3
14 15 16
LSB
MSB
MSB
ADC: 16-Bit, MSB-First, Left-Justified
LRCIN
BCKIN
L–ch
R–ch
1
2
3
14 15 16
1
2
3
14 15 16
1
DOUT
MSB
LSB
MSB
LSB
FORMAT 1: PCM3002/3003
DAC: 20-Bit, MSB-First, Right-Justified
L–ch
R–ch
LRCIN
BCKIN
20
1
2
3
18 19 20
LSB
1
2
3
18 19 20
LSB
DIN
MSB
MSB
ADC: 20-Bit, MSB-First, Left-Justified
LRCIN
BCKIN
L–ch
R–ch
DOUT
1
2
3
18 19 20
1
2
3
18 19 20
LSB
1
MSB
LSB
MSB
FORMAT 2: PCM3002 Only
DAC: 20-Bit, MSB-First, Left-Justified
L–ch
R–ch
LRCIN
BCIN
1
1
2
3
18 19 20
LSB
1
2
3
18 19 20
LSB
DIN
MSB
MSB
ADC: 20-Bit, MSB-First, Left-Justified
LRCIN
BCIN
L–ch
R–ch
1
2
3
18 19 20
LSB
1
2
3
18 19 20
LSB
DOUT
1
MSB
MSB
FIGURE 2. Audio Data Input/Output Format.
®
13
PCM3002/3003
FORMAT 3: PCM3002 Only
DAC: 20-Bit, MSB-First, I2S
L-ch
LRCIN
BCKIN
R-ch
1
2
3
18 19 20
LSB
1
2
3
18 19 20
LSB
DIN
MSB
MSB
ADC: 18-Bit, MSB-First, I2S
L-ch
LRCIN
BCKIN
R-ch
1
2
3
18 19 20
LSB
1
2
3
18 19 20
LSB
DOUT
MSB
MSB
FIGURE 3. Audio Data Input/Output Format.
tLRP
LRCIN
0.5VDD
tLB
tBL
tBCH
tBCL
0.5VDD
0.5VDD
0.5VDD
BCKIN
tBCY
tDIS
tDIH
DIN
tBDO
tLDO
DOUT
BCKIN Pulse Cycle Time
BCKIN Pulse Width High
BCKIN Pulse Width Low
tBCY
300ns (min)
120ns (min)
120ns (min)
40ns (min)
40ns (min)
tBCY (min)
tBCH
tBCL
tBL
BCKIN Rising Edge to LRCIN Edge
LRCIN Edge to BCKIN Rising Edge
LRCIN Pulse Width
tLB
tLRP
tDIS
tDIH
tBDO
tLDO
DIN Set-up Time
40ns (min)
40ns (min)
40ns (max)
40ns (max)
20ns (max)
20ns (max)
DIN Hold Time
DOUT Delay Time to BCKIN Falling Edge
DOUT Delay Time to LRCIN Edge
Rising Time of All Signals
tRISE
tFALL
Falling Time of All Signals
FIGURE 4. Audio Data Input/Output Timing.
®
PCM3002/3003
14
RESET
SYSTEM CLOCK
PCM3002/3003 has an internal Power-On Reset circuit, as
well as an external forced reset. The internal Power-On Reset
initializes (resets) when the supply voltage VDD >2.0V (typ).
External forced reset occurs when RST = LOW for PCM3002,
or both, PDAD = LOW and PDDA = LOW for PCM3003.
During VCC < 2.2V and/or internal initialize state (1024
system clocks count after VCC >2.2V) for Power-On Reset or
during reset signal is forced to device or internal initialize
state (1024 system clocks count after PDAD = HIGH or
PDDA = HIGH) for external reset, the outputs of the DAC
are invalid and forced to GND. The analog outputs are then
forced to 0.5VCC during tDACDLY1 (16384/fS) after reset
removal. The outputs of ADC are also invalid, the digital
outputs are forced to all zero during tADCDLY1 (18432/fS)
after reset removal. Figures 6 and 7 illustrate the Power-On
reset timing, external reset timing and ADC, DAC output
response for Reset and Power-Down ON/OFF.
The system clock for PCM3002/3003 must be either 256fS,
384fS or 512fS, where fS is the audio sampling frequency.
The system clock should be provided to SYSCLK (pin 9).
PCM3002/3003 also has a system clock detection circuit
which automatically senses if the system clock is operating at
256fS, 384fS, or 512fS. When 384fS or 512fS system clock is
used, the clock is divded into 256fS automatically. The 256fS
clock is used to operate the digital filter and the delta-sigma
modulator.
Table I lists the relationship of typical sampling frequencies
and system clock frequencies and Figure 5 illustrates the
system clock timing.
SAMPLING RATE FREQUENCY
(kHz)
SYSTEM CLOCK FREQUENCY
(MHz)
256fS
384fS
512fS
32
44.1
48
8.1920
11.2896
12.2880
12.2880
16.9340
18.4320
16.3840
22.5792
24.5760
TABLE I. System Clock Frequencies.
tSCKH
"H"
"L"
0.7V
SYSCLK
0.3VDD
tSCKL
1/256fS,1/384fS,or 1/512fS
System Clock Pulse Width High tSCKH
System Clock Pulse Width Low tSCKL
12ns
12ns
(min)
(min)
FIGURE 5. System Clock Timing.
4.4V
4.0V
3.6V
VDD
Reset
Reset Removal
Internal Reset
System Clock
1024 System Clock Periods
FIGURE 6. Internal Power-On Reset Timing.
tRST = 40ns minimum
RSTB-pin
tRST
Reset
Reset Removal
Internal Reset
1024 System Clock Periods
System Clock
FIGURE 7. External Forced Reset Timing.
®
15
PCM3002/3003
SYNCHRONIZATION WITH THE DIGITAL AUDIO
SYSTEM
synchronization occurs followed by tADCDLY2 delay time. If
LRCIN is synchronized with 5 or less bit clocks to the system
clock, operation will be normal. Figures 8 and 9 illustrate the
effects on the output when synchronization is lost. Before the
outputs are forced to bipolar zero (<1/fS seconds), the outputs
are not defined and some noise may occur. During the
transitions between normal data and undefined states, the
output has discontinuities, which will cause output noise.
PCM3002/3003 operates with LRCIN synchronized to the
system clock. PCM3002/3003 does not require any specific
phase relationship between LRCIN and the system clock, but
there must be synchronization. If the synchronization be-
tween the system clock and LRCIN changes more than 6 bit
clocks (BCKIN) during one sample (LRCIN) period because
of phase jitter on LRCIN, internal operation of the DAC will
stop within 1/fS, and the analog output will be forced to
bipolar zero (0.5VCC) until the system clock is re-synchro-
nized to LRCIN followed by tDACDLY2 delay time. Internal
operation of the ADC will also stop within 1/fS, and the
digital output codes will be set to bipolar zero until re-
ZERO FLAG OUTPUT: PCM3002 ONLY
Pin 16 is an open-drain output for infinite zero detection flag
on the PCM3002 only. When input data is continuously zero
for 65,536 BCKIN cycles, ZFLG is LOW, otherwise, ZFLG
is in a high-impedance state.
Reset Removal or Power Down OFF
Internal Reset
or Power Down
Ready/Operation
Reset
Power Down
tDACDLY1 (16384/fS)
VCOM
GND
Zero
DAC VOUT
(0.5VCC
)
tADCDLY1 (18436/fS)
Zero
Normal Data(1)
ADC DOUT
NOTE: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR
with 200ms time constant) appears initially.
FIGURE 8. DAC Output and ADC Output for Reset and Power Down.
Synchronization
Lost
Resynchronization
State of
Synchronization
Synchronous
Asynchronous
Synchronous
within
1/fS
tDACDLY2 (32/fS)
Undefined Data
Undefined Data
VCOM
(= 1/2 x VCC
Normal
Normal
DAC VOUT
Normal
)
tADCDLY2 (32/fS)
ADC DOUT
Normal(1 )
Zero
NOTES: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR
with 200ms time constant) appears initially.
FIGURE 9. DAC Output and ADC Output for Loss of Synchronization.
®
PCM3002/3003
16
ML
MC
MD
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
FIGURE 10. Control Data Input Format.
tMLH
tMLH
tMLS
ML
MC
MD
tMCH
tMCL
tMLL
tMCY
LSB
tMDS
tMDH
MC Pulse Cycle Time
MC Pulse Width LOW
MC Pulse Width HIGH
MD Setup Time
tMCY
tMCL
tMCH
tMDS
tMDH
tMLL
tMLH
tMLS
tMLH
100ns (min)
40ns (min)
40ns (min)
40ns (min)
40ns (min)
40ns + 1SYSCLK (min)
40ns + 1SYSCLK (min)
40ns (min)
MD Hold Time
ML Low Level Time
ML High Level Time
ML Setup Time
ML Hold Time
40ns (min)
SYSCLK: 1/256fS or 1/384fS
FIGURE 11. Control Data Input Timing.
FUNCTION
ADC/DAC
PCM3002
PCM3002
Audio Data Format
LRCIN Polarity
ADC/DAC
ADC/DAC
4 Selectable Formats
O
2 Selectable Formats
X
Loop-Back Control
ADC/DAC
DAC
O
O
O
O
O
O
X
X
X
X
X
X
Left Channel Attenuation
Right Channel Attenuation
Attenuation Control
DAC
DAC
Infinite Zero Detection
DAC Output Control
DAC
DAC
Soft Mute Control
De-Emphasis (OFF, 32kHz, 44.1kHz, 48kHz)
DAC
DAC
O
O
X
O
ADC Power-Down Control
DAC Power-Down Control
High Pass Filter Operation
ADC
DAC
ADC
O
O
O
O
O
X
TABLE II. Selectable Functions.
OPERATIONAL CONTROL
PCM3002 can be controlled in a software mode with a
three-wire serial interface on MC (pin 18), MD (pin 19), and
ML (pin 8). Table II indicates selectable functions, and
Figure 10 illustrates control data input format and timing.
PCM3003 only allows for control of 16-/20-bit data format,
digital de-emphasis, and Power-Down Control by hardware
pins.
®
17
PCM3002/3003
MAPPING OF PROGRAM REGISTERS
B15
res
B14
res
B13
res
B12
res
B11
res
B10
A1
B9
A0
B8
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER 0
REGISTER 1
LDL
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
res
res
res
res
res
res
res
res
res
res
res
res
res
res
res
A1
A1
A1
A0
A0
A0
LDR
AR7
AR6
AR5
ATC
LOP
AR4
IZD
res
AR3
OUT
AR2
AR1
AR0
REGISTER 2
REGISTER 3
PDAD BYPS PDDA
res res res
DEM1 DEM0 MUT
LRP res
FMT1 FMT0
SOFTWARE CONTROL (PCM3002)
new attenuation data will be ignored, and the
output level will remain at the previous attenua-
tion level. The LDR bit in REGISTER 1 has the
equivalent function as LDL. When either LDL or
LDR is set to “1”, the output level of the left and
right channels are simultaneously controlled.
PCM3002’s special functions are controlled using four pro-
gram registers which are 16 bits long. There are four distinct
registers, with bits 9 and 10 determining which register is in
use. Table III describes the functions of the four registers.
REGISTER
NAME
BIT
NAME
AL (7:0): Bit 7:0 DAC Attenuation Data for Left Channel
DESCRIPTION
AL7 and AL0 are MSB and LSB, respectively.
The attenuation level (ATT) is given by:
Register 0
Register 1
Register 2
A (1:0)
res
LDL
Register Address “00”
Reserved, should be set to “0”
DAC Attenuation Data Load Control for Lch
Attenuation Data for Lch
ATT = 20 x log10 (ATT data/255) (dB)
AL (7:0)
A (1:0)
res
LDR
Register Address “01”
AL (7:0)
ATTENUATION LEVEL
Reserved, should be set to “0”
DAC Attenuation Data Load Control for Rch
DAC Attenuation for Rch
00h
01h
:
–∞dB (Mute)
–48.16dB
:
AR (7:0)
A (1:0)
res
PDAD
PDDA
BYPS
ATC
Register Address “10”
Reserved, should be set to “0”
ADC Power-Down Control
FEh
FFh
–0.07dB
0dB
DAC Power-Down Control
ADC High-Pass Filter Operation Control
DAC Attenuation Data Mode Control
DAC Infinite Zero Detection Circuit Control
DAC Output Enable Control
PROGRAM REGISTER 1
IZD
OUT
A (1:0): Register Address
DEM (1:0)
MUT
DAC De-emphasis Control
Lch and Rch Soft Mute Control
These bits define the address for REGISTER 1:
A1
A0
Register 3
A (1:0)
res
LOP
FMT (1:0)
LRP
Register Address “11”
Reserved, should be set to “0”
ADC/DAC Analog Loop-Back Control
ADC/DAC Audio Data Format Selection
ADC/DAC Polarity of LR-clock Selection
0
1
Register 1
res:
Bit 15:11
Reserved
These bits are reserved and should be set to “0”
TABLE III. Functions of the Registers.
LDR:
Bit 8 DAC Attenuation Data Load Control for
Right Channel
PROGRAM REGISTER 0
This bit is used to simultaneously set analog
outputs of the left and right channels. The output
level is controlled by AL (7:0) attenuation data
when this bit is set to “1”. When set to “0”, the
new attenuation data will be ignored, and the
output level will remain at the previous attenua-
tion level. The LDL bit in REGISTER 0 has the
equivalent function as LDR. When either LDL or
LDR is set to “1”, the output level of the left and
right channels are simultaneously controlled.
A (1:0): Bit 10, 9
Register Address
These bits define the address for REGISTER 0:
A1
A0
0
0
Register 0
res:
Bit 11 : 15 Reserved
These bits are reserved and should be set to “0”.
LDL:
Bit 8 DAC Attenuation Data Load Control for
Left Channel
AR (7:0): Bit 7:0
DAC Attenuation Data for Left
Channel
This bit is used to simultaneously set analog
outputs of the left and right channels. The output
level is controlled by AL (7:0) attenuation data
when this bit is set to “1”. When set to “0”, the
AR7 and AR0 are MSB and LSB respectively.
See REGISTER 0 for the attenuation formula.
®
PCM3002/3003
18
PROGRAM REGISTER 2
A (1:0): Bit 10, 9 Register Address
These bits define the address for REGISTER 2:
IZD:
Bit 4
DAC Infinite Zero Detection Circuit
Control
This bit enables the Infinite Zero Detection Circuit
in PCM3002. When enabled, this circuit will dis-
connect the analog output amplifier from the delta-
sigma DAC when the input is continuously zero for
65,536 consecutive cycles of BCKIN.
A1
A0
1
0
Register 2
res:
Bit 15:11, 6 Reserved
These bits are reserved and should be set to “0”.
PDAD: Bit 8 ADC Power-Down Control
IZD
0
1
Infinite Zero Detection Disabled
Infinite Zero Detection Enabled
This bit places the ADC section in the lowest
power consumption mode. The ADC operation is
stopped by cutting the supply current to the ADC
section, and DOUT is fixed to zero during ADC
Power-down mode enable. Figure 8 illustrates the
ADC DOUT response for ADC power-down ON/
OFF. This does not affect the DAC operation.
OUT:
Bit 3
DAC Output Enable Control
When set to “1”, the outputs are forced to VCC/2
(bipolar zero). In this case, all registers in
PCM3002 hold the present data. Therefore, when
set to “0”, the outputs return to the previous
programmed state.
OUT
PDAD
DAC POWER-DOWN
0
1
Power Down Mode Disabled
Power Down Mode Enabled
0
1
DAC Outputs Enabled (normal operation)
DAC Outputs Disabled (forced to BPZ)
BYPS: Bit 7
ADC High-Pass Filter Bypass Control
DEM (1:0):Bit 2,1
DAC De-emphasis Control
These bits select the de-emphasis mode as shown
below:
This bit determines enables or disables the high-
pass filter for the ADC.
DEM1
DEM0
BYPS
0
0
1
0
1
0
De-emphasis 44.1kHz ON
De-emphasis OFF
De-emphasis 48kHz ON
0
1
High-Pass Filter Enabled
High-Pass Filter Disabled (bypassed)
1
1
De-emphasis 32kHz ON
PDDA: Bit 6
DAC Power-Down Control
This bit places the DAC section in the lowest power
consumption mode. The DAC operation is stopped
by cutting the supply current to the DAC section
and VOUT is fixed to GND during DAC Power-
Down Mode enable. Figure 8 illustrates the DAC
VOUT response for DAC Power-Down ON/OFF.
This does not affect the ADC operation.
MUT:
Bit 0
DAC Soft Mute Control
When set to “1”, both left and right-channel DAC
outputs are muted at the same time. This muting
is done by attenuating the data in the digital filter,
so there is no audible click noise when soft mute
is turned on.
MUT
PDDA
0
1
Mute Disable
Mute Enable
0
1
Power-Down Mode Disabled
Power-Down Mode Enabled
ATC:
Bit 5
DAC Attenuation Channel Control
PROGRAM REGISTER 3
A (1:0): Bit 10:9 Register Address
These bits define the address for REGISTER 3:
When set to “1”, the REGISTER 0 attenuation
data can be used for both DAC channels. In this
case, the REGISTER 1 attenuation data is ig-
nored.
A1
A0
1
1
Register 3
ATC
0
1
Individual Channel Attenuation Data Control
Common Channel Attenuation Data Control
res:
Bit 15:11, 8:6, 4:0
Reserved
These bits are reserved, and should be set to “0”.
®
19
PCM3002/3003
LOP:
Bit 5
ADC to DAC Loop-Back Control
LRP:
Bit 1
ADC and DAC Polarity of LR-clock
Selection. Applies only to Formats
0 through 2.
When this bit is set to “1”, the ADC’s audio data
is sent directly to the DAC. The data format will
default to I2S. In Format 3 (I2S Frame), Loop-
back is not supported.
LRP
0
1
Left-channel is “H”, Right-channel is “L”.
Left-channel is “L”, Right-channel is “H”.
LOP
0
1
Loop-back Disable
Loop-back Enable
FMT (1,0) Bit 3:2
Audio Data Format Select
These bits determine the input and output audio
data formats.
FMT1 FMT0
DAC
ADC
Data Format
Data Format
NAME
0
0
1
1
0
1
0
1
16-bit, MSB-first,
Right-justified
16-bit, MSB-first,
Left-justified
Format 0
20-bit, MSB-first,
Right-justified
20-bit, MSB-first,
Left-justified
Format 1
Format 2
Format 3
20-bit, MSB-first,
Left-justified
20-bit, MSB-first,
Left-justified
20-bit, MSB-first,
I2S
20-bit, MSB-first,
I2S
+3V Analog VCC
PCM3002/3003
0.1µF
0.1µF and 10µF(1)
and 10µF(1)
+
VCC
1
VCC
2
1
2
24
23
22
21
20
19
18
17
16
15
14
13
+
V
V
V
V
V
CC1
INR
AGND1
AGND2
VCOM
1µF
+
Rch In
Lch In
3
4.7µF(4)
+
4.7µF(2)
4.7µF(2)
+
+
REFL
REFR
INL
4
4.7µF(4)
+
VOUT
R
5
Rch Out
1µF
+
4.7µF(4)
VOUTL
6
+
Lch Out
MC(6)/DEM0(7)
RST/PDAD
ML/PDDA
SYSCLK
LRCIN
MC/DEM0
MD/DEM1
ZFLG/20BIT
DIN
7
MD(6)/DEM1(7)
8
ZFLG(6)/20BIT(7)
SYSCLK
9
L/R CLK
BIT CLK
R
10
11
12
Control
Interface
BCKIN
VDD
Audio
Interface
DOUT
DATA OUT
DGND
0.1µF
and
10µF(1)
DATA IN
ML(6)/PDDA(7)
RST(6)/PDAD(7)
NOTES: (1) 0.1µF ceramic and 10µF tantalum, typical, depending on power supply quality and
pattern layout. (2) 4.7µF typical, gives settling time with 30ms (4.7µF x 6.4kΩ) time constant in
Power ON and Power-Down OFF period. (3) 1µF typical, gives 5.3Hz cut-off frequency of input
HPF in normal operation and gives settling time with 30ms (1µF x 30kΩ) time constant in Power
ON and Power -Down OFF period. (4) 4.7µF typical, gives 3.4Hz cut-off frequency of output HPF
in normal operation and gives settling time with 47ms (4.7µF x 10kΩ) time constant in Power ON
and Power-Down OFF period. (5) Post low pass filter with RIN >10kΩ, depending on requirement
of system performance. (6) MC, MD, ML, ZFLG, RST and 10kΩ pull-up resistor are for the
PCM3002. (7) DEM0, DEM1, 20BIT, PDAD, PDDA are for the PCM3003.
FIGURE 12. Typical Connection Diagram for PCM3002/3003.
®
PCM3002/3003
20
PCM3003 DATA FORMAT CONTROL
GROUNDING
PCM3003 has hardwire functional control using PDAD (pin
7) and PDDA (pin 8) for Power-Down Control, DEM0 (pin
18) and DEM1 (pin 17) for de-emphasis and 20BIT (pin 16)
for 16-/20-bit format selection.
In order to optimize the dynamic performance of PCM3002/
3003, the analog and digital grounds are not connected
internally. The PCM3002/3003 performance is optimized
with a single ground plane for all returns. It is recommended
to tie all PCM3002/3003 ground pins with low impedance
connections to the analog ground plane. PCM3002/3003
should reside entirely over this plane to avoid coupling high
frequency digital switching noise into the analog ground
plane.
Power-Down Control (Pin 7 and Pin 8)
Both the ADC’s and DAC’s Power-Down Control pins
place the ADC or DAC section in the lowest power con-
sumption mode. The ADC/DAC operation is stopped by
cutting the supply current to the ADC/DAC section. DOUT
is fixed to zero during ADC Power-Down Mode enable and
VOUT is fixed to GND during DAC Power-Down Mode
enable. Figure 7 illustrates the ADC and DAC output re-
sponse for Power-Down ON/OFF. This does not affect the
ADC or DAC operation.
VOLTAGE INPUT PINS
A tantalum capacitor, between 1µF and 10µF, is recom-
mended as an AC-coupling capacitor at the inputs. Combined
with the 30kΩ characteristic input impedance, a 1.0µF cou-
pling capacitor will establish a 5.3Hz cut-off frequency for
blocking DC. The input voltage range can be increased by
adding a series resistor on the analog input line. This series
resistor, when combined with the 30kΩ input impedance,
creates a voltage divider and enables larger input ranges.
PDAD
PDDA
POWER DOWN
Low
Low
High
High
Low
High
Low
High
Reset (ADC/DAC Power-Down Enable)
ADC Power-Down/DAC Operate
ADC Operate/DAC Power-Down
ADC and DAC Normal Operation
VREF INPUTS
De-Emphasis Control (Pin 17 and Pin 18)
A 4.7µF to 10µF tantalum capacitor is recommended be-
tween VREFL, VREFR, and AGND1 to ensure low source
impedance for the ADC’s references. These capacitors should
be located as close as possible to the reference pins to reduce
dynamic errors on the ADC reference.
DEM0 (pin 18) and DEM1 (pin 17) are used as de-emphasis
control pins.
DEM1
DEM0
DE-EMPHASIS
Low
Low
High
High
Low
High
Low
High
De-Emphasis Enable at 44.1kHz
De-Emphasis Disable
De-Emphasis Enable at 48kHz
De-Emphasis Enable at 32kHz
VCOM INPUTS
A 4.7µF to 10µF tantalum capacitor is recommended be-
tween VCOM and AGND1 to ensure low source impedance
of the ADC and DAC common voltage. This capacitor
should be located as close as possible to the VCOM pin to
reduce dynamic errors on the DAC common.
20BIT Audio Data Selection (Pin 16)
20BIT
FORMAT
Low
ADC: 16-bit MSB-first, Left-justified
DAC: 16-bit MSB-first, Right-justified
ADC: 20-bit MSB-first, Left-justified
DAC: 20-bit MSB-first, Right-justified
High
SYSTEM CLOCK
The quality of the system clock can influence dynamic
performance of both the ADC and DAC in the PCM3002/
3003. The duty cycle and jitter at the system clock input pin
must be carefully managed. When power is supplied to the
part, the system clock, bit clock (BCKIN) and a word clock
(LCRIN) should also be supplied simultaneously. Failure to
supply the audio clocks will result in a power dissipation
increase of up to three times normal dissipation and may
degrade long term reliability if the maximum power dissipa-
tion limit is exceeded.
APPLICATION AND LAYOUT
CONSIDERATIONS
POWER SUPPLY BYPASSING
The digital and analog power supply lines to PCM3002/
3003 should be bypassed to the corresponding ground pins
with both 0.1µF ceramic and 10µF tantalum capacitors as
close to the device pins as possible. Although PCM3002/
3003 has three power supply lines to optimize dynamic
performance, the use of one common power supply is
generally recommended to avoid unexpected latch-up or pop
noise due to power supply sequencing problems. If separate
power supplies are used, back-to-back diodes are recom-
mended to avoid latch-up problems.
RST CONTROL
If the capacitance between VREF and VCOM exceeds 2.2µF,
an external reset control delay time circuit must be used.
®
21
PCM3002/3003
oversampling rate, eliminating the need for a sample-and-
hold circuit, and simplifying anti-alias filtering require-
ments. The 5th-order delta-sigma noise shaper consists of
five integrators which use a switched-capacitor topology, a
comparator and a feedback loop consisting of a one-bit
DAC. The delta-sigma modulator shapes the quantization
noise, shifting it out of the audio band in the frequency
domain. The high order of the modulator enables it to
randomize the modulator outputs, reducing idle tone levels.
EXTERNAL MUTE CONTROL
For Power-Down ON/OFF control without click noise which
is generated by DAC output DC level change, the External
Mute control is general required. The control sequence,
which is External Mute ON, CODEC Power-Down ON,
SYSCLK stop and resume if necessary, CODEC Power-
down OFF, and External Mute OFF is recommended. Note
that if SYSCLK is stopped when Power-Down condition for
the PCM3002, all internal mode is initialized and need to re-
write mode register value.
The 64fS one-bit data stream from the modulator is con-
verted to 1fS 18-bit data words by the decimation filter,
which also acts as a low pass filter to remove the shaped
quantization noise. The DC components are removed by a
high pass filter function contained within the decimation
filter.
THEORY OF OPERATION
ADC SECTION
The PCM3002/3003 ADC consists of two reference circuits,
a stereo single-to-differential converter, a fully differential
5th-order delta-sigma modulator, a decimation filter (includ-
ing digital high pass), and a serial interface circuit. The
Block Diagram in this data sheet illustrates the architecture
of the ADC section, Figure 1 shows the single-to-differential
converter, and Figure 14 illustrates the architecture of the
5th-order delta-sigma modulator and transfer functions.
THEORY OF OPERATION
DAC SECTION
The delta-sigma DAC section of PCM3002/3003 is based on
a 5-level amplitude quantizer and a 3rd-order noise shaper.
This section converts the oversampled input data to 5-level
delta-sigma format. A block diagram of the 5-level delta-
sigma modulator is shown in Figure 14. This 5-level delta-
sigma modulator has the advantage of stability and clock
jitter sensitivity over the typical one-bit (2 level) delta-sigma
modulator. The combined oversampling rate of the delta-
sigma modulator and the internal 8X interpolation filter is
64fS for a 256fSsystem clock. The theoretical quantization
noise performance of the 5-level delta-sigma modulator is
shown in Figure 15.
An internal reference circuit with three external capacitors
provides all reference voltages which are required by the
ADC, which defines the full scale range for the converter.
The internal single-to-differential voltage converter saves
the design, space and extra parts needed for external cir-
cuitry required by many delta-sigma converters. The internal
full-differential signal processing architecture provides a
wide dynamic range and excellent power supply rejection
performance. The input signal is sampled at 64X
Analog In
X(z)
–
–
+
–
1st SW-CAP
Integrator
+
2nd SW-CAP
Integrator
3rd SW-CAP
Integrator
+
4th SW-CAP
Integrator
5th SW-CAP
Integrator
Qn(z)
Digital Out
Y(z)
+
+
+
+
+
+
+
+
H(z)
Comparator
1-Bit
DAC
Y(z) = STF(z) • X(z) + NTF(z) • Qn(z)
Signal Transfer Function
Noise Transfer Function
STF(z) = H(z)/[1 + H(z)]
NTF(z) = 1/[1 + H(z)]
FIGURE 13. Simplified 5th-Order Delta-Sigma Modulator.
®
PCM3002/3003
22
+
–
+
–
+
+
+
+
Z–1
Z–1
Z–1
In
8fS
18-Bit
+
+
+
5-level Quantizer
4
3
2
1
0
Out
64fS (256fS)
FIGURE 14. 5-Level Delta-Sigma Modulator Block Diagram.
3rd ORDER ∆Σ MODULATOR
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
0
5
10
15
20
25
30
Frequency (kHz)
FIGURE 15. Quantization Noise Spectrum.
®
23
PCM3002/3003
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