PCM3002E [TI]
具有线性输出的低功耗立体声编解码器（S/W 控制） | DB | 24 | -25 to 85;
| 型号： | PCM3002E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有线性输出的低功耗立体声编解码器（S/W 控制） | DB | 24 | -25 to 85 光电二极管 商用集成电路 编解码器 |
| 文件： | 总42页 (文件大小：1144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PCM3003
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SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
16/20-BIT SINGLE-ENDED ANALOG INPUT/OUTPUT STEREO AUDIO CODECS
FEATURES
•
•
Single 3-V Power Supply
Small Package: SSOP-24
•
•
•
•
•
Monolithic 20-Bit ∆Σ ADC and DAC
16/20-Bit Input/Output Data
Software Control: PCM3002
Hardware Control: PCM3003
Stereo ADC:
APPLICATIONS
•
•
•
DVC Applications
DSC Applications
Portable/Mobile Audio Applications
– Single-Ended Voltage Input
– Antialiasing Filter
DESCRIPTION
– 64× Oversampling
The PCM3002 and PCM3003 are low-cost,
single-chip stereo audio codecs (analog-to-digital and
digital-to-analog converters) with single-ended analog
voltage input and output.
– High Performance
• THD+N: –86 dB
• SNR: 90 dB
The ADCs and DACs employ delta-sigma modulation
with 64-times oversampling. The ADCs include a
digital decimation filter, and the DACs include an
8-times oversampling digital interpolation filter. The
DACs also include digital attenuation, de-emphasis,
infinite zero detection, and soft mute to form a
complete subsystem. The PCM3002 and PCM3003
operate with left-justified (ADC) and right-justified
(DAC) formats, while the PCM3002 also supports
other formats, including the I2S data format.
• Dynamic Range: 90 dB
Stereo DAC:
•
– Single-Ended Voltage Output
– Analog Low-Pass Filter
– 64× Oversampling
– High Performance
• THD+N: –86 dB
• SNR: 94 dB
The PCM3002 and PCM3003 provide a power-down
mode that operates on the ADCs and DACs indepen-
dently.
• Dynamic Range: 94 dB
Special Features (PCM3002, PCM3003)
•
•
– Digital De-Emphasis: 32 kHz, 44.1 kHz,
48 kHz
The PCM3002 and PCM3003 are fabricated using a
highly advanced CMOS process, and are available in
– Power Down: ADC/DAC Independent
Special Features (PCM3002)
– Digital Attenuation (256 Steps)
– Soft Mute
a
24-pin SSOP package. The PCM3002 and
PCM3003 are suitable for wide variety of
a
cost-sensitive consumer applications where good per-
formance is required.
The PCM3002 programmable functions are controlled
by software. The PCM3003 functions, which are
controlled by hardware, include de-emphasis,
power-down, and audio data format selections.
– Digital Loopback
– Four Alternative Audio Data Formats
Sampling Rate: 4 kHz to 48 kHz
•
Digital
Decimation
Filter
Lch In
Digital Out
Digital In
Delta-Sigma
Analog Front-End
Modulator
Rch In
Serial Interface
and
*
Mode Control
Low-Pass Filter
and
Output Buffer
Multilevel
Delta-Sigma
Modulator
Digital
Interpolation
Filter
Lch Out
Rch Out
Mode Control
System Clock
* PCM3002 Only
B0006-01
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2004, Texas Instruments Incorporated
PCM3002
PCM3003
www.ti.com
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, VDD = VCC = 3 V, fS = 44.1 kHz, SYSCLK = 384 fS, and 16-bit data, unless otherwise noted
PCM3002E/3003E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUT/OUTPUT
Input Logic
(1)(2)(3)
VIH
0.7 VDD
Input logic level
VDC
(1)(2)(3)
VIL
0.3 VDD
±1
(2)
IIN
Input logic current
µA
(1)(3)
IIN
100
Output Logic
(4)
VOH
IOUT = –1 mA
IOUT = 1 mA
IOUT = 1 mA
VDD – 0.3
(4)
VOL
VOL
Output logic level
0.3
0.3
VDC
(5)
CLOCK FREQUENCY
fs Sampling frequency
4(6)
44.1
48
kHz
256 fS
384 fS
512 fS
1.024
1.536
2.048
11.2896
16.9344
22.5792
12.288
18.432
24.576
System clock frequency
MHz
ADC CHARACTERISTICS
Resolution
20
Bits
DC Accuracy
Gain mismatch, channel-
to-channel
±1
±3
±5
% of FSR
Gain error
±2
% of FSR
ppm of FSR/°C
% of FSR
Gain drift
±20
±1.7
±20
Bipolar zero error
Bipolar zero drift
Dynamic Performance(8)
High-pass filter bypassed(7)
High-pass filter bypassed(7)
ppm of FSR/°C
VIN = –0.5 dB
VIN = –60 dB
A-weighted
A-weighted
–86
–28
90
–80
THD+N
dB
Dynamic range
86
86
84
dB
dB
dB
Signal-to-noise ratio
Channel separation
90
88
(1) Pins 7, 8, 17 and 18: RST, ML, MD, and MC for the PCM3002; PDAD, PDDA, DEM1, and DEM0 for PCM3003 (Schmitt-trigger input
with 100-kΩ typical internal pulldown resistor)
(2) Pins 9, 10, 11, 15: SYSCLK, LRCIN, BCKIN, DIN (Schmitt-trigger input)
(3) Pin 16: 20BIT for PCM3003 (Schmitt-trigger input, 100-kΩ typical internal pulldown resistor)
(4) Pin 12: DOUT
(5) Pin 16: ZFLG for PCM3002 (open-drain output)
(6) See Application Bulletin SBAA033 for information relating to operation at lower sampling frequencies.
(7) High-pass filter for offset cancel
(8) fIN = 1 kHz, using the System Two™ audio measurement system by Audio Precision™ in rms mode with 20-kHz LPF, 400-Hz HPF used
for performance calculation.
2
PCM3002
PCM3003
www.ti.com
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VDD = VCC = 3 V, fS = 44.1 kHz, SYSCLK = 384 fS, and 16-bit data, unless otherwise noted
PCM3002E/3003E
PARAMETER
CONDITIONS
MIN
TYP
MAX
0.454 fS
±0.05
UNITS
Digital Filter Performance
Pass band
Hz
Hz
dB
dB
s
Stop band
0.583 fS
–65
Pass-band ripple
Stop-band attenuation
Delay time
17.4/fS
HPF frequency response
Analog Input
–3 dB
–3 dB
0.019 fS
mHz
Voltage range
0.6 VCC
0.5 VCC
30
Vp-p
VDC
kΩ
Center voltage
Input impedance
Antialiasing filter frequency
response
150
kHz
DAC CHARACTERISTICS
Resolution
20
Bits
DC Accuracy
Gain mismatch, channel-
to-channel
±1
±3
±5
% of FSR
Gain error
Gain drift
±1
% of FSR
ppm of FSR/°C
% of FSR
±20
±2.5
±20
Bipolar zero error
Bipolar zero drift
ppm of FSR/°C
Dynamic Performance(9)
VOUT = 0 dB (full scale)
VOUT = –60 dB
–86
–32
94
–80
THD+N
dB
Dynamic range
Signal-to-noise ratio
Channel separation
Digital Filter Performance
Pass band
EIAJ, A-weighted
EIAJ, A-weighted
88
88
86
dB
dB
dB
94
91
0.445 fS
Hz
Hz
dB
dB
s
Stop band
0.555 fS
–35
Pass-band ripple
Stop-band attenuation
Delay time
±0.17
11.1/fS
Analog Output
Voltage range
0.6 VCC
0.5 VCC
Vp-p
VDC
kΩ
Center voltage
Load impedance
LPF frequency response
AC coupling
f = 20 kHz
10
–0.16
dB
(9) fOUT = 1 kHz, using the System Two audio measurement system by Audio Precision in rms mode with 20-kHz LPF, 400-Hz HPF used
for performance calculation.
3
PCM3002
PCM3003
www.ti.com
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VDD = VCC = 3 V, fS = 44.1 kHz, SYSCLK = 384 fS, and 16-bit data, unless otherwise noted
PCM3002E/3003E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY REQUIREMENTS
–25°C to 85°C
0° C to 70°C(10)
2.7
2.4
3
3.6
3.6
24
VDC
VDC
mA
VCC, VDD
Supply voltage
Supply current
3
Operation, VCC = VDD = 3 V
Power down, VCC = VDD = 3 V
Operation, VCC = VDD = 3 V
18
50
54
µA
72
mW
Power down(11), VCC = VDD
3 V
=
Power dissipation
150
µW
TEMPERATURE RANGE
TA
Operation
–25
–55
85
°C
°C
Tstg
θJA
Storage
125
Thermal resistance
100
°C/W
(10) Applies for voltages between 2.4 V and 2.7 V for 0°C to 70°C and 256 fS/512 fS operation (384 fS not available)
(11) SYSCLK, BCKIN, and LRCIN are stopped.
PACKAGE/ORDERING INFORMATION
PACKAGE
TYPE
PACKAGE
CODE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
PRODUCT
QUANTITY
PCM3002E
PCM3002E/2K
PCM3003E
Rails
58
2000
58
PCM3002E
24-pin SSOP
24-pin SSOP
DB
DB
PCM3002E
PCM3003E
Tape and reel
Rails
PCM3003E
PCM3003E/2K
Tape and reel
2000
ABSOLUTE MAXIMUM RATINGS
Supply voltage VDD, VCC1, VCC
Supply voltage differences
GND voltage differences
Digital input voltage
2
–0.3 V to 6.5 V
±0.1 V
±0.1 V
–0.3 V to VDD + 0.3 V, < 6.5 V
Analog input voltage
–0.3 V to VCC1, VCC2 + 0.3 V, < 6.5 V
Power dissipation
300 mW
±10 mA
Input current (any pins except supplies)
Operating temperature
–25°C to 85°C
–55°C to 125°C
260°C, 5 s
Storage temperature
Lead temperature, soldering
Package temperature (IR reflow, peak)
235°C
4
PCM3002
PCM3003
www.ti.com
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range
MIN
2.7
NOM
3
MAX
3.6
UNIT
V
Analog supply voltage, VCC1, VCC
2
Digital supply voltage, VDD
2.7
3
3.6
V
Analog input voltage, full scale (–0 dB)
Digital input logic family
VCC = 3 V
1.8
Vp-p
CMOS
System clock
8.192
32
24.576
48
MHz
kHz
kΩ
Digital input clock frequency
Sampling clock
Analog output load resistance
Analog output load capacitance
Digital output load capacitance
Operating free-air temperature, TA
10
30
10
pF
pF
–25
85
°C
PCM3002
PCM3003
(TOP VIEW)
(TOP VIEW)
1
24
23
22
21
20
19
18
17
16
15
14
13
1
24
23
22
21
20
19
18
17
16
15
14
13
V
V
V R
1
1
V
2
V
V
V R
IN
1
1
V
2
CC
CC
CC
CC
2
2
AGND1
AGND2
AGND1
AGND2
CC
CC
3
3
IN
4
4
V
REF
V
REF
1
2
V
V
V
V
REF
V
REF
1
2
V
V
V
COM
COM
5
5
R
L
R
L
OUT
OUT
6
6
V L
RST
ML
V L
PDAD
PDDA
IN
OUT
IN
OUT
7
7
MC
MD
ZFLG
DIN
DEM0
DEM1
20BIT
DIN
V
DD
DGND
8
8
9
9
SYSCLK
LRCIN
BCKIN
DOUT
SYSCLK
LRCIN
BCKIN
DOUT
10
11
12
10
11
12
V
DD
DGND
P0004-02
PIN ASSIGNMENTS—PCM3002
NAME
AGND1
AGND2
BCKIN
DGND
DIN
PIN
23
22
11
13
15
12
10
18
17
8
I/O
DESCRIPTION
–
–
I
ADC analog ground
DAC analog ground
Bit clock input(1)
Digital ground
–
I
Data input(1)
DOUT
LRCIN
MC
O
I
Data output
Sample rate clock input (fs)(1)
Bit clock for mode control(1)(2)
Serial data for mode control(1)(2)
Strobe pulse for mode control(1)(2)
Reset, active LOW(1)(2)
I
MD
I
ML
I
RST
7
I
SYSCLK
9
I
System clock input(1)
VCC
1
2
1, 2
24
21
14
–
–
–
–
ADC analog power supply
DAC analog power supply
ADC/DAC common
VCC
VCOM
VDD
Digital power supply
(1) Schmitt-trigger input
(2) With 100-kΩ typical internal pulldown resistor
5
PCM3002
PCM3003
www.ti.com
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
PIN ASSIGNMENTS—PCM3002 (continued)
NAME
VIN
VIN
VOUT
VOUT
PIN
6
I/O
I
DESCRIPTION
L
ADC analog input, Lch
ADC analog input, Rch
DAC analog output, Lch
DAC analog output, Rch
ADC reference 1
R
3
I
L
19
20
4
O
O
–
R
VREF
VREF
1
2
5
–
ADC reference 2
ZFLG
16
O
Zero flag output, active LOW(3)
(3) Open-drain output
PIN ASSIGNMENTS—PCM3003
NAME
AGND1
AGND2
BCKIN
DEM0
DEM1
DGND
DIN
PIN
23
22
11
18
17
13
15
12
10
7
I/O
DESCRIPTION
–
–
I
ADC analog ground
DAC analog ground
Bit clock input(1)
De-emphasis control 0(1)(2)
De-emphasis control 1(1)(2)
Digital ground
I
I
–
I
Data input(1)
DOUT
LRCIN
PDAD
PDDA
SYSCLK
O
I
Data output
Sample rate clock input (fs)(1)
ADC power down, active LOW(1)(2)
DAC power down, active LOW(1)(2)
System clock input(1)
I
8
I
9
I
VCC
1
2
1, 2
24
21
14
6
–
–
–
–
I
ADC analog power supply
DAC analog power supply
ADC/DAC common
VCC
VCOM
VDD
Digital power supply
VIN
VIN
VOUT
VOUT
L
ADC analog input, Lch
ADC analog input, Rch
DAC analog output, Lch
DAC analog output, Rch
ADC reference 1
R
3
I
L
19
20
4
O
O
–
–
I
R
VREF
VREF
1
2
5
ADC reference 2
20-bit format select(1)(2)
20BIT
16
(1) Schmitt-trigger input
(2) With 100-kΩ typical internal pulldown resistor
6
PCM3002
PCM3003
www.ti.com
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES
All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted
ADC SECTION
THD+N
vs
TEMPERATURE
DYNAMIC RANGE and SNR
vs
TEMPERATURE
0.010
0.008
0.006
0.004
0.002
94
92
90
88
86
5
4
94
92
Dynamic Range
−60 dB
90
88
86
3
2
1
SNR
−0.5 dB
−25
0
25
50
75
100
−25
0
25
50
75
100
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
G002
G001
Figure 1.
Figure 2.
THD+N
vs
SUPPLY VOLTAGE
DYNAMIC RANGE and SNR
vs
SUPPLY VOLTAGE
0.010
0.008
0.006
0.004
0.002
94
92
90
88
86
5
4
94
92
−60 dB
Dynamic Range
90
88
86
3
2
1
SNR
−0.5 dB
2.1
2.4
2.7
3.0
3.3
3.6
3.9
2.1
2.4
2.7
3.0
3.3
3.6
3.9
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
G004
G003
Figure 3.
Figure 4.
NOTE: All characteristics at supply voltages from 2.4 V to 2.7 V are measured at SYSCLK = 256 fS.
7
PCM3002
PCM3003
www.ti.com
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted
THD+N
vs
SAMPLING FREQUENCY
DYNAMIC RANGE and SNR
vs
SAMPLING FREQUENCY
0.010
0.008
0.006
0.004
0.002
5
4
94
92
90
88
86
94
92
90
88
86
−60 dB
Dynamic Range
3
2
1
SNR
−0.5 dB
32
44.1
48
32
44.1
48
f − Sampling Frequency − kHz
S
f
S
− Sampling Frequency − kHz
G006
G005
Figure 5.
Figure 6.
DAC SECTION
THD+N
vs
TEMPERATURE
DYNAMIC RANGE and SNR
vs
TEMPERATURE
0.010
0.008
0.006
0.004
0.002
98
96
94
92
90
4
3
98
96
−60 dB
Dynamic Range
94
92
90
2
1
0
SNR
FS
−25
0
25
50
75
100
−25
0
25
50
75
100
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
G008
G007
Figure 7.
Figure 8.
8
PCM3002
PCM3003
www.ti.com
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted
THD+N
vs
SUPPLY VOLTAGE
DYNAMIC RANGE and SNR
vs
SUPPLY VOLTAGE
0.010
0.008
0.006
0.004
0.002
98
96
94
92
90
4
3
98
96
−60 dB
Dynamic Range
94
92
90
2
1
0
SNR
FS
2.1
2.4
2.7
3.0
3.3
3.6
3.9
2.1
2.4
2.7
3.0
3.3
3.6
3.9
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
G010
G009
Figure 9.
Figure 10.
NOTE: All characteristics at supply voltages from 2.4 V to 2.7 V are measured at SYSCLK = 256 fS.
THD+N
DYNAMIC RANGE and SNR
vs
SAMPLING FREQUENCY and SYSTEM CLOCK
vs
SAMPLING FREQUENCY and SYSTEM CLOCK
0.010
0.008
0.006
0.004
0.002
4
98
96
94
92
90
98
256 f , 512 f
S
S
3
96
94
92
90
−60 dB
384 f
S
SNR
256 f , 512 f
S
S
2
1
0
384 f
S
Dynamic
Range
FS
256 f , 512 f
S
S
384 f
S
32
44.1
48
32
44.1
48
f − Sampling Frequency − kHz
S
f
S
− Sampling Frequency − kHz
G012
G011
Figure 11.
Figure 12.
9
PCM3002
PCM3003
www.ti.com
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted
OUTPUT SPECTRUM
ADCs
OUTPUT SPECTRUM (–0.5 dB, N = 8192)
OUTPUT SPECTRUM (–60 dB, N = 8192)
0
−20
0
−20
−40
−40
−60
−60
−80
−80
−100
−120
−140
−100
−120
−140
0
5
10
15
20
25
0
5
10
15
20
25
f − Frequency − kHz
f − Frequency − kHz
G013
G015
Figure 13.
Figure 14.
THD+N
vs
SIGNAL LEVEL
100
10
1
0.1
0.01
0.001
−96 −84 −72 −60 −48 −36 −24 −12
0
Signal Level − dB
G017
Figure 15.
10
PCM3002
PCM3003
www.ti.com
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted
DACs
OUTPUT SPECTRUM (0 dB, N = 8192)
OUTPUT SPECTRUM (–60 dB, N = 8192)
0
−20
0
−20
−40
−40
−60
−60
−80
−80
−100
−120
−140
−100
−120
−140
0
5
10
15
20
25
0
5
10
15
20
25
f − Frequency − kHz
f − Frequency − kHz
G014
G016
Figure 16.
Figure 17.
THD+N
vs
SIGNAL LEVEL
100
10
1
0.1
0.01
0.001
−96 −84 −72 −60 −48 −36 −24 −12
0
Signal Level − dB
G018
Figure 18.
11
PCM3002
PCM3003
www.ti.com
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES
All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, DIN = BPZ, and VIN = BPZ, unless otherwise
noted
SUPPLY CURRENT
ICC + IDD
vs
SUPPLY VOLTAGE
ICC + IDD
vs
TEMPERATURE
25
20
15
10
5
25
20
15
10
5
2.5
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
ADC and DAC
ADC and DAC
ADC
DAC
ADC
DAC
Power Down and Off
Power Down and Off
0
0
2.1
2.4
2.7
3.0
3.3
3.6
3.9
−50
−25
0
25
50
75
100
V
CC
− Supply Voltage − V
T
A
− Free-Air Temperature − °C
G020
G019
Figure 19.
Figure 20.
All characteristics at supply voltages from 2.4 V to
2.7 V are measured at SYSCLK = 256 fS.
ICC + IDD
vs
SAMPLING FREQUENCY
20
19
18
17
16
15
ADC and DAC
512 f
S
256 f
S
32
44.1
48
f
S
− Sampling Frequency − kHz
G021
Figure 21.
12
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PCM3003
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SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs)
All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted
DECIMATION FILTER
OVERALL CHARACTERISTICS
STOP-BAND ATTENUATION CHARACTERISTICS
0
−50
0
−20
−40
−100
−150
−200
−60
−80
−100
0
8
16
24
32
0.0
0.2
0.4
0.6
0.8
1.0
Normalized Frequency [× f Hz]
Normalized Frequency [× f Hz]
S
S
G022
G023
Figure 22.
Figure 23.
PASS-BAND RIPPLE CHARACTERISTICS
TRANSITION BAND CHARACTERISTICS
0.2
0.0
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−0.2
−0.4
−0.6
−0.8
−1.0
−4.13 dB at 0.5 f
S
0.0
0.1
0.2
0.3
0.4
0.5
0.45
0.47
0.49
0.51
0.53
0.55
Normalized Frequency [× f Hz]
Normalized Frequency [× f Hz]
S
S
G024
G025
Figure 24.
Figure 25.
13
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SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) (continued)
All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted
HIGH-PASS FILTER
HIGH-PASS FILTER RESPONSE
HIGH-PASS FILTER RESPONSE
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0.2
0.0
−0.2
−0.4
−0.6
−0.8
−1.0
0.0
0.1
0.2
0.3
0.4
0.5
0
1
2
3
4
Normalized Frequency [× f /1000 Hz]
S
Normalized Frequency [× f /1000 Hz]
S
G027
G026
Figure 26.
Figure 27.
ANTIALIASING FILTER
ANTIALIASING FILTER OVERALL
FREQUENCY RESPONSE
ANTIALIASING FILTER PASS-BAND
FREQUENCY RESPONSE
0.2
0.0
0
−10
−20
−30
−40
−50
−0.2
−0.4
−0.6
−0.8
−1.0
1
10
100
1k
10k 100k
1M
10M
1
10
100
1k
10k
100k
f − Frequency − Hz
f − Frequency − Hz
G028
G029
Figure 28.
Figure 29.
14
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SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs)
All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted
DIGITAL FILTER
OVERALL FREQUENCY CHARACTERISTICS
PASS-BAND RIPPLE CHARACTERISTICS
(fS = 44.1 kHz)
(fS = 44.1 kHz)
0
−20
0.00
−0.20
−0.40
−0.60
−0.80
−1.00
−40
−60
−80
−100
0
25k
50k
75k 100k 125k 150k 175k
0
5k
10k
15k
20k
f − Frequency − Hz
f − Frequency − Hz
G030
G031
Figure 30.
Figure 31.
DE-EMPHASIS FILTER
DE-EMPHASIS FREQUENCY RESPONSE (32 kHz)
DE-EMPHASIS ERROR (32 kHz)
0
−2
0.6
0.4
−4
0.2
−6
0.0
−8
−0.2
−0.4
−0.6
−10
−12
0
5k
10k
15k
20k
25k
0
3628
7256
10884
14512
f − Frequency − Hz
f − Frequency − Hz
G032
G033
Figure 32.
Figure 33.
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SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued)
All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted
DE-EMPHASIS FREQUENCY RESPONSE (44.1 kHz)
DE-EMPHASIS ERROR (44.1 kHz)
0
−2
0.6
0.4
−4
0.2
−6
0.0
−8
−0.2
−0.4
−0.6
−10
−12
0
5k
10k
15k
20k
25k
0
4999.8375 9999.675 14999.5125 19999.35
f − Frequency − Hz
f − Frequency − Hz
G034
G035
Figure 34.
Figure 35.
DE-EMPHASIS FREQUENCY RESPONSE (48 kHz)
DE-EMPHASIS ERROR (48 kHz)
0
−2
0.6
0.4
−4
0.2
−6
0.0
−8
−0.2
−0.4
−0.6
−10
−12
0
5k
10k
15k
20k
25k
0
5442
10884
16326
21768
f − Frequency − Hz
f − Frequency − Hz
G036
G037
Figure 36.
Figure 37.
16
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SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued)
All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted
ANALOG LOW-PASS FILTER
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(1 Hz–10 MHz)
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(1 Hz–100 kHz)
20
0.15
0
−20
0.10
0.05
−40
0.00
−60
−0.05
−0.10
−0.15
−80
−100
1
10
100
1k
10k 100k
1M
10M
1
10
100
1k
10k
100k
f − Frequency − Hz
f − Frequency − Hz
G038
G039
Figure 38.
Figure 39.
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SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
BLOCK DIAGRAM
(+)
Analog
Front-End
Circuit
Decimation
Delta-Sigma
Modulator
V
L
and
LRCIN
BCKIN
IN
(−)
High-Pass Filter
V
1
REF
Serial Data
Interface
V
COM
Reference
ADC
V
2
REF
DIN
(−)
(+)
Analog
Front-End
Circuit
Decimation
and
High-Pass Filter
Delta-Sigma
Modulator
V R
IN
DOUT
(1)
(2)
MC /DEM0
Analog
Low-Pass
Filter
Multilevel
Delta-Sigma
Modulator
Interpolation
Filter
8× Oversampling
(1)
(2)
MD /DEM1
Mode
Control
Interface
V L
OUT
(1)
ML
(2)
20BIT
DAC
Analog
Low-Pass
Filter
Multilevel
Delta-Sigma
Modulator
Interpolation
Filter
8× Oversampling
V R
OUT
(2)
PDDA
Reset and
Power Down
(1)
(2)
RST /PDAD
(1)
Power Supply
Clock
Zero Detect
(1)
AGND2
V 2
CC
AGND1
V 1
CC
DGND
V
DD
SYSCLK
ZFLG
B0004-03
(1) MC, MD, ML, RST, and ZFLG are for PCM3002 only.
(2) DEM0, DEM1, 20BIT, PDAD, and PDDA are for PCM3003 only.
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SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
1.0 µF
30 kΩ
R
V
IN
−
+
3
+
−
+
(+)
(−)
V
V
V
COM
21
4
Delta-Sigma
Modulator
+
4.7 µF
1
REF
+
4.7 µF
2
REF
5
+
4.7 µF
V
REF
S0011-03
Figure 40. Analog Front-End (Single-Channel)
PCM AUDIO INTERFACE
The four-wire digital audio interface for the PCM3002/3003 comprises LRCIN (pin 10), BCKIN (pin 11), DIN
(pin 15), and DOUT (pin 12). The PCM3002 can be used with any of the four input/output data formats (formats
0–3), while the PCM3003 can only be used with selected input/output formats (formats 0–1). For the PCM3002,
these formats are selected through program register 3 in the software mode. For the PCM3003, data formats are
selected by the 20BIT input (pin 16). Figure 41, Figure 42, and Figure 43 illustrate audio data input/output
formats and timing.
The PCM3002/3003 can accept 32, 48, or 64 bit clocks (BCKIN) in one clock of LRCIN. Only the 16-bit data
format can be selected when 32-bit clocks/LRCIN are applied.
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SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
FORMAT 0: PCM3002/3003
DAC: 16-Bit, MSB-First, Right-Justified
LRCIN
BCKIN
DIN
Left-Channel
Right-Channel
16
1
2
3
14 15 16
LSB
1
2
3
14 15 16
MSB
MSB
LSB
ADC: 16-Bit, MSB-First, Left-Justified
Left-Channel
Right-Channel
LRCIN
BCKIN
DOUT
1
1
2
3
14 15 16
LSB
1
2
3
14 15 16
LSB
MSB
MSB
FORMAT 1: PCM3002/3003
DAC: 20-Bit, MSB-First, Right-Justified
LRCIN
BCKIN
Left-Channel
Right-Channel
DIN
20
1
2
3
18 19 20
LSB
1
2
3
18 19 20
LSB
MSB
MSB
ADC: 20-Bit, MSB-First, Left-Justified
Left-Channel
Right-Channel
LRCIN
BCKIN
DOUT
1
1
2
3
18 19 20
LSB
1
2
3
18 19 20
LSB
MSB
MSB
T0016-04
Figure 41. Audio Data Input/Output Format
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SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
FORMAT 2: PCM3002 Only
DAC: 20-Bit, MSB-First, Left-Justified
Left-Channel
Right-Channel
LRCIN
BCKIN
DIN
1
1
2
3
18 19 20
LSB
1
2
3
18 19 20
LSB
MSB
MSB
ADC: 20-Bit, MSB-First, Left-Justified
Left-Channel
Right-Channel
LRCIN
BCKIN
DOUT
1
1
2
3
18 19 20
LSB
1
2
3
18 19 20
LSB
MSB
MSB
FORMAT 3: PCM3002 Only
2
DAC: 20-Bit, MSB-First, I S
Left-Channel
Right-Channel
LRCIN
BCKIN
DIN
1
2
3
18 19 20
1
2
3
18 19 20
MSB
LSB
MSB
LSB
2
ADC: 20-Bit, MSB-First, I S
Left-Channel
Right-Channel
LRCIN
BCKIN
DOUT
1
2
3
18 19 20
LSB
1
2
3
18 19 20
LSB
MSB
MSB
T0016-05
Figure 42. Audio Data Input/Output Format (PCM3002)
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SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
t
(LRP)
0.5 V
DD
LRCIN
t
t
(BCL)
(LB)
t
t
(BL)
(BCH)
0.5 V
DD
BCKIN
DIN
t
t
t
(DIS)
(DIH)
(BCY)
0.5 V
DD
t
t
(LDO)
(BDO)
0.5 V
DD
DOUT
T0021−01
BCKIN pulse cycle time
t(BCY)
t(BCH)
t(BCL)
t(BL)
300 ns (min)
120 ns (min)
120 ns (min)
40 ns (min)
40 ns (min)
t(BCY) (min)
40 ns (min)
40 ns (min)
40 ns (max)
40 ns (max)
20 ns (max)
20 ns (max)
BCKIN pulse duration, HIGH
BCKIN pulse duration, LOW
BCKIN rising edge to LRCIN edge
LRCIN edge to BCKIN rising edge
LRCIN pulse duration
DIN setup time
t(LB)
t(LRP)
t(DIS)
t(DIH)
t(BDO)
t(LDO)
t(RISE)
t(FALL)
DIN hold time
DOUT delay time to BCKIN falling edge
DOUT delay time to LRCIN edge
Rising time of all signals
Falling time of all signals
Figure 43. Audio Data Input/Output Timing
SYSTEM CLOCK
The system clock for the PCM3002/3003 must be either 256 fS, 384 fS, or 512 fS, where fS is the audio sampling
frequency. The system clock should be provided at the SYSCLK input (pin 9).
The PCM3002/3003 also has a system-clock detection circuit that automatically senses if the system clock is
operating at 256 fS, 384 fS, or 512 fS. When a 384-fS or 512-fS system clock is used, the clock is divided to 256 fS
automatically. The 256-fS clock is used to operate the digital filters and the delta-sigma modulators.
Table 1 lists the relationship of typical sampling frequencies and system clock frequencies; Figure 44 illustrates
the system clock timing.
Table 1. System Clock Frequencies
SAMPLING RATE FREQUENCY (kHz)
SYSTEM CLOCK FREQUENCY (MHz)
256 fs
8.1920
11.2896
12.2880
384 fs
512 fs
32
44.1
48
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
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SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
t
(SCKH)
H
0.7 V
0.3 V
DD
SYSCLK
DD
L
t
1/256 f ,
S
1/384 f ,
S
(SCKL)
or 1/512 f
S
T0005-05
Figure 44. System Clock Timing
System clock pulse duration, HIGH
System clock pulse duration, LOW
t(SCKH)
t(SCKL)
12 ns (min)
12 ns (min)
POWER-ON RESET
Both the PCM3002 and PCM3003 have internal power-on reset circuitry. Power-on reset occurs when the
system clock (SYSCLK) is active and VDD > 2.2 V. For the PCM3003, the SYSCLK must complete a minimum of
three complete cycles prior to VDD > 2.2 V to ensure proper reset operation. The initialization sequence requires
1024 SYSCLK cycles for completion, as shown in Figure 45. Figure 46 shows the state of the DAC and ADC
outputs during and after the reset sequence.
2.4 V
2.2 V
2.0 V
V
DD
Reset
Reset Removal
Internal Reset
System Clock
3 Clocks Minimum
1024 System Clock Periods
T0014-03
Figure 45. Internal Power-On Reset Timing
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SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
Reset Removal or Power Down Off
Ready/Operation
Internal Reset
or Power Down
Reset
Power Down
t
(DACDLY1)
(16384/f )
S
V
COM
GND
DAC V
OUT
(0.5 V
)
CC
t
(ADCDLY1)
(18432/f )
S
(1)
Zero Data
Zero Data
Normal Data
ADC DOUT
T0019-02
(1) The HPF transient response (exponentially attenuated signal from ±0.2% dc of FSR with 200-ms time constant)
appears initially.
Figure 46. DAC Output and ADC Output for Reset and Power Down
EXTERNAL RESET
The PCM3002 includes a reset input, RST (pin 7), while the PCM3003 uses both PDAD (pin 7) and PDDA
(pin 8) for external reset control. As shown in Figure 47, the external reset signal must drive RST or PDAD and
PDDA low for a minimum of 40 nanoseconds while SYSCLK is active in order to initiate the reset sequence.
Initialization starts on the rising edge of RST or PDAD and PDDA, and requires 1024 SYSCLK cycles for
completion. Figure 46 shows the state of the DAC and ADC outputs during and after the reset sequence.
t
= 40 ns (min)
(RST)
RST Pulse Duration
RST
or
PDAD and PDDA
t
(RST)
Reset
Reset Removal
Internal Reset
System Clock
1024 System Clock Periods
T0015-02
Figure 47. External Forced-Reset Timing
SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM
The PCM3002/3003 operates with LRCIN synchronized to the system clock. The PCM3002/3003 does not
require any specific phase relationship between LRCIN and the system clock, but there must be synchronization
of LRCIN and the system clock. If the synchronization between the system clock and LRCIN changes more than
6 bit clocks (BCKIN) during one sample (LRCIN) period because of phase jitter on LRCIN, internal operation of
the DAC stops within 1/fS, and the analog output is forced to bipolar zero (0.5 VCC) until the system clock is
resynchronized to LRCIN followed by t(DACDLY2) delay time. Internal operation of the ADC also stops within 1/fS,
and the digital output codes are set to bipolar zero until resynchronization occurs followed by t(ADCDLY2) delay
time. If LRCIN is synchronized within 5 or fewer bit clocks to the system clock, operation is normal. Figure 48
illustrates the effects on the output when synchronization is lost. Before the outputs are forced to bipolar zero
(<1/fS seconds), the outputs are not defined and some noise may occur. During the transitions between normal
data and undefined states, the output has discontinuities, which cause output noise.
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SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
Resynchronization
Synchronization Lost
Synchronous
Asynchronous
Synchronous
State of Synchronization
t
(DACDLY2)
Within 1/f
S
(32/f )
S
V
COM
Undefined
DAC V
OUT
Normal Data
Normal Data
Data
(0.5 V )
CC
t
(ADCDLY2)
(32/f )
S
Undefined
Data
(1)
ADC DOUT
Normal Data
Zero Data
Normal Data
T0020-03
(1) The HPF transient response (exponentially attenuated signal from ±0.2% dc of FSR with 200-ms time constant)
appears initially.
Figure 48. DAC Output and ADC Output for Loss of Synchronization
ZERO FLAG OUTPUT: PCM3002 ONLY
Pin 16 is an open-drain output, used as the infinite zero detection flag on the PCM3002 only. When input data is
continuously zero for 65,536 BCKIN cycles, ZFLG is LOW; otherwise, ZFLG is in a high-impedance state.
OPERATIONAL CONTROL
The PCM3002 can be controlled in a software mode with a three-wire serial interface on MC (pin 18),
MD (pin 17), and ML (pin 8). Table 2 indicates selectable functions, and Figure 49 and Figure 50 illustrate the
control data input format and timing. The PCM3003 only allows for control of 16/20-bit data format, digital
de-emphasis, and power-down control by hardware pins.
Table 2. Selectable Functions (O = User Selectable; X = Not Available)
FUNCTION
ADC/DAC
ADC/DAC
ADC/DAC
ADC/DAC
DAC
PCM3002
PCM3003
Audio data format
LRCIN polarity
Four selectable formats
Two selectable formats
O
O
O
O
O
O
O
O
O
O
O
O
X
X
X
X
X
X
X
X
O
O
O
X
Loopback control
Left-channel attenuation
Right-channel attenuation
Attenuation control
DAC
DAC
Infinite zero detection and mute
DAC output control
DAC
DAC
Soft mute control
DAC
De-emphasis (OFF, 32 kHz, 44.1 kHz, 48 kHz)
ADC power-down control
DAC power-down control
High-pass filter operation
DAC
ADC
DAC
ADC
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SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
ML
MC
B14 B13 B12 B11 B10
B9
B8
B6
B5
B4
B3
B2
B1
B0
MD
B15
B7
T0023-01
Figure 49. Control Data Input Format
t
(MHH)
t
(MLH)
t
(MLS)
0.5 V
ML
DD
t
(MCL)
t
(MLL)
t
(MCH)
MC
MD
0.5 V
0.5 V
DD
t
(MCY)
LSB
DD
t
(MDS)
t
(MDH)
T0024-02
MC pulse cycle time
t(MCY)
t(MCL)
t(MCH)
t(MDS)
t(MDH)
t(MLL)
t(MHH)
t(MLS)
t(MLH)
100 ns (min)
40 ns (min)
40 ns (min)
40 ns (min)
40 ns (min)
MC pulse duration, LOW
MC pulse duration, HIGH
MD setup time
MD hold time
ML low-level time
ML high-level time
ML setup time(3)
ML hold time(2)
40 ns + 1 SYSCLK(1) (min)
40 ns + 1 SYSCLK(1) (min)
40 ns (min)
40 ns (min)
SYSCLK: 1/256 fS or 1/384 fS or 1/512 fS
(1) SYSCLK: System clock cycle
(2) MC rising edge of LSB to ML rising edge
(3) ML rising edge to the next MC rising edge
Figure 50. Control Data Input Timing
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SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
MAPPING OF PROGRAM REGISTERS
B15 B14 B13 B12 B11
B10
A1
B9
A0
B8
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER 0 res
REGISTER 1 res
REGISTER 2 res
REGISTER 3 res
res
res
res
res
res
res
res
res
res
res
res
res
res
res
res
res
LDL
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
A1
A1
A1
A0
A0
A0
LDR
AR7
AR6
AR5
AR4
IZD
res
AR3
AR2
AR1
AR0
PDAD BYPS PDDA ATC
res res res LOP
OUT DEM1 DEM0 MUT
FMT1 FMT0 LRP res
NOTE: res indicates a reserved bit that should be set to 0.
SOFTWARE CONTROL (PCM3002)
The PCM3002 special functions are controlled using four program registers which are each 16 bits long. There
are four distinct registers, with bits 9 and 10 determining which register is in use. Table 3 describes the functions
of the four registers.
Table 3. Functions of the Registers
REGISTER NAME
REGISTER BIT(S)
BIT NAME
res
DESCRIPTION
Reserved, should be set to 0
Register address 00
Register 0
15–11
10–9
8
A[1:0]
LDL
DAC attenuation data load control for
Lch
7–0
15–11
10–9
8
AL[7:0]
res
DAC attenuation data for Lch
Reserved, should be set to 0
Register address 01
Register 1
Register 2
A[1:0]
LDR
DAC attenuation data load control for
Rch
7–0
AR[7:0]
res
DAC attenuation data for Rch
Reserved, should be set to 0
Register address 10
15–11
10–9
A[1:0]
PDAD
BYPS
PDDA
ATC
8
7
6
5
4
ADC power-down control
ADC high-pass filter bypass control
DAC power-down control
DAC attenuation data mode control
IZD
DAC infinite zero detection and mute
control
3
2–1
0
OUT
DEM[1:0]
MUT
res
DAC output enable control
DAC de-emphasis control
DAC Lch and Rch soft mute control
Reserved, should be set to 0
Register address 11
Register 3
15–11
10–9
8–6
5
A[1:0]
res
Reserved, should be set to 0
ADC/DAC digital loopback control
Reserved, should be set to 0
ADC/DAC audio data format selection
ADC/DAC polarity of LR-clock selection
Reserved, should be set to 0
LOP
4
res
3–2
1
FMT[1:0]
LRP
0
res
PROGRAM REGISTER 0
res:
Bits 15–11: Reserved
These bits are reserved and should be set to 0.
27
PCM3002
PCM3003
www.ti.com
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
A[1:0]
Bits 10, 9: Register address
These bits define the address for register 0:
A1
A0
REGISTER
0
0
Register 0
LDL
Bit 8: DAC attenuation data load control for left channel
This bit is used to set analog outputs of the left and right channels simultaneously. The output level
is controlled by AL[7:0] attenuation data when this bit is set to 1. When set to 0, the new attenuation
data is ignored, and the output level remains at the previous attenuation level. The LDR bit in
register 1 has the equivalent function as LDL. When either LDL or LDR is set to 1, the output levels
of the left and right channels are controlled simultaneously.
AL (7:0)
Bits 7–0: DAC attenuation data for left channel
AL7 and AL0 are the MSB and LSB, respectively. The attenuation level (ATT) is given by:
ATT = 20 × log10 (AL[7:0]/256) [dB], except AL[7:0] = FFh
AL[7:0]
00h
01h
:
ATTENUATION LEVEL
–∞dB (mute)
–48.16 dB
:
FEh
FFh
–0.07 dB
0 dB (default)
PROGRAM REGISTER 1
res:
Bits 15–11: Reserved
These bits are reserved and should be set to 0.
A[1:0]
Bits 10, 9: Register address
These bits define the address for register 1:
A1
A0
REGISTER
0
1
Register 1
LDR
Bit 8: DAC attenuation data load control for right channel
This bit is used to set analog outputs of the left and right channels simultaneously. The output level
is controlled by AR[7:0] attenuation data when this bit is set to 1. When set to 0, the new
attenuation data is ignored, and the output level remains at the previous attenuation level. The LDL
bit in register 0 has the equivalent function as LDR. When either LDL or LDR is set to 1, the output
levels of the left and right channels are controlled simultaneously.
AR[7:0]
Bits 7–0: DAC attenuation data for right channel
AR7 and AR0 are the MSB and LSB, respectively.
ATT = 20 × log10 (AR[7:0]/256) [dB], except AR[7:0] = FFh
AR[7:0]
00h
01h
:
ATTENUATION LEVEL
–∞dB (mute)
–48.16 dB
:
FEh
FFh
–0.07 dB
0 dB (default)
PROGRAM REGISTER 2
res:
Bits 15–11: Reserved
These bits are reserved and should be set to 0.
28
PCM3002
PCM3003
www.ti.com
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
A[1:0]
Bits 10, 9: Register address
These bits define the address for register 2:
A1
A0
REGISTER
1
0
Register 2
PDAD:
Bit 8: ADC power-down control
This bit places the ADC section in the lowest power-consumption mode. The ADC operation is
stopped by cutting the supply current to the ADC section, and DOUT is fixed to zero during ADC
power-down mode enable. Figure 46 illustrates the ADC DOUT response for ADC power-down
ON/OFF. This does not affect the DAC operation.
PDAD
DAC POWER-DOWN STATUS
Power-down mode disabled (default)
Power-down mode enabled
0
1
BYPS:
Bit 7: ADC high-pass filter bypass control
This bit enables or disables the high-pass filter for the ADC.
BYPS
FILTER BYPASS STATUS
High-pass filter enabled (default)
0
1
High-pass filter disabled (bypassed)
PDDA:
Bit 6: DAC power-down control
This bit places the DAC section in the lowest power-consumption mode. The DAC operation is
stopped by cutting the supply current to the DAC section, and VOUT is fixed to GND during DAC
power-down mode enable. Figure 46 illustrates the DAC VOUT response for DAC power-down
ON/OFF. This does not affect the ADC operation.
PDDA
ADC POWER-DOWN STATUS
Power-down mode disabled (default)
Power-down mode enabled
0
1
ATC:
Bit 5: DAC attenuation data mode control
When set to 1, the register 0 attenuation data can be used for both DAC channels. In this case, the
register 1 attenuation data is ignored.
ATC
ATTENUATION CONTROL
Individual channel attenuation data control (default)
Common channel attenuation data control
0
1
IZD:
Bit 4: DAC infinite zero detection and mute control
This bit enables the infinite zero detection circuit in the PCM3002. When enabled, this circuit
disconnects the analog output amplifier from the delta-sigma DAC when the input is continuously
zero for 65,536 consecutive cycles of BCKIN.
IZD
0
INFINITE ZERO DETECT STATUS
Infinite zero detection and mute control disabled (default)
Infinite zero detection and mute control enabled
1
OUT:
Bit 3: DAC output enable control
When set to 1, the outputs are forced to VCC/2 (bipolar zero). In this case, all registers in the
PCM3002 hold the present data. Therefore, when set to 0, the outputs return to the previous
programmed state.
OUT
DAC OUTPUT STATUS
DAC outputs enabled (default normal operation)
DAC outputs disabled (forced to BPZ)
0
1
29
PCM3002
PCM3003
www.ti.com
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
DEM[1:0]: Bits 2, 1: DAC de-emphasis control
These bits select the de-emphasis mode as shown below:
DEM1
DEM0
DE-EMPHASIS STATUS
De-emphasis 44. 1 kHz ON
0
0
1
1
0
1
0
1
De-emphasis OFF (default)
De-emphasis 48 kHz ON
De-emphasis 32 kHz ON
MUT:
Bit 0: DAC soft mute control
When set to 1, both left- and right-channel DAC outputs are muted at the same time. This muting is
done by attenuating the data in the digital filter, so there is no audible click noise when soft mute is
turned on.
MUT
MUTE STATUS
Mute disabled (default)
Mute enabled
0
1
PROGRAM REGISTER 3
res:
Bits 15–11: Reserved
These bits are reserved and should be set to 0.
A[1:0]
Bits 10, 9: Register address
These bits define the address for register 3:
A1
A0
REGISTER
1
1
Register 3
res:
Bits 8–6: Reserved
These bits are reserved and should be set to 0.
LOP:
Bit 5: ADC to DAC loopback control
When this bit is set to 1, the ADC audio data is sent directly to the DAC. The data format defaults to
I2S; DOUT is still available in loopback mode.
LOP
LOOPBACK STATUS
Loopback disabled (default)
Loopback enabled
0
1
res:
Bit 4: Reserved
This bit is reserved and should be set to 0.
FMT[1:0]
Bits 3–2: Audio data format select
These bits determine the input and output audio data formats.
FMT1
FMT0
DAC DATA FORMAT
16-bit, MSB-first, right-justified
20-bit, MSB-first, right-justified
20-bit, MSB-first, left-justified
20-bit, MSB-first, I2S
ADC DATA FORMAT
16-bit, MSB-first, left-justified
20-bit, MSB-first, left-justified
20-bit, MSB-first, left-justified
20-bit, MSB-first, I2S
NAME
Format 0 (default)
Format 1
0
0
1
1
0
1
0
1
Format 2
Format 3
LRP:
Bit 1: ADC to DAC LRCIN polarity select
Polarity of LRCIN applies only to formats 0 through 2.
LRP
LEFT/RIGHT POLARITY
Left channel is H, right channel is L (default).
Left channel is L, right channel is H.
0
1
30
PCM3002
PCM3003
www.ti.com
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
res:
Bit 0: Reserved
This bit is reserved and should be set to 0.
PCM3003 DATA FORMAT CONTROL
The PCM3003 has hardware functional control using PDAD (pin 7) and PDDA (pin 8) for power-down control;
DEM0 (pin 18) and DEM1 (pin 17) for de-emphasis; and 20BIT (pin 16) for 16/20-bit format selection.
Power-Down Control (Pin 7 and Pin 8)
Both the ADC and DAC power-down control pins place the ADC or DAC section in the lowest
power-consumption mode. The ADC/DAC operation is stopped by cutting the supply current to the ADC/DAC
section. DOUT is fixed to zero during ADC power-down mode enable and VOUT is fixed to GND during DAC
power-down mode enable. Figure 46 illustrates the ADC and DAC output response for power-down ON/OFF.
PDAD
Low
PDDA
Low
POWER DOWN
Reset (ADC/DAC power down enabled)
ADC power-down/DAC operates
ADC operates/DAC power down
ADC and DAC normal operation
Low
High
Low
High
High
High
De-Emphasis Control (Pin 17 and Pin 18)
DEM0 (pin 18) and DEM1 (pin 17) are used as de-emphasis control pins.
DEM1
Low
DEMO
Low
DE-EMPHASIS
De-emphasis enabled for 44.1 kHz
Low
High
Low
De-emphasis disabled
High
High
De-emphasis enabled for 48 kHz
De-emphasis enabled for 32 kHz
High
20BIT Audio Data Selection (Pin 16)
20BIT
FORMAT
ADC: 16-bit MSB-first, left-justified
Low
DAC: 16-bit MSB-first, right-justified
ADC: 20-bit MSB-first, left-justified
DAC: 20-bit MSB-first, right-justified
High
31
PCM3002
PCM3003
www.ti.com
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
APPLICATION AND LAYOUT CONSIDERATIONS
POWER-SUPPLY BYPASSING
The digital and analog power supply lines to PCM3002/3003 should be bypassed to the corresponding ground
pins with both 0.1-µF ceramic and 10-µF tantalum capacitors as close to the device pins as possible. Although
the PCM3002/3003 has three power-supply lines to optimize dynamic performance, the use of one common
power supply is generally recommended to avoid unexpected latch-up or pop noise due to power-supply
sequencing problems. If separate power supplies are used, back-to-back diodes are recommended to avoid
latch-up problems.
GROUNDING
In order to optimize the dynamic performance of the PCM3002/3003, the analog and digital grounds are not
connected internally. The PCM3002/3003 performance is optimized with a single ground plane for all returns. It is
recommended to tie all PCM3002/3003 ground pins to the analog ground plane using low-impedance
connections. The PCM3002/3003 should reside entirely over this plane to avoid coupling high-frequency digital
switching noise into the analog ground plane.
VOLTAGE INPUT
A tantalum or aluminum electrolytic capacitor, between 1 µF and 10 µF, is recommended as an ac-coupling
capacitor at the inputs. Combined with the 30-kΩ characteristic input impedance, a 1-µF coupling capacitor
establishes a 5.3-Hz cutoff frequency for blocking dc. The input voltage range can be increased by adding a
series resistor on the analog input line. This series resistor, when combined with the 30-kΩ input impedance,
creates a voltage divider and enables larger input ranges.
VREF INPUTS
A 4.7-µF to 10-µF tantalum capacitor is recommended between VREF1, VREF2, and AGND1 to ensure low source
impedance for the ADC references. These capacitors should be located as close as possible to the reference
pins to reduce dynamic errors on the ADC reference.
VCOM INPUT
A 4.7-µF to 10-µF tantalum capacitor is recommended between VCOM and AGND1 to ensure low source
impedance of the ADC and DAC common voltage. This capacitor should be located as close as possible to the
VCOM pin to reduce dynamic errors on the dc common-mode voltage.
SYSTEM CLOCK
The quality of the system clock can influence dynamic performance of both the ADC and DAC in the
PCM3002/3003. The duty cycle and jitter at the system-clock input pin should be carefully managed. When
power is supplied to the part, the system clock, bit clock (BCKIN), and word clock (LCRIN) also must be supplied
simultaneously. Failure to supply the audio clocks results in a power-dissipation increase of up to three times
normal dissipation and can degrade long-term reliability if the maximum power-dissipation limit is exceeded.
RESET CONTROL
If capacitors larger than 22 µF are used on VREF and VCOM, external reset control (RST = low for the PCM3002,
PDAD = low and PDDA = low for the PCM3003) is required after the VREF, VCOM transient response is settled.
EXTERNAL MUTE CONTROL
For power-down ON/OFF control without click noise, which is generated by a DC level change on the DAC
output, use of the external mute control is recommended. The control sequence, which is external mute ON,
codec power-down ON, SYSCLK stop and resume if necessary, codec power-down OFF, and external mute
OFF is recommended.
TYPICAL CONNECTION DIAGRAM
A typical connection diagram for the PCM3002/3003 is shown in Figure 51.
32
PCM3002
PCM3003
www.ti.com
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
+3 V Analog V
CC
0.1 µF
and 10 µF
+
0.1 µF
and 10 µF
+
PCM3002/3003
(1)
(1)
V
V
V
V
V
V
1
1
V
2
1
2
24
23
22
21
20
19
18
17
16
15
14
13
CC
CC
AGND1
AGND2
CC
(3)
1 µF
+
Rch In
Lch In
R
3
IN
(2)
4.7 µF
+
(2)
(2)
4.7 µF
+
+
1
V
COM
4
REF
REF
4.7 µF
(4)
(4)
4.7 µF
4.7 µF
+
+
(5)
2
V
R
L
5
Rch Out
OUT
(3)
+
1 µF
(5)
L
V
6
Lch Out
IN
OUT
(6)
(7)
RST/PDAD
ML/PDDA
SYSCLK
LRCIN
MC/DEM0
MD/DEM1
ZFLG/20BIT
DIN
7
MC /DEM0
(6)
(7)
8
MD /DEM1
(6)
(7)
SYSCLK
ZFLG /20BIT
9
L/R CLK
BIT CLK
10 kΩ
10
11
12
BCKIN
V
DD
Control
Interface
Audio
Interface
DATA OUT
DOUT
DGND
0.1 µF
and 10 µF
(1)
DATA IN
(6)
(7)
ML /PDDA
(6)
(7)
RST /PDAD
S0014-01
(1) 0.1-µF ceramic and 10-µF tantalum, typical, depending on power supply quality and pattern layout
(2) 4.7-µF, typical, gives settling time with 30-ms (4.7 µF × 6.4 kΩ) time constant in the power ON and power-down OFF
periods.
(3) 1-µF, typical, gives 5.3-Hz cutoff frequency for the input HPF in normal operation and gives settling time with 30-ms
(1 µF × 30 kΩ) time constant in the power ON and power-down OFF periods.
(4) 4.7-µF, typical, gives 3.4-Hz cutoff frequency for the output HPF in normal operation and gives settling time with
47-ms (4.7 µF × 10 kΩ) time constant in the power ON and power-down OFF periods.
(5) Post low-pass filter with RIN > 10 kΩ, depending on system performance requirements
(6) MC, MD, ML, ZFLG, RST, and 10-kΩ pullup resistor are for the PCM3002.
(7) DEM0, DEM1, 20BIT, PDAD, PDDA are for the PCM3003.
Figure 51. Typical Connection Diagram for PCM3002/3003
33
PCM3002
PCM3003
www.ti.com
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
THEORY OF OPERATION
ADC SECTION
The PCM3002/3003 ADC consists of two reference circuits, a stereo single-to-differential converter, a fully
differential fifth-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface
circuit. The block diagram in this data sheet illustrates the architecture of the ADC section, Figure 40 shows the
single-to-differential converter, and Figure 52 illustrates the architecture of the fifth-order delta-sigma modulator
and transfer functions.
An internal reference circuit with three external capacitors provides all reference voltages required by the ADC,
which defines the full-scale range for the converter. The internal single-to-differential voltage converter saves the
space and extra parts needed for the external circuitry required by many delta-sigma converters. The internal
full-differential signal processing architecture provides a wide dynamic range and excellent power supply
rejection performance. The input signal is sampled at a 64× oversampling rate, eliminating the need for a
sample-and-hold circuit, and simplifying antialias filtering requirements. The fifth-order delta-sigma noise shaper
consists of five integrators which use a switched-capacitor topology, a comparator, and a feedback loop
consisting of a one-bit DAC. The delta-sigma modulator shapes the quantization noise, shifting it out of the audio
band in the frequency domain. The high order of the modulator enables it to randomize the modulator outputs,
reducing idle tone levels.
The 64-fS, one-bit data stream from the modulator is converted to 1-fS, 16/20-bit data words by the decimation
filter, which also acts as a low-pass filter to remove the shaped quantization noise. The dc components are
removed by a high-pass filter function contained within the decimation filter.
DAC SECTION
The delta-sigma DAC section of the PCM3002/3003 is based on a 5-level amplitude quantizer and a third-order
noise shaper. This section converts the oversampled input data to a 5-level delta-sigma format. A block diagram
of the 5-level delta-sigma modulator is shown in Figure 53. This 5-level delta-sigma modulator has the advantage
of improved stability and reduced clock-jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modulator and the internal 8× interpolation filter is 64 fS for a
256-fS system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator is
shown in Figure 54.
Analog
In
−
−
st
nd
rd
th
th
1
2
3
4
5
X(z)
+
+
+
SW-CAP
SW-CAP
SW-CAP
SW-CAP
SW-CAP
Qn(z)
Integrator
Integrator
Integrator
Integrator
Integrator
−
Digital
Out
Y(z)
+
+
+
+
+
+
+
+
H(z)
Comparator
1-Bit
DAC
Y(z) = STF(z) * X(z) + NTF(z) * Qn(z)
Signal Transfer Function
Noise Transfer Function
STF(z) = H(z) / [1 + H(z)]
NTF(z) = 1 / [1 + H(z)]
B0005-01
Figure 52. Simplified Fifth-Order Delta-Sigma Modulator
34
PCM3002
PCM3003
www.ti.com
SBAS079A–OCTOBER 2000–REVISED OCTOBER 2004
THEORY OF OPERATION (continued)
+
−
+
−
+
In
+
+
+
−1
−1
−1
Z
8 f
S
Z
Z
21-Bit
+
+
+
5-Level Quantizer
4
3
2
1
0
Out
64 f
S
B0008-01
Figure 53. Five-Level Delta-Sigma Modulator Block Diagram
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
0
5
10
15
20
25
30
f − Frequency − kHz
G040
Figure 54. Quantization Noise Spectrum
35
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PCM3002E
PCM3002E/2K
PCM3003E
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
SSOP
DB
DB
DB
DB
24
24
24
24
58
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-25 to 85
-25 to 85
PCM3002E
Samples
Samples
Samples
Samples
2000 RoHS & Green
58 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
PCM3002E
PCM3003E
PCM3003E
PCM3003E/2K
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM3002E/2K
PCM3003E/2K
SSOP
SSOP
DB
DB
24
24
2000
2000
330.0
330.0
17.4
17.4
8.5
8.5
8.6
8.6
2.4
2.4
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
PCM3002E/2K
PCM3003E/2K
SSOP
SSOP
DB
DB
24
24
2000
2000
336.6
336.6
336.6
336.6
28.6
28.6
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
PCM3002E
PCM3003E
DB
DB
SSOP
SSOP
24
24
58
58
500
500
10.6
10.6
500
500
9.6
9.6
Pack Materials-Page 3
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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