PDM31096SA10T [ETC]

4 Megabit 3.3V Static RAM 512K x 8-Bit; 4兆位3.3V静态RAM 512K ×8位


型号：	PDM31096SA10T
厂家：	ETC
描述：	4 Megabit 3.3V Static RAM 512K x 8-Bit 4兆位3.3V静态RAM 512K ×8位内存集成电路静态存储器光电二极管
文件：	总8页 (文件大小：237K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PDM31096

PRELIMINARY

4 Megabit 3.3V Static RAM

512K x 8-Bit

Features

Description

■ High-speed access times

Com’l: 8, 10, 12, 15, and 20 ns

Ind’l.: 12, 15 and 20 ns

The PDM31096 is a high-performance CMOS static

RAM organized as 524,288 x 8 bits. Writing is

accomplished when the write enable (WE) and chip

enable CE inputs are both LOW. Reading is

accomplished when WE remains HIGH and CE and

OE are both LOW.

■ Low power operation

- PDM31096SA

Active: 300 mA (Max)

Standby: 25mW

The PDM31096 operates from a single +3.3V power

supply and all the inputs and outputs are fully TTL-

compatible.

■ Single +3.3V (±0.3V) power supply

■ TTL-compatible inputs and outputs

■ Packages

The PDM31096 is available in a 36-pin 400-mil plas-

tic SOJ package and a 44-pin plastic TSOP (II)

package.

Plastic SOJ (400 mil) - SO

Plastic TSOP (II) - T

Functional Block Diagram

A₀

•

Decoder

Memory

Matrix

•

Addresses

•

A₁₈

• • • • •

I/O₀

Input

Data

Control

Column I/O

•

I/O₇

•

Rev. 2.4 - 5/27/98

PRELIMINARY

PDM31096

Pin Conﬁguration

TSOP (II)

SOJ

Pin Description

Name

Description

Address Inputs

A18-A0

I/O7-I/O0

Data Inputs/Outputs

Output Enable Input

Write Enable Input

Chip Enable Inputs

No Connect

I/O7

I/O6

Vss

Vcc

I/O5

I/O4

I/O0

I/O1

Vcc

Vss

I/O2

I/O3

A18

A17

A16

A15

A14

I/O7

I/O6

Vss

Vcc

I/O5

I/O4

I/OO

I/O1

Vcc

Vss

Power (+3.3V)

I/O2

I/O3

A18

A17

A16

A15

A14

A10

A11

A12

A13

Ground

A10

A11

A12

A13

(1)

Truth Table

I/O

MODE

Hi-Z

Standby

Read

OUT

Write

Hi-Z

Output Disable

NOTE: 1. H = V , L = V , X = DON’T CARE

(1)

Absolute Maximum Ratings

Symbol

Rating

Com’l.

Ind.

Unit

Terminal Voltage with Respect to V

Temperature Under Bias

Storage Temperature

–0.5 to +4.6

–55 to +125

1.0

–0.5 to +4.6

–65 to +135

–65 to +150

1.0

°C

TERM

BIAS

STG

Power Dissipation

DC Output Current

°C

OUT

(2)

Maximum Junction Temperature

125

145

NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this speciﬁcation is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. Appropriate thermal calculations should be performed in all cases and speciﬁcally for

those where the chosen package has a large thermal resistance (e.g., TSOP). The cal-

culation should be of the form: T = T + P * θ where T is the ambient temperature, P

is average operating power and θ the thermal resistance of the package. For this

product, use the following θ value:

SOJ: 59 C/W

TSOP : TBD

Rev. 2.4 - 5/27/98

PRELIMINARY

PDM31096

DC Electrical Characteristics (V = 3.3V ± 0.3V)

Symbol

Parameter

Test Conditions

Min.

–5

Max.

Unit

µA

Input Leakage Current

Output Leakage Current

= Max., V = V to V

= Max.,

–5

µA

CE = V

= V to V

OUT

SS CC

(1)

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

–0.3

2.2

—

0.8

Vcc+0.3

0.4

= 8 mA, V = Min.

OL CC

= –4 mA, V = Min.

2.4

—

NOTE:1.V (min) = –3.0V for pulse width less than 20 ns

Power Supply Characteristics

-8

-10

-12

-15

-20

Symbol Parameter

Operating Current

CE = V

Com’l.

Com’l. Com’l Ind. Com’l Ind. Com’l Ind. Unit

230

215

200

220

160

200

120

160

f = f

= 1/t

= Max.

= 0 mA

MAX

OUT

Standby Current

CE = V

f = f

= 1/t

MAX

= Max.

Full Standby Current

SB1

CE ≥ V – 0.2V

f = 0

= Max.,

≥ V – 0.2V or ≤ 0.2V

NOTES: All values are maximum guaranteed values.

(1)

Capacitance (T = +25°C, f = 1.0 MHz)

Symbol

Parameter

Max.

Unit

Input Capacitance

Output Capacitance

OUT

NOTE: 1.This parameter is determined by device characterization but is not production tested.

Rev. 2.4 - 5/27/98

PRELIMINARY

PDM31096

Recommended DC Operating Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

3.0

3.3

3.6

Supply Voltage

Industrial

Ambient Temperature

–40

–0

°C

Commercial

AC Test Conditions

Input pulse levels

to 3.0V

2.5 ns

1.5V

Input rise and fall times

Input timing reference levels

Output reference levels

Output load

1.5V

See Figures 1 and 2

+3.3V

317Ω

D_OUT

351Ω

D_OUT

351Ω

30 pF

5 pF

Figure 1. Output Load Equivalent

Figure 2. Output Load Equivalent

(for t , t , t , t , t

LZCE HZCE LZWE HZWE LZOE

)

HZOE

Rev. 2.4 - 5/27/98

PRELIMINARY

PDM31096

(4, 5)

Read Cycle No. 1

ADDR

PREVIOUS DATA VALID

DATA VALID

OUT

(2, 4, 6)

Read Cycle No. 2

ADDR

ACE

HZCE

LZCE

HZOE

LZOE

DATA VALID

OUT

AOE

AC Electrical Characteristics

Description

-8*

-10*

–12

–15

–20

READ Cycle

Sym

Min Max Min Max Min Max Min Max Min Max Units

READ cycle time

—

Address access time

Chip enable access time

Output hold from address change

ACE

—

(1,3)

Chip enable to output in low Z

LZCE

(1,2,3)

Chip disable to output in high Z

Output enable access time

—

HZCE

AOE

(1,3)

Output Enable to output in low Z

—

LZOE

HZOE

Output disable to output in high Z

* V = 3.3V +5%

—

Rev. 2.4 - 5/27/98

PRELIMINARY

PDM31096

Write Cycle No. 1 (Write Enable Controlled)

ADDR

DATA VALID

HZWE

LZWE

HIGH-Z

OUT

Write Cycle No. 2 (Write Enable Controlled)

ADDR

DATA VALID

HIGH-Z

OUT

NOTE: Output Enable (OE) is inactive (high)

Rev. 2.4 - 5/27/98

PRELIMINARY

PDM31096

Write Cycle No. 3 (Chip Enable Controlled)

ADDR

DATA VALID

HIGH-Z

OUT

NOTE: Output Enable (OE) is inactive (high)

AC Electrical Characteristics

Description

-8*

-10*

-12

-15

-20

WRITE Cycle

Sym

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

WRITE cycle time

—

Chip enable to end of write

Address valid to end of write

Address setup time

—

Address hold from end of write

Write pulse width

Data setup time

Data hold time

—

(1,3)

Write disable to output in low Z

Write enable to output in high Z

LZWE

(1,3)

—

HZWE

* V = 3.3V +5%

NOTES: (For two previous Electrical Characteristics tables)

1. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state voltage.

2. At any given temperature and voltage condition, t

3. This parameter is sampled.

4. WE is high for a READ cycle.

5. The device is continuously selected. All the Chip Enables are held in their active state.

6. The address is valid prior to or coincident with the latest occuring Chip Enable.

is less than t

HZCE

LZCE

Rev. 2.4 - 5/27/98

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